diff --git a/.gitignore b/.gitignore
index fc32b283a..9876051be 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,5 +1,7 @@
 **/work*
 **/wally_*.log
+/**/obj_dir*
+/**/gmon*
 
 .nfs*
 
@@ -115,10 +117,10 @@ tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S
 tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag
 sim/branch_BP_GSHARE10.log
 sim/branch_BP_GSHARE16.log
-sim/imperas.log
+sim/questa/imperas.log
 sim/results-error/
 sim/test1.rep
-sim/vsim.log
+sim/questa/vsim.log
 tests/coverage/*.elf
 *.elf.memfile
 sim/*Cache.log
@@ -186,7 +188,10 @@ sim/cfi/*
 sim/branch/*
 sim/obj_dir
 examples/verilog/fulladder/obj_dir
+examples/verilog/fulladder/fulladder.vcd
 config/deriv
+docs/docker/buildroot-config-src
+docs/docker/testvector-generation
 sim/questa/cov
 sim/questa/covhtmlreport/
 sim/questa/logs
@@ -196,3 +201,40 @@ sim/verilator/wkdir
 sim/vcs/logs
 sim/vcs/wkdir
 benchmarks/coremark/coremark_results.csv
+fpga/zsbl/OBJ/*
+fpga/zsbl/bin/*
+sim/*.svg
+sim/vcs/csrc
+sim/vcs/profileReport*
+sim/vcs/program.out
+sim/vcs/sim_out*
+sim/vcs/simprofile_dir
+sim/vcs/ucli.key
+sim/vcs/verdi_config_file
+sim/vcs/vcdplus.vpd
+sim/*/testbench.vcd 
+sim/questa/imperas.log
+sim/questa/functcov.log
+sim/questa/functcov_logs/*
+sim/questa/functcov_ucdbs/*
+sim/questa/functcov
+sim/questa/riscv.ucdb
+sim/questa/riscv.ucdb.log
+sim/questa/riscv.ucdb.summary.log
+sim/questa/riscv.ucdb.testdetails.log
+tests/riscvdv
+examples/verilog/fulladder/csrc/
+examples/verilog/fulladder/profileReport.html
+examples/verilog/fulladder/profileReport.json
+examples/verilog/fulladder/profileReport.txt
+examples/verilog/fulladder/profileReport/
+examples/verilog/fulladder/simprofile_dir/
+examples/verilog/fulladder/simv.daidir/
+examples/verilog/fulladder/ucli.key
+examples/verilog/fulladder/verdi_config_file
+examples/crypto/gfmul/gfmul
+tests/functcov
+tests/functcov/*
+tests/functcov/*/*
+sim/vcs/simprofile*
+soc/fsbl/*.a
diff --git a/.gitmodules b/.gitmodules
index 3961a407c..aafd924ad 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -23,6 +23,7 @@
 [submodule "addins/riscv-arch-test"]
 	path = addins/riscv-arch-test
 	url = https://github.com/riscv-non-isa/riscv-arch-test
+	branch = dev
 [submodule "addins/branch-predictor-simulator"]
 	path = addins/branch-predictor-simulator
 	url = https://github.com/ross144/branch-predictor-simulator
diff --git a/Makefile b/Makefile
index 33eeea45d..740287dcc 100644
--- a/Makefile
+++ b/Makefile
@@ -2,26 +2,16 @@
 # Top-level Makefile for CORE-V-Wally
 # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
+SIM = ${WALLY}/sim
+
 all:
-	make install
 	make riscof	
 	make testfloat
 #	make verify
-	make coverage
-	make benchmarks
-
-# install copies over the Makefile.include from riscv-isa-sim
-# And corrects the TARGETDIR path and the RISCV_PREFIX
-
-install:
-	# *** 1/15/23 dh: check if any of this is still needed
-	#cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
-	#sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include
-	#echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include
-	##cd tests/linux-testgen/linux-testvectors; source ./tvLinker.sh # needs to be run in local directory
-	##rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
-	##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
+#	make coverage
+#	make benchmarks
 
+# riscof builds the riscv-arch-test and wally-riscv-arch-test suites
 riscof:
 	make -C sim
 
@@ -31,8 +21,8 @@ testfloat:
 	cd ${WALLY}/tests/fp; ./create_all_vectors.sh
 
 verify:
-	cd ${WALLY}/sim; ./regression-wally
-	cd ${WALLY}/sim; ./sim-testfloat-batch all
+	cd ${SIM}; ./regression-wally
+	cd ${SIM}/sim; ./sim-testfloat-batch all
 	make imperasdv
 
 imperasdv:
@@ -40,12 +30,13 @@ imperasdv:
 	iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m
 
 imperasdv_cov:
-	touch ${WALLY}/sim/seed0.txt
-	echo "0" > ${WALLY}/sim/seed0.txt
+	touch ${SIM}/seed0.txt
+	echo "0" > ${SIM}/seed0.txt
 #	/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --verbose --seed 0 --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
-#	/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb ${WALLY}/sim/cov/rv64gc_arch64i.ucdb --verbose
-	/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb riscv.ucdb --verbose
-	vcover report -details -html sim/riscv.ucdb
+#	/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/cov/rv64gc_arch64i.ucdb --verbose
+#	/opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose
+	run-elf-cov.bash --elf ${WALLY}/tests/riscvdv/asm_test/riscv_arithmetic_basic_test_0.elf --seed ${SIM}/questa/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose
+	vcover report -details -html ${SIM}/questa/riscv.ucdb
 
 funcovreg:
 	#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m --cover
@@ -54,10 +45,69 @@ funcovreg:
 	#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/Q --cover
 	rm -f ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/*/src/*/dut/my.elf
 	iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I --cover
-	vcover report -details -html sim/riscv.ucdb
-
-coverage:
-	cd ${WALLY}/sim; ./regression-wally -coverage -fp
+	vcover report -details -html ${SIM}/questa/riscv.ucdb
+
+
+
+# test_name=riscv_arithmetic_basic_test
+riscvdv: 
+	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen,gcc_compile			>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+#	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile	>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+#	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim		>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+#	run-elf.bash --seed ${SIM}/questa/seed0.txt --verbose --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o													>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+	#run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/riscv.ucdb --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o								>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+	#cp ${SIM}/questa/riscv.ucdb ${SIM}/questa/functcov_ucdbs/${test_name}.ucdb
+
+riscvdv_functcov:
+	mkdir -p ${SIM}/questa/functcov_logs
+	mkdir -p ${SIM}/questa/functcov_ucdbs
+	cd ${SIM}/questa/functcov_logs && rm -rf *
+	cd ${SIM}/questa/functcov_ucdbs && rm -rf *
+	make riscvdv test_name=riscv_arithmetic_basic_test				>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_amo_test							>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_ebreak_debug_mode_test			>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_ebreak_test						>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_floating_point_arithmetic_test	>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_floating_point_mmu_stress_test	>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_floating_point_rand_test			>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_full_interrupt_test				>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_hint_instr_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_illegal_instr_test				>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_invalid_csr_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_jump_stress_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_loop_test							>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_machine_mode_rand_test			>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_mmu_stress_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_no_fence_test						>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_non_compressed_instr_test			>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_pmp_test							>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_privileged_mode_rand_test			>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_rand_instr_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_rand_jump_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_sfence_exception_test				>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_unaligned_load_store_test			>> ${SIM}/questa/functcov.log 2>&1
+
+combine_functcov:
+	mkdir -p ${SIM}/questa/functcov
+	mkdir -p ${SIM}/questa/functcov_logs
+	cd ${SIM}/questa/functcov && rm -rf *
+	run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/add.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf								>> ${SIM}/questa/functcov_logs/add.log 2>&1
+	run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/and.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-and.elf								>> ${SIM}/questa/functcov_logs/add.log 2>&1
+	run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/ori.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-ori.elf								>> ${SIM}/questa/functcov_logs/add.log 2>&1
+
+	vcover merge ${SIM}/questa/functcov/functcov.ucdb ${SIM}/questa/functcov/*.ucdb ${SIM}/questa/functcov_ucdbs/* -suppress 6854 -64
+	# vcover merge ${SIM}/questa/functcov/functcov.ucdb ${SIM}/questa/functcov_ucdbs/* -suppress 6854 -64
+	vcover report -details -html ${SIM}/questa/functcov/functcov.ucdb
+	vcover report ${SIM}/questa/functcov/functcov.ucdb -details -cvg > ${SIM}/questa/functcov/functcov.log
+	vcover report ${SIM}/questa/functcov/functcov.ucdb -testdetails -cvg > ${SIM}/questa/functcov/functcov.testdetails.log
+#	vcover report ${SIM}/questa/functcov/functcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > ${SIM}/questa/functcov/functcov.ucdb.summary.log
+	vcover report ${SIM}/questa/functcov/functcov.ucdb -details -cvg | egrep "Coverpoint|Covergroup|Cross|TYPE"  > ${SIM}/questa/functcov/functcov.summary.log
+	grep "Total Coverage By Instance" ${SIM}/questa/functcov/functcov.ucdb.log
+
+remove_functcov_artifacts:
+	rm ${SIM}/questa/riscv.ucdb ${SIM}/questa/functcov.log covhtmlreport/ ${SIM}/questa/functcov_logs/ ${SIM}/questa/functcov_ucdbs/ ${SIM}/questa/functcov/ -rf
+
+collect_functcov: remove_functcov_artifacts riscvdv_functcov combine_functcov
 
 benchmarks:
 	make coremark
diff --git a/README.md b/README.md
index d75e8fb98..084741107 100644
--- a/README.md
+++ b/README.md
@@ -41,38 +41,46 @@ Clone your fork of the repo and run the setup script. Change <yourgithubid> to y
 	$ git remote add upstream https://github.com/openhwgroup/cvw
 	$ source ./setup.sh
 
+If you are installing on a new system without any tools installed please jump to the next section, Toolchain Installation then come back here.
+
 Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in.
 
 	if [ -f ~/cvw/setup.sh ]; then
 		source ~/cvw/setup.sh
 	fi
 
-Edit setup.sh and change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server.  If you only have Questa, you can still simulate but cannot run logic synthesis.
-
-	export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu                # Change this to your Siemens license server
-	export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu                # Change this to your Synopsys license server
-	export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin     # Change this for your path to Questa
-	export SNPSPATH=/cad/synopsys/SYN/bin                               # Change this for your path to Design Compiler
-
 If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below.
 
 Build the tests and run a regression simulation with Questa to prove everything is installed.  Building tests will take a while.
 
 	$ make
-	$ cd sim
-	$ ./regression-wally       (depends on having Questa installed)
+	$ regression-wally       (depends on having Questa installed)
 
 # Toolchain Installation (Sys Admin)
 
 This section describes the open source toolchain installation.  The
-current version of the toolchain has been tested on Ubuntu and Red
+current version of the toolchain has been tested on Ubuntu and partly on Red
 Hat/Rocky 8 Linux.  Ubuntu works more smoothly and is recommended
-unless you have a compelling need for RedHat.  
+unless you have a compelling need for RedHat.  However, Ubuntu 22.04LTS
+is incompatible with Synopsys Design Compiler.
 
 Ubuntu users can install the tools by running
 
 	$ sudo $WALLY/bin/wally-tool-chain-install.sh
 
+The default installation directory is /opt/riscv defined by the environment variable RISCV. You must copy and edit ~/cvw/site-setup.sh to $RISCV/site-setup.sh.
+
+~/cvw/setup.sh sources $RISCV/site-setup.sh.
+This allows for customization of the site specific information such as commerical licenses and PATH variables.
+
+Change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server.  If you only have Questa, you can still simulate but cannot run logic synthesis.  If Questa or Design Compiler are already setup on this system then don't set these variables.
+
+	export MGLS_LICENSE_FILE=..         # Change this to your Siemens license server
+	export SNPSLMD_LICENSE_FILE=..      # Change this to your Synopsys license server
+	export QUESTAPATH=..                # Change this for your path to Questa
+	export SNPSPATH=..                  # Change this for your path to Design Compiler
+
+
 See wally-tool-chain-install.sh for a detailed description of each component,
 or to issue the commands one at a time to install on the command line.
 ## Installing EDA Tools
@@ -131,9 +139,54 @@ Startups can expect to spend more than $1 million on CAD tools to get a chip to
 ## Adding Cron Job for nightly builds
 
 If you want to add a cronjob you can do the following:
-1) `crontab -e`
-2) add this code:
+1) Set up the email client `mutt` for your distribution
+2) Enter `crontab -e` into a terminal
+3) add this code to test building CVW and then running `regression-wally --nightly` at 9:30 PM each day
 ```
-0 3 * * * BASH_ENV=~/.bashrc bash -l -c "PATH_TO_CVW/cvw/bin/wrapper_nightly_runs.sh > PATH_TO_LOG_FOLDER/cron.log"
+30 21 * * * bash -l -c "source ~/PATH/TO/CVW/setup.sh; PATH_TO_CVW/cvw/bin/wrapper_nightly_runs.sh --path {PATH_TO_TEST_LOCATION} --target all --tests nightly --send_email harris@hmc.edu,kaitlin.verilog@gmail.com"
 ```
 
+# Example wsim commands
+
+wsim runs one of multiple simulators, Questa, VCS, or Verilator using a specific configuration and either a suite of tests or a specific elf file.
+The general syntax is
+wsim <config> <suite or elf file or directory> [--options]
+
+Parameters and options:
+
+	-h, --help                                                   show this help message and exit
+	--sim {questa,verilator,vcs}, -s {questa,verilator,vcs}      Simulator
+	--tb {testbench,testbench_fp}, -t {testbench,testbench_fp}   Testbench
+	--gui, -g                                                    Simulate with GUI
+	--coverage, -c                                               Code & Functional Coverage
+	--fcov, -f                                                   Code & Functional Coverage
+	--args ARGS, -a ARGS                                         Optional arguments passed to simulator via $value$plusargs
+	--vcd, -v                                                    Generate testbench.vcd
+	--lockstep, -l                                               Run ImperasDV lock, step, and compare.
+	--locksteplog LOCKSTEPLOG, -b LOCKSTEPLOG                    Retired instruction number to be begin logging.
+	--covlog COVLOG, -d COVLOG                                   Log coverage after n instructions.
+	--elfext ELFEXT, -e ELFEXT                                   When searching for elf files only includes ones which end in this extension
+
+Run basic test with questa
+
+	wsim rv64gc arch64i
+
+Run Questa with gui
+
+	wsim rv64gc wally64priv --gui
+
+Run lockstep against ImperasDV with a single elf file in the --gui.  Lockstep requires single elf.
+
+	wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --gui
+
+Run lockstep against ImperasDV with a single elf file.  Compute coverage.
+
+	wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --coverage
+
+Run lockstep against ImperasDV with directory file.  
+
+	wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep
+
+Run lockstep against ImperasDV with directory file and specify specific extension.
+
+	wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep --elfext ref.elf
diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index 8a0cdceca..7152865ac 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit 8a0cdceca9f0b91b81905eb8497f6586bf8d1c6b
+Subproject commit 7152865aca51062c87ff2cbb014e199a24bdc874
diff --git a/addins/riscv-dv b/addins/riscv-dv
index a7e27bc04..f0c570d11 160000
--- a/addins/riscv-dv
+++ b/addins/riscv-dv
@@ -1 +1 @@
-Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172
+Subproject commit f0c570d11236f94f9c5449870223a5ac717cc580
diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile
index 9ac905950..63afc34bf 100644
--- a/benchmarks/coremark/Makefile
+++ b/benchmarks/coremark/Makefile
@@ -5,14 +5,14 @@
 PORT_DIR = $(CURDIR)/riscv64-baremetal
 cmbase= $(WALLY)/addins/coremark
 work_dir= $(WALLY)/benchmarks/coremark/work
-XLEN ?=64
+XLEN ?=32
 sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h  \
 	$(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \
 	$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
 	$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
 ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32)
-#ARCH := rv$(XLEN)gc_zba_zbb_zbc
-ARCH := rv$(XLEN)im_zicsr_zba_zbb_zbc
+ARCH := rv$(XLEN)im_zicsr_zba_zbb_zbs
+CONFIG := rv$(XLEN)gc
 #ARCH := rv$(XLEN)gc
 #ARCH := rv$(XLEN)imc_zicsr
 #ARCH := rv$(XLEN)im_zicsr
@@ -27,9 +27,9 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 
 all: $(work_dir)/coremark.bare.riscv.elf.memfile
 
-run:
-	time wsim rv$(XLEN)gc coremark 2>&1 | tee $(work_dir)/coremark.sim.log
-	#(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
+run: $(work_dir)/coremark.bare.riscv.elf.memfile
+#	time wsim rv$(XLEN)gc coremark --sim verilator 2>&1 | tee $(work_dir)/coremark.sim.log
+	time wsim ${CONFIG} coremark 2>&1 | tee $(work_dir)/coremark.sim.log
 
 $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
 	riscv64-unknown-elf-objdump -D $< > $<.elf.objdump
diff --git a/benchmarks/coremark/coremark_sweep.py b/benchmarks/coremark/coremark_sweep.py
index 527f5f44f..d912349dc 100755
--- a/benchmarks/coremark/coremark_sweep.py
+++ b/benchmarks/coremark/coremark_sweep.py
@@ -34,27 +34,29 @@
 import csv
 # list of architectures to run. 
 arch_list = [
-    "rv32gc_zba_zbb_zbc",
-    "rv32im_zicsr_zba_zbb_zbc",
-    "rv32gc",
-    "rv32imc_zicsr",
-    "rv32im_zicsr",
     "rv32i_zicsr",
-    "rv64gc_zba_zbb_zbc",
-    "rv64im_zicsr_zba_zbb_zbc",
-    "rv64gc",
-    "rv64imc_zicsr",
+    "rv32im_zicsr",
+    "rv32imc_zicsr",
+    "rv32im_zicsr_zba_zbb_zbs",
+    "rv32gc",
+    "rv32gc_zba_zbb_zbs",
+    "rv64i_zicsr",
     "rv64im_zicsr",
-    "rv64i_zicsr"
+    "rv64imc_zicsr",
+    "rv64im_zicsr_zba_zbb_zbs",
+    "rv64gc",
+    "rv64gc_zba_zbb_zbs"
 ]
 str="32" 
+        
 # Define regular expressions to match the desired fields
 mt_regex = r"Elapsed MTIME: (\d+).*?Elapsed MINSTRET: (\d+).*?COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+).*?CPI: \d+ / \d+ = (\d+\.\d+).*?Load Stalls (\d+).*?Store Stalls (\d+).*?D-Cache Accesses (\d+).*?D-Cache Misses (\d+).*?I-Cache Accesses (\d+).*?I-Cache Misses (\d+).*?Branches (\d+).*?Branches Miss Predictions (\d+).*?BTB Misses (\d+).*?Jump and JR (\d+).*?RAS Wrong (\d+).*?Returns (\d+).*?BP Class Wrong (\d+)"
 #cpi_regex = r"CPI: \d+ / \d+ = (\d+\.\d+)"
 #cmhz_regex = r"COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+)"
 # Open a CSV file to write the results
-with open('coremark_results.csv', mode='w', newline='') as csvfile:
-    fieldnames = ['Architecture', 'MTIME','MINSTRET','CM / MHz','CPI','Load Stalls','Store Stalls','D$ Accesses',
+resultfile = 'coremark_results.csv'
+with open(resultfile, mode='w', newline='') as csvfile:
+    fieldnames = ['Architecture', 'CM / MHz','CPI','MTIME','MINSTRET','Load Stalls','Store Stalls','D$ Accesses',
                     'D$ Misses','I$ Accesses','I$ Misses','Branches','Branch Mispredicts','BTB Misses',
                     'Jump/JR','RAS Wrong','Returns','BP Class Pred Wrong']
     writer = csv.DictWriter(csvfile, fieldnames=fieldnames)
@@ -101,7 +103,11 @@
         ret= mt_match.group(16)
         bpc= mt_match.group(17)
         #minstret = mt_instret_match.group(2)
-        writer.writerow({'Architecture': arch, 'MTIME': mtime,'MINSTRET':minstret,'CM / MHz':cmhz,'CPI':cpi,
+        writer.writerow({'Architecture': arch, 'CM / MHz':cmhz,'CPI':cpi, 'MTIME': mtime,'MINSTRET':minstret,
                             'Load Stalls':lstalls,
                             'Store Stalls':swtalls,'D$ Accesses':dacc,'D$ Misses':dmiss,'I$ Accesses':iacc,'I$ Misses':imiss,
                             'Branches':br,'Branch Mispredicts':brm,'BTB Misses':btb,'Jump/JR':jmp,'RAS Wrong':ras,'Returns':ret,'BP Class Pred Wrong':bpc})
+        csvfile.flush()
+    csvfile.close()
+
+
diff --git a/benchmarks/coremark/riscv64-baremetal/core_portme.h b/benchmarks/coremark/riscv64-baremetal/core_portme.h
index 4f5efc1d8..8db43d20a 100755
--- a/benchmarks/coremark/riscv64-baremetal/core_portme.h
+++ b/benchmarks/coremark/riscv64-baremetal/core_portme.h
@@ -109,11 +109,11 @@ typedef unsigned short ee_u16;
 typedef signed int ee_s32;
 typedef double ee_f32;
 typedef unsigned char ee_u8;
-//typedef unsigned int ee_u32;
-typedef signed int ee_u32; // replaced with signed to improve performance per https://github.com/sifive/benchmark-coremark/blob/master/linux64/core_portme.h#L102
 #if (XLEN==64) 
+	typedef signed int ee_u32; // replaced with signed to improve performance by avoiding zero extension in RV64 per https://github.com/sifive/benchmark-coremark/blob/master/linux64/core_portme.h#L102
 	typedef unsigned long long ee_ptr_int;
 #else
+	typedef unsigned int ee_u32;
 	typedef ee_u32 ee_ptr_int;
 #endif
 typedef size_t ee_size_t;
diff --git a/benchmarks/coremark/riscv64-baremetal/core_portme.mak b/benchmarks/coremark/riscv64-baremetal/core_portme.mak
index 27e31b859..e07196061 100755
--- a/benchmarks/coremark/riscv64-baremetal/core_portme.mak
+++ b/benchmarks/coremark/riscv64-baremetal/core_portme.mak
@@ -107,7 +107,7 @@ port_prebuild: $(PGO_STAGE)
 
 .PHONY: build_pgo_gcc
 build_pgo_gcc:
-	$(MAKE) PGO=gen XCFLAGS="$(XCFLAGS) -fprofile-generate -DTOTAL_DATA_SIZE=1200" ITERATIONS=10 gen_pgo_data REBUILD=1
+	$(MAKE) PGO=gen XCFLAGS="$(XCFLAGS) -fprofile-generate -DTOTAL_DATA_SIZE=1200" gen_pgo_data REBUILD=1
 
 # Target: port_postbuild
 # Generate any files that are needed after actual build end.
diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile
index d8fbddae9..e4b671c59 100644
--- a/benchmarks/embench/Makefile
+++ b/benchmarks/embench/Makefile
@@ -38,26 +38,27 @@ build_speedopt_size:
 build_sizeopt_size:
 	$(embench_dir)/build_all.py --builddir=bd_sizeopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S -march=$(ARCH)" --cflags="-Os -msave-restore -march=$(ARCH)" --dummy-libs="libgcc libm libc crt0"
 
-# builds dependencies, then launches modelsim and finally runs python wrapper script to present results
-sim: modelsim_build_memfile modelsim_run speed
+# builds dependencies, then launches sim and finally runs python wrapper script to present results
+sim: sim_build_memfile sim_run speed
 
-# launches modelsim to simulate tests on wally
-modelsim_run:
-	mkdir -p ../../sim/wkdir
-	(cd ../../sim/ && vsim -c -do "do wally-batch.do rv32gc embench")
-	cd ../../benchmarks/embench/
+# launches sim to simulate tests on wally
+sim_run:
+	wsim rv32gc embench
+	#mkdir -p ../../sim/wkdir
+	#(cd ../../sim/ && wsim rv32gc embench)
+	#cd ../../benchmarks/embench/
 
 # builds the objdump based on the compiled c elf files
 objdump:
 	find $(embench_dir)/bd_*_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-objdump -S -D "$$f" > "$$f.objdump"; done
 
 # build memfiles, objdump.lab and objdump.addr files
-modelsim_build_memfile: objdump
+sim_build_memfile: objdump
 	find $(embench_dir)/bd_*_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done
 	find $(embench_dir)/bd_*_speed/ -type f -name "*.elf.objdump" | while read f; do extractFunctionRadix.sh $$f; done
 
 # builds the tests for speed, runs them on spike and then launches python script to present results
-# note that the speed python script benchmark_speed.py can get confused if there's both a .output file created from spike and modelsim
+# note that the speed python script benchmark_speed.py can get confused if there's both a .output file created from spike and questa
 # you'll need to manually remove one of the two .output files, or run make clean
 spike: buildspeed spike_run speed
 
diff --git a/bin/derivgen.pl b/bin/derivgen.pl
index 630962ca8..21ffc7019 100755
--- a/bin/derivgen.pl
+++ b/bin/derivgen.pl
@@ -70,10 +70,10 @@
 }
 &terminateDeriv();
 close($fh);
+system("rm -rf $ENV{WALLY}/config/deriv");
 #foreach my $key (keys %derivs) {
 foreach my $key (@derivnames) {
     my $dir = "$ENV{WALLY}/config/deriv/$key";
-    system("rm -rf $dir");
     system("mkdir -p $dir");
     my $configunmod = "$dir/config_unmod.vh";
     my $config = "$dir/config.vh";
@@ -90,7 +90,7 @@
 
     my $datestring = localtime();
     my %hit = ();
-    print $fh "// Config $key automatically derived from $basederiv{$key} on $datestring usubg derivgen.pl\n";
+    print $fh "// Config $key automatically derived from $basederiv{$key} on $datestring using derivgen.pl\n";
     foreach my $line (<$unmod>) {
         foreach my $entry (@{$derivs{$key}}) {    
             my @ent = @{$entry};
diff --git a/bin/hw_debug_test.py b/bin/hw_debug_test.py
new file mode 100755
index 000000000..2cebebf96
--- /dev/null
+++ b/bin/hw_debug_test.py
@@ -0,0 +1,182 @@
+#!/usr/bin/env python3
+
+#########################################################################################
+# hw_debug_test.py
+#
+# Written: matthew.n.otto@okstate.edu
+# Created: 19 April 2024
+#
+# Purpose: script to automate testing of hardware debug interface
+#
+# A component of the CORE-V-WALLY configurable RISC-V project.
+# https:#github.com/openhwgroup/cvw
+#
+# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+#
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+#
+# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+# except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+# may obtain a copy of the License at
+#
+# https:#solderpad.org/licenses/SHL-2.1/
+#
+# Unless required by applicable law or agreed to in writing, any work distributed under the 
+# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+# either express or implied. See the License for the specific language governing permissions 
+# and limitations under the License.
+#########################################################################################
+
+import random
+import time
+
+from openocd_tcl_wrapper import OpenOCD
+
+random_stimulus = True
+random_order = False
+
+
+def prog_buff_test(cvw):
+    cvw.halt()
+    pb = ["0x00840413", "0xd2e3ca40", "0x00100073"]
+    cvw.write_data("DCSR", hex(0x1 << 15))
+    cvw.write_progbuf(pb)
+    cvw.exec_progbuf()
+
+    cvw.resume()
+    print()
+
+
+def flow_control_test(cvw):
+    #time.sleep(200)  # wait for full boot
+
+    #cvw.halt()
+    for _ in range(5):
+        time.sleep(random.randint(5,10))
+        cvw.halt()
+        cvw.step()
+        cvw.step()
+        cvw.resume()
+    return
+
+    time.sleep(1)
+    #cvw.read_data("DCSR")
+    for _ in range(100):
+        time.sleep(random.randint(5,10))
+        print("Halting")
+        cvw.halt()
+        cvw.resume()
+        #cvw.step()
+        #print(cvw.read_data("PCM"))
+    #cvw.resume()
+
+
+def register_rw_test(cvw):
+    registers = dict.fromkeys(cvw.register_translations.keys(),[])
+    reg_addrs = list(registers.keys())
+
+    global XLEN
+    XLEN = cvw.LLEN
+    global nonstandard_register_lengths
+    nonstandard_register_lengths = cvw.nonstandard_register_lengths
+
+    #time.sleep(70)  # wait for OpenSBI
+
+    cvw.halt()
+
+    # dump data in all registers
+    for r in reg_addrs:
+        try:
+            data = cvw.read_data(r)
+            registers[r] = data
+            print(f"{r}: {data}")
+        except Exception as e:
+            if e.args[0] == "exception":  # Invalid register (not implemented)
+                del registers[r]
+                cvw.clear_abstrcmd_err()
+            else:
+                raise e
+    input("Compare values to ILA, press any key to continue")
+
+    # Write random data to all registers
+    reg_addrs = list(registers.keys())
+    if random_order:
+        random.shuffle(reg_addrs)
+    test_reg_data = {}
+    for r in reg_addrs:
+        test_data = random_hex(r)
+        try:
+            cvw.write_data(r, test_data)
+            test_reg_data[r] = test_data
+            print(f"Writing {test_data} to {r}")
+        except Exception as e:
+            if e.args[0] == "not supported":  # Register is read only
+                del registers[r]
+                cvw.clear_abstrcmd_err()
+            else:
+                raise e
+
+    # GPR X0 is always 0
+    test_reg_data["x0"] = "0x" + "0"*(cvw.LLEN//4)
+
+    # Confirm data was written correctly
+    reg_addrs = list(registers.keys())
+    if random_order:
+        random.shuffle(reg_addrs)
+    for r in reg_addrs:
+        try:
+            rdata = cvw.read_data(r)
+        except Exception as e:
+            raise e
+        if rdata != test_reg_data[r]:
+            print(f"Error: register {r} read did not return correct data: {rdata} != {test_reg_data[r]}")
+        else:
+            print(f"Reading {rdata} from {r}")
+
+    # Return all registers to original state
+    reg_addrs = list(registers.keys())
+    for r in reg_addrs:
+        print(f"Writing {registers[r]} to {r}")
+        try:
+            cvw.write_data(r, registers[r])
+        except Exception as e:
+            raise e
+
+    # Confirm data was written correctly
+    for r in reg_addrs:
+        try:
+            rdata = cvw.read_data(r)
+        except Exception as e:
+            raise e
+        if rdata != registers[r]:
+            raise Exception(f"Register {r} read did not return correct data: {rdata} != {registers[r]}")
+    print("All writes successful")
+
+    cvw.resume()
+
+
+def random_hex(reg_name):
+    pad = XLEN // 4
+    if reg_name in nonstandard_register_lengths:
+        size = nonstandard_register_lengths[reg_name]
+    else:
+        size = XLEN
+
+    # Reset ReadDataM to a value
+    nonstandard_register_lengths["READDATAM"] = XLEN
+    if random_stimulus:
+        return "0x" + f"{random.getrandbits(size):x}".rjust(pad, "0")
+    else:
+        data = 0xa5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5
+        return "0x" + f"{(data & (2**size-1)):x}".rjust(pad, "0")
+
+
+with OpenOCD() as cvw:
+    #cvw.trst()
+    cvw.reset_dm()
+    time.sleep(1)
+    cvw.reset_hart()
+    time.sleep(1)
+    #register_rw_test(cvw)
+    #flow_control_test(cvw)
+    prog_buff_test(cvw)
diff --git a/bin/imperas-one-time.sh b/bin/imperas-one-time.sh
deleted file mode 100755
index 339b4c74f..000000000
--- a/bin/imperas-one-time.sh
+++ /dev/null
@@ -1,55 +0,0 @@
-#!/bin/bash
-###########################################
-## imperas-one-time.sh
-##
-## Written: Ross Thompson (ross1728@gmail.com) and Lee Moore (moore@imperas.com)
-## Created: 31 January 2023
-## Modified: 31 January 2023
-##
-## Purpose: One time setup script for running imperas.
-## 
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-## 
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https://solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
-
-IMP_HASH=355a055ff7e36bc897e942e41f06e1baf96e34d5
-
-# clone the Imperas repo
-cd $WALY
-if [ ! -d external ]; then
-    mkdir -p external
-fi
-pushd external
-    if [ ! -d ImperasDV-HMC ]; then
-	git clone git@github.com:Imperas/ImperasDV-HMC.git
-    fi
-    pushd ImperasDV-HMC
-    git checkout $IMP_HASH
-    popd
-popd
-
-# Setup Imperas
-source ${WALLY}/external/ImperasDV-HMC/Imperas/bin/setup.sh
-setupImperas ${WALLY}/external/ImperasDV-HMC/Imperas
-export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
-
-# setup QUESTA (Imperas only command, YMMV)
-#svsetup -questa
-
-
diff --git a/bin/lint-wally b/bin/lint-wally
index 4187b0429..78332b2b2 100755
--- a/bin/lint-wally
+++ b/bin/lint-wally
@@ -11,8 +11,8 @@ GREEN='\033[0;32m'
 NC='\033[0m' # No Color
 fails=0
 
-if [ "$1" == "-nightly" ]; then
-    configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) # fdqh_rv64gc
+if [ "$1" == "--nightly" ]; then
+    configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) 
     derivconfigs=`ls $WALLY/config/deriv`
     for entry in $derivconfigs
     do
@@ -21,12 +21,15 @@ if [ "$1" == "-nightly" ]; then
         fi
     done
 else
-    configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i ) # add fdqh_rv64gc when working
+    configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc)
 fi
 
 for config in ${configs[@]}; do
 #    echo "$config linting..."
-    if !($verilator --no-timing --lint-only --top-module wallywrapper "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
+    if !($verilator --lint-only --quiet --top-module wallywrapper \
+         "-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" \
+         $basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv \
+         -Wall -Wno-UNUSEDSIGNAL -Wno-UNUSEDPARAM -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY); then
         if [ "$1" == "-nightly" ]; then
             echo -e "${RED}$config failed lint${NC}"
             fails=$((fails+1))
@@ -48,4 +51,5 @@ echo -e "${GREEN}All ${#configs[@]} lints run with no errors or warnings"
 # -I points to the include directory where files such as `include config.vh  are found
 
 # For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
+# verilator --lint-only -Wall --quiet --top-module wallywrapper -Iconfig/shared -Iconfig/rv64gc src/cvw.sv testbench/wallywrapper.sv src/*/*.sv src/*/*/*.sv -Wno-UNUSEDPARAM -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY
 # Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.
diff --git a/bin/nightly_build.py b/bin/nightly_build.py
index 1a268a42b..d82877a7a 100755
--- a/bin/nightly_build.py
+++ b/bin/nightly_build.py
@@ -16,6 +16,7 @@
         These emails serve as communication channels for stakeholders, providing them with timely updates on the software's regression status.
 
 Usage:
+                    shutil.rmtree(file)
 
 - The script is designed to be scheduled and executed automatically on a nightly basis using task scheduling tools such as Cronjobs. To create a cronjob do the following:
     1)  Open Terminal:
@@ -67,7 +68,8 @@
 
 import os
 import shutil
-from datetime import datetime
+from datetime import datetime, timedelta
+import time
 import re
 import markdown
 import subprocess
@@ -115,6 +117,46 @@ def create_folders(self, folders):
             if not os.path.exists(folder):
                 os.makedirs(folder)
 
+
+    def remove_folder(self, folders):
+        """
+        Delete a folder, including all of its contents
+
+        Args:
+            folders (list): A folder to be deleted
+        
+        Returns:
+            None
+        """
+
+        for folder in folders:
+            if os.path.exists(folder):
+                shutil.rmtree(folder)
+
+    def remove_stale_folders(self, folder, days_old=30):
+        """
+        Delete all folders over X days old in a folder. 
+
+        Args:
+            folder (str): Folder to delete folders and files from
+            days_old (int): Number of days old a file must be before deleting
+
+        Returns:
+            None
+        """
+        dirs = os.listdir(folder)
+        threshold = time.time() - days_old*86400
+        
+        for file in dirs:
+            file = os.path.join(folder, file)
+            file_mtime = os.stat(file).st_mtime
+            if file_mtime < threshold:
+                if os.path.isfile(file):
+                    os.remove(file)
+                elif os.path.isdir(file):
+                    shutil.rmtree(file)
+
+
     def clone_repository(self, folder, repo_url):
         """
         Clone a repository into the 'cvw' folder if it does not already exist.
@@ -185,8 +227,23 @@ def copy_setup_script(self, folder):
             self.logger.error(f"Error copying setup script: {e}")
             return False
 
+    
+    def set_env_var(self, envar, value):
+        """
+        Set an environment variable to a value
+
+        Args:
+            envar (str): Environment variable to set
+            value (str): New value for the environment variable
 
-    def set_env_var(self, folder):
+        Returns:
+            None
+        """
+        self.logger.info(f"Setting {envar}={value}")
+        os.environ[envar] = value
+
+
+    def source_setup(self, folder):
         """
         Source a shell script.
 
@@ -204,46 +261,19 @@ def set_env_var(self, folder):
         os.environ["WALLY"] = str(cvw)
 
         self.cvw = cvw
-        self.sim_dir = cvw.joinpath("sim")
+        self.sim_dir = cvw.joinpath("bin")
         self.base_parent_dir = folder
         self.results_dir = folder.joinpath("results")
 
         self.logger.info(f"Tests are going to be ran from: {self.cvw}")
-    
 
-    def change_time_dur(self, time_duriation=1):
-        
-        # Prepare the command to execute the Makefile
-        regression_path = self.sim_dir.joinpath("regression-wally")
-        self.logger.info(f"Regression file path: {regression_path}")
-        try:
-            os.chdir(self.sim_dir)
-        except Exception as e:
-            self.logger.error(f"Error nagivating to the make file path. Error: {e}")
-        file_path = "regression-wally"
-        line_number = 450 # TIMEOUT_DUR = 1 day at this line in regression-wally 
-        new_line = f"        TIMEOUT_DUR = {60*time_duriation}"
-
-        with open(file_path, 'r') as file:
-            lines = file.readlines()
-
-        if line_number < 1 or line_number > len(lines):
-            self.logger.error("Error: Line number out of range.")
-            return False
-
-        lines[line_number - 1] = new_line + '\n'
 
-        with open(file_path, 'w') as file:
-            file.writelines(lines)
-            self.logger.info(f"Timeduration in ./regression-wally has been changed to: {time_duriation*60} seconds")
-            return True
-
-    def execute_makefile(self, target=None):
+    def execute_makefile(self, makefile_path=None, target=None):
         """
         Execute a Makefile with optional target.
 
         Args:
-            makefile_path (str): Path to the Makefile.
+            makefile_path (str): Path to the Makefile within the test repository
             target (str, optional): Target to execute in the Makefile.
 
         Returns:
@@ -251,8 +281,9 @@ def execute_makefile(self, target=None):
             False if the tests didnt pass
         """
         # Prepare the command to execute the Makefile
-        os.chdir(self.sim_dir)
-        
+        makefile_location = self.cvw.joinpath(makefile_path)
+        os.chdir(makefile_location)
+
         output_file = self.log_dir.joinpath(f"make-{target}-output.log")
 
         command = ["make"]
@@ -260,9 +291,9 @@ def execute_makefile(self, target=None):
         # Add target to the command if specified
         if target:
             command.append(target)
-            self.logger.info(f"Command used: {command[0]} {command[1]}")
+            self.logger.info(f"Command used in directory {makefile_location}: {command[0]} {command[1]}")
         else:
-            self.logger.info(f"Command used: {command[0]}")
+            self.logger.info(f"Command used in directory {makefile_location}: {command[0]}")
 
         # Execute the command using subprocess and save the output into a file
         with open(output_file, "w") as f:
@@ -282,7 +313,7 @@ def execute_makefile(self, target=None):
             self.logger.error(f"Error making the tests. Target: {target}")
             return False
             
-    def run_tests(self, test_type=None, test_name=None, test_exctention=None):
+    def run_tests(self, test_type=None, test_name=None, test_extension=None):
         """
         Run a script through the terminal and save the output to a file.
 
@@ -298,9 +329,9 @@ def run_tests(self, test_type=None, test_name=None, test_exctention=None):
         output_file = self.log_dir.joinpath(f"{test_name}-output.log")
         os.chdir(self.sim_dir)
 
-        if test_exctention:
-            command = [test_type, test_name, test_exctention]
-            self.logger.info(f"Command used to run tests: {test_type} {test_name} {test_exctention}")
+        if test_extension:
+            command = [test_type, test_name, test_extension]
+            self.logger.info(f"Command used to run tests: {test_type} {test_name} {test_extension}")
         else:
             command = [test_type, test_name]
             self.logger.info(f"Command used to run tests: {test_type} {test_name}")
@@ -317,13 +348,36 @@ def run_tests(self, test_type=None, test_name=None, test_exctention=None):
             self.logger.error("There was an error in running the tests in the run_tests function: {e}")
         # Check if the command executed successfuly
         if result.returncode or result.returncode == 0:
-            self.logger.info(f"Test ran successfuly. Test type: {test_type}, test name: {test_name}, test extention: {test_exctention}")
+            self.logger.info(f"Test ran successfuly. Test type: {test_type}, test name: {test_name}, test extention: {test_extension}")
             return True, output_file
         else:
-            self.logger.error(f"Error making test. Test type: {test_type}, test name: {test_name}, test extention: {test_exctention}")
+            self.logger.error(f"Error making test. Test type: {test_type}, test name: {test_name}, test extention: {test_extension}")
             return False, output_file
 
 
+    def copy_sim_logs(self, sim_log_folders):
+        """
+        Save script outputs from a directory back into the main log directory.
+
+        Args:
+            sim_log_folders (list): Locations to grab logs from. Will name new log folder the directory 
+            the log directory is in
+        Returns:
+            None
+        """
+
+        for sim_log_folder in sim_log_folders:
+            try:
+                log_folder_name = os.path.basename(sim_log_folder)
+                self.logger.info(f"{log_folder_name}")
+                sim_folder_name = os.path.basename(os.path.dirname(sim_log_folder))
+                new_log_folder = self.log_dir / sim_folder_name
+                self.logger.info(f"Copying {sim_log_folder} to {new_log_folder}")
+                shutil.copytree(sim_log_folder, new_log_folder)
+            except Exception as e:
+                self.logger.error(f"There was an error copying simulation logs from {sim_log_folder} to {new_log_folder}: {e}")
+
+
     def clean_format_output(self, input_file, output_file=None):
         """
         Clean and format the output from tests.
@@ -339,13 +393,13 @@ def clean_format_output(self, input_file, output_file=None):
 
         # Open up the file with only read permissions
         with open(input_file, 'r') as input_file:
-            unlceaned_output = input_file.read()
+            uncleaned_output = input_file.read()
 
         # use something like this function to detect pass and fail
         passed_configs = []
         failed_configs = []
 
-        lines = unlceaned_output.split('\n')
+        lines = uncleaned_output.split('\n')
         index = 0
 
         while index < len(lines):
@@ -547,9 +601,11 @@ def convert_to_html(self, markdown_file="results.md", html_file="results.html"):
         
         self.logger.info("Converting markdown file to html file.")
  
-    def send_email(self, sender_email=None, receiver_emails=None, subject="Nightly Regression Test"):
+    def send_email(self, receiver_emails=None, subject="Nightly Regression Test"):
         """
-        Send email with HTML content.
+        Send email with HTML content. 
+        
+        !!! Requires mutt to be set up to send emails !!!
 
         Args:
             self: The instance of the class.
@@ -580,7 +636,6 @@ def send_email(self, sender_email=None, receiver_emails=None, subject="Nightly R
                     '/usr/bin/mutt',
                     '-s', subject,
                     '-e', 'set content_type=text/html',
-                    '-e', 'my_hdr From: James Stine <james.stine@okstate.edu>',
                     '--', receiver_email
                 ]
                 try:
@@ -588,10 +643,10 @@ def send_email(self, sender_email=None, receiver_emails=None, subject="Nightly R
                     process = subprocess.Popen(command, stdin=subprocess.PIPE)
                     # Write the email body to the subprocess
                     process.communicate(body.encode('utf-8'))
-                    self.logger.info("Sent email")
-                except expression as identifier:
+                    self.logger.info(f"Sent email to {receiver_email}")
+                except Exception as identifier:
                     self.logger.error(f"Error sending email with error: {identifier}")
-        except expression as identifier:
+        except Exception as identifier:
             self.logger.error(f"Error sending email with error: {identifier}")
 
 
@@ -605,25 +660,29 @@ def main():
 
     parser.add_argument('--path',default = "nightly", help='specify the path for where the nightly repositories will be cloned ex: "nightly-runs')
     parser.add_argument('--repository',default = "https://github.com/openhwgroup/cvw", help='specify which github repository you want to clone')
-    parser.add_argument('--target', default = "all", help='types of tests you can make are: all, wally-riscv-arch-test')
-    parser.add_argument('--send_email',default = "yes", help='do you want to send emails: "yes" or "y"')
+    parser.add_argument('--target', default = "all", help='types of tests you can make are: all, wally-riscv-arch-test, no')
+    parser.add_argument('--tests', default = "nightly", help='types of tests you can run are: nightly, test, test_lint')
+    parser.add_argument('--send_email',default = "", nargs="+", help='What emails to send test results to. Example: "[email1],[email2],..."')
 
     args = parser.parse_args()
 
-    
-
-    
     #############################################
     #                 SETUP                     #
     #############################################
+
+    receiver_emails = args.send_email
+
     # file paths for where the results and repos will be saved: repos and results can be changed to whatever
     today = datetime.now().strftime("%Y-%m-%d")
+    yesterday_dt = datetime.now() - timedelta(days=1)
+    yesterday = yesterday_dt.strftime("%Y-%m-%d")
     cvw_path = Path.home().joinpath(args.path, today)
     results_path = Path.home().joinpath(args.path, today, "results")
     log_path = Path.home().joinpath(args.path, today, "logs")
     log_file_path = log_path.joinpath("nightly_build.log")
+    previous_cvw_path = Path.home().joinpath(args.path,f"{yesterday}/cvw")
     # creates the object
-    folder_manager = FolderManager() 
+    folder_manager = FolderManager()
 
     # setting the path on where to clone new repositories of cvw
     folder_manager.create_folders([cvw_path, results_path, log_path])
@@ -631,6 +690,17 @@ def main():
     # clone the cvw repo
     folder_manager.clone_repository(cvw_path, args.repository)
 
+    # Define tests that we can run
+    if (args.tests == "nightly"):
+        test_list = [["python", "regression-wally", "--nightly"]]
+    elif (args.tests == "test"):
+        test_list = [["python", "regression-wally", ""]]
+    elif (args.tests == "test_lint"):
+        test_list = [["bash", "lint-wally", "-nightly"]]
+    else:
+        print(f"Error: Invalid test '"+args.test+"' specified")
+        raise SystemExit
+
     #############################################
     #                 LOGGER                    #
     #############################################
@@ -670,46 +740,35 @@ def main():
     
 
     test_runner = TestRunner(logger, log_path) # creates the object
-    test_runner.set_env_var(cvw_path) # ensures that the new WALLY environmental variable is set correctly
-
-
-    #############################################
-    #             TMP SETUP                     #
-    #############################################
-
-    """
-    The goal of this section is to replace the TIMEOUT_DUR for regression tests.
-
-    """
-    if test_runner.change_time_dur(time_duriation=1):
-        pass
-    else:
-        logger.error("Error occured changing the TIMEOUT duration in './regression-wally'")
-
+    test_runner.source_setup(cvw_path) # ensures that the new WALLY environmental variable is set correctly
     #############################################
     #              MAKE TESTS                   #
     #############################################
 
     if args.target != "no":
-        # test_runner.execute_makefile(target = "deriv")
-        test_runner.execute_makefile(target = args.target)
+        test_runner.execute_makefile(target = args.target, makefile_path=test_runner.cvw)
+    if args.target == "all":
+        # Compile Linux for local testing
+        test_runner.set_env_var("RISCV",str(test_runner.cvw))
+        linux_path = test_runner.cvw / "linux"
+        test_runner.execute_makefile(target = "all_nosudo", makefile_path=linux_path)
+        test_runner.execute_makefile(target = "dumptvs_nosudo", makefile_path=linux_path)
 
     #############################################
     #               RUN TESTS                   #
     #############################################
 
 
-    test_list = [["python", "regression-wally", "-nightly"], ["bash", "lint-wally", "-nightly"], ["bash", "coverage", "--search"]]
-    output_log_list = [] # a list where the output markdown file lcoations will be saved to
+    output_log_list = [] # a list where the output markdown file locations will be saved to
     total_number_failures = 0  # an integer where the total number failures from all of the tests will be collected
     total_number_success = 0    # an integer where the total number of sucess will be collected
 
     total_failures = []
     total_success = []
 
-    for test_type, test_name, test_exctention in test_list:
+    for test_type, test_name, test_extension in test_list:
         
-        check, output_location = test_runner.run_tests(test_type=test_type, test_name=test_name, test_exctention=test_exctention)
+        check, output_location = test_runner.run_tests(test_type=test_type, test_name=test_name, test_extension=test_extension)
         try:
             if check: # this checks if the test actually ran successfuly
                 output_log_list.append(output_location)
@@ -736,10 +795,8 @@ def main():
     logger.info(f"The total sucesses for all tests ran are: {total_number_success}")
     logger.info(f"The total failures for all tests ran are: {total_number_failures}")
 
-
-
-
-        
+    # Copy actual test logs from sim/questa, sim/verilator
+    test_runner.copy_sim_logs([test_runner.cvw / "sim/questa/logs", test_runner.cvw / "sim/verilator/logs"])
 
     #############################################
     #               FORMAT TESTS                #
@@ -757,20 +814,33 @@ def main():
     test_runner.convert_to_html()
 
 
-
     #############################################
     #                SEND EMAIL                 #
     #############################################
 
-    sender_email = 'james.stine@okstate.edu'
+    if receiver_emails:
+        test_runner.send_email(receiver_emails=receiver_emails)
 
-    receiver_emails = ['thomas.kidd@okstate.edu', 'james.stine@okstate.edu', 'harris@g.hmc.edu', 'rose.thompson10@okstate.edu', 'sarah.harris@unlv.edu', 'nlucio@hmc.edu']
-    testing_emails = ['thomas.kidd@okstate.edu']
-    
-    if (args.send_email == "yes" or args.send_email == "y"):
-        test_runner.send_email(sender_email=sender_email, receiver_emails=receiver_emails)
-    if (args.send_email == "test"):
-        test_runner.send_email(sender_email=sender_email, receiver_emails=testing_emails)
+    #############################################
+    #   DELETE REPOSITORY OF PREVIOUS NIGHTLYS  #
+    #############################################
+    threshold = time.time() - 86400*1
+
+    for log_dir in os.listdir(args.path):
+        try:
+            cvw_dir = os.path.join(args.path,log_dir,"cvw")
+            cvw_mtime = os.stat(cvw_dir).st_mtime
+            if cvw_mtime < threshold:
+                    logger.info(f"Found {cvw_dir} older than 1 day, removing")
+                    shutil.rmtree(cvw_dir)
+        except Exception as e:
+            if os.path.exists(cvw_dir):
+                logger.info(f"ERROR: Failed to remove previous nightly run repo with error {e}")
+
+    #############################################
+    #      DELETE STALE LOGS AFTER TESTING      #
+    #############################################
+    folder_manager.remove_stale_folders(folder=args.path, days_old=30)
 
 if __name__ == "__main__":
     main()
diff --git a/bin/openocd_tcl_wrapper.py b/bin/openocd_tcl_wrapper.py
new file mode 100644
index 000000000..cf5630ae8
--- /dev/null
+++ b/bin/openocd_tcl_wrapper.py
@@ -0,0 +1,541 @@
+#########################################################################################
+# openocd_tcl_wrapper.py
+#
+# Written: matthew.n.otto@okstate.edu
+# Created: 8 June 2024
+#
+# Purpose: Python wrapper library used to send debug commands to OpenOCD
+#
+# A component of the CORE-V-WALLY configurable RISC-V project.
+# https://github.com/openhwgroup/cvw
+#
+# Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+#
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+#
+# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+# except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+# may obtain a copy of the License at
+#
+# https://solderpad.org/licenses/SHL-2.1/
+#
+# Unless required by applicable law or agreed to in writing, any work distributed under the 
+# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+# either express or implied. See the License for the specific language governing permissions 
+# and limitations under the License.
+#########################################################################################
+
+import math
+import socket
+import time
+
+ENDMSG = b'\x1a'
+
+class OpenOCD:
+    def __init__(self):
+        self.tcl = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+
+    def __enter__(self):
+        self.tcl.connect(("127.0.0.1", 6666))
+        self.LLEN = 64 #TODO: find this
+        return self
+
+    def __exit__(self, type, value, traceback):
+        try:
+            self.send("exit")
+        finally:
+            self.tcl.close()
+
+    def capture(self, cmd):
+        return self.send(f"capture \"{cmd}\"")
+
+    def send(self, cmd):
+        data = cmd.encode("ascii") + ENDMSG
+        self.tcl.send(data)
+        return self.receive()
+
+    def receive(self):
+        data = bytes()
+        while True:
+            byte = self.tcl.recv(1)
+            if byte == ENDMSG:
+                break
+            else:
+                data += byte
+        data = data.decode("ascii").rstrip()
+        return data
+
+    def trst(self):
+        self.send("pathmove RESET IDLE")
+
+    def write_dtmcs(self, dtmhardreset=False, dmireset=False):
+        """Send reset commands to DTMCS. Used to clear sticky DMI OP error status"""
+        data = 0
+        data |= dtmhardreset << 17
+        data |= dmireset << 16
+        if not data:
+            print("Warning: not writing DTMCS (dtmhardreset and dmireset are both false)")
+            return
+        tapname = "cvw.cpu"
+        self.send(f"irscan {tapname} 0x10")  # dtmcs instruction
+        self.send(f"drscan {tapname} 32 {hex(data)}")
+        op = self.capture(f"drscan {tapname} 32 0x0")
+        if (int(op) >> 10) & 0x3:
+            raise Exception("Error: failed to reset DTMCS (nonzero dmistat)")
+
+    def write_dmi(self, address, data):
+        cmd = f"riscv dmi_write {address} {data}"
+        rsp = self.capture(cmd)
+        if "Failed" in rsp:
+            raise Exception(rsp)
+
+    def read_dmi(self, address):
+        cmd = f"riscv dmi_read {address}"
+        return self.capture(cmd)
+
+    def activate_dm(self):
+        self.write_dmi("0x10", "0x1")
+        dmstat = int(self.read_dmi("0x10"), 16)
+        if not dmstat & 0x1:
+            raise Exception("Error: failed to activate debug module")
+
+    def reset_dm(self):
+        self.write_dmi("0x10", "0x0")
+        dmstat = int(self.read_dmi("0x10"), 16)
+        if dmstat & 0x1:
+            raise Exception("Error: failed to deactivate debug module")
+        self.activate_dm()
+
+    def reset_hart(self):
+        self.write_dmi("0x10", "0x3")
+        self.write_dmi("0x10", "0x1")
+        dmstat = int(self.read_dmi("0x11"), 16)  # check HaveReset
+        if not ((dmstat >> 18) & 0x3):
+            raise Exception("Error: Hart failed to reset")
+        self.write_dmi("0x10", "0x10000001")  # ack HaveReset
+
+    def write_progbuf(self, data):
+        #TODO query progbuf size and error if len(data) is greater
+        baseaddr = 0x20
+        for idx, instr in enumerate(data):
+            z = hex(baseaddr+idx) #debug
+            self.write_dmi(hex(baseaddr+idx), instr)
+
+    def exec_progbuf(self):
+        self.write_dmi("0x17", hex(0x1 << 18))
+
+    def set_haltonreset(self):
+        self.write_dmi("0x10", "0x9")
+
+    def clear_haltonreset(self):
+        self.write_dmi("0x10", "0x5")
+
+    def halt(self):
+        self.write_dmi("0x10", "0x80000001")
+        dmstat = int(self.read_dmi("0x11"), 16)  # Check halted bit
+        if not ((dmstat >> 8) & 0x3):
+            raise Exception("Error: Hart failed to halt")
+
+    def resume(self):
+        self.write_dmi("0x10", "0x40000001")  # Send resume command
+        dmstat = int(self.read_dmi("0x11"), 16)  # Check resumeack bit
+        if not ((dmstat >> 16) & 0x3):
+            raise Exception("Error: Hart failed to resume")
+
+    def step(self):
+        # Set step bit if it isn't already set
+        dcsr = int(self.read_data("DCSR"), 16)
+        if not (dcsr >> 2) & 0x1:
+            dcsr |= 0x4
+            self.write_data("DCSR", hex(dcsr))
+        # Resume once
+        self.write_dmi("0x10", "0x40000001")
+        # Unset step bit
+        dcsr &= ~0x4
+        self.write_data("DCSR", hex(dcsr))
+
+    def access_register(self, write, regno, addr_size=None):
+        data = 1 << 17  # transfer bit always set
+        if not addr_size:
+            addr_size = self.LLEN
+        elif addr_size not in (32, 64, 128):
+            raise Exception("must provide valid register access size (32, 64, 128). See: 3.7.1.1 aarsize")
+        data += int(math.log2(addr_size // 8)) << 20
+        data += write << 16
+        data += regno
+        self.write_dmi("0x17", hex(data))  
+
+    def write_data(self, register, data):
+        """Write data to specified register"""
+        # Write data to 32 bit message registers
+        data = int(data, 16)
+        self.write_dmi("0x4", hex(data & 0xffffffff))
+        if self.LLEN >= 64:
+            self.write_dmi("0x5", hex((data >> 32) & 0xffffffff))
+        if self.LLEN == 128:
+            self.write_dmi("0x6", hex((data >> 64) & 0xffffffff))
+            self.write_dmi("0x7", hex((data >> 96) & 0xffffffff))
+        # Translate register alias to DM regno
+        regno = self.translate_regno(register)
+        # Transfer data from msg registers to target register
+        self.access_register(write=True, regno=regno)
+        # Check that operations completed without error
+        if acerr := self.check_abstrcmderr():
+            raise Exception(acerr)
+
+    def read_data(self, register):
+        """Read data from specified register"""
+        # Translate register alias to DM regno
+        regno = self.translate_regno(register)
+        # Transfer data from target register to msg registers
+        self.access_register(write=False, regno=regno)
+        # Read data from 32 bit message registers
+        data = ""
+        data = self.read_dmi("0x4").replace("0x", "").zfill(8)
+        if self.LLEN >= 64:
+            data = self.read_dmi("0x5").replace("0x", "").zfill(8) + data
+        if self.LLEN == 128:
+            data = self.read_dmi("0x6").replace("0x", "").zfill(8) + data
+            data = self.read_dmi("0x7").replace("0x", "").zfill(8) + data
+        # Check that operations completed without error
+        if acerr := self.check_abstrcmderr():
+            raise Exception(acerr)
+        return f"0x{data}"
+
+    def translate_regno(self, register):
+        if register not in self.register_translations:
+            register = self.abi_translations[register]
+        return int(self.register_translations[register], 16)
+
+    def check_abstrcmderr(self):
+        """These errors must be cleared using clear_abstrcmd_err() before another OP can be executed"""
+        abstractcs = int(self.read_dmi("0x16"), 16)
+        # CmdErr is only valid if Busy is 0
+        while True:
+            if not bool((abstractcs & 0x1000) >> 12):  # if not Busy
+                break
+            time.sleep(0.05)
+            abstractcs = int(self.read_dmi("0x16"), 16)
+        return self.cmderr_translations[(abstractcs & 0x700) >> 8]
+
+    def clear_abstrcmd_err(self):
+        self.write_dmi("0x16", "0x700")
+        if self.check_abstrcmderr():
+            raise Exception("Error: failed to clear AbstrCmdErr")
+
+    # 6.1.4 dtmcs errinfo translation table
+    errinfo_translations = {
+        0 : "not implemented",
+        1 : "dmi error",
+        2 : "communication error",
+        3 : "device error",
+        4 : "unknown",
+    }
+
+    # 6.1.5 DMI op translation table
+    op_translations = {
+        0 : "success",
+        1 : "reserved",
+        2 : "failed",
+        3 : "busy",
+    }
+
+    # 3.14.6 Abstract command CmdErr value translation table
+    cmderr_translations = {
+        0 : None,
+        1 : "busy",
+        2 : "not supported",
+        3 : "exception",
+        4 : "halt/resume",
+        5 : "bus",
+        6 : "reserved",
+        7 : "other",
+    }
+
+    # Register alias to regno translation table
+    register_translations = {
+        "FFLAGS"         : "0x0001",
+        "FRM"            : "0x0002",
+        "FCSR"           : "0x0003",
+        "MSTATUS"        : "0x0300",
+        "MISA"           : "0x0301",
+        "MEDELEG"        : "0x0302",
+        "MIDELEG"        : "0x0303",
+        "MIE"            : "0x0304",
+        "MTVEC"          : "0x0305",
+        "MCOUNTEREN"     : "0x0306",
+        "MENVCFG"        : "0x030A",
+        "MSTATUSH"       : "0x0310",
+        "MENVCFGH"       : "0x031A",
+        "MCOUNTINHIBIT"  : "0x0320",
+        "MSCRATCH"       : "0x0340",
+        "MEPC"           : "0x0341",
+        "MCAUSE"         : "0x0342",
+        "MTVAL"          : "0x0343",
+        "MIP"            : "0x0344",
+        "PMPCFG0"        : "0x03A0",
+        "PMPCFG1"        : "0x03A1",
+        "PMPCFG2"        : "0x03A2",
+        "PMPCFG3"        : "0x03A3",
+        "PMPCFG4"        : "0x03A4",
+        "PMPCFG5"        : "0x03A5",
+        "PMPCFG6"        : "0x03A6",
+        "PMPCFG7"        : "0x03A7",
+        "PMPCFG8"        : "0x03A8",
+        "PMPCFG9"        : "0x03A9",
+        "PMPCFGA"        : "0x03AA",
+        "PMPCFGB"        : "0x03AB",
+        "PMPCFGC"        : "0x03AC",
+        "PMPCFGD"        : "0x03AD",
+        "PMPCFGE"        : "0x03AE",
+        "PMPCFGF"        : "0x03AF",
+        "PMPADDR0"       : "0x03B0",
+        "PMPADDR1"       : "0x03B1",
+        "PMPADDR2"       : "0x03B2",
+        "PMPADDR3"       : "0x03B3",
+        "PMPADDR4"       : "0x03B4",
+        "PMPADDR5"       : "0x03B5",
+        "PMPADDR6"       : "0x03B6",
+        "PMPADDR7"       : "0x03B7",
+        "PMPADDR8"       : "0x03B8",
+        "PMPADDR9"       : "0x03B9",
+        "PMPADDRA"       : "0x03BA",
+        "PMPADDRB"       : "0x03BB",
+        "PMPADDRC"       : "0x03BC",
+        "PMPADDRD"       : "0x03BD",
+        "PMPADDRE"       : "0x03BE",
+        "PMPADDRF"       : "0x03BF",
+        "PMPADDR10"      : "0x03C0",
+        "PMPADDR11"      : "0x03C1",
+        "PMPADDR12"      : "0x03C2",
+        "PMPADDR13"      : "0x03C3",
+        "PMPADDR14"      : "0x03C4",
+        "PMPADDR15"      : "0x03C5",
+        "PMPADDR16"      : "0x03C6",
+        "PMPADDR17"      : "0x03C7",
+        "PMPADDR18"      : "0x03C8",
+        "PMPADDR19"      : "0x03C9",
+        "PMPADDR1A"      : "0x03CA",
+        "PMPADDR1B"      : "0x03CB",
+        "PMPADDR1C"      : "0x03CC",
+        "PMPADDR1D"      : "0x03CD",
+        "PMPADDR1E"      : "0x03CE",
+        "PMPADDR1F"      : "0x03CF",
+        "PMPADDR20"      : "0x03D0",
+        "PMPADDR21"      : "0x03D1",
+        "PMPADDR22"      : "0x03D2",
+        "PMPADDR23"      : "0x03D3",
+        "PMPADDR24"      : "0x03D4",
+        "PMPADDR25"      : "0x03D5",
+        "PMPADDR26"      : "0x03D6",
+        "PMPADDR27"      : "0x03D7",
+        "PMPADDR28"      : "0x03D8",
+        "PMPADDR29"      : "0x03D9",
+        "PMPADDR2A"      : "0x03DA",
+        "PMPADDR2B"      : "0x03DB",
+        "PMPADDR2C"      : "0x03DC",
+        "PMPADDR2D"      : "0x03DD",
+        "PMPADDR2E"      : "0x03DE",
+        "PMPADDR2F"      : "0x03DF",
+        "PMPADDR30"      : "0x03E0",
+        "PMPADDR31"      : "0x03E1",
+        "PMPADDR32"      : "0x03E2",
+        "PMPADDR33"      : "0x03E3",
+        "PMPADDR34"      : "0x03E4",
+        "PMPADDR35"      : "0x03E5",
+        "PMPADDR36"      : "0x03E6",
+        "PMPADDR37"      : "0x03E7",
+        "PMPADDR38"      : "0x03E8",
+        "PMPADDR39"      : "0x03E9",
+        "PMPADDR3A"      : "0x03EA",
+        "PMPADDR3B"      : "0x03EB",
+        "PMPADDR3C"      : "0x03EC",
+        "PMPADDR3D"      : "0x03ED",
+        "PMPADDR3E"      : "0x03EE",
+        "PMPADDR3F"      : "0x03EF",
+        "TSELECT"        : "0x07A0",
+        "TDATA1"         : "0x07A1",
+        "TDATA2"         : "0x07A2",
+        "TDATA3"         : "0x07A3",
+        "DCSR"           : "0x07B0",
+        "DPC"            : "0x07B1",
+        "MVENDORID"      : "0x0F11",
+        "MARCHID"        : "0x0F12",
+        "MIMPID"         : "0x0F13",
+        "MHARTID"        : "0x0F14",
+        "MCONFIGPTR"     : "0x0F15",
+        "SIP"            : "0x0144",
+        "MIP"            : "0x0344",
+        "MHPMEVENTBASE"    : "0x0320",
+        "MHPMCOUNTERBASE"  : "0x0B00",
+        "MHPMCOUNTERHBASE" : "0x0B80",
+        "HPMCOUNTERBASE"   : "0x0C00",
+        "TIME"             : "0x0C01",
+        "HPMCOUNTERHBASE"  : "0x0C80",
+        "TIMEH"            : "0x0C81",
+        "SSTATUS"        : "0x0100",
+        "SIE"            : "0x0104",
+        "STVEC"          : "0x0105",
+        "SCOUNTEREN"     : "0x0106",
+        "SENVCFG"        : "0x010A",
+        "SSCRATCH"       : "0x0140",
+        "SEPC"           : "0x0141",
+        "SCAUSE"         : "0x0142",
+        "STVAL"          : "0x0143",
+        "SIP"            : "0x0144",
+        "STIMECMP"       : "0x014D",
+        "STIMECMPH"      : "0x015D",
+        "SATP"           : "0x0180",
+        "SIE"            : "0x0104",
+        "SIP"            : "0x0144",
+        "MIE"            : "0x0304",
+        "MIP"            : "0x0344",
+        "TRAPM"       : "0xC000",
+        "PCM"         : "0xC001",
+        "INSTRM"      : "0xC002",
+        "MEMRWM"      : "0xC003",
+        "INSTRVALIDM" : "0xC004",
+        "WRITEDATAM"  : "0xC005",
+        "IEUADRM"     : "0xC006",
+        "READDATAM"   : "0xC007",
+        "x0"          : "0x1000",
+        "x1"          : "0x1001",
+        "x2"          : "0x1002",
+        "x3"          : "0x1003",
+        "x4"          : "0x1004",
+        "x5"          : "0x1005",
+        "x6"          : "0x1006",
+        "x7"          : "0x1007",
+        "x8"          : "0x1008",
+        "x9"          : "0x1009",
+        "x10"         : "0x100A",
+        "x11"         : "0x100B",
+        "x12"         : "0x100C",
+        "x13"         : "0x100D",
+        "x14"         : "0x100E",
+        "x15"         : "0x100F",
+        "x16"         : "0x1010",
+        "x17"         : "0x1011",
+        "x18"         : "0x1012",
+        "x19"         : "0x1013",
+        "x20"         : "0x1014",
+        "x21"         : "0x1015",
+        "x22"         : "0x1016",
+        "x23"         : "0x1017",
+        "x24"         : "0x1018",
+        "x25"         : "0x1019",
+        "x26"         : "0x101A",
+        "x27"         : "0x101B",
+        "x28"         : "0x101C",
+        "x29"         : "0x101D",
+        "x30"         : "0x101E",
+        "x31"         : "0x101F",
+        "f0"          : "0x1020",
+        "f1"          : "0x1021",
+        "f2"          : "0x1022",
+        "f3"          : "0x1023",
+        "f4"          : "0x1024",
+        "f5"          : "0x1025",
+        "f6"          : "0x1026",
+        "f7"          : "0x1027",
+        "f8"          : "0x1028",
+        "f9"          : "0x1029",
+        "f10"         : "0x102A",
+        "f11"         : "0x102B",
+        "f12"         : "0x102C",
+        "f13"         : "0x102D",
+        "f14"         : "0x102E",
+        "f15"         : "0x102F",
+        "f16"         : "0x1030",
+        "f17"         : "0x1031",
+        "f18"         : "0x1032",
+        "f19"         : "0x1033",
+        "f20"         : "0x1034",
+        "f21"         : "0x1035",
+        "f22"         : "0x1036",
+        "f23"         : "0x1037",
+        "f24"         : "0x1038",
+        "f25"         : "0x1039",
+        "f26"         : "0x103A",
+        "f27"         : "0x103B",
+        "f28"         : "0x103C",
+        "f29"         : "0x103D",
+        "f30"         : "0x103E",
+        "f31"         : "0x103F",
+    }
+
+    abi_translations = {
+        "x0"  : "zero",
+        "x1"  : "ra",
+        "x2"  : "sp",
+        "x3"  : "gp",
+        "x4"  : "tp",
+        "x5"  : "t0",
+        "x6"  : "t1",
+        "x7"  : "t2",
+        "x8"  : "s0/fp",
+        "x9"  : "s1",
+        "x10" : "a0",
+        "x11" : "a1",
+        "x12" : "a2",
+        "x13" : "a3",
+        "x14" : "a4",
+        "x15" : "a5",
+        "x16" : "a6",
+        "x17" : "a7",
+        "x18" : "s2",
+        "x19" : "s3",
+        "x20" : "s4",
+        "x21" : "s5",
+        "x22" : "s6",
+        "x23" : "s7",
+        "x24" : "s8",
+        "x25" : "s9",
+        "x26" : "s10",
+        "x27" : "s11",
+        "x28" : "t3",
+        "x29" : "t4",
+        "x30" : "t5",
+        "x31" : "t6",
+        "f0"  : "ft0",
+        "f1"  : "ft1",
+        "f2"  : "ft2",
+        "f3"  : "ft3",
+        "f4"  : "ft4",
+        "f5"  : "ft5",
+        "f6"  : "ft6",
+        "f7"  : "ft7",
+        "f8"  : "fs0",
+        "f9"  : "fs1",
+        "f10" : "fa0",
+        "f11" : "fa1",
+        "f12" : "fa2",
+        "f13" : "fa3",
+        "f14" : "fa4",
+        "f15" : "fa5",
+        "f16" : "fa6",
+        "f17" : "fa7",
+        "f18" : "fs2",
+        "f19" : "fs3",
+        "f20" : "fs4",
+        "f21" : "fs5",
+        "f22" : "fs6",
+        "f23" : "fs7",
+        "f24" : "fs8",
+        "f25" : "fs9",
+        "f26" : "fs10",
+        "f27" : "fs11",
+        "f28" : "ft8",
+        "f29" : "ft9",
+        "f30" : "ft10",
+        "f31" : "ft11",
+    }
+    abi_translations |= dict(map(reversed, abi_translations.items())) # two way translations
+
+    nonstandard_register_lengths = {
+        "TRAPM"       : 1,
+        "INSTRM"      : 32,
+        "MEMRWM"      : 2,
+        "INSTRVALIDM" : 1,
+        "READDATAM"   : 64
+    }
diff --git a/bin/regression-wally b/bin/regression-wally
index c86006dae..61aead096 100755
--- a/bin/regression-wally
+++ b/bin/regression-wally
@@ -12,7 +12,6 @@
 ##################################
 import sys,os,shutil
 import multiprocessing
-#import os
 from collections import namedtuple
 from multiprocessing import Pool, TimeoutError
 
@@ -24,26 +23,37 @@ from multiprocessing import Pool, TimeoutError
 # The element consists of the configuration name, a list of test suites to run, 
 # optionally a string to pass to the simulator, and optionally a nonstandard grep string to check for success
 
-INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
 tests = [
         ["rv32e", ["arch32e"]],
         ["rv32i", ["arch32i"]],
         ["rv32imc", ["arch32i", "arch32c", "arch32m", "wally32periph"]],
         ["rv32gc", ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", 
-                    "arch32i", "arch32priv", "arch32c",  "arch32m", "arch32a", "arch32zifencei", "arch32zicond", 
+                    "arch32i", "arch32priv", "arch32c",  "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond", 
                     "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", 
-                    "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", 
-                    "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], # "arch32zcb", "arch32zfad",
-        ["rv64i", ["arch64i"]],
-        ["buildroot", ["buildroot"], [f"+INSTR_LIMIT={INSTR_LIMIT}"], str(INSTR_LIMIT)+" instructions"]
+                    "arch32zfh_divsqrt", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "wally32priv", "wally32periph", "arch32zcb",
+                    "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], 
+         ["rv64i", ["arch64i"]]
         ]
 
+# Separate test for short buildroot run through OpenSBI UART output
+tests_buildrootshort = [
+                    ["buildroot", ["buildroot"], [f"+INSTR_LIMIT=1400000"], # Instruction limit gets to first OpenSBI UART output  
+                        "OpenSBI v", "buildroot_uart.out"]
+    ]
+
+# Separate test for full buildroot run
+tests_buildrootboot = [
+                    ["buildroot", ["buildroot"], [f"+INSTR_LIMIT=600000000"], # boot entire buildroot Linux to login prompt
+                        "WallyHostname login: ", "buildroot_uart.out"]
+    ]
+
+
 # Separate out floating-point tests for RV64 to speed up coverage
 tests64gc_nofp = [
-        ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m",
-                    "arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv", 
+        ["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m", "arch64zcb",
+                    "arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc", "wally64periph", "wally64priv", 
                     "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
-                    "arch64zba",  "arch64zbb",  "arch64zbc", "arch64zbs"]] # add when working: "arch64zcb", "arch64zicboz"
+                    "arch64zba",  "arch64zbb",  "arch64zbc", "arch64zbs"]] # add when working:  "arch64zicboz"
     ]
 
 tests64gc_fp = [
@@ -83,6 +93,35 @@ derivconfigtests = [
         ["nodcache_rv64gc", ["ahb64"]],
         ["nocache_rv64gc", ["ahb64"]],
 
+# Atomic variatnts
+        ["zaamo_rv64gc", ["arch64i", "arch64a_amo"]],
+        ["zalrsc_rv64gc", ["arch64i", "wally64a_lrsc"]],
+        ["zaamo_rv32gc", ["arch32i", "arch32a_amo"]],
+        ["zalrsc_rv32gc", ["arch32i", "wally32a_lrsc"]],
+
+# Bit manipulation and crypto variants
+        ["zba_rv32gc", ["arch32i", "arch32zba"]],
+        ["zbb_rv32gc", ["arch32i", "arch32zbb"]],
+        ["zbc_rv32gc", ["arch32i", "arch32zbc"]],
+        ["zbs_rv32gc", ["arch32i", "arch32zbs"]],
+        ["zbkb_rv32gc", ["arch32i", "arch32zbkb"]],
+        ["zbkc_rv32gc", ["arch32i", "arch32zbkc"]],
+        ["zbkx_rv32gc", ["arch32i", "arch32zbkx"]],
+        ["zkne_rv32gc", ["arch32i", "arch32zkne"]],
+        ["zknd_rv32gc", ["arch32i", "arch32zknd"]],
+        ["zknh_rv32gc", ["arch32i", "arch32zknh"]],
+
+        ["zba_rv64gc", ["arch64i", "arch64zba"]],
+        ["zbb_rv64gc", ["arch64i", "arch64zbb"]],
+        ["zbc_rv64gc", ["arch64i", "arch64zbc"]],
+        ["zbs_rv64gc", ["arch64i", "arch64zbs"]],
+        ["zbkb_rv64gc", ["arch64i", "arch64zbkb"]],
+        ["zbkc_rv64gc", ["arch64i", "arch64zbkc"]],
+        ["zbkx_rv64gc", ["arch64i", "arch64zbkx"]],
+        ["zkne_rv64gc", ["arch64i", "arch64zkne"]],
+        ["zknd_rv64gc", ["arch64i", "arch64zknd"]],
+        ["zknh_rv64gc", ["arch64i", "arch64zknh"]],
+
         ### add misaligned tests
 
         # fp/int divider permutations
@@ -109,22 +148,24 @@ derivconfigtests = [
         ["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
         ["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
         ["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
-        ["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
+        ["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], 
 
         # fpu permutations
-        ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],
-        ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]],
-        ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
-        ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32i"]],
-        ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32i"]],
-        ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]],
-        ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], 
-        ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
-        ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64i"]],
-        ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64i", "wally64q"]],
+        ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfaf"]],
+        ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32zfaf"]],
+        ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32zfaf", "arch32zfad"]],
+        ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32i", "arch32zfaf", "arch32zfad"]],
+        ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32i", "arch32zfaf", "arch32zfad"]],
+        ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfaf"]],
+        ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf"]], 
+        ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf", "arch64zfad"]],
+        ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64i", "arch64zfaf", "arch64zfad"]],
+        ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64i", "wally64q", "arch64zfaf", "arch64zfad"]],
     ]
 
 bpredtests = [
+    
+        ["nobpred_rv32gc", ["rv32i"]],
         ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
         ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
         ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],        
@@ -176,7 +217,7 @@ bpredtests = [
 # Data Types & Functions
 ##################################
 
-TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
+TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfile'])
 # name:     the name of this test configuration (used in printing human-readable
 #           output and picking logfile names)
 # cmd:      the command to run to test (should include the logfile as '{}', and
@@ -184,6 +225,7 @@ TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
 # grepstr:  the string to grep through the log file for. The test succeeds iff
 #           grep finds that string in the logfile (is used by grep, so it may
 #           be any pattern grep accepts, see `man 1 grep` for more info).
+# grepfile:  a string containing the location of the file to be searched for output
 
 class bcolors:
     HEADER = '\033[95m'
@@ -197,6 +239,7 @@ class bcolors:
     UNDERLINE = '\033[4m'
 
 def addTests(tests, sim):
+    sim_logdir = WALLY+ "/sim/" + sim + "/logs/"
     for test in tests:
         config = test[0];
         suites = test[1];
@@ -208,38 +251,45 @@ def addTests(tests, sim):
             gs = test[3]
         else:
             gs = "All tests ran without failures"
-        cmdPrefix="wsim --sim " + sim + " " + config
+        cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config
         for t in suites:
+            sim_log = sim_logdir + config + "_" + t + ".log"
+            if (len(test) >= 5):
+                grepfile = sim_logdir + test[4]
+            else:
+                grepfile = sim_log
             tc = TestCase(
                     name=t,
                     variant=config,
-                    cmd=cmdPrefix + " " + t + args,
-                    grepstr=gs)
+                    cmd=cmdPrefix + " " + t + args + " > " + sim_log,
+                    grepstr=gs,
+                    grepfile = grepfile)
             configs.append(tc)
 
-def search_log_for_text(text, logfile):
+def search_log_for_text(text, grepfile):
     """Search through the given log file for text, returning True if it is found or False if it is not"""
-    grepcmd = "grep -e '%s' '%s' > /dev/null" % (text, logfile)
+    grepwarn = "grep -H Warning: " + grepfile
+    os.system(grepwarn)
+    greperr = "grep -H Error: " + grepfile
+    os.system(greperr)
+    grepcmd = "grep -a -e '%s' '%s' > /dev/null" % (text, grepfile)
 #    print("  search_log_for_text invoking %s" % grepcmd)
     return os.system(grepcmd) == 0
 
 def run_test_case(config):
     """Run the given test case, and return 0 if the test suceeds and 1 if it fails"""
-    logname = WALLY + "/sim/questa/logs/"+config.variant+"_"+config.name+".log"   ### *** fix hardwiring to questa log
-    #cmd = config.cmd + " > " + logname
-    if ("lint-wally" in config.cmd):
-        cmd = config.cmd + " | tee " + logname
-    else:
-        cmd = config.cmd + " > " + logname
+    grepfile = config.grepfile
+    cmd = config.cmd
     os.chdir(regressionDir)
-#    print("  run_test_case invoking %s" % cmd)
+    # print("  run_test_case invoking %s" % cmd)
     os.system(cmd)
-    if search_log_for_text(config.grepstr, logname):
-        print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name))
+    if search_log_for_text(config.grepstr, grepfile):
+#        print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name))
+        print(f"{bcolors.OKGREEN}%s: Success{bcolors.ENDC}" % (config.cmd))
         return 0
     else:
-        print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name))
-        print("  Check %s" % logname)
+        print(f"{bcolors.FAIL}%s: Failures detected in output{bcolors.ENDC}" % (config.cmd))
+        print("  Check %s" % grepfile)
         return 1
 
 ##################################
@@ -252,7 +302,9 @@ regressionDir = WALLY + '/sim'
 os.chdir(regressionDir)
 
 coveragesim = "questa"  # Questa is required for code/functional coverage
+#defaultsim = "vcs"   # Default simulator for all other tests; change to Verilator when flow is ready
 defaultsim = "questa"   # Default simulator for all other tests; change to Verilator when flow is ready
+#defaultsim = "verilator"   # Default simulator for all other tests
 
 coverage = '--coverage' in sys.argv
 fp = '--fp' in sys.argv
@@ -262,9 +314,11 @@ soc = '--soc' in sys.argv
 
 if (nightly):
     nightMode = "--nightly";
-    sims = ["questa", "verilator", "vcs"]
+#    sims = [defaultsim] 
+    sims = ["questa", "vcs"] 
+#    sims = ["questa", "verilator", "vcs"] # *** uncomment to exercise all simulators
 else:
-    nightMode = "";
+    nightMode = ""
     sims = [defaultsim]
 
 if (coverage):  # only run RV64GC tests in coverage mode
@@ -278,9 +332,9 @@ configs = [
     TestCase(
         name="lints",
         variant="all",
-        cmd="lint-wally " + nightMode,
-        grepstr="lints run with no errors or warnings"
-    )
+        cmd="lint-wally " + nightMode + " | tee " + WALLY + "/sim/verilator/logs/all_lints.log",
+        grepstr="lints run with no errors or warnings",
+        grepfile = WALLY + "/sim/verilator/logs/all_lints.log")
     ]
 
 if (coverage):  # only run RV64GC tests on Questa in coverage mode
@@ -292,25 +346,32 @@ else:
         addTests(tests, sim)
         addTests(tests64gc_nofp, sim)
         addTests(tests64gc_fp, sim)
+
     # run derivative configurations in nightly regression
-    if (nightly):
-        addTests(derivconfigtests, defaultsim)
+if (nightly):
+#    addTests(tests_buildrootboot, defaultsim)
+    addTests(tests_buildrootshort, defaultsim)
+    addTests(derivconfigtests, defaultsim)
+else:
+    addTests(tests_buildrootshort, defaultsim)
 
 # testfloat tests
-if (testfloat):
+if (testfloat): # for testfloat alone, just run testfloat tests
     configs = []
-
+if (testfloat or nightly): # for nightly, run testfloat along with othres
     testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"]
     for config in testfloatconfigs:
         tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"]
         if ("f_" in config):
             tests.remove("cvtfp")
         for test in tests:
+            sim_log = WALLY + "/sim/questa/logs/"+config+"_"+test+".log" # TODO: Change hardcoded questa log directory to simulator
             tc = TestCase(
                     name=test,
                     variant=config,
-                    cmd="wsim --tb testbench_fp " + config + " " + test,
-                    grepstr="All Tests completed with          0 errors")
+                    cmd="wsim --tb testbench_fp " + config + " " + test + " > " + sim_log,
+                    grepstr="All Tests completed with          0 errors",
+                    grepfile = sim_log)
             configs.append(tc)
 
 
@@ -349,22 +410,27 @@ if (testfloat):
         if ("f_" in config):
             tests.remove("cvtfp")
         for test in tests:
+            sim_log = WALLY + "/sim/questa/logs/"+config+"_"+test+".log"
             tc = TestCase(
                     name=test,
                     variant=config,
-                    cmd="wsim --tb testbench_fp --sim questa " + config + " " + test,
-                    grepstr="All Tests completed with          0 errors")
+                    cmd="wsim --tb testbench_fp " + config + " " + test + " > " + sim_log,
+                    grepstr="All Tests completed with          0 errors",
+                    grepfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log")
             configs.append(tc)
 
 if (soc):
     configs = []
-    addTests(tests64gc_nofp, defaultsim)
+    addTests([['soc', tests64gc_nofp[0][1]]], defaultsim)
+    addTests([['soc', tests64gc_fp[0][1]]], defaultsim)
+    addTests([['soc', ['custom']]], defaultsim)
 
 
 def main():
     """Run the tests and count the failures"""
     global configs, coverage
     os.chdir(regressionDir)
+    os.system('rm -rf questa/wkdir')
     for d in ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"]:
         try:
             os.mkdir(d)
@@ -374,30 +440,15 @@ def main():
     if '--makeTests' in sys.argv:
         os.chdir(regressionDir)
         os.system('./make-tests.sh | tee ./logs/make-tests.log')
-
-    if '--all' in sys.argv:
-        TIMEOUT_DUR = 30*7200 # seconds
-        #configs.append(getBuildrootTC(boot=True))
-    elif '--buildroot' in sys.argv:
-        TIMEOUT_DUR = 30*7200 # seconds
-        #configs=[getBuildrootTC(boot=True)]
     elif '--coverage' in sys.argv:
-        TIMEOUT_DUR = 20*60 # seconds    
-    #   Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage.
-    #   Also it is slow to run.   
-    #    configs.append(getBuildrootTC(boot=False))
-        os.system('rm -f cov/*.ucdb')
+        TIMEOUT_DUR = 20*60 # seconds
+        os.system('rm -f questa/cov/*.ucdb')
     elif '--nightly' in sys.argv:
         TIMEOUT_DUR = 60*1440 # 1 day
-        #configs.append(getBuildrootTC(boot=False))
     elif '--testfloat' in sys.argv:
-        TIMEOUT_DUR = 60*60 # seconds
-    elif '--soc' in sys.argv:
-        TIMEOUT_DUR = 10*60 # seconds
-        # Don't run buildroot because soc is based on rv64gc
+        TIMEOUT_DUR = 30*60 # seconds
     else:
         TIMEOUT_DUR = 10*60 # seconds
-        #configs.append(getBuildrootTC(boot=False))
 
     # Scale the number of concurrent processes to the number of test cases, but
     # max out at a limited number of concurrent processes to not overwhelm the system
@@ -415,7 +466,7 @@ def main():
 
     # Coverage report
     if coverage:
-       os.system('make coverage')
+       os.system('make QuestaCoverage')
     # Count the number of failures
     if num_fail:
         print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
diff --git a/bin/testcount.pl b/bin/testcount.pl
index 139902dd3..7ac75d676 100755
--- a/bin/testcount.pl
+++ b/bin/testcount.pl
@@ -34,6 +34,10 @@
 do
     dir=$(echo $dir | cut -d':' -f1)
     echo $dir
+    if [ $dir == "src" ]
+    then
+        continue
+    fi
     for fn in `ls $dir/src/*.S`
     do
         result=`grep 'inst_' $fn | tail -n 1`
diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
index 1810747ec..9c38f54d0 100755
--- a/bin/wally-tool-chain-install.sh
+++ b/bin/wally-tool-chain-install.sh
@@ -46,9 +46,10 @@ sudo mkdir -p $RISCV
 # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/)
 sudo apt update -y
 sudo apt upgrade -y
-sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev  gperf libtool patchutils bc mutt
+sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev  gperf libtool patchutils bc mutt ssmtp cmake gfortran usbutils
 # Other python libraries used through the book.
-sudo pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown 
+sudo -H pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml 
+sudo -H pip3 install riscv_isac # to generate new tests, such as quads with fp_dataset.py
 
 # needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3.
 if ! command -v python &> /dev/null
@@ -68,7 +69,7 @@ cd $RISCV
 git clone https://github.com/riscv/riscv-gnu-toolchain
 cd riscv-gnu-toolchain
 ./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
-make -j ${NUM_THREADS}
+make -j 8
 
 # elf2hex (https://github.com/sifive/elf2hex)
 #The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation. 
@@ -92,7 +93,7 @@ cd $RISCV
 git clone --recurse-submodules https://github.com/qemu/qemu
 cd qemu
 ./configure --target-list=riscv64-softmmu --prefix=$RISCV 
-make -j ${NUM_THREADS}
+make -j 8
 make install
 
 # Spike (https://github.com/riscv-software-src/riscv-isa-sim)
@@ -103,7 +104,7 @@ git clone https://github.com/riscv-software-src/riscv-isa-sim
 mkdir -p riscv-isa-sim/build
 cd riscv-isa-sim/build
 ../configure --prefix=$RISCV 
-make -j ${NUM_THREADS}
+make -j 8
 make install 
 
 
@@ -111,7 +112,6 @@ make install
 # Verilator needs to be built from scratch to get the latest version
 # apt-get install verilator installs version 4.028 as of 6/8/23
 sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g 
-sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g 
 cd $RISCV
 git clone https://github.com/verilator/verilator   # Only first time
 # unsetenv VERILATOR_ROOT  # For csh; ignore error if on bash
@@ -121,7 +121,7 @@ git pull         # Make sure git repository is up-to-date
 git checkout master      
 autoconf         # Create ./configure script
 ./configure      # Configure and create Makefile
-make -j ${NUM_THREADS}  # Build Verilator itself (if error, try just 'make')
+make -j 8  # Build Verilator itself (if error, try just 'make')
 sudo make install
 
 # Sail (https://github.com/riscv/sail-riscv)
@@ -158,7 +158,7 @@ sudo make install
 #cd z3
 #python scripts/mk_make.py
 #cd build
-#make  -j ${NUM_THREADS}
+#make  -j 8
 #make install
 #cd ../..
 #pip3 install chardet==3.0.4
@@ -176,14 +176,15 @@ git clone https://github.com/riscv/sail-riscv.git
 cd sail-riscv
 # For now, use checkout that is stable for Wally
 #git checkout 72b2516d10d472ac77482fd959a9401ce3487f60  # not new enough for Zicboz?
-make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64
-ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32
+export OPAMCLI=2.0  # Sail is not compatible with opam 2.1 as of 4/16/24
+ARCH=RV64 make -j 8 c_emulator/riscv_sim_RV64
+ARCH=RV32 make -j 8 c_emulator/riscv_sim_RV32
 sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
 sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
 
 # riscof
-sudo pip3 install -U testresources riscv_config
-sudo pip3 install git+https://github.com/riscv/riscof.git
+sudo -H pip3 install -U testresources riscv_config
+sudo -H pip3 install git+https://github.com/riscv/riscof.git
 
 # Download OSU Skywater 130 cell library
 sudo mkdir -p $RISCV/cad/lib
diff --git a/bin/wsim b/bin/wsim
index 7e386e4a3..9884992e4 100755
--- a/bin/wsim
+++ b/bin/wsim
@@ -14,6 +14,68 @@
 import argparse
 import os
 
+def LaunchSim(ElfFile):
+    # Launch selected simulator
+    cd = "cd $WALLY/sim/" +args.sim
+    # ugh.  can't have more than 9 arguments passed to vsim. why? I'll have to remove --lockstep when running
+    # functional coverage and imply it.
+    if (args.sim == "questa"):
+        if (args.lockstep):
+            prefix = "IMPERAS_TOOLS=" + WALLY + "/sim/imperas.ic"
+            if(int(args.locksteplog) >= 1): EnableLog = 1
+            else: EnableLog = 0
+            if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog) 
+            else: ImperasPlusArgs = ""
+            if(args.fcov):
+                CovEnableStr = "1" if int(args.covlog) > 0  else "0";
+                if(args.covlog >= 1): EnableLog = 1
+                else: EnableLog = 0
+                ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr;
+                suffix = ""
+            else:
+                CovEnableStr = ""
+                suffix = "--lockstep"
+        else:
+            prefix = ""
+            ImperasPlusArgs = ""
+            suffix = ""
+        if (args.tb == "testbench_fp"):
+            args.args = " -GTEST=\"" + args.testsuite + "\" " + args.args
+        cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args + " " + ElfFile + " " + suffix + " " + ImperasPlusArgs
+        if (args.coverage):
+            cmd += " --coverage"
+        if (args.fcov):
+            cmd += " --fcov"
+        if (args.gui):  # launch Questa with GUI; add +acc to keep variables accessible
+            if(args.tb == "testbench"): 
+                cmd = cd + "; " + prefix + " vsim -do \"" + cmd + " +acc -GDEBUG=1\""
+            elif(args.tb == "testbench_fp"):
+                cmd = cd + "; " + prefix + " vsim -do \"" + cmd + " +acc\""
+        else: # launch Questa in batch mode
+            cmd = cd + "; " + prefix + " vsim -c -do \"" + cmd + "\""
+        print("Running Questa with command: " + cmd)
+        os.system(cmd)
+    elif (args.sim == "verilator"):
+        # PWD=${WALLY}/sim CONFIG=rv64gc TESTSUITE=arch64i
+        print(f"Running Verilator on {args.config} {args.testsuite}")
+        if (args.coverage):
+            print("Coverage option not available for Verilator")
+            exit(1)
+        if (args.gui):
+            print("GUI option not available for Verilator")
+            exit(1)
+        os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} EXTRA_ARGS='{args.args}'")
+    elif (args.sim == "vcs"):
+        print(f"Running VCS on " + args.config + " " + args.testsuite)
+        if (args.gui):  
+            args.args += "gui"
+        elif (args.coverage):
+            args.args += "coverage"
+        cmd = cd + "; ./run_vcs " + args.config + " " + args.testsuite + " " + args.args
+        print(cmd)
+        os.system(cmd)
+
+
 # Parse arguments
 parser = argparse.ArgumentParser()
 parser.add_argument("config", help="Configuration file")
@@ -22,21 +84,45 @@ parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilat
 parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
 parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
 parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true")
+parser.add_argument("--fcov", "-f", help="Code & Functional Coverage", action="store_true")
 parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
+parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true")
+parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
+parser.add_argument("--locksteplog", "-b", help="Retired instruction number to be begin logging.", default=0)
+parser.add_argument("--covlog", "-d", help="Log coverage after n instructions.", default=0)
+parser.add_argument("--elfext", "-e", help="When searching for elf files only includes ones which end in this extension", default=".elf")
 args = parser.parse_args()
 print("Config=" + args.config + " tests=" + args.testsuite + " sim=" + args.sim + " gui=" + str(args.gui) + " args='" + args.args + "'")
+ElfFile=""
+DirectorMode = 0
+ElfList = []
+
+if(os.path.isfile(args.testsuite)):
+    ElfFile = "+ElfFile=" + args.testsuite
+    args.testsuite = "none"
+    ElfList.append("+ElfFile=" + args.testsuite)
+elif(os.path.isdir(args.testsuite)):
+    DirectorMode = 1
+    for dirpath, dirnames, filenames in os.walk(args.testsuite):
+        for file in filenames:
+            if file.endswith(args.elfext):
+                ElfList.append("+ElfFile=" + os.path.join(dirpath, file))
+    args.testsuite = "none"
+print(ElfList)
 
 # Validate arguments
 if (args.gui):
-    if (args.sim != "questa"):
-        print("GUI option only supported for Questa")
+    if args.sim not in ["questa", "vcs"]:
+        print("GUI option only supported for Questa and VCS")
         exit(1)
 
 if (args.coverage):
-    if (args.sim != "questa"):
-        print("Coverage option only available for Questa")
+    if args.sim not in ["questa", "vcs"]:
+        print("Coverage option only available for Questa and VCS")
         exit(1)
 
+if (args.vcd):
+    args.args += " -DMAKEVCD=1"
 
 #  create the output sub-directories.
 WALLY = os.environ.get('WALLY')
@@ -47,24 +133,9 @@ for d in ["logs", "wkdir", "cov"]:
     except:
         pass
         
-# Launch selected simulator
-cd = "cd $WALLY/sim/" +args.sim
-if (args.sim == "questa"):
-    if (args.tb == "testbench_fp"):
-         args.args = " -GTEST=" + args.testsuite + " " + args.args
-#         cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + " -GTEST=" + args.testsuite + " " + args.args
-#    else:
-#        cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args
-    cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args
-    if (args.coverage):
-        cmd += " -coverage"
-    if (args.gui):  # launch Questa with GUI; add +acc to keep variables accessible
-         cmd = cd + "; vsim -do \"" + cmd + " +acc\""        
-    else: # launch Questa in batch mode
-        cmd = cd + "; vsim -c -do \"" + cmd + "\""
-    print("Running Questa with command: " + cmd)
-    os.system(cmd)
-elif (args.sim == "verilator"):
-    print("Running Verilator on %s %s", args.config, args.testsuite)
-elif (args.sim == "vcs"):
-    print("Running VCS on %s %s", args.config, args.testsuite)
+if(DirectorMode):
+    for ElfFile in ElfList:
+        LaunchSim(ElfFile)
+
+else:
+    LaunchSim(ElfFile)
diff --git a/config/derivlist.txt b/config/derivlist.txt
index 3f6a869d9..f123a0d16 100644
--- a/config/derivlist.txt
+++ b/config/derivlist.txt
@@ -71,7 +71,7 @@ BTB_SIZE            32'd5
 # The other syn configurations have the same trimming
 deriv syn_rv32i rv32i syn_rv32e
 deriv syn_rv32imc rv32imc syn_rv32e
-deriv syn_rv32gc syn_rv32e
+deriv syn_rv32gc rv32gc syn_rv32e
 deriv syn_rv64i rv64i syn_rv32e
 deriv syn_rv64gc rv64gc syn_rv32e
 
@@ -84,35 +84,41 @@ USE_SRAM            1
 # The other syn configurations have the same trimming
 deriv syn_sram_rv32i rv32i syn_sram_rv32e
 deriv syn_sram_rv32imc rv32imc syn_sram_rv32e
-deriv syn_sram_rv32gc syn_sram_rv32e
+deriv syn_sram_rv32gc rv32gc syn_sram_rv32e
 deriv syn_sram_rv64i rv64i syn_sram_rv32e
 deriv syn_sram_rv64gc rv64gc syn_sram_rv32e
 
 # The following syn configurations gradually turn off features
-deriv syn_pmp0_rv64gc syn_rv64gc
+deriv syn_rv64gc_pmp0 syn_rv64gc
 PMP_ENTRIES         32'd0
-deriv syn_sram_pmp0_rv64gc syn_sram_rv64gc
+deriv syn_sram_rv64gc_pmp0 syn_sram_rv64gc
 PMP_ENTRIES         32'd0
 
-deriv syn_noPriv_rv64gc syn_pmp0_rv64gc
+deriv syn_rv64gc_noPriv syn_rv64gc_pmp0
 ZICSR_SUPPORTED     0
-deriv syn_sram_noPriv_rv64gc syn_sram_pmp0_rv64gc
+deriv syn_sram_rv64gc_noPriv syn_sram_rv64gc_pmp0
 ZICSR_SUPPORTED     0
 
-deriv syn_noFPU_rv64gc syn_noPriv_rv64gc
-MISA                (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
-deriv syn_sram_noFPU_rv64gc syn_sram_noPriv_rv64gc
-MISA                (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
-
-deriv syn_noMulDiv_rv64gc syn_noFPU_rv64gc
-MISA                (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)
-deriv syn_sram_noMulDiv_rv64gc syn_sram_noFPU_rv64gc
-MISA                (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)
-
-deriv syn_noAtomic_rv64gc syn_noMulDiv_rv64gc
-MISA                (32'h00000104 | 1 << 18 | 1 << 20)
-deriv syn_sram_noAtomic_rv64gc syn_sram_noMulDiv_rv64gc
-MISA                (32'h00000104 | 1 << 18 | 1 << 20)
+deriv syn_rv64gc_noFPU syn_rv64gc_noPriv
+F_SUPPORTED         0
+D_SUPPORTED         0
+deriv syn_sram_rv64gc_noFPU syn_sram_rv64gc_noPriv
+F_SUPPORTED         0
+D_SUPPORTED         0
+
+deriv syn_rv64gc_noMulDiv syn_rv64gc_noFPU
+M_SUPPORTED         0
+ZMMUL_SUPPORTED     0
+deriv syn_sram_rv64gc_noMulDiv syn_sram_rv64gc_noFPU
+M_SUPPORTED         0
+ZMMUL_SUPPORTED     0
+
+deriv syn_rv64gc_noAtomic syn_rv64gc_noMulDiv
+ZAAMO_SUPPORTED     0
+ZALRSC_SUPPORTED    0
+deriv syn_sram_rv64gc_noAtomic syn_sram_rv64gc_noMulDiv
+ZAAMO_SUPPORTED     0
+ZALRSC_SUPPORTED    0
 
 # Divider variants to check logical correctness
 
@@ -140,7 +146,6 @@ deriv div_4_2_rv32gc    rv32gc
 RADIX               32'd4
 IDIV_ON_FPU         0
 DIVCOPIES           32'd2
-IDIV_ON_FPU         0
 
 deriv div_4_4_rv32gc    rv32gc
 RADIX               32'd4
@@ -237,6 +242,9 @@ BURST_EN            1
 
 # Branch predictor simulations
 
+deriv nobpred_rv32gc rv32gc 
+BPRED_SUPPORTED     0
+
 deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc 
 BPRED_SIZE          32'd6
 
@@ -288,9 +296,6 @@ RAS_SIZE          32'd6
 deriv bpred_GSHARE_10_10_10_1_rv32gc rv32gc
 RAS_SIZE          32'd10
 
-deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
-RAS_SIZE          32'd16
-
 deriv bpred_GSHARE_10_16_6_1_rv32gc rv32gc
 BTB_SIZE          32'd6
 
@@ -306,9 +311,6 @@ BTB_SIZE          32'd14
 deriv bpred_GSHARE_10_16_16_1_rv32gc rv32gc
 BTB_SIZE          32'd16
 
-
-
-
 deriv bpred_GSHARE_6_16_10_0_rv32gc bpred_GSHARE_6_16_10_1_rv32gc 
 INSTR_CLASS_PRED  0
 
@@ -360,9 +362,6 @@ INSTR_CLASS_PRED          0
 deriv bpred_GSHARE_10_10_10_0_rv32gc bpred_GSHARE_10_10_10_1_rv32gc
 INSTR_CLASS_PRED          0
 
-deriv bpred_GSHARE_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_1_rv32gc
-INSTR_CLASS_PRED          0
-
 deriv bpred_GSHARE_10_16_6_0_rv32gc bpred_GSHARE_10_16_6_1_rv32gc
 INSTR_CLASS_PRED          0
 
@@ -386,10 +385,23 @@ VIRTMEM_SUPPORTED    0
 
 deriv nodcache_rv32gc rv32gc
 DCACHE_SUPPORTED    0
+D_SUPPORTED         0
+ZALRSC_SUPPORTED    0
+ZAAMO_SUPPORTED     0
+ZICBOM_SUPPORTED    0
+ZICBOZ_SUPPORTED    0
+VIRTMEM_SUPPORTED    0
 
+# nocache_rv32gc must also disable several features incompatible with no cache
 deriv nocache_rv32gc rv32gc
 ICACHE_SUPPORTED    0
 DCACHE_SUPPORTED    0
+D_SUPPORTED         0
+ZALRSC_SUPPORTED    0
+ZAAMO_SUPPORTED     0
+ZICBOM_SUPPORTED    0
+ZICBOZ_SUPPORTED    0
+VIRTMEM_SUPPORTED    0
 
 deriv noicache_rv64gc rv64gc
 ICACHE_SUPPORTED    0
@@ -404,7 +416,8 @@ ZICBOM_SUPPORTED    0
 ZICBOZ_SUPPORTED    0
 SVPBMT_SUPPORTED    0
 SVNAPOT_SUPPORTED   0
-MISA                (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12)
+ZAAMO_SUPPORTED     0
+ZALRSC_SUPPORTED    0
 
 deriv nocache_rv64gc rv64gc
 ICACHE_SUPPORTED    0
@@ -414,7 +427,8 @@ ZICBOM_SUPPORTED    0
 ZICBOZ_SUPPORTED    0
 SVPBMT_SUPPORTED    0
 SVNAPOT_SUPPORTED   0
-MISA                (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12)
+ZAAMO_SUPPORTED     0
+ZALRSC_SUPPORTED    0
 
 deriv way_1_4096_512_rv32gc rv32gc
 DCACHE_NUMWAYS      32'd1
@@ -508,54 +522,302 @@ BIGENDIAN_SUPPORTED 0
 deriv nobigendian_rv64gc rv64gc
 BIGENDIAN_SUPPORTED 0
 
+deriv zaamo_rv32gc rv32gc
+ZALRSC_SUPPORTED    0
+
+deriv zalrsc_rv32gc rv32gc
+ZAAMO_SUPPORTED     0
+
+deriv zaamo_rv64gc rv64gc
+ZALRSC_SUPPORTED    0
+
+deriv zalrsc_rv64gc rv64gc
+ZAAMO_SUPPORTED     0
+
+deriv zba_rv32gc rv32gc
+ZBA_SUPPORTED     1     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zbb_rv32gc rv32gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     1     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zbc_rv32gc rv32gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     1     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zbs_rv32gc rv32gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     1     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zbkb_rv32gc rv32gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     1     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zbkc_rv32gc rv32gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     1     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zbkx_rv32gc rv32gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     1     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zknd_rv32gc rv32gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     1     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zkne_rv32gc rv32gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     1     
+ZKNH_SUPPORTED     0     
+
+deriv zknh_rv32gc rv32gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     1     
+
+deriv zba_rv64gc rv64gc
+ZBA_SUPPORTED     1     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zbb_rv64gc rv64gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     1     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zbc_rv64gc rv64gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     1     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zbs_rv64gc rv64gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     1     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zbkb_rv64gc rv64gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     1     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zbkc_rv64gc rv64gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     1     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zbkx_rv64gc rv64gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     1     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zknd_rv64gc rv64gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     1     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     0     
+
+deriv zkne_rv64gc rv64gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     1     
+ZKNH_SUPPORTED     0     
+
+deriv zknh_rv64gc rv64gc
+ZBA_SUPPORTED     0     
+ZBB_SUPPORTED     0     
+ZBS_SUPPORTED     0     
+ZBC_SUPPORTED     0     
+ZBKB_SUPPORTED     0     
+ZBKC_SUPPORTED     0     
+ZBKX_SUPPORTED     0     
+ZKND_SUPPORTED     0     
+ZKNE_SUPPORTED     0     
+ZKNH_SUPPORTED     1     
+
 # Floating-point modes supported
 
 deriv f_rv32gc rv32gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv fh_rv32gc rv32gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fd_rv32gc rv32gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fdh_rv32gc rv32gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdq_rv32gc rv32gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 deriv fdqh_rv32gc rv32gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 deriv f_rv64gc rv64gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv fh_rv64gc rv64gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fd_rv64gc rv64gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fdh_rv64gc rv64gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdq_rv64gc rv64gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 deriv fdqh_rv64gc rv64gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 # IEEE compatible variants for TestFloat
@@ -600,302 +862,276 @@ IEEE754     1
 
 #### F_only, RK variable
 deriv f_div_2_1_rv32gc    div_2_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_2_2_rv32gc    div_2_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_2_4_rv32gc    div_2_4_rv32gc
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_4_1_rv32gc    div_4_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_4_2_rv32gc    div_4_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_4_4_rv32gc    div_4_4_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_2_1_rv64gc    div_2_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_2_2_rv64gc    div_2_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_2_4_rv64gc    div_2_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_4_1_rv64gc    div_4_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_4_2_rv64gc    div_4_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_4_4_rv64gc    div_4_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
-
 #### FH_only, RK variable
 deriv fh_div_2_1_rv32gc    div_2_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_2_2_rv32gc    div_2_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_2_4_rv32gc    div_2_4_rv32gc
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_4_1_rv32gc    div_4_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_4_2_rv32gc    div_4_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_4_4_rv32gc    div_4_4_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_2_1_rv64gc    div_2_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_2_2_rv64gc    div_2_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_2_4_rv64gc    div_2_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_4_1_rv64gc    div_4_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_4_2_rv64gc    div_4_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_4_4_rv64gc    div_4_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 # FD only , rk variable
 
 deriv fd_div_2_1_rv32gc    div_2_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_2_2_rv32gc    div_2_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_2_4_rv32gc    div_2_4_rv32gc
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_4_1_rv32gc    div_4_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_4_2_rv32gc    div_4_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_4_4_rv32gc    div_4_4_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_2_1_rv64gc    div_2_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_2_2_rv64gc    div_2_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_2_4_rv64gc    div_2_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_4_1_rv64gc    div_4_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_4_2_rv64gc    div_4_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_4_4_rv64gc    div_4_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
-
 # FDH only , rk variable
 
 deriv fdh_div_2_1_rv32gc    div_2_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_2_2_rv32gc    div_2_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_2_4_rv32gc    div_2_4_rv32gc
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_4_1_rv32gc    div_4_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_4_2_rv32gc    div_4_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_4_4_rv32gc    div_4_4_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_2_1_rv64gc    div_2_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_2_2_rv64gc    div_2_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_2_4_rv64gc    div_2_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_4_1_rv64gc    div_4_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_4_2_rv64gc    div_4_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_4_4_rv64gc    div_4_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 # FDQ only , rk variable
 
 deriv fdq_div_2_1_rv32gc    div_2_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 deriv fdq_div_2_2_rv32gc    div_2_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 deriv fdq_div_2_4_rv32gc    div_2_4_rv32gc
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 deriv fdq_div_4_1_rv32gc    div_4_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 deriv fdq_div_4_2_rv32gc    div_4_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 deriv fdq_div_4_4_rv32gc    div_4_4_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 deriv fdq_div_2_1_rv64gc    div_2_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 deriv fdq_div_2_2_rv64gc    div_2_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 deriv fdq_div_2_4_rv64gc    div_2_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 deriv fdq_div_4_1_rv64gc    div_4_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 deriv fdq_div_4_2_rv64gc    div_4_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 deriv fdq_div_4_4_rv64gc    div_4_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 # FDQH only , rk variable
 
 deriv fdqh_div_2_1_rv32gc    div_2_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_2_2_rv32gc    div_2_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_2_4_rv32gc    div_2_4_rv32gc
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_4_1_rv32gc    div_4_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_4_2_rv32gc    div_4_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_4_4_rv32gc    div_4_4_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_2_1_rv64gc    div_2_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_2_2_rv64gc    div_2_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_2_4_rv64gc    div_2_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_4_1_rv64gc    div_4_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_4_2_rv64gc    div_4_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_4_4_rv64gc    div_4_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 #### DIVIDER VARIANTS WITH IEEE
diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh
index 5e1f883d4..d4a481ea0 100644
--- a/config/rv32e/config.vh
+++ b/config/rv32e/config.vh
@@ -2,10 +2,10 @@
 // config.vh
 //
 // Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
+// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
 //
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
+// Purpose: Specify which features of Wally are enabled and set
+//          configuration parameters
 // 
 // A component of the Wally configurable RISC-V project.
 // 
@@ -33,32 +33,91 @@ localparam XLEN = 32'd32;
 // IEEE 754 compliance
 localparam IEEE754 = 0;
 
-// E
-localparam MISA = (32'h00000010); 
-localparam ZICSR_SUPPORTED = 0;
-localparam ZIFENCEI_SUPPORTED = 0;
+// Debug Module implemented                                                                                                          
+localparam logic DEBUG_SUPPORTED = 1'b0;
+
+// RISC-V configuration per specification
+// Base instruction set (defaults to I if E is not supported)
+localparam logic E_SUPPORTED = 1;
+
+// Integer instruction set extensions
+localparam logic ZIFENCEI_SUPPORTED = 0; // Instruction-Fetch fence
+localparam logic ZICSR_SUPPORTED    = 0; // CSR Instructions
+localparam logic ZICCLSM_SUPPORTED  = 0; // Misaligned loads/stores
+localparam logic ZICOND_SUPPORTED   = 0; // Integer conditional operations
+
+// Multiplication & division extensions
+// M implies (and in the configuration file requires) Zmmul
+localparam logic M_SUPPORTED     = 0;
+localparam logic ZMMUL_SUPPORTED = 0;
+
+// Atomic extensions
+// A extension is Zaamo + Zalrsc
+localparam logic ZAAMO_SUPPORTED  = 0;
+localparam logic ZALRSC_SUPPORTED = 0;
+
+// Bit manipulation extensions
+// B extension is Zba + Zbb + Zbs
+localparam logic ZBA_SUPPORTED = 0;
+localparam logic ZBB_SUPPORTED = 0;
+localparam logic ZBS_SUPPORTED = 0;
+localparam logic ZBC_SUPPORTED = 0;
+
+// Scalar crypto extensions
+// Zkn is all 6 of these
+localparam logic ZBKB_SUPPORTED = 0;
+localparam logic ZBKC_SUPPORTED = 0;
+localparam logic ZBKX_SUPPORTED = 0;
+localparam logic ZKND_SUPPORTED = 0;
+localparam logic ZKNE_SUPPORTED = 0;
+localparam logic ZKNH_SUPPORTED = 0;
+
+// Compressed extensions
+// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
+// All compressed extensions require Zca
+localparam logic ZCA_SUPPORTED = 0;
+localparam logic ZCB_SUPPORTED = 0;
+localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
+localparam logic ZCD_SUPPORTED = 0; // requires D
+
+// Floating point extensions
+localparam logic F_SUPPORTED   = 0;
+localparam logic D_SUPPORTED   = 0;
+localparam logic Q_SUPPORTED   = 0;
+localparam logic ZFH_SUPPORTED = 0;
+localparam logic ZFA_SUPPORTED = 0;
+
+// privilege modes
+localparam logic S_SUPPORTED = 0; // Supervisor mode
+localparam logic U_SUPPORTED = 0; // User mode
+
+// Supervisor level extensions
+localparam logic SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
+
+// Hardware performance counters
+localparam logic ZICNTR_SUPPORTED = 0;
+localparam logic ZIHPM_SUPPORTED  = 0;
 localparam COUNTERS = 12'd0;
-localparam ZICNTR_SUPPORTED = 0;
-localparam ZIHPM_SUPPORTED = 0;
-localparam ZFH_SUPPORTED = 0;
-localparam ZFA_SUPPORTED = 0;
-localparam SSTC_SUPPORTED = 0;
-localparam ZICBOM_SUPPORTED = 0;
-localparam ZICBOZ_SUPPORTED = 0;
-localparam ZICBOP_SUPPORTED = 0;
-localparam ZICCLSM_SUPPORTED = 0;
-localparam ZICOND_SUPPORTED = 0;
-localparam SVPBMT_SUPPORTED = 0;
-localparam SVNAPOT_SUPPORTED = 0;
-localparam SVINVAL_SUPPORTED = 0;
+
+// Cache-management operation extensions
+localparam logic ZICBOM_SUPPORTED = 0;
+localparam logic ZICBOZ_SUPPORTED = 0;
+localparam logic ZICBOP_SUPPORTED = 0;
+
+// Virtual memory extensions
+localparam logic SVPBMT_SUPPORTED  = 0;
+localparam logic SVNAPOT_SUPPORTED = 0;
+localparam logic SVINVAL_SUPPORTED = 0;
+localparam logic SVADU_SUPPORTED   = 0;
+
 
 // LSU microarchitectural Features
-localparam BUS_SUPPORTED = 1;
-localparam DCACHE_SUPPORTED = 0;
-localparam ICACHE_SUPPORTED = 0;
-localparam VIRTMEM_SUPPORTED = 0;
-localparam VECTORED_INTERRUPTS_SUPPORTED = 0; 
-localparam BIGENDIAN_SUPPORTED = 0;
+localparam logic BUS_SUPPORTED = 1;
+localparam logic DCACHE_SUPPORTED = 0;
+localparam logic ICACHE_SUPPORTED = 0;
+localparam logic VIRTMEM_SUPPORTED = 0;
+localparam logic VECTORED_INTERRUPTS_SUPPORTED = 0;
+localparam logic BIGENDIAN_SUPPORTED = 0;
 
 // TLB configuration.  Entries should be a power of 2
 localparam ITLB_ENTRIES = 32'd0;
@@ -77,7 +136,7 @@ localparam CACHE_SRAMLEN = 32'd128;
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 localparam IDIV_BITSPERCYCLE = 32'd1;
-localparam IDIV_ON_FPU = 0;
+localparam logic IDIV_ON_FPU = 0;
 
 // Legal number of PMP entries are 0, 16, or 64
 localparam PMP_ENTRIES = 32'd0;
@@ -88,63 +147,73 @@ localparam logic [63:0] RESET_VECTOR = 64'h80000000;
 // WFI Timeout Wait
 localparam WFI_TIMEOUT_BIT = 32'd16;
 
-// Peripheral Addresses
+// Peripheral Physical Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-localparam DTIM_SUPPORTED = 1'b0;
-localparam logic [63:0] DTIM_BASE = 64'h80000000;      
-localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF;     
-localparam IROM_SUPPORTED = 1'b0;
-localparam logic [63:0] IROM_BASE = 64'h80000000;     
-localparam logic [63:0] IROM_RANGE = 64'h007FFFFF;     
-localparam BOOTROM_SUPPORTED = 1'b1;
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+localparam logic DTIM_SUPPORTED = 0;
+localparam logic [63:0] DTIM_BASE          = 64'h80000000;
+localparam logic [63:0] DTIM_RANGE         = 64'h007FFFFF;
+localparam logic IROM_SUPPORTED = 0;
+localparam logic [63:0] IROM_BASE          = 64'h80000000;
+localparam logic [63:0] IROM_RANGE         = 64'h007FFFFF;
+localparam logic BOOTROM_SUPPORTED = 1;
+localparam logic [63:0] BOOTROM_BASE       = 64'h00001000;
+localparam logic [63:0] BOOTROM_RANGE      = 64'h00000FFF;
 localparam BOOTROM_PRELOAD = 1'b0;
-localparam logic [63:0] BOOTROM_BASE = 64'h00001000;  
-localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; 
-localparam UNCORE_RAM_SUPPORTED = 1'b1;
-localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;      
-localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;     
+localparam logic UNCORE_RAM_SUPPORTED = 1;
+localparam logic [63:0] UNCORE_RAM_BASE    = 64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE   = 64'h07FFFFFF;
 localparam UNCORE_RAM_PRELOAD = 1'b0;
-localparam EXT_MEM_SUPPORTED = 1'b0;
-localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;      
-localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF;     
-localparam CLINT_SUPPORTED = 1'b0;
-localparam logic [63:0] CLINT_BASE = 64'h02000000; 
-localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
-localparam GPIO_SUPPORTED = 1'b0;
-localparam logic [63:0] GPIO_BASE = 64'h10060000;  
-localparam logic [63:0] GPIO_RANGE = 64'h000000FF; 
-localparam UART_SUPPORTED = 1'b0;
-localparam logic [63:0] UART_BASE = 64'h10000000;  
-localparam logic [63:0] UART_RANGE = 64'h00000007; 
-localparam PLIC_SUPPORTED = 1'b0;
-localparam logic [63:0] PLIC_BASE = 64'h0C000000;  
-localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; 
-localparam  SDC_SUPPORTED = 1'b0;
-localparam logic [63:0] SDC_BASE =  64'h00013000;
-localparam logic [63:0] SDC_RANGE = 64'h0000007F;
-localparam SPI_SUPPORTED = 1'b0;
-localparam logic [63:0] SPI_BASE = 64'h10040000;
-localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
+localparam logic EXT_MEM_SUPPORTED = 0;
+localparam logic [63:0] EXT_MEM_BASE       = 64'h80000000;
+localparam logic [63:0] EXT_MEM_RANGE      = 64'h07FFFFFF;
+localparam logic CLINT_SUPPORTED = 0;
+localparam logic [63:0] CLINT_BASE         = 64'h02000000;
+localparam logic [63:0] CLINT_RANGE        = 64'h0000FFFF;
+localparam logic GPIO_SUPPORTED = 0;
+localparam logic [63:0] GPIO_BASE          = 64'h10060000;
+localparam logic [63:0] GPIO_RANGE         = 64'h000000FF;
+localparam logic UART_SUPPORTED = 0;
+localparam logic [63:0] UART_BASE          = 64'h10000000;
+localparam logic [63:0] UART_RANGE         = 64'h00000007;
+localparam logic PLIC_SUPPORTED = 0;
+localparam logic [63:0] PLIC_BASE          = 64'h0C000000;
+localparam logic [63:0] PLIC_RANGE         = 64'h03FFFFFF;
+localparam logic SDC_SUPPORTED = 0;
+localparam logic [63:0] SDC_BASE           = 64'h00013000;
+localparam logic [63:0] SDC_RANGE          = 64'h0000007F;
+localparam logic SPI_SUPPORTED = 0;
+localparam logic [63:0] SPI_BASE           = 64'h10040000;
+localparam logic [63:0] SPI_RANGE          = 64'h00000FFF;
+localparam logic PLL_SUPPORTED = 1'b0;
+localparam logic [63:0] PLL_CONF_BASE      = 64'h00020000;
+localparam logic [63:0] PLL_CONF_RANGE     = 64'h000000FF;
+localparam logic BSG_DMC_SUPPORTED = 1'b0;
+localparam logic [63:0] BSG_DMC_CONF_BASE  = 64'h00030000;
+localparam logic [63:0] BSG_DMC_CONF_RANGE = 64'h000000FF;
+// Debug program buffer support is enabled with DEBUG_SUPPORTED
+localparam logic [63:0] PROGBUF_BASE     = 64'h00002000;
+localparam logic [63:0] PROGBUF_RANGE    = 64'h0000000F;
 
 // Bus Interface width
-localparam AHBW = 32'd32;
+localparam AHBW = (XLEN);
 
 // Test modes
 
 // AHB 
 localparam RAM_LATENCY = 32'b0;
-localparam BURST_EN    = 1;
+localparam logic BURST_EN = 1;
 
 // Tie GPIO outputs back to inputs
-localparam GPIO_LOOPBACK_TEST = 1;
-localparam SPI_LOOPBACK_TEST = 0;
+localparam logic GPIO_LOOPBACK_TEST = 1;
+localparam logic SPI_LOOPBACK_TEST  = 0;
 
 // Hardware configuration
 localparam UART_PRESCALE = 32'd1;
 
 // Interrupt configuration
-localparam PLIC_NUM_SRC = 32'd10; 
+localparam PLIC_NUM_SRC = 32'd10;
 // comment out the following if >=32 sources
 localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
 localparam PLIC_GPIO_ID = 32'd3;
@@ -152,7 +221,8 @@ localparam PLIC_UART_ID = 32'd10;
 localparam PLIC_SPI_ID = 32'd6;
 localparam PLIC_SDC_ID = 32'd9;
 
-localparam BPRED_SUPPORTED = 0;
+// Branch prediction
+localparam logic BPRED_SUPPORTED = 0;
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 localparam BPRED_SIZE = 32'd10;
 localparam BPRED_NUM_LHR = 32'd6;
@@ -160,36 +230,11 @@ localparam BTB_SIZE = 32'd10;
 localparam RAS_SIZE = 32'd16;
 localparam INSTR_CLASS_PRED = 0;
 
-localparam SVADU_SUPPORTED = 0;
-localparam ZMMUL_SUPPORTED = 0;
-
 // FPU division architecture
 localparam RADIX = 32'd4;
 localparam DIVCOPIES = 32'd4;
 
-// bit manipulation
-localparam ZBA_SUPPORTED = 0;
-localparam ZBB_SUPPORTED = 0;
-localparam ZBC_SUPPORTED = 0;
-localparam ZBS_SUPPORTED = 0;
-
-// New compressed instructions
-localparam ZCB_SUPPORTED = 0;
-localparam ZCA_SUPPORTED = 0;
-localparam ZCF_SUPPORTED = 0;
-localparam ZCD_SUPPORTED = 0;
-
-// K extension instructions                                                                
-localparam ZBKB_SUPPORTED = 0;
-localparam ZBKC_SUPPORTED = 0;
-localparam ZBKX_SUPPORTED = 0;
-localparam ZKNE_SUPPORTED = 0;
-localparam ZKND_SUPPORTED = 0;
-localparam ZK_SUPPORTED = 0;
-localparam ZKNH_SUPPORTED = 0;
-
 // Memory synthesis configuration
-localparam USE_SRAM = 0;
+localparam logic USE_SRAM = 0;
 
 `include "config-shared.vh"
- 
diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh
index d6fb995b1..097332a7f 100644
--- a/config/rv32gc/config.vh
+++ b/config/rv32gc/config.vh
@@ -2,10 +2,10 @@
 // config.vh
 //
 // Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
+// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
 //
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
+// Purpose: Specify which features of Wally are enabled and set
+//          configuration parameters
 // 
 // A component of the Wally configurable RISC-V project.
 // 
@@ -25,8 +25,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-// include shared configuration
-// `include "wally-shared.vh"
 `include "BranchPredictorType.vh"
 
 // RV32 or RV64: XLEN = 32 or 64
@@ -35,31 +33,91 @@ localparam XLEN = 32'd32;
 // IEEE 754 compliance
 localparam IEEE754 = 0;
 
-localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5);
-localparam ZICSR_SUPPORTED = 1;
-localparam ZIFENCEI_SUPPORTED = 1;
+// Debug Module implemented                                                                                                          
+localparam logic DEBUG_SUPPORTED = 1'b1;
+
+// RISC-V configuration per specification
+// Base instruction set (defaults to I if E is not supported)
+localparam logic E_SUPPORTED = 0;
+
+// Integer instruction set extensions
+localparam logic ZIFENCEI_SUPPORTED = 1; // Instruction-Fetch fence
+localparam logic ZICSR_SUPPORTED    = 1; // CSR Instructions
+localparam logic ZICCLSM_SUPPORTED  = 0; // Misaligned loads/stores
+localparam logic ZICOND_SUPPORTED   = 1; // Integer conditional operations
+
+// Multiplication & division extensions
+// M implies (and in the configuration file requires) Zmmul
+localparam logic M_SUPPORTED     = 1;
+localparam logic ZMMUL_SUPPORTED = 1;
+
+// Atomic extensions
+// A extension is Zaamo + Zalrsc
+localparam logic ZAAMO_SUPPORTED  = 1;
+localparam logic ZALRSC_SUPPORTED = 1;
+
+// Bit manipulation extensions
+// B extension is Zba + Zbb + Zbs
+localparam logic ZBA_SUPPORTED = 1;
+localparam logic ZBB_SUPPORTED = 1;
+localparam logic ZBS_SUPPORTED = 1;
+localparam logic ZBC_SUPPORTED = 1;
+
+// Scalar crypto extensions
+// Zkn is all 6 of these
+localparam logic ZBKB_SUPPORTED = 1;
+localparam logic ZBKC_SUPPORTED = 1;
+localparam logic ZBKX_SUPPORTED = 1;
+localparam logic ZKND_SUPPORTED = 1;
+localparam logic ZKNE_SUPPORTED = 1;
+localparam logic ZKNH_SUPPORTED = 1;
+
+// Compressed extensions
+// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
+// All compressed extensions require Zca
+localparam logic ZCA_SUPPORTED = 1;
+localparam logic ZCB_SUPPORTED = 1;
+localparam logic ZCF_SUPPORTED = 1; // RV32 only, requires F
+localparam logic ZCD_SUPPORTED = 1; // requires D
+
+// Floating point extensions
+localparam logic F_SUPPORTED   = 1;
+localparam logic D_SUPPORTED   = 1;
+localparam logic Q_SUPPORTED   = 0;
+localparam logic ZFH_SUPPORTED = 1;
+localparam logic ZFA_SUPPORTED = 1;
+
+// privilege modes
+localparam logic S_SUPPORTED = 1; // Supervisor mode
+localparam logic U_SUPPORTED = 1; // User mode
+
+// Supervisor level extensions
+localparam logic SSTC_SUPPORTED = 1; // Supervisor-mode timer interrupts
+
+// Hardware performance counters
+localparam logic ZICNTR_SUPPORTED = 1;
+localparam logic ZIHPM_SUPPORTED  = 1;
 localparam COUNTERS = 12'd32;
-localparam ZICNTR_SUPPORTED = 1;
-localparam ZIHPM_SUPPORTED = 1;
-localparam ZFH_SUPPORTED = 1;
-localparam ZFA_SUPPORTED = 1;
-localparam SSTC_SUPPORTED = 1;
-localparam ZICBOM_SUPPORTED = 1;
-localparam ZICBOZ_SUPPORTED = 1;
-localparam ZICBOP_SUPPORTED = 1;
-localparam ZICCLSM_SUPPORTED = 0;
-localparam ZICOND_SUPPORTED = 1;
-localparam SVPBMT_SUPPORTED = 0;
-localparam SVNAPOT_SUPPORTED = 0;
-localparam SVINVAL_SUPPORTED = 1;
+
+// Cache-management operation extensions
+localparam logic ZICBOM_SUPPORTED = 1;
+localparam logic ZICBOZ_SUPPORTED = 1;
+localparam logic ZICBOP_SUPPORTED = 1;
+
+// Virtual memory extensions
+localparam logic SVPBMT_SUPPORTED  = 0;
+localparam logic SVNAPOT_SUPPORTED = 0;
+localparam logic SVINVAL_SUPPORTED = 1;
+localparam logic SVADU_SUPPORTED   = 1;
+
 
 // LSU microarchitectural Features
-localparam BUS_SUPPORTED = 1;
-localparam DCACHE_SUPPORTED = 1;
-localparam ICACHE_SUPPORTED = 1;
-localparam VIRTMEM_SUPPORTED = 1;
-localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
-localparam BIGENDIAN_SUPPORTED = 1;
+localparam logic BUS_SUPPORTED = 1;
+localparam logic DCACHE_SUPPORTED = 1;
+localparam logic ICACHE_SUPPORTED = 1;
+localparam logic VIRTMEM_SUPPORTED = 1;
+localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
+localparam logic BIGENDIAN_SUPPORTED = 1;
 
 // TLB configuration.  Entries should be a power of 2
 localparam ITLB_ENTRIES = 32'd32;
@@ -78,7 +136,7 @@ localparam CACHE_SRAMLEN = 32'd128;
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 localparam IDIV_BITSPERCYCLE = 32'd2;
-localparam IDIV_ON_FPU = 0;
+localparam logic IDIV_ON_FPU = 0;
 
 // Legal number of PMP entries are 0, 16, or 64
 localparam PMP_ENTRIES = 32'd16;
@@ -89,57 +147,67 @@ localparam logic [63:0] RESET_VECTOR = 64'h80000000;
 // WFI Timeout Wait
 localparam WFI_TIMEOUT_BIT = 32'd16;
 
-// Peripheral Addresses
+// Peripheral Physical Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-localparam DTIM_SUPPORTED = 1'b0;
-localparam logic [63:0] DTIM_BASE       = 64'h80000000;
-localparam logic [63:0] DTIM_RANGE      = 64'h007FFFFF;
-localparam IROM_SUPPORTED = 1'b0;
-localparam logic [63:0] IROM_BASE       = 64'h80000000;
-localparam logic [63:0] IROM_RANGE      = 64'h007FFFFF;
-localparam BOOTROM_SUPPORTED = 1'b1;
-localparam logic [63:0] BOOTROM_BASE   = 64'h00001000;
-localparam logic [63:0] BOOTROM_RANGE  = 64'h00000FFF;
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+localparam logic DTIM_SUPPORTED = 0;
+localparam logic [63:0] DTIM_BASE          = 64'h80000000;
+localparam logic [63:0] DTIM_RANGE         = 64'h007FFFFF;
+localparam logic IROM_SUPPORTED = 0;
+localparam logic [63:0] IROM_BASE          = 64'h80000000;
+localparam logic [63:0] IROM_RANGE         = 64'h007FFFFF;
+localparam logic BOOTROM_SUPPORTED = 1;
+localparam logic [63:0] BOOTROM_BASE       = 64'h00001000;
+localparam logic [63:0] BOOTROM_RANGE      = 64'h00000FFF;
 localparam BOOTROM_PRELOAD = 1'b0;
-localparam UNCORE_RAM_SUPPORTED = 1'b1;
-localparam logic [63:0] UNCORE_RAM_BASE       = 64'h80000000;
-localparam logic [63:0] UNCORE_RAM_RANGE      = 64'h07FFFFFF;
+localparam logic UNCORE_RAM_SUPPORTED = 1;
+localparam logic [63:0] UNCORE_RAM_BASE    = 64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE   = 64'h07FFFFFF;
 localparam UNCORE_RAM_PRELOAD = 1'b0;
-localparam EXT_MEM_SUPPORTED = 1'b0;
+localparam logic EXT_MEM_SUPPORTED = 0;
 localparam logic [63:0] EXT_MEM_BASE       = 64'h80000000;
 localparam logic [63:0] EXT_MEM_RANGE      = 64'h07FFFFFF;
-localparam CLINT_SUPPORTED = 1'b1;
-localparam logic [63:0] CLINT_BASE  = 64'h02000000;
-localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
-localparam GPIO_SUPPORTED = 1'b1;
-localparam logic [63:0] GPIO_BASE   = 64'h10060000;
-localparam logic [63:0] GPIO_RANGE  = 64'h000000FF;
-localparam UART_SUPPORTED = 1'b1;
-localparam logic [63:0] UART_BASE   = 64'h10000000;
-localparam logic [63:0] UART_RANGE  = 64'h00000007;
-localparam PLIC_SUPPORTED = 1'b1;
-localparam logic [63:0] PLIC_BASE   = 64'h0C000000;
-localparam logic [63:0] PLIC_RANGE  = 64'h03FFFFFF;
-localparam  SDC_SUPPORTED = 1'b0;
-localparam logic [63:0] SDC_BASE =  64'h00013000;
-localparam logic [63:0] SDC_RANGE = 64'h0000007F;
-localparam SPI_SUPPORTED = 1'b1;
-localparam logic [63:0] SPI_BASE = 64'h10040000;
-localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
+localparam logic CLINT_SUPPORTED = 1;
+localparam logic [63:0] CLINT_BASE         = 64'h02000000;
+localparam logic [63:0] CLINT_RANGE        = 64'h0000FFFF;
+localparam logic GPIO_SUPPORTED = 1;
+localparam logic [63:0] GPIO_BASE          = 64'h10060000;
+localparam logic [63:0] GPIO_RANGE         = 64'h000000FF;
+localparam logic UART_SUPPORTED = 1;
+localparam logic [63:0] UART_BASE          = 64'h10000000;
+localparam logic [63:0] UART_RANGE         = 64'h00000007;
+localparam logic PLIC_SUPPORTED = 1;
+localparam logic [63:0] PLIC_BASE          = 64'h0C000000;
+localparam logic [63:0] PLIC_RANGE         = 64'h03FFFFFF;
+localparam logic SDC_SUPPORTED = 0;
+localparam logic [63:0] SDC_BASE           = 64'h00013000;
+localparam logic [63:0] SDC_RANGE          = 64'h0000007F;
+localparam logic SPI_SUPPORTED = 1;
+localparam logic [63:0] SPI_BASE           = 64'h10040000;
+localparam logic [63:0] SPI_RANGE          = 64'h00000FFF;
+localparam logic PLL_SUPPORTED = 1'b0;
+localparam logic [63:0] PLL_CONF_BASE      = 64'h00020000;
+localparam logic [63:0] PLL_CONF_RANGE     = 64'h000000FF;
+localparam logic BSG_DMC_SUPPORTED = 1'b0;
+localparam logic [63:0] BSG_DMC_CONF_BASE  = 64'h00030000;
+localparam logic [63:0] BSG_DMC_CONF_RANGE = 64'h000000FF;
+// Debug program buffer support is enabled with DEBUG_SUPPORTED
+localparam logic [63:0] PROGBUF_BASE     = 64'h00002000;
+localparam logic [63:0] PROGBUF_RANGE    = 64'h0000000F;
 
 // Bus Interface width
-localparam AHBW = 32'd32;
+localparam AHBW = (XLEN);
 
 // Test modes
 
 // AHB 
 localparam RAM_LATENCY = 32'b0;
-localparam BURST_EN    = 1;
+localparam logic BURST_EN = 1;
 
 // Tie GPIO outputs back to inputs
-localparam GPIO_LOOPBACK_TEST = 1;
-localparam SPI_LOOPBACK_TEST = 1;
+localparam logic GPIO_LOOPBACK_TEST = 1;
+localparam logic SPI_LOOPBACK_TEST  = 1;
 
 // Hardware configuration
 localparam UART_PRESCALE = 32'd1;
@@ -153,7 +221,8 @@ localparam PLIC_UART_ID = 32'd10;
 localparam PLIC_SPI_ID = 32'd6;
 localparam PLIC_SDC_ID = 32'd9;
 
-localparam BPRED_SUPPORTED = 1;
+// Branch prediction
+localparam logic BPRED_SUPPORTED = 1;
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 localparam BPRED_SIZE = 32'd10;
 localparam BPRED_NUM_LHR = 32'd6;
@@ -161,35 +230,11 @@ localparam BTB_SIZE = 32'd10;
 localparam RAS_SIZE = 32'd16;
 localparam INSTR_CLASS_PRED = 1;
 
-localparam SVADU_SUPPORTED = 1;
-localparam ZMMUL_SUPPORTED = 0;
-
 // FPU division architecture
 localparam RADIX = 32'd4;
 localparam DIVCOPIES = 32'd2;
 
-// bit manipulation
-localparam ZBA_SUPPORTED = 1;
-localparam ZBB_SUPPORTED = 1;
-localparam ZBC_SUPPORTED = 1;
-localparam ZBS_SUPPORTED = 1;
-
-// New compressed instructions
-localparam ZCB_SUPPORTED = 1;
-localparam ZCA_SUPPORTED = 0;
-localparam ZCF_SUPPORTED = 0;
-localparam ZCD_SUPPORTED = 0;
-
-// K extension instructions                                                                
-localparam ZBKB_SUPPORTED = 1;
-localparam ZBKC_SUPPORTED = 1;
-localparam ZBKX_SUPPORTED = 1;
-localparam ZKND_SUPPORTED = 1;
-localparam ZKNE_SUPPORTED = 1;
-localparam ZKNH_SUPPORTED = 1;
-localparam ZK_SUPPORTED = 1;
-
 // Memory synthesis configuration
-localparam USE_SRAM = 0;
+localparam logic USE_SRAM = 0;
 
 `include "config-shared.vh"
diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh
index 490937558..ca1bf3029 100644
--- a/config/rv32i/config.vh
+++ b/config/rv32i/config.vh
@@ -2,10 +2,10 @@
 // config.vh
 //
 // Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
+// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
 //
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
+// Purpose: Specify which features of Wally are enabled and set
+//          configuration parameters
 // 
 // A component of the Wally configurable RISC-V project.
 // 
@@ -33,32 +33,91 @@ localparam XLEN = 32'd32;
 // IEEE 754 compliance
 localparam IEEE754 = 0;
 
-// I
-localparam MISA = (32'h00000100);
-localparam ZICSR_SUPPORTED = 0;
-localparam ZIFENCEI_SUPPORTED = 0;
-localparam COUNTERS = 0;
-localparam ZICNTR_SUPPORTED = 0;
-localparam ZIHPM_SUPPORTED = 0;
-localparam ZFH_SUPPORTED = 0;
-localparam ZFA_SUPPORTED = 0;
-localparam SSTC_SUPPORTED = 0;
-localparam ZICBOM_SUPPORTED = 0;
-localparam ZICBOZ_SUPPORTED = 0;
-localparam ZICBOP_SUPPORTED = 0;
-localparam ZICCLSM_SUPPORTED = 0;
-localparam ZICOND_SUPPORTED = 0;
-localparam SVPBMT_SUPPORTED = 0;
-localparam SVNAPOT_SUPPORTED = 0;
-localparam SVINVAL_SUPPORTED = 0;
+// Debug Module implemented                                                                                                          
+localparam logic DEBUG_SUPPORTED = 1'b0;
+
+// RISC-V configuration per specification
+// Base instruction set (defaults to I if E is not supported)
+localparam logic E_SUPPORTED = 0;
+
+// Integer instruction set extensions
+localparam logic ZIFENCEI_SUPPORTED = 0; // Instruction-Fetch fence
+localparam logic ZICSR_SUPPORTED    = 0; // CSR Instructions
+localparam logic ZICCLSM_SUPPORTED  = 0; // Misaligned loads/stores
+localparam logic ZICOND_SUPPORTED   = 0; // Integer conditional operations
+
+// Multiplication & division extensions
+// M implies (and in the configuration file requires) Zmmul
+localparam logic M_SUPPORTED     = 0;
+localparam logic ZMMUL_SUPPORTED = 0;
+
+// Atomic extensions
+// A extension is Zaamo + Zalrsc
+localparam logic ZAAMO_SUPPORTED  = 0;
+localparam logic ZALRSC_SUPPORTED = 0;
+
+// Bit manipulation extensions
+// B extension is Zba + Zbb + Zbs
+localparam logic ZBA_SUPPORTED = 0;
+localparam logic ZBB_SUPPORTED = 0;
+localparam logic ZBS_SUPPORTED = 0;
+localparam logic ZBC_SUPPORTED = 0;
+
+// Scalar crypto extensions
+// Zkn is all 6 of these
+localparam logic ZBKB_SUPPORTED = 0;
+localparam logic ZBKC_SUPPORTED = 0;
+localparam logic ZBKX_SUPPORTED = 0;
+localparam logic ZKND_SUPPORTED = 0;
+localparam logic ZKNE_SUPPORTED = 0;
+localparam logic ZKNH_SUPPORTED = 0;
+
+// Compressed extensions
+// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
+// All compressed extensions require Zca
+localparam logic ZCA_SUPPORTED = 0;
+localparam logic ZCB_SUPPORTED = 0;
+localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
+localparam logic ZCD_SUPPORTED = 0; // requires D
+
+// Floating point extensions
+localparam logic F_SUPPORTED   = 0;
+localparam logic D_SUPPORTED   = 0;
+localparam logic Q_SUPPORTED   = 0;
+localparam logic ZFH_SUPPORTED = 0;
+localparam logic ZFA_SUPPORTED = 0;
+
+// privilege modes
+localparam logic S_SUPPORTED = 0; // Supervisor mode
+localparam logic U_SUPPORTED = 0; // User mode
+
+// Supervisor level extensions
+localparam logic SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
+
+// Hardware performance counters
+localparam logic ZICNTR_SUPPORTED = 0;
+localparam logic ZIHPM_SUPPORTED  = 0;
+localparam COUNTERS = 12'd0;
+
+// Cache-management operation extensions
+localparam logic ZICBOM_SUPPORTED = 0;
+localparam logic ZICBOZ_SUPPORTED = 0;
+localparam logic ZICBOP_SUPPORTED = 0;
+
+// Virtual memory extensions
+localparam logic SVPBMT_SUPPORTED  = 0;
+localparam logic SVNAPOT_SUPPORTED = 0;
+localparam logic SVINVAL_SUPPORTED = 0;
+localparam logic SVADU_SUPPORTED   = 0;
+
 
 // LSU microarchitectural Features
-localparam BUS_SUPPORTED = 0;
-localparam DCACHE_SUPPORTED = 0;
-localparam ICACHE_SUPPORTED = 0;
-localparam VIRTMEM_SUPPORTED = 0;
-localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
-localparam BIGENDIAN_SUPPORTED = 0;
+localparam logic BUS_SUPPORTED = 0;
+localparam logic DCACHE_SUPPORTED = 0;
+localparam logic ICACHE_SUPPORTED = 0;
+localparam logic VIRTMEM_SUPPORTED = 0;
+localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
+localparam logic BIGENDIAN_SUPPORTED = 0;
 
 // TLB configuration.  Entries should be a power of 2
 localparam ITLB_ENTRIES = 32'd32;
@@ -77,7 +136,7 @@ localparam CACHE_SRAMLEN = 32'd128;
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 localparam IDIV_BITSPERCYCLE = 32'd4;
-localparam IDIV_ON_FPU = 0;
+localparam logic IDIV_ON_FPU = 0;
 
 // Legal number of PMP entries are 0, 16, or 64
 localparam PMP_ENTRIES = 32'd0;
@@ -88,57 +147,67 @@ localparam logic [63:0] RESET_VECTOR = 64'h80000000;
 // WFI Timeout Wait
 localparam WFI_TIMEOUT_BIT = 32'd16;
 
-// Peripheral Addresses
+// Peripheral Physical Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-localparam DTIM_SUPPORTED = 1'b1;
-localparam logic [63:0] DTIM_BASE       = 64'h80000000;
-localparam logic [63:0] DTIM_RANGE      = 64'h007FFFFF;
-localparam IROM_SUPPORTED = 1'b1;
-localparam logic [63:0] IROM_BASE       = 64'h80000000;
-localparam logic [63:0] IROM_RANGE      = 64'h007FFFFF;
-localparam BOOTROM_SUPPORTED = 1'b0;
-localparam logic [63:0] BOOTROM_BASE   = 64'h00001000;
-localparam logic [63:0] BOOTROM_RANGE  = 64'h00000FFF;
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+localparam logic DTIM_SUPPORTED = 1;
+localparam logic [63:0] DTIM_BASE          = 64'h80000000;
+localparam logic [63:0] DTIM_RANGE         = 64'h007FFFFF;
+localparam logic IROM_SUPPORTED = 1;
+localparam logic [63:0] IROM_BASE          = 64'h80000000;
+localparam logic [63:0] IROM_RANGE         = 64'h007FFFFF;
+localparam logic BOOTROM_SUPPORTED = 0;
+localparam logic [63:0] BOOTROM_BASE       = 64'h00001000;
+localparam logic [63:0] BOOTROM_RANGE      = 64'h00000FFF;
 localparam BOOTROM_PRELOAD = 1'b0;
-localparam UNCORE_RAM_SUPPORTED = 1'b0;
-localparam logic [63:0] UNCORE_RAM_BASE       = 64'h80000000;
-localparam logic [63:0] UNCORE_RAM_RANGE      = 64'h07FFFFFF;
+localparam logic UNCORE_RAM_SUPPORTED = 0;
+localparam logic [63:0] UNCORE_RAM_BASE    = 64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE   = 64'h07FFFFFF;
 localparam UNCORE_RAM_PRELOAD = 1'b0;
-localparam EXT_MEM_SUPPORTED = 1'b0;
+localparam logic EXT_MEM_SUPPORTED = 0;
 localparam logic [63:0] EXT_MEM_BASE       = 64'h80000000;
 localparam logic [63:0] EXT_MEM_RANGE      = 64'h07FFFFFF;
-localparam CLINT_SUPPORTED = 1'b0;
-localparam logic [63:0] CLINT_BASE  = 64'h02000000;
-localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
-localparam GPIO_SUPPORTED = 1'b0;
-localparam logic [63:0] GPIO_BASE   = 64'h10060000;
-localparam logic [63:0] GPIO_RANGE  = 64'h000000FF;
-localparam UART_SUPPORTED = 1'b0;
-localparam logic [63:0] UART_BASE   = 64'h10000000;
-localparam logic [63:0] UART_RANGE  = 64'h00000007;
-localparam PLIC_SUPPORTED = 1'b0;
-localparam logic [63:0] PLIC_BASE   = 64'h0C000000;
-localparam logic [63:0] PLIC_RANGE  = 64'h03FFFFFF;
-localparam  SDC_SUPPORTED = 1'b0;
-localparam logic [63:0] SDC_BASE =  64'h00013000;
-localparam logic [63:0] SDC_RANGE = 64'h0000007F;
-localparam SPI_SUPPORTED = 1'b0;
-localparam logic [63:0] SPI_BASE = 64'h10040000;
-localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
+localparam logic CLINT_SUPPORTED = 0;
+localparam logic [63:0] CLINT_BASE         = 64'h02000000;
+localparam logic [63:0] CLINT_RANGE        = 64'h0000FFFF;
+localparam logic GPIO_SUPPORTED = 0;
+localparam logic [63:0] GPIO_BASE          = 64'h10060000;
+localparam logic [63:0] GPIO_RANGE         = 64'h000000FF;
+localparam logic UART_SUPPORTED = 0;
+localparam logic [63:0] UART_BASE          = 64'h10000000;
+localparam logic [63:0] UART_RANGE         = 64'h00000007;
+localparam logic PLIC_SUPPORTED = 0;
+localparam logic [63:0] PLIC_BASE          = 64'h0C000000;
+localparam logic [63:0] PLIC_RANGE         = 64'h03FFFFFF;
+localparam logic SDC_SUPPORTED = 0;
+localparam logic [63:0] SDC_BASE           = 64'h00013000;
+localparam logic [63:0] SDC_RANGE          = 64'h0000007F;
+localparam logic SPI_SUPPORTED = 0;
+localparam logic [63:0] SPI_BASE           = 64'h10040000;
+localparam logic [63:0] SPI_RANGE          = 64'h00000FFF;
+localparam logic PLL_SUPPORTED = 1'b0;
+localparam logic [63:0] PLL_CONF_BASE      = 64'h00020000;
+localparam logic [63:0] PLL_CONF_RANGE     = 64'h000000FF;
+localparam logic BSG_DMC_SUPPORTED = 1'b0;
+localparam logic [63:0] BSG_DMC_CONF_BASE  = 64'h00030000;
+localparam logic [63:0] BSG_DMC_CONF_RANGE = 64'h000000FF;
+// Debug program buffer support is enabled with DEBUG_SUPPORTED
+localparam logic [63:0] PROGBUF_BASE     = 64'h00002000;
+localparam logic [63:0] PROGBUF_RANGE    = 64'h0000000F;
 
 // Bus Interface width
-localparam AHBW = 32'd32;
+localparam AHBW = (XLEN);
 
 // Test modes
 
 // AHB 
 localparam RAM_LATENCY = 32'b0;
-localparam BURST_EN    = 1;
+localparam logic BURST_EN = 1;
 
 // Tie GPIO outputs back to inputs
-localparam GPIO_LOOPBACK_TEST = 1;
-localparam SPI_LOOPBACK_TEST = 1;
+localparam logic GPIO_LOOPBACK_TEST = 1;
+localparam logic SPI_LOOPBACK_TEST  = 1;
 
 // Hardware configuration
 localparam UART_PRESCALE = 32'd1;
@@ -150,10 +219,10 @@ localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
 localparam PLIC_GPIO_ID = 32'd3;
 localparam PLIC_UART_ID = 32'd10;
 localparam PLIC_SPI_ID = 32'd6;
-
 localparam PLIC_SDC_ID = 32'd9;
 
-localparam BPRED_SUPPORTED = 0;
+// Branch prediction
+localparam logic BPRED_SUPPORTED = 0;
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 localparam BPRED_SIZE = 32'd10;
 localparam BPRED_NUM_LHR = 32'd6;
@@ -161,35 +230,11 @@ localparam BTB_SIZE = 32'd10;
 localparam RAS_SIZE = 32'd16;
 localparam INSTR_CLASS_PRED = 0;
 
-localparam SVADU_SUPPORTED = 0;
-localparam ZMMUL_SUPPORTED = 0;
-
 // FPU division architecture
-localparam RADIX = 32'h4;
-localparam DIVCOPIES = 32'h4;
-
-// bit manipulation
-localparam ZBA_SUPPORTED = 0;
-localparam ZBB_SUPPORTED = 0;
-localparam ZBC_SUPPORTED = 0;
-localparam ZBS_SUPPORTED = 0;
-
-// New compressed instructions
-localparam ZCB_SUPPORTED = 0;
-localparam ZCA_SUPPORTED = 0;
-localparam ZCF_SUPPORTED = 0;
-localparam ZCD_SUPPORTED = 0;
-
-// K extension instructions                                                                
-localparam ZBKB_SUPPORTED = 0;
-localparam ZBKC_SUPPORTED = 0;
-localparam ZBKX_SUPPORTED = 0;
-localparam ZKNE_SUPPORTED = 0;
-localparam ZKND_SUPPORTED = 0;
-localparam ZK_SUPPORTED = 0;
-localparam ZKNH_SUPPORTED = 0;
+localparam RADIX = 32'd4;
+localparam DIVCOPIES = 32'd4;
 
 // Memory synthesis configuration
-localparam USE_SRAM = 0;
+localparam logic USE_SRAM = 0;
 
 `include "config-shared.vh"
diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh
index 357eba840..32504a45b 100644
--- a/config/rv32imc/config.vh
+++ b/config/rv32imc/config.vh
@@ -2,10 +2,10 @@
 // config.vh
 //
 // Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
+// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
 //
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
+// Purpose: Specify which features of Wally are enabled and set
+//          configuration parameters
 // 
 // A component of the Wally configurable RISC-V project.
 // 
@@ -33,31 +33,91 @@ localparam XLEN = 32'd32;
 // IEEE 754 compliance
 localparam IEEE754 = 0;
 
-localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12);
-localparam ZICSR_SUPPORTED = 1;
-localparam ZIFENCEI_SUPPORTED = 1;
+// Debug Module implemented                                                                                                          
+localparam logic DEBUG_SUPPORTED = 1'b0;
+
+// RISC-V configuration per specification
+// Base instruction set (defaults to I if E is not supported)
+localparam logic E_SUPPORTED = 0;
+
+// Integer instruction set extensions
+localparam logic ZIFENCEI_SUPPORTED = 1; // Instruction-Fetch fence
+localparam logic ZICSR_SUPPORTED    = 1; // CSR Instructions
+localparam logic ZICCLSM_SUPPORTED  = 0; // Misaligned loads/stores
+localparam logic ZICOND_SUPPORTED   = 0; // Integer conditional operations
+
+// Multiplication & division extensions
+// M implies (and in the configuration file requires) Zmmul
+localparam logic M_SUPPORTED     = 1;
+localparam logic ZMMUL_SUPPORTED = 1;
+
+// Atomic extensions
+// A extension is Zaamo + Zalrsc
+localparam logic ZAAMO_SUPPORTED  = 0;
+localparam logic ZALRSC_SUPPORTED = 0;
+
+// Bit manipulation extensions
+// B extension is Zba + Zbb + Zbs
+localparam logic ZBA_SUPPORTED = 0;
+localparam logic ZBB_SUPPORTED = 0;
+localparam logic ZBS_SUPPORTED = 0;
+localparam logic ZBC_SUPPORTED = 0;
+
+// Scalar crypto extensions
+// Zkn is all 6 of these
+localparam logic ZBKB_SUPPORTED = 0;
+localparam logic ZBKC_SUPPORTED = 0;
+localparam logic ZBKX_SUPPORTED = 0;
+localparam logic ZKND_SUPPORTED = 0;
+localparam logic ZKNE_SUPPORTED = 0;
+localparam logic ZKNH_SUPPORTED = 0;
+
+// Compressed extensions
+// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
+// All compressed extensions require Zca
+localparam logic ZCA_SUPPORTED = 1;
+localparam logic ZCB_SUPPORTED = 0;
+localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
+localparam logic ZCD_SUPPORTED = 0; // requires D
+
+// Floating point extensions
+localparam logic F_SUPPORTED   = 0;
+localparam logic D_SUPPORTED   = 0;
+localparam logic Q_SUPPORTED   = 0;
+localparam logic ZFH_SUPPORTED = 0;
+localparam logic ZFA_SUPPORTED = 0;
+
+// privilege modes
+localparam logic S_SUPPORTED = 1; // Supervisor mode
+localparam logic U_SUPPORTED = 1; // User mode
+
+// Supervisor level extensions
+localparam logic SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
+
+// Hardware performance counters
+localparam logic ZICNTR_SUPPORTED = 1;
+localparam logic ZIHPM_SUPPORTED  = 1;
 localparam COUNTERS = 12'd32;
-localparam ZICNTR_SUPPORTED = 1;
-localparam ZIHPM_SUPPORTED = 1;
-localparam ZFH_SUPPORTED = 0;
-localparam ZFA_SUPPORTED = 0;
-localparam SSTC_SUPPORTED = 0;
-localparam ZICBOM_SUPPORTED = 0;
-localparam ZICBOZ_SUPPORTED = 0;
-localparam ZICBOP_SUPPORTED = 0;
-localparam ZICCLSM_SUPPORTED = 0;
-localparam ZICOND_SUPPORTED = 0;
-localparam SVPBMT_SUPPORTED = 0;
-localparam SVNAPOT_SUPPORTED = 0;
-localparam SVINVAL_SUPPORTED = 0;
+
+// Cache-management operation extensions
+localparam logic ZICBOM_SUPPORTED = 0;
+localparam logic ZICBOZ_SUPPORTED = 0;
+localparam logic ZICBOP_SUPPORTED = 0;
+
+// Virtual memory extensions
+localparam logic SVPBMT_SUPPORTED  = 0;
+localparam logic SVNAPOT_SUPPORTED = 0;
+localparam logic SVINVAL_SUPPORTED = 0;
+localparam logic SVADU_SUPPORTED   = 0;
+
 
 // LSU microarchitectural Features
-localparam BUS_SUPPORTED = 1;
-localparam DCACHE_SUPPORTED = 0;
-localparam ICACHE_SUPPORTED = 0;
-localparam VIRTMEM_SUPPORTED = 0;
-localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
-localparam BIGENDIAN_SUPPORTED = 0;
+localparam logic BUS_SUPPORTED = 1;
+localparam logic DCACHE_SUPPORTED = 0;
+localparam logic ICACHE_SUPPORTED = 0;
+localparam logic VIRTMEM_SUPPORTED = 0;
+localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
+localparam logic BIGENDIAN_SUPPORTED = 0;
 
 // TLB configuration.  Entries should be a power of 2
 localparam ITLB_ENTRIES = 32'd0;
@@ -76,7 +136,7 @@ localparam CACHE_SRAMLEN = 32'd128;
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 localparam IDIV_BITSPERCYCLE = 32'd2;
-localparam IDIV_ON_FPU = 0;
+localparam logic IDIV_ON_FPU = 0;
 
 // Legal number of PMP entries are 0, 16, or 64
 localparam PMP_ENTRIES = 32'd0;
@@ -87,57 +147,67 @@ localparam logic [63:0] RESET_VECTOR = 64'h80000000;
 // WFI Timeout Wait
 localparam WFI_TIMEOUT_BIT = 32'd16;
 
-// Peripheral Addresses
+// Peripheral Physical Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-localparam DTIM_SUPPORTED = 1'b1;
-localparam logic [63:0] DTIM_BASE       = 64'h80000000;
-localparam logic [63:0] DTIM_RANGE      = 64'h007FFFFF;
-localparam IROM_SUPPORTED = 1'b1;
-localparam logic [63:0] IROM_BASE       = 64'h80000000;
-localparam logic [63:0] IROM_RANGE      = 64'h007FFFFF;
-localparam BOOTROM_SUPPORTED = 1'b0;
-localparam logic [63:0] BOOTROM_BASE   = 64'h00001000;
-localparam logic [63:0] BOOTROM_RANGE  = 64'h00000FFF;
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+localparam logic DTIM_SUPPORTED = 1;
+localparam logic [63:0] DTIM_BASE          = 64'h80000000;
+localparam logic [63:0] DTIM_RANGE         = 64'h007FFFFF;
+localparam logic IROM_SUPPORTED = 1;
+localparam logic [63:0] IROM_BASE          = 64'h80000000;
+localparam logic [63:0] IROM_RANGE         = 64'h007FFFFF;
+localparam logic BOOTROM_SUPPORTED = 0;
+localparam logic [63:0] BOOTROM_BASE       = 64'h00001000;
+localparam logic [63:0] BOOTROM_RANGE      = 64'h00000FFF;
 localparam BOOTROM_PRELOAD = 1'b0;
-localparam UNCORE_RAM_SUPPORTED = 1'b0;
-localparam logic [63:0] UNCORE_RAM_BASE       = 64'h80000000;
-localparam logic [63:0] UNCORE_RAM_RANGE      = 64'h07FFFFFF;
+localparam logic UNCORE_RAM_SUPPORTED = 0;
+localparam logic [63:0] UNCORE_RAM_BASE    = 64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE   = 64'h07FFFFFF;
 localparam UNCORE_RAM_PRELOAD = 1'b0;
-localparam EXT_MEM_SUPPORTED = 1'b0;
+localparam logic EXT_MEM_SUPPORTED = 0;
 localparam logic [63:0] EXT_MEM_BASE       = 64'h80000000;
 localparam logic [63:0] EXT_MEM_RANGE      = 64'h07FFFFFF;
-localparam CLINT_SUPPORTED = 1'b1;
-localparam logic [63:0] CLINT_BASE  = 64'h02000000;
-localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
-localparam GPIO_SUPPORTED = 1'b1;
-localparam logic [63:0] GPIO_BASE   = 64'h10060000;
-localparam logic [63:0] GPIO_RANGE  = 64'h000000FF;
-localparam UART_SUPPORTED = 1'b1;
-localparam logic [63:0] UART_BASE   = 64'h10000000;
-localparam logic [63:0] UART_RANGE  = 64'h00000007;
-localparam PLIC_SUPPORTED = 1'b1;
-localparam logic [63:0] PLIC_BASE   = 64'h0C000000;
-localparam logic [63:0] PLIC_RANGE  = 64'h03FFFFFF;
-localparam  SDC_SUPPORTED = 1'b0;
-localparam logic [63:0] SDC_BASE =  64'h00013000;
-localparam logic [63:0] SDC_RANGE = 64'h0000007F;
-localparam SPI_SUPPORTED = 1'b1;
-localparam logic [63:0] SPI_BASE = 64'h10040000;
-localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
+localparam logic CLINT_SUPPORTED = 1;
+localparam logic [63:0] CLINT_BASE         = 64'h02000000;
+localparam logic [63:0] CLINT_RANGE        = 64'h0000FFFF;
+localparam logic GPIO_SUPPORTED = 1;
+localparam logic [63:0] GPIO_BASE          = 64'h10060000;
+localparam logic [63:0] GPIO_RANGE         = 64'h000000FF;
+localparam logic UART_SUPPORTED = 1;
+localparam logic [63:0] UART_BASE          = 64'h10000000;
+localparam logic [63:0] UART_RANGE         = 64'h00000007;
+localparam logic PLIC_SUPPORTED = 1;
+localparam logic [63:0] PLIC_BASE          = 64'h0C000000;
+localparam logic [63:0] PLIC_RANGE         = 64'h03FFFFFF;
+localparam logic SDC_SUPPORTED = 0;
+localparam logic [63:0] SDC_BASE           = 64'h00013000;
+localparam logic [63:0] SDC_RANGE          = 64'h0000007F;
+localparam logic SPI_SUPPORTED = 1;
+localparam logic [63:0] SPI_BASE           = 64'h10040000;
+localparam logic [63:0] SPI_RANGE          = 64'h00000FFF;
+localparam logic PLL_SUPPORTED = 1'b0;
+localparam logic [63:0] PLL_CONF_BASE      = 64'h00020000;
+localparam logic [63:0] PLL_CONF_RANGE     = 64'h000000FF;
+localparam logic BSG_DMC_SUPPORTED = 1'b0;
+localparam logic [63:0] BSG_DMC_CONF_BASE  = 64'h00030000;
+localparam logic [63:0] BSG_DMC_CONF_RANGE = 64'h000000FF;
+// Debug program buffer support is enabled with DEBUG_SUPPORTED
+localparam logic [63:0] PROGBUF_BASE     = 64'h00002000;
+localparam logic [63:0] PROGBUF_RANGE    = 64'h0000000F;
 
 // Bus Interface width
-localparam AHBW = 32'd32;
+localparam AHBW = (XLEN);
 
 // Test modes
 
 // AHB 
 localparam RAM_LATENCY = 32'b0;
-localparam BURST_EN    = 1;
+localparam logic BURST_EN = 1;
 
 // Tie GPIO outputs back to inputs
-localparam GPIO_LOOPBACK_TEST = 1;
-localparam SPI_LOOPBACK_TEST = 1;
+localparam logic GPIO_LOOPBACK_TEST = 1;
+localparam logic SPI_LOOPBACK_TEST  = 1;
 
 // Hardware configuration
 localparam UART_PRESCALE = 32'd1;
@@ -151,7 +221,8 @@ localparam PLIC_UART_ID = 32'd10;
 localparam PLIC_SPI_ID = 32'd6;
 localparam PLIC_SDC_ID = 32'd9;
 
-localparam BPRED_SUPPORTED = 0;
+// Branch prediction
+localparam logic BPRED_SUPPORTED = 0;
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 localparam BPRED_SIZE = 32'd10;
 localparam BPRED_NUM_LHR = 32'd6;
@@ -159,35 +230,11 @@ localparam BTB_SIZE = 32'd10;
 localparam RAS_SIZE = 32'd16;
 localparam INSTR_CLASS_PRED = 0;
 
-localparam SVADU_SUPPORTED = 0;
-localparam ZMMUL_SUPPORTED = 0;
-
 // FPU division architecture
-localparam RADIX = 32'h4;
-localparam DIVCOPIES = 32'h4;
-
-// bit manipulation
-localparam ZBA_SUPPORTED = 0;
-localparam ZBB_SUPPORTED = 0;
-localparam ZBC_SUPPORTED = 0;
-localparam ZBS_SUPPORTED = 0;
-
-// New compressed instructions
-localparam ZCB_SUPPORTED = 0;
-localparam ZCA_SUPPORTED = 0;
-localparam ZCF_SUPPORTED = 0;
-localparam ZCD_SUPPORTED = 0;
-
-// K extension instructions                                                                
-localparam ZBKB_SUPPORTED = 0;
-localparam ZBKC_SUPPORTED = 0;
-localparam ZBKX_SUPPORTED = 0;
-localparam ZKNE_SUPPORTED = 0;
-localparam ZKND_SUPPORTED = 0;
-localparam ZK_SUPPORTED = 0;
-localparam ZKNH_SUPPORTED = 0;
+localparam RADIX = 32'd4;
+localparam DIVCOPIES = 32'd4;
 
 // Memory synthesis configuration
-localparam USE_SRAM = 0;
+localparam logic USE_SRAM = 0;
 
 `include "config-shared.vh"
diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh
index 1d6c5e9f4..e64ef7fa0 100644
--- a/config/rv64gc/config.vh
+++ b/config/rv64gc/config.vh
@@ -2,10 +2,10 @@
 // config.vh
 //
 // Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
+// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
 //
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
+// Purpose: Specify which features of Wally are enabled and set
+//          configuration parameters
 // 
 // A component of the Wally configurable RISC-V project.
 // 
@@ -33,32 +33,91 @@ localparam XLEN = 32'd64;
 // IEEE 754 compliance
 localparam IEEE754 = 0;
 
-// MISA RISC-V configuration per specification
-localparam MISA = (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0);
-localparam ZICSR_SUPPORTED = 1;
-localparam ZIFENCEI_SUPPORTED = 1;
+// Debug Module implemented                                                                                                          
+localparam logic DEBUG_SUPPORTED = 1'b1;
+
+// RISC-V configuration per specification
+// Base instruction set (defaults to I if E is not supported)
+localparam logic E_SUPPORTED = 0;
+
+// Integer instruction set extensions
+localparam logic ZIFENCEI_SUPPORTED = 1; // Instruction-Fetch fence
+localparam logic ZICSR_SUPPORTED    = 1; // CSR Instructions
+localparam logic ZICCLSM_SUPPORTED  = 1; // Misaligned loads/stores
+localparam logic ZICOND_SUPPORTED   = 1; // Integer conditional operations
+
+// Multiplication & division extensions
+// M implies (and in the configuration file requires) Zmmul
+localparam logic M_SUPPORTED     = 1;
+localparam logic ZMMUL_SUPPORTED = 1;
+
+// Atomic extensions
+// A extension is Zaamo + Zalrsc
+localparam logic ZAAMO_SUPPORTED  = 1;
+localparam logic ZALRSC_SUPPORTED = 1;
+
+// Bit manipulation extensions
+// B extension is Zba + Zbb + Zbs
+localparam logic ZBA_SUPPORTED = 1;
+localparam logic ZBB_SUPPORTED = 1;
+localparam logic ZBS_SUPPORTED = 1;
+localparam logic ZBC_SUPPORTED = 1;
+
+// Scalar crypto extensions
+// Zkn is all 6 of these
+localparam logic ZBKB_SUPPORTED = 1;
+localparam logic ZBKC_SUPPORTED = 1;
+localparam logic ZBKX_SUPPORTED = 1;
+localparam logic ZKND_SUPPORTED = 1;
+localparam logic ZKNE_SUPPORTED = 1;
+localparam logic ZKNH_SUPPORTED = 1;
+
+// Compressed extensions
+// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
+// All compressed extensions require Zca
+localparam logic ZCA_SUPPORTED = 1;
+localparam logic ZCB_SUPPORTED = 1;
+localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
+localparam logic ZCD_SUPPORTED = 1; // requires D
+
+// Floating point extensions
+localparam logic F_SUPPORTED   = 1;
+localparam logic D_SUPPORTED   = 1;
+localparam logic Q_SUPPORTED   = 0;
+localparam logic ZFH_SUPPORTED = 1;
+localparam logic ZFA_SUPPORTED = 1;
+
+// privilege modes
+localparam logic S_SUPPORTED = 1; // Supervisor mode
+localparam logic U_SUPPORTED = 1; // User mode
+
+// Supervisor level extensions
+localparam logic SSTC_SUPPORTED = 1; // Supervisor-mode timer interrupts
+
+// Hardware performance counters
+localparam logic ZICNTR_SUPPORTED = 1;
+localparam logic ZIHPM_SUPPORTED  = 1;
 localparam COUNTERS = 12'd32;
-localparam ZICNTR_SUPPORTED = 1;
-localparam ZIHPM_SUPPORTED = 1;
-localparam ZFH_SUPPORTED = 1;
-localparam ZFA_SUPPORTED = 1;
-localparam SSTC_SUPPORTED = 1;
-localparam ZICBOM_SUPPORTED = 1;
-localparam ZICBOZ_SUPPORTED = 1;
-localparam ZICBOP_SUPPORTED = 1;
-localparam ZICCLSM_SUPPORTED = 1;
-localparam ZICOND_SUPPORTED = 1;
-localparam SVPBMT_SUPPORTED = 1;
-localparam SVNAPOT_SUPPORTED = 1;
-localparam SVINVAL_SUPPORTED = 1;
+
+// Cache-management operation extensions
+localparam logic ZICBOM_SUPPORTED = 1;
+localparam logic ZICBOZ_SUPPORTED = 1;
+localparam logic ZICBOP_SUPPORTED = 1;
+
+// Virtual memory extensions
+localparam logic SVPBMT_SUPPORTED  = 1;
+localparam logic SVNAPOT_SUPPORTED = 1;
+localparam logic SVINVAL_SUPPORTED = 1;
+localparam logic SVADU_SUPPORTED   = 1;
+
 
 // LSU microarchitectural Features
-localparam BUS_SUPPORTED = 1;
-localparam DCACHE_SUPPORTED = 1;
-localparam ICACHE_SUPPORTED = 1;
-localparam VIRTMEM_SUPPORTED = 1;
-localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
-localparam BIGENDIAN_SUPPORTED = 1;
+localparam logic BUS_SUPPORTED = 1;
+localparam logic DCACHE_SUPPORTED = 1;
+localparam logic ICACHE_SUPPORTED = 1;
+localparam logic VIRTMEM_SUPPORTED = 1;
+localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
+localparam logic BIGENDIAN_SUPPORTED = 1;
 
 // TLB configuration.  Entries should be a power of 2
 localparam ITLB_ENTRIES = 32'd32;
@@ -77,7 +136,7 @@ localparam CACHE_SRAMLEN = 32'd128;
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 localparam IDIV_BITSPERCYCLE = 32'd4;
-localparam IDIV_ON_FPU = 1;
+localparam logic IDIV_ON_FPU = 1;
 
 // Legal number of PMP entries are 0, 16, or 64
 localparam PMP_ENTRIES = 32'd16;
@@ -85,62 +144,70 @@ localparam PMP_ENTRIES = 32'd16;
 // Address space
 localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
 
-// Bus Interface width
-localparam AHBW = 32'd64;
-
 // WFI Timeout Wait
 localparam WFI_TIMEOUT_BIT = 32'd16;
 
 // Peripheral Physical Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-
 // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
-localparam DTIM_SUPPORTED = 1'b0;
-localparam logic [63:0] DTIM_BASE =       64'h80000000;
-localparam logic [63:0] DTIM_RANGE =      64'h007FFFFF;
-localparam IROM_SUPPORTED = 1'b0;
-localparam logic [63:0] IROM_BASE =       64'h80000000;
-localparam logic [63:0] IROM_RANGE =      64'h007FFFFF;
-localparam BOOTROM_SUPPORTED = 1'b1;
-localparam logic [63:0] BOOTROM_BASE =   64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder;
-localparam logic [63:0] BOOTROM_RANGE =  64'h00000FFF;
+localparam logic DTIM_SUPPORTED = 0;
+localparam logic [63:0] DTIM_BASE          = 64'h80000000;
+localparam logic [63:0] DTIM_RANGE         = 64'h007FFFFF;
+localparam logic IROM_SUPPORTED = 0;
+localparam logic [63:0] IROM_BASE          = 64'h80000000;
+localparam logic [63:0] IROM_RANGE         = 64'h007FFFFF;
+localparam logic BOOTROM_SUPPORTED = 1;
+localparam logic [63:0] BOOTROM_BASE       = 64'h00001000;
+localparam logic [63:0] BOOTROM_RANGE      = 64'h00000FFF;
 localparam BOOTROM_PRELOAD = 1'b0;
-localparam UNCORE_RAM_SUPPORTED = 1'b1;
-localparam logic [63:0] UNCORE_RAM_BASE =       64'h80000000;
-localparam logic [63:0] UNCORE_RAM_RANGE =      64'h07FFFFFF;
+localparam logic UNCORE_RAM_SUPPORTED = 1;
+localparam logic [63:0] UNCORE_RAM_BASE    = 64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE   = 64'h07FFFFFF;
 localparam UNCORE_RAM_PRELOAD = 1'b0;
-localparam EXT_MEM_SUPPORTED = 1'b0;
-localparam logic [63:0] EXT_MEM_BASE =       64'h80000000;
-localparam logic [63:0] EXT_MEM_RANGE =      64'h07FFFFFF;
-localparam CLINT_SUPPORTED = 1'b1;
-localparam logic [63:0] CLINT_BASE =  64'h02000000;
-localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
-localparam GPIO_SUPPORTED = 1'b1;
-localparam logic [63:0] GPIO_BASE =   64'h10060000;
-localparam logic [63:0] GPIO_RANGE =  64'h000000FF;
-localparam UART_SUPPORTED = 1'b1;
-localparam logic [63:0] UART_BASE =   64'h10000000;
-localparam logic [63:0] UART_RANGE =  64'h00000007;
-localparam PLIC_SUPPORTED = 1'b1;
-localparam logic [63:0] PLIC_BASE =   64'h0C000000;
-localparam logic [63:0] PLIC_RANGE =  64'h03FFFFFF;
-localparam  SDC_SUPPORTED = 1'b0;
-localparam logic [63:0] SDC_BASE =  64'h00013000;
-localparam logic [63:0] SDC_RANGE = 64'h0000007F;
-localparam SPI_SUPPORTED = 1'b1;
-localparam logic [63:0] SPI_BASE = 64'h10040000;
-localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
+localparam logic EXT_MEM_SUPPORTED = 0;
+localparam logic [63:0] EXT_MEM_BASE       = 64'h80000000;
+localparam logic [63:0] EXT_MEM_RANGE      = 64'h07FFFFFF;
+localparam logic CLINT_SUPPORTED = 1;
+localparam logic [63:0] CLINT_BASE         = 64'h02000000;
+localparam logic [63:0] CLINT_RANGE        = 64'h0000FFFF;
+localparam logic GPIO_SUPPORTED = 1;
+localparam logic [63:0] GPIO_BASE          = 64'h10060000;
+localparam logic [63:0] GPIO_RANGE         = 64'h000000FF;
+localparam logic UART_SUPPORTED = 1;
+localparam logic [63:0] UART_BASE          = 64'h10000000;
+localparam logic [63:0] UART_RANGE         = 64'h00000007;
+localparam logic PLIC_SUPPORTED = 1;
+localparam logic [63:0] PLIC_BASE          = 64'h0C000000;
+localparam logic [63:0] PLIC_RANGE         = 64'h03FFFFFF;
+localparam logic SDC_SUPPORTED = 0;
+localparam logic [63:0] SDC_BASE           = 64'h00013000;
+localparam logic [63:0] SDC_RANGE          = 64'h0000007F;
+localparam logic SPI_SUPPORTED = 1;
+localparam logic [63:0] SPI_BASE           = 64'h10040000;
+localparam logic [63:0] SPI_RANGE          = 64'h00000FFF;
+localparam logic PLL_SUPPORTED = 1'b0;
+localparam logic [63:0] PLL_CONF_BASE      = 64'h00020000;
+localparam logic [63:0] PLL_CONF_RANGE     = 64'h000000FF;
+localparam logic BSG_DMC_SUPPORTED = 1'b0;
+localparam logic [63:0] BSG_DMC_CONF_BASE  = 64'h00030000;
+localparam logic [63:0] BSG_DMC_CONF_RANGE = 64'h000000FF;
+// Debug program buffer support is enabled with DEBUG_SUPPORTED
+localparam logic [63:0] PROGBUF_BASE     = 64'h00002000;
+localparam logic [63:0] PROGBUF_RANGE    = 64'h0000000F;
+
+// Bus Interface width
+localparam AHBW = (XLEN);
 
 // Test modes
 
 // AHB 
 localparam RAM_LATENCY = 32'b0;
-localparam BURST_EN    = 1;
+localparam logic BURST_EN = 1;
 
 // Tie GPIO outputs back to inputs
-localparam GPIO_LOOPBACK_TEST = 1;
-localparam SPI_LOOPBACK_TEST = 1;
+localparam logic GPIO_LOOPBACK_TEST = 1;
+localparam logic SPI_LOOPBACK_TEST  = 1;
 
 // Hardware configuration
 localparam UART_PRESCALE = 32'd1;
@@ -154,44 +221,20 @@ localparam PLIC_UART_ID = 32'd10;
 localparam PLIC_SPI_ID = 32'd6;
 localparam PLIC_SDC_ID = 32'd9;
 
-localparam BPRED_SUPPORTED = 1;
+// Branch prediction
+localparam logic BPRED_SUPPORTED = 1;
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-localparam BPRED_NUM_LHR = 32'd6;
 localparam BPRED_SIZE = 32'd10;
+localparam BPRED_NUM_LHR = 32'd6;
 localparam BTB_SIZE = 32'd10;
 localparam RAS_SIZE = 32'd16;
 localparam INSTR_CLASS_PRED = 1;
 
-localparam SVADU_SUPPORTED = 1;
-localparam ZMMUL_SUPPORTED = 0;
-
 // FPU division architecture
-localparam RADIX = 32'h4;
-localparam DIVCOPIES = 32'h4;
-
-// bit manipulation
-localparam ZBA_SUPPORTED = 1;
-localparam ZBB_SUPPORTED = 1;
-localparam ZBC_SUPPORTED = 1;
-localparam ZBS_SUPPORTED = 1;
-
-// New compressed instructions
-localparam ZCB_SUPPORTED = 1;
-localparam ZCA_SUPPORTED = 0;
-localparam ZCF_SUPPORTED = 0;
-localparam ZCD_SUPPORTED = 0;
-
-// K extension instructions                                                                
-localparam ZBKB_SUPPORTED = 1;
-localparam ZBKC_SUPPORTED = 1;
-localparam ZBKX_SUPPORTED = 1;
-localparam ZKND_SUPPORTED = 1;
-localparam ZKNE_SUPPORTED = 1;
-localparam ZKNH_SUPPORTED = 1;
-localparam ZK_SUPPORTED = 1;
+localparam RADIX = 32'd4;
+localparam DIVCOPIES = 32'd4;
 
 // Memory synthesis configuration
-localparam USE_SRAM = 0;
+localparam logic USE_SRAM = 0;
 
 `include "config-shared.vh"
-
diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh
index a289003cc..4afc77f11 100644
--- a/config/rv64i/config.vh
+++ b/config/rv64i/config.vh
@@ -2,10 +2,10 @@
 // config.vh
 //
 // Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
+// Modified: Jordan Carlin jcarlin@hmc.edu 14 May 2024
 //
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
+// Purpose: Specify which features of Wally are enabled and set
+//          configuration parameters
 // 
 // A component of the Wally configurable RISC-V project.
 // 
@@ -33,32 +33,91 @@ localparam XLEN = 32'd64;
 // IEEE 754 compliance
 localparam IEEE754 = 0;
 
-// MISA RISC-V configuration per specification
-localparam MISA = (32'h00000100);
-localparam ZICSR_SUPPORTED = 0;
-localparam ZIFENCEI_SUPPORTED = 0;
-localparam COUNTERS = 0;
-localparam ZICNTR_SUPPORTED = 0;
-localparam ZIHPM_SUPPORTED = 0;
-localparam ZFH_SUPPORTED = 0;
-localparam ZFA_SUPPORTED = 0;
-localparam SSTC_SUPPORTED = 0;
-localparam ZICBOM_SUPPORTED = 0;
-localparam ZICBOZ_SUPPORTED = 0;
-localparam ZICBOP_SUPPORTED = 0;
-localparam ZICCLSM_SUPPORTED = 0;
-localparam ZICOND_SUPPORTED = 0;
-localparam SVPBMT_SUPPORTED = 0;
-localparam SVNAPOT_SUPPORTED = 0;
-localparam SVINVAL_SUPPORTED = 0;
+// Debug Module implemented                                                                                                          
+localparam logic DEBUG_SUPPORTED = 1'b0;
+
+// RISC-V configuration per specification
+// Base instruction set (defaults to I if E is not supported)
+localparam logic E_SUPPORTED = 0;
+
+// Integer instruction set extensions
+localparam logic ZIFENCEI_SUPPORTED = 0; // Instruction-Fetch fence
+localparam logic ZICSR_SUPPORTED    = 0; // CSR Instructions
+localparam logic ZICCLSM_SUPPORTED  = 0; // Misaligned loads/stores
+localparam logic ZICOND_SUPPORTED   = 0; // Integer conditional operations
+
+// Multiplication & division extensions
+// M implies (and in the configuration file requires) Zmmul
+localparam logic M_SUPPORTED     = 0;
+localparam logic ZMMUL_SUPPORTED = 0;
+
+// Atomic extensions
+// A extension is Zaamo + Zalrsc
+localparam logic ZAAMO_SUPPORTED  = 0;
+localparam logic ZALRSC_SUPPORTED = 0;
+
+// Bit manipulation extensions
+// B extension is Zba + Zbb + Zbs
+localparam logic ZBA_SUPPORTED = 0;
+localparam logic ZBB_SUPPORTED = 0;
+localparam logic ZBS_SUPPORTED = 0;
+localparam logic ZBC_SUPPORTED = 0;
+
+// Scalar crypto extensions
+// Zkn is all 6 of these
+localparam logic ZBKB_SUPPORTED = 0;
+localparam logic ZBKC_SUPPORTED = 0;
+localparam logic ZBKX_SUPPORTED = 0;
+localparam logic ZKND_SUPPORTED = 0;
+localparam logic ZKNE_SUPPORTED = 0;
+localparam logic ZKNH_SUPPORTED = 0;
+
+// Compressed extensions
+// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
+// All compressed extensions require Zca
+localparam logic ZCA_SUPPORTED = 0;
+localparam logic ZCB_SUPPORTED = 0;
+localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
+localparam logic ZCD_SUPPORTED = 0; // requires D
+
+// Floating point extensions
+localparam logic F_SUPPORTED   = 0;
+localparam logic D_SUPPORTED   = 0;
+localparam logic Q_SUPPORTED   = 0;
+localparam logic ZFH_SUPPORTED = 0;
+localparam logic ZFA_SUPPORTED = 0;
+
+// privilege modes
+localparam logic S_SUPPORTED = 0; // Supervisor mode
+localparam logic U_SUPPORTED = 0; // User mode
+
+// Supervisor level extensions
+localparam logic SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
+
+// Hardware performance counters
+localparam logic ZICNTR_SUPPORTED = 0;
+localparam logic ZIHPM_SUPPORTED  = 0;
+localparam COUNTERS = 12'd0;
+
+// Cache-management operation extensions
+localparam logic ZICBOM_SUPPORTED = 0;
+localparam logic ZICBOZ_SUPPORTED = 0;
+localparam logic ZICBOP_SUPPORTED = 0;
+
+// Virtual memory extensions
+localparam logic SVPBMT_SUPPORTED  = 0;
+localparam logic SVNAPOT_SUPPORTED = 0;
+localparam logic SVINVAL_SUPPORTED = 0;
+localparam logic SVADU_SUPPORTED   = 0;
+
 
 // LSU microarchitectural Features
-localparam BUS_SUPPORTED = 0;
-localparam DCACHE_SUPPORTED = 0;
-localparam ICACHE_SUPPORTED = 0;
-localparam VIRTMEM_SUPPORTED = 0;
-localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
-localparam BIGENDIAN_SUPPORTED = 0;
+localparam logic BUS_SUPPORTED = 0;
+localparam logic DCACHE_SUPPORTED = 0;
+localparam logic ICACHE_SUPPORTED = 0;
+localparam logic VIRTMEM_SUPPORTED = 0;
+localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
+localparam logic BIGENDIAN_SUPPORTED = 0;
 
 // TLB configuration.  Entries should be a power of 2
 localparam ITLB_ENTRIES = 32'd0;
@@ -77,7 +136,7 @@ localparam CACHE_SRAMLEN = 32'd128;
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
 localparam IDIV_BITSPERCYCLE = 32'd4;
-localparam IDIV_ON_FPU = 0;
+localparam logic IDIV_ON_FPU = 0;
 
 // Legal number of PMP entries are 0, 16, or 64
 localparam PMP_ENTRIES = 32'd0;
@@ -85,62 +144,70 @@ localparam PMP_ENTRIES = 32'd0;
 // Address space
 localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
 
-// Bus Interface width
-localparam AHBW = (XLEN);
-
 // WFI Timeout Wait
 localparam WFI_TIMEOUT_BIT = 32'd16;
 
-// Peripheral Physiccal Addresses
+// Peripheral Physical Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-
 // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
-localparam DTIM_SUPPORTED = 1'b1;
-localparam logic [63:0] DTIM_BASE =       64'h80000000;
-localparam logic [63:0] DTIM_RANGE =      64'h007FFFFF;
-localparam IROM_SUPPORTED = 1'b1;
-localparam logic [63:0] IROM_BASE =       64'h80000000;
-localparam logic [63:0] IROM_RANGE =      64'h007FFFFF;
-localparam BOOTROM_SUPPORTED = 1'b0;
-localparam logic [63:0] BOOTROM_BASE =   64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-localparam logic [63:0] BOOTROM_RANGE =  64'h00000FFF;
+localparam logic DTIM_SUPPORTED = 1;
+localparam logic [63:0] DTIM_BASE          = 64'h80000000;
+localparam logic [63:0] DTIM_RANGE         = 64'h007FFFFF;
+localparam logic IROM_SUPPORTED = 1;
+localparam logic [63:0] IROM_BASE          = 64'h80000000;
+localparam logic [63:0] IROM_RANGE         = 64'h007FFFFF;
+localparam logic BOOTROM_SUPPORTED = 0;
+localparam logic [63:0] BOOTROM_BASE       = 64'h00001000;
+localparam logic [63:0] BOOTROM_RANGE      = 64'h00000FFF;
 localparam BOOTROM_PRELOAD = 1'b0;
-localparam UNCORE_RAM_SUPPORTED = 1'b0;
-localparam logic [63:0] UNCORE_RAM_BASE =       64'h80000000;
-localparam logic [63:0] UNCORE_RAM_RANGE =      64'h7FFFFFFF;
+localparam logic UNCORE_RAM_SUPPORTED = 0;
+localparam logic [63:0] UNCORE_RAM_BASE    = 64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE   = 64'h07FFFFFF;
 localparam UNCORE_RAM_PRELOAD = 1'b0;
-localparam EXT_MEM_SUPPORTED = 1'b0;
-localparam logic [63:0] EXT_MEM_BASE =       64'h80000000;
-localparam logic [63:0] EXT_MEM_RANGE =      64'h07FFFFFF;
-localparam CLINT_SUPPORTED = 1'b0;
-localparam logic [63:0] CLINT_BASE =  64'h02000000;
-localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
-localparam GPIO_SUPPORTED = 1'b0;
-localparam logic [63:0] GPIO_BASE =   64'h10060000;
-localparam logic [63:0] GPIO_RANGE =  64'h000000FF;
-localparam UART_SUPPORTED = 1'b0;
-localparam logic [63:0] UART_BASE =   64'h10000000;
-localparam logic [63:0] UART_RANGE =  64'h00000007;
-localparam PLIC_SUPPORTED = 1'b0;
-localparam logic [63:0] PLIC_BASE =   64'h0C000000;
-localparam logic [63:0] PLIC_RANGE =  64'h03FFFFFF;
-localparam SDC_SUPPORTED = 1'b0;
-localparam logic [63:0] SDC_BASE =  64'h00013000;
-localparam logic [63:0] SDC_RANGE = 64'h0000007F;
-localparam SPI_SUPPORTED = 1'b0;
-localparam logic [63:0] SPI_BASE = 64'h10040000;
-localparam logic [63:0] SPI_RANGE = 64'h00000FFF;
+localparam logic EXT_MEM_SUPPORTED = 0;
+localparam logic [63:0] EXT_MEM_BASE       = 64'h80000000;
+localparam logic [63:0] EXT_MEM_RANGE      = 64'h07FFFFFF;
+localparam logic CLINT_SUPPORTED = 0;
+localparam logic [63:0] CLINT_BASE         = 64'h02000000;
+localparam logic [63:0] CLINT_RANGE        = 64'h0000FFFF;
+localparam logic GPIO_SUPPORTED = 0;
+localparam logic [63:0] GPIO_BASE          = 64'h10060000;
+localparam logic [63:0] GPIO_RANGE         = 64'h000000FF;
+localparam logic UART_SUPPORTED = 0;
+localparam logic [63:0] UART_BASE          = 64'h10000000;
+localparam logic [63:0] UART_RANGE         = 64'h00000007;
+localparam logic PLIC_SUPPORTED = 0;
+localparam logic [63:0] PLIC_BASE          = 64'h0C000000;
+localparam logic [63:0] PLIC_RANGE         = 64'h03FFFFFF;
+localparam logic SDC_SUPPORTED = 0;
+localparam logic [63:0] SDC_BASE           = 64'h00013000;
+localparam logic [63:0] SDC_RANGE          = 64'h0000007F;
+localparam logic SPI_SUPPORTED = 0;
+localparam logic [63:0] SPI_BASE           = 64'h10040000;
+localparam logic [63:0] SPI_RANGE          = 64'h00000FFF;
+localparam logic PLL_SUPPORTED = 1'b0;
+localparam logic [63:0] PLL_CONF_BASE      = 64'h00020000;
+localparam logic [63:0] PLL_CONF_RANGE     = 64'h000000FF;
+localparam logic BSG_DMC_SUPPORTED = 1'b0;
+localparam logic [63:0] BSG_DMC_CONF_BASE  = 64'h00030000;
+localparam logic [63:0] BSG_DMC_CONF_RANGE = 64'h000000FF;
+// Debug program buffer support is enabled with DEBUG_SUPPORTED
+localparam logic [63:0] PROGBUF_BASE     = 64'h00002000;
+localparam logic [63:0] PROGBUF_RANGE    = 64'h0000000F;
+
+// Bus Interface width
+localparam AHBW = (XLEN);
 
 // Test modes
 
 // AHB 
 localparam RAM_LATENCY = 32'b0;
-localparam BURST_EN    = 1;
+localparam logic BURST_EN = 1;
 
 // Tie GPIO outputs back to inputs
-localparam GPIO_LOOPBACK_TEST = 1;
-localparam SPI_LOOPBACK_TEST = 1;
+localparam logic GPIO_LOOPBACK_TEST = 1;
+localparam logic SPI_LOOPBACK_TEST  = 1;
 
 // Hardware configuration
 localparam UART_PRESCALE = 32'd1;
@@ -154,7 +221,8 @@ localparam PLIC_UART_ID = 32'd10;
 localparam PLIC_SPI_ID = 32'd6;
 localparam PLIC_SDC_ID = 32'd9;
 
-localparam BPRED_SUPPORTED = 0;
+// Branch prediction
+localparam logic BPRED_SUPPORTED = 0;
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 localparam BPRED_SIZE = 32'd10;
 localparam BPRED_NUM_LHR = 32'd6;
@@ -162,35 +230,11 @@ localparam BTB_SIZE = 32'd10;
 localparam RAS_SIZE = 32'd16;
 localparam INSTR_CLASS_PRED = 0;
 
-localparam SVADU_SUPPORTED = 0;
-localparam ZMMUL_SUPPORTED = 0;
-
 // FPU division architecture
-localparam RADIX = 32'h4;
-localparam DIVCOPIES = 32'h4;
-
-// bit manipulation
-localparam ZBA_SUPPORTED = 0;
-localparam ZBB_SUPPORTED = 0;
-localparam ZBC_SUPPORTED = 0;
-localparam ZBS_SUPPORTED = 0;
-
-// New compressed instructions
-localparam ZCB_SUPPORTED = 0;
-localparam ZCA_SUPPORTED = 0;
-localparam ZCF_SUPPORTED = 0;
-localparam ZCD_SUPPORTED = 0;
-
-// K extension instructions                                                                
-localparam ZBKB_SUPPORTED = 0;
-localparam ZBKC_SUPPORTED = 0;
-localparam ZBKX_SUPPORTED = 0;
-localparam ZKNE_SUPPORTED = 0;
-localparam ZKND_SUPPORTED = 0;
-localparam ZK_SUPPORTED = 0;
-localparam ZKNH_SUPPORTED = 0;
+localparam RADIX = 32'd4;
+localparam DIVCOPIES = 32'd4;
 
 // Memory synthesis configuration
-localparam USE_SRAM = 0;
+localparam logic USE_SRAM = 0;
 
 `include "config-shared.vh"
diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh
index 481247eae..44bf77eac 100644
--- a/config/shared/config-shared.vh
+++ b/config/shared/config-shared.vh
@@ -24,20 +24,15 @@ localparam SV39 = 4'd8;
 localparam SV48 = 4'd9;
 
 // macros to define supported modes
-localparam A_SUPPORTED = ((MISA >> 0) % 2 == 1);
-localparam B_SUPPORTED = ((ZBA_SUPPORTED | ZBB_SUPPORTED | ZBC_SUPPORTED | ZBS_SUPPORTED));// not based on MISA
-localparam C_SUPPORTED = ((MISA >> 2) % 2 == 1);
-localparam COMPRESSED_SUPPORTED = C_SUPPORTED | ZCA_SUPPORTED;
-localparam D_SUPPORTED = ((MISA >> 3) % 2 == 1);
-localparam E_SUPPORTED = ((MISA >> 4) % 2 == 1);
-localparam F_SUPPORTED = ((MISA >> 5) % 2 == 1);
-localparam I_SUPPORTED = ((MISA >> 8) % 2 == 1);
-localparam K_SUPPORTED = ((ZBKB_SUPPORTED | ZBKC_SUPPORTED | ZBKX_SUPPORTED | ZKND_SUPPORTED | ZKNE_SUPPORTED | ZKNH_SUPPORTED));
-localparam M_SUPPORTED = ((MISA >> 12) % 2 == 1);
-localparam Q_SUPPORTED = ((MISA >> 16) % 2 == 1);
-localparam S_SUPPORTED = ((MISA >> 18) % 2 == 1);
-localparam U_SUPPORTED = ((MISA >> 20) % 2 == 1);
-// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
+localparam logic I_SUPPORTED = (!E_SUPPORTED);
+localparam logic A_SUPPORTED = (ZAAMO_SUPPORTED & ZALRSC_SUPPORTED);
+localparam logic B_SUPPORTED = ((ZBA_SUPPORTED & ZBB_SUPPORTED & ZBS_SUPPORTED));
+localparam logic C_SUPPORTED = ZCA_SUPPORTED & (D_SUPPORTED ? ZCD_SUPPORTED : 1) & (F_SUPPORTED ? ((XLEN == 32) ? ZCF_SUPPORTED : 1) : 1);
+localparam logic ZKN_SUPPORTED = (ZBKB_SUPPORTED & ZBKC_SUPPORTED & ZBKX_SUPPORTED & ZKND_SUPPORTED & ZKNE_SUPPORTED & ZKNH_SUPPORTED);
+
+// Configure MISA based on supported extensions
+localparam MISA = {6'b0, 5'b0, U_SUPPORTED, 1'b0, S_SUPPORTED, 1'b0, Q_SUPPORTED, 3'b0, M_SUPPORTED, 3'b0, I_SUPPORTED, 2'b0, 
+                   F_SUPPORTED, E_SUPPORTED, D_SUPPORTED, C_SUPPORTED, B_SUPPORTED, A_SUPPORTED};
 
 // logarithm of XLEN, used for number of index bits to select
 localparam LOG_XLEN = (XLEN == 32 ? 32'd5 : 32'd6);
@@ -75,6 +70,7 @@ localparam NE   = Q_SUPPORTED ? Q_NE   : D_SUPPORTED ? D_NE   : S_NE;
 localparam NF   = Q_SUPPORTED ? Q_NF   : D_SUPPORTED ? D_NF   : S_NF;
 localparam FMT  = Q_SUPPORTED ? 2'd3   : D_SUPPORTED ? 2'd1   : 2'd0;
 localparam BIAS = Q_SUPPORTED ? Q_BIAS : D_SUPPORTED ? D_BIAS : S_BIAS;
+localparam LOGFLEN = $clog2(FLEN);
 
 // Floating point constants needed for FPU paramerterization
 // LEN1/NE1/NF1/FNT1 is the size of the second longest supported format
@@ -99,7 +95,6 @@ localparam RK          = LOGR*DIVCOPIES;                            // r*k bits
 
 // intermediate division parameters not directly used in fdivsqrt hardware
 localparam FPDIVMINb   = NF + 2; // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit to allow sqrt being shifted right
-//localparam FPDIVMINb   = NF + 2 + (RADIX == 2); // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit for preshifting radix2 square root right, if radix4 doesn't use a right shift.  This version saves one cycle on double-precision with R=4,k=4.  However, it doesn't work yet because C is too short, so k is incorrectly calculated as a 1 in the lsb after the last step.
 localparam DIVMINb     = ((FPDIVMINb<XLEN) & IDIV_ON_FPU) ? XLEN : FPDIVMINb; // minimum fractional bits b = max(XLEN, FPDIVMINb)
 localparam RESBITS     = DIVMINb + LOGR; // number of bits in a result: r integer + b fractional
 
@@ -111,13 +106,17 @@ localparam DIVBLEN     = $clog2(DIVb+1);                            // enough bi
 
 // largest length in IEU/FPU
 localparam BASECVTLEN = `max(XLEN, NF); // convert length excluding Zfa fcvtmod.w.d
-localparam CVTLEN = ZFA_SUPPORTED ? `max(BASECVTLEN, 32'd84) : BASECVTLEN; // fcvtmod.w.d needs at least 32+52 because a double with 52 fractional bits might be into upper bits of 32 bit word
+localparam CVTLEN = (ZFA_SUPPORTED & D_SUPPORTED) ? `max(BASECVTLEN, 32'd84) : BASECVTLEN; // fcvtmod.w.d needs at least 32+52 because a double with 52 fractional bits might be into upper bits of 32 bit word
 localparam LLEN = `max($unsigned(FLEN), $unsigned(XLEN));
 localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
-localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (3*NF+6));
-localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ));
-localparam CORRSHIFTSZ = `max((NORMSHIFTSZ-2), (DIVMINb + 1 + NF));
 
+// size of FMA output in U(NF+4).(3NF+2) format
+localparam FMALEN = 3*NF + 6;
+
+// NORMSHIFTSIZE is the bits out of the normalization shifter
+localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (FMALEN + 2));
+
+localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ));                  // log_2(NORMSHIFTSZ)
 
 // Disable spurious Verilator warnings
 
diff --git a/config/shared/debug.vh b/config/shared/debug.vh
new file mode 100755
index 000000000..24091620b
--- /dev/null
+++ b/config/shared/debug.vh
@@ -0,0 +1,360 @@
+/////////////////////////////////////////// debug.vh
+// Written: matthew.n.otto@okstate.edu
+// Created: 15 March 2024
+// Purpose: debug port definitions
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You
+// may obtain a copy of the License at
+// https://solderpad.org/licenses/SHL-2.1/
+// Unless required by applicable law or agreed to in writing, any work distributed under the
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+// either express or implied. See the License for the specific language governing permissions
+// and limitations under the License.
+//////////////////////////////////////////////////////////////////////////////////////////////
+// DMI op field constants
+`define OP_NOP     2'b00
+`define OP_READ    2'b01
+`define OP_WRITE   2'b10
+`define OP_SUCCESS 2'b00
+`define OP_FAILED  2'b10
+`define OP_BUSY    2'b11
+
+// DMI Bus Address Width
+`define DMI_ADDR_WIDTH 7
+
+// Debug Module Debug Bus Register Addresses
+// DM Internal registers
+`define DATA0        `DMI_ADDR_WIDTH'h04
+`define DATA1        `DMI_ADDR_WIDTH'h05
+`define DATA2        `DMI_ADDR_WIDTH'h06
+`define DATA3        `DMI_ADDR_WIDTH'h07
+`define DATA4        `DMI_ADDR_WIDTH'h08
+`define DATA5        `DMI_ADDR_WIDTH'h09
+`define DATA6        `DMI_ADDR_WIDTH'h0A
+`define DATA7        `DMI_ADDR_WIDTH'h0B
+`define DATA8        `DMI_ADDR_WIDTH'h0C
+`define DATA9        `DMI_ADDR_WIDTH'h0D
+`define DATA10       `DMI_ADDR_WIDTH'h0E
+`define DATA11       `DMI_ADDR_WIDTH'h0F
+`define DMCONTROL    `DMI_ADDR_WIDTH'h10
+`define DMSTATUS     `DMI_ADDR_WIDTH'h11
+`define HARTINFO     `DMI_ADDR_WIDTH'h12
+`define ABSTRACTCS   `DMI_ADDR_WIDTH'h16
+`define COMMAND      `DMI_ADDR_WIDTH'h17
+`define ABSTRACTAUTO `DMI_ADDR_WIDTH'h18
+`define NEXTDM       `DMI_ADDR_WIDTH'h1d
+`define PROGBUF0     `DMI_ADDR_WIDTH'h20
+`define PROGBUF1     `DMI_ADDR_WIDTH'h21
+`define PROGBUF2     `DMI_ADDR_WIDTH'h22
+`define PROGBUF3     `DMI_ADDR_WIDTH'h23
+`define PROGBUF4     `DMI_ADDR_WIDTH'h24
+`define PROGBUF5     `DMI_ADDR_WIDTH'h25
+`define PROGBUF6     `DMI_ADDR_WIDTH'h26
+`define PROGBUF7     `DMI_ADDR_WIDTH'h27
+`define PROGBUF8     `DMI_ADDR_WIDTH'h28
+`define PROGBUF9     `DMI_ADDR_WIDTH'h29
+`define PROGBUFA     `DMI_ADDR_WIDTH'h2A
+`define PROGBUFB     `DMI_ADDR_WIDTH'h2B
+`define PROGBUFC     `DMI_ADDR_WIDTH'h2C
+`define PROGBUFD     `DMI_ADDR_WIDTH'h2D
+`define PROGBUFE     `DMI_ADDR_WIDTH'h2E
+`define PROGBUFF     `DMI_ADDR_WIDTH'h2F
+//`define dmcs2        `DMI_ADDR_WIDTH'h32
+`define SBCS         `DMI_ADDR_WIDTH'h38
+
+
+//// Register field ranges
+// DMCONTROL 0x10
+`define HALTREQ         31
+`define RESUMEREQ       30
+`define HARTRESET       29
+`define ACKHAVERESET    28
+`define ACKUNAVAIL      27
+`define HASEL           26
+`define HARTSELLO       25:16
+`define HARTSELHI       15:6
+`define SETKEEPALIVE    5
+`define CLRKEEPALIVE    4
+`define SETRESETHALTREQ 3
+`define CLRRESETHALTREQ 2
+`define NDMRESET        1
+`define DMACTIVE        0
+
+// DMSTATUS 0x11
+`define NDMRESETPENDING 24
+`define STICKYUNAVAIL   23
+`define IMPEBREAK       22
+`define ALLHAVERESET    19
+`define ANYHAVERESET    18
+`define ALLRESUMEACK    17
+`define ANYRESUMEACK    16
+`define ALLNONEXISTENT  15
+`define ANYNONEXISTENT  14
+`define ALLUNAVAIL      13
+`define ANYUNAVAIL      12
+`define ALLRUNNING      11
+`define ANYRUNNING      10
+`define ALLHALTED       9
+`define ANYHALTED       8
+`define AUTHENTICATED   7
+`define AUTHBUSY        6
+`define HASRESETHALTREQ 5
+`define CONFSTRPTRVALID 4
+`define VERSION         3:0
+
+// ABSTRACTCS 0x16
+`define PROGBUFSIZE 28:24
+`define BUSY        12
+`define RELAXEDPRIV 11
+`define CMDERR      10:8
+`define DATACOUNT   3:0
+
+// COMMAND 0x17
+`define CMDTYPE 31:24
+`define CONTROL 23:0
+
+// DCSR
+`define EBREAKVS  17
+`define EBREAKVU  16
+`define EBREAKM   15
+`define EBREAKS   13
+`define EBREAKU   12
+`define STEPIE    11
+`define STOPCOUNT 10
+`define STOPTIME  9
+`define V         5
+`define MPRVEN    4
+`define STEP      2
+`define PRV       1:0
+
+//// Abstract Commands
+// cmderr
+`define CMDERR_NONE          3'h0
+`define CMDERR_BUSY          3'h1
+`define CMDERR_NOT_SUPPORTED 3'h2
+`define CMDERR_EXCEPTION     3'h3
+`define CMDERR_HALTRESUME    3'h4
+`define CMDERR_BUS           3'h5
+`define CMDERR_OTHER         3'h7
+
+// Abstract CmdType Constants (3.7.1)
+`define ACCESS_REGISTER 0
+`define QUICK_ACCESS    1
+`define ACCESS_MEMORY   2
+
+// ACCESS_REGISTER Control ranges
+`define AARSIZE          22:20
+`define AARPOSTINCREMENT 19
+`define POSTEXEC         18
+`define TRANSFER         17
+`define AARWRITE         16
+`define REGNO            15:0
+
+// aarsize
+`define AAR32  2
+`define AAR64  3
+`define AAR128 4
+
+// debug mode cause
+`define CAUSE_EBREAK       3'h1
+`define CAUSE_TRIGGER      3'h2
+`define CAUSE_HALTREQ      3'h3
+`define CAUSE_STEP         3'h4
+`define CAUSE_RESETHALTREQ 3'h5
+`define CAUSE_GROUP        3'h6
+
+// Register Numbers (regno)
+// (Table 3.3)
+// 0x0000 – 0x0fff | CSRs. The “PC” can be accessed here through dpc.
+// 0x1000 – 0x101f | GPRs
+// 0x1020 – 0x103f | Floating point registers
+// 0xc000 – 0xffff | Reserved for non-standard extensions and internal use.
+
+// wallypipelinedcore
+`define TRAPM_REGNO       16'hC000 // 1'b  P.ZICSR_SUPPORTED (Read Only)
+// src/ifu
+`define PCM_REGNO         16'hC001 // XLEN P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED
+`define INSTRM_REGNO      16'hC002 // 32'b P.ZICSR_SUPPORTED | P.A_SUPPORTED
+// ieu/controller
+`define MEMRWM_REGNO      16'hC003 // 2'b
+`define INSTRVALIDM_REGNO 16'hC004 // 1'b
+// ieu/datapath
+`define WRITEDATAM_REGNO  16'hC005 // XLEN
+// lsu
+`define IEUADRM_REGNO     16'hC006 // XLEN
+`define READDATAM_REGNO   16'hC007 // LLEN (Read Only)
+
+// CSR
+// privileged/csru
+`define FFLAGS_REGNO         16'h0001
+`define FRM_REGNO            16'h0002
+`define FCSR_REGNO           16'h0003
+// privileged/csrm
+`define MSTATUS_REGNO        16'h0300
+`define MISA_REGNO           16'h0301
+`define MEDELEG_REGNO        16'h0302
+`define MIDELEG_REGNO        16'h0303
+`define MIE_REGNO            16'h0304
+`define MTVEC_REGNO          16'h0305
+`define MCOUNTEREN_REGNO     16'h0306
+
+`define MENVCFG_REGNO        16'h030A
+
+`define MSTATUSH_REGNO       16'h0310
+
+`define MENVCFGH_REGNO       16'h031A
+
+`define MCOUNTINHIBIT_REGNO  16'h0320
+
+`define MSCRATCH_REGNO       16'h0340
+`define MEPC_REGNO           16'h0341
+`define MCAUSE_REGNO         16'h0342
+`define MTVAL_REGNO          16'h0343
+`define MIP_REGNO            16'h0344
+
+`define PMPCFG0_REGNO        16'h03A0
+//range
+`define PMPCFGF_REGNO        16'h03AF
+`define PMPADDR0_REGNO       16'h03B0// P.PA_BITS
+//range
+`define PMPADDR3F_REGNO      16'h03EF
+
+`define TSELECT_REGNO        16'h07A0
+`define TDATA1_REGNO         16'h07A1
+`define TDATA2_REGNO         16'h07A2
+`define TDATA3_REGNO         16'h07A3
+
+`define DCSR_REGNO           16'h07B0
+`define DPC_REGNO            16'h07B1
+
+`define MVENDORID_REGNO      16'h0F11
+`define MARCHID_REGNO        16'h0F12
+`define MIMPID_REGNO         16'h0F13
+`define MHARTID_REGNO        16'h0F14
+`define MCONFIGPTR_REGNO     16'h0F15
+// privileged/csr
+`define SIP_REGNO            16'h0144
+`define MIP_REGNO            16'h0344
+// privileged/csrc
+`define MHPMEVENTBASE_REGNO    16'h0320
+
+`define MHPMCOUNTERBASE_REGNO  16'h0B00
+
+`define MHPMCOUNTERHBASE_REGNO 16'h0B80
+
+`define HPMCOUNTERBASE_REGNO   16'h0C00
+`define TIME_REGNO             16'h0C01
+
+`define HPMCOUNTERHBASE_REGNO  16'h0C80
+`define TIMEH_REGNO            16'h0C81
+// privileged/csrs
+`define SSTATUS_REGNO        16'h0100
+
+`define SIE_REGNO            16'h0104
+`define STVEC_REGNO          16'h0105
+`define SCOUNTEREN_REGNO     16'h0106
+
+`define SENVCFG_REGNO        16'h010A
+
+`define SSCRATCH_REGNO       16'h0140
+`define SEPC_REGNO           16'h0141
+`define SCAUSE_REGNO         16'h0142
+`define STVAL_REGNO          16'h0143
+`define SIP_REGNO            16'h0144
+
+`define STIMECMP_REGNO       16'h014D
+
+`define STIMECMPH_REGNO      16'h015D
+
+`define SATP_REGNO           16'h0180
+// privileged/csri
+`define SIE_REGNO            16'h0104
+`define SIP_REGNO            16'h0144
+`define MIE_REGNO            16'h0304
+`define MIP_REGNO            16'h0344
+
+// src/ieu/datapath
+`define X0_REGNO          16'h1000
+`define X1_REGNO          16'h1001
+`define X2_REGNO          16'h1002
+`define X3_REGNO          16'h1003
+`define X4_REGNO          16'h1004
+`define X5_REGNO          16'h1005
+`define X6_REGNO          16'h1006
+`define X7_REGNO          16'h1007
+`define X8_REGNO          16'h1008
+`define X9_REGNO          16'h1009
+`define X10_REGNO         16'h100A
+`define X11_REGNO         16'h100B
+`define X12_REGNO         16'h100C
+`define X13_REGNO         16'h100D
+`define X14_REGNO         16'h100E
+`define X15_REGNO         16'h100F
+`define X16_REGNO         16'h1010 // E_SUPPORTED
+`define X17_REGNO         16'h1011 // E_SUPPORTED
+`define X18_REGNO         16'h1012 // E_SUPPORTED
+`define X19_REGNO         16'h1013 // E_SUPPORTED
+`define X20_REGNO         16'h1014 // E_SUPPORTED
+`define X21_REGNO         16'h1015 // E_SUPPORTED
+`define X22_REGNO         16'h1016 // E_SUPPORTED
+`define X23_REGNO         16'h1017 // E_SUPPORTED
+`define X24_REGNO         16'h1018 // E_SUPPORTED
+`define X25_REGNO         16'h1019 // E_SUPPORTED
+`define X26_REGNO         16'h101A // E_SUPPORTED
+`define X27_REGNO         16'h101B // E_SUPPORTED
+`define X28_REGNO         16'h101C // E_SUPPORTED
+`define X29_REGNO         16'h101D // E_SUPPORTED
+`define X30_REGNO         16'h101E // E_SUPPORTED
+`define X31_REGNO         16'h101F // E_SUPPORTED
+
+// src/fpu/fpu
+`define FP0_REGNO         16'h1020 // F/D_SUPPORTED
+`define FP1_REGNO         16'h1021 // F/D_SUPPORTED
+`define FP2_REGNO         16'h1022 // F/D_SUPPORTED
+`define FP3_REGNO         16'h1023 // F/D_SUPPORTED
+`define FP4_REGNO         16'h1024 // F/D_SUPPORTED
+`define FP5_REGNO         16'h1025 // F/D_SUPPORTED
+`define FP6_REGNO         16'h1026 // F/D_SUPPORTED
+`define FP7_REGNO         16'h1027 // F/D_SUPPORTED
+`define FP8_REGNO         16'h1028 // F/D_SUPPORTED
+`define FP9_REGNO         16'h1029 // F/D_SUPPORTED
+`define FP10_REGNO        16'h102A // F/D_SUPPORTED
+`define FP11_REGNO        16'h102B // F/D_SUPPORTED
+`define FP12_REGNO        16'h102C // F/D_SUPPORTED
+`define FP13_REGNO        16'h102D // F/D_SUPPORTED
+`define FP14_REGNO        16'h102E // F/D_SUPPORTED
+`define FP15_REGNO        16'h102F // F/D_SUPPORTED
+`define FP16_REGNO        16'h1030 // F/D_SUPPORTED
+`define FP17_REGNO        16'h1031 // F/D_SUPPORTED
+`define FP18_REGNO        16'h1032 // F/D_SUPPORTED
+`define FP19_REGNO        16'h1033 // F/D_SUPPORTED
+`define FP20_REGNO        16'h1034 // F/D_SUPPORTED
+`define FP21_REGNO        16'h1035 // F/D_SUPPORTED
+`define FP22_REGNO        16'h1036 // F/D_SUPPORTED
+`define FP23_REGNO        16'h1037 // F/D_SUPPORTED
+`define FP24_REGNO        16'h1038 // F/D_SUPPORTED
+`define FP25_REGNO        16'h1039 // F/D_SUPPORTED
+`define FP26_REGNO        16'h103A // F/D_SUPPORTED
+`define FP27_REGNO        16'h103B // F/D_SUPPORTED
+`define FP28_REGNO        16'h103C // F/D_SUPPORTED
+`define FP29_REGNO        16'h103D // F/D_SUPPORTED
+`define FP30_REGNO        16'h103E // F/D_SUPPORTED
+`define FP31_REGNO        16'h103F // F/D_SUPPORTED
+
+// ACCESS_MEMORY Control ranges (Not implemented)
+//`define AAMVIRTUAL       23
+//`define AAMSIZE          22:20
+//`define AAMPOSTINCREMENT 19
+//`define AAMWRITE         16
+//`define TARGET_SPECIFIC  15:14
+
+// aamsize
+//`define AAM8   0
+//`define AAM16  1
+//`define AAM32  2
+//`define AAM64  3
+//`define AAM128 4
diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh
index 5635b286c..ff254a29b 100644
--- a/config/shared/parameter-defs.vh
+++ b/config/shared/parameter-defs.vh
@@ -31,6 +31,8 @@ localparam cvw_t P = '{
   SVPBMT_SUPPORTED :     SVPBMT_SUPPORTED,
   SVNAPOT_SUPPORTED :    SVNAPOT_SUPPORTED,
   SVINVAL_SUPPORTED :    SVINVAL_SUPPORTED,
+  ZAAMO_SUPPORTED :      ZAAMO_SUPPORTED,
+  ZALRSC_SUPPORTED :     ZALRSC_SUPPORTED, 
   BUS_SUPPORTED :        BUS_SUPPORTED,
   DCACHE_SUPPORTED :     DCACHE_SUPPORTED,
   ICACHE_SUPPORTED :     ICACHE_SUPPORTED,
@@ -83,6 +85,14 @@ localparam cvw_t P = '{
   SPI_SUPPORTED :        SPI_SUPPORTED,
   SPI_BASE :        SPI_BASE,
   SPI_RANGE :        SPI_RANGE,
+  PLL_SUPPORTED :       PLL_SUPPORTED,
+  PLL_CONF_BASE :        PLL_CONF_BASE,
+  PLL_CONF_RANGE :        PLL_CONF_RANGE,
+  BSG_DMC_SUPPORTED :        BSG_DMC_SUPPORTED,
+  BSG_DMC_CONF_BASE :        BSG_DMC_CONF_BASE,
+  BSG_DMC_CONF_RANGE :        BSG_DMC_CONF_RANGE,
+  PROGBUF_BASE : PROGBUF_BASE,
+  PROGBUF_RANGE : PROGBUF_RANGE,
   GPIO_LOOPBACK_TEST :        GPIO_LOOPBACK_TEST,
   SPI_LOOPBACK_TEST :        SPI_LOOPBACK_TEST,
   UART_PRESCALE :        UART_PRESCALE ,
@@ -119,7 +129,7 @@ localparam cvw_t P = '{
   ZKND_SUPPORTED:        ZKND_SUPPORTED,
   ZKNE_SUPPORTED:        ZKNE_SUPPORTED,
   ZKNH_SUPPORTED:        ZKNH_SUPPORTED,
-  ZK_SUPPORTED  :        ZK_SUPPORTED,
+  ZKN_SUPPORTED :        ZKN_SUPPORTED,
   USE_SRAM :        USE_SRAM,
   M_MODE  : M_MODE, 
   S_MODE  : S_MODE, 
@@ -138,12 +148,10 @@ localparam cvw_t P = '{
   A_SUPPORTED : A_SUPPORTED,
   B_SUPPORTED : B_SUPPORTED,
   C_SUPPORTED : C_SUPPORTED,
-  COMPRESSED_SUPPORTED : COMPRESSED_SUPPORTED,
   D_SUPPORTED : D_SUPPORTED,
   E_SUPPORTED : E_SUPPORTED,
   F_SUPPORTED : F_SUPPORTED,
   I_SUPPORTED : I_SUPPORTED,
-  K_SUPPORTED : K_SUPPORTED,
   M_SUPPORTED : M_SUPPORTED,
   Q_SUPPORTED : Q_SUPPORTED,
   S_SUPPORTED : S_SUPPORTED,
@@ -171,6 +179,7 @@ localparam cvw_t P = '{
   H_BIAS : H_BIAS,
   H_FMT : H_FMT,
   FLEN : FLEN,
+  LOGFLEN : LOGFLEN,
   NE   : NE  ,
   NF   : NF  ,
   FMT  : FMT ,
@@ -190,13 +199,14 @@ localparam cvw_t P = '{
   CVTLEN : CVTLEN,
   LLEN : LLEN,
   LOGCVTLEN : LOGCVTLEN,
+  FMALEN : FMALEN,
   NORMSHIFTSZ : NORMSHIFTSZ,
   LOGNORMSHIFTSZ : LOGNORMSHIFTSZ,
-  CORRSHIFTSZ : CORRSHIFTSZ,
   LOGR        : LOGR,
   RK          : RK,
   FPDUR       : FPDUR,
   DURLEN      : DURLEN,
   DIVb        : DIVb,
-  DIVBLEN     : DIVBLEN
+  DIVBLEN     : DIVBLEN,
+  DEBUG_SUPPORTED : DEBUG_SUPPORTED
 };
diff --git a/config/soc/config.vh b/config/soc/config.vh
new file mode 100644
index 000000000..3d52511a4
--- /dev/null
+++ b/config/soc/config.vh
@@ -0,0 +1,240 @@
+//////////////////////////////////////////
+// config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: infinitymdm@gmail.com 7 June 2024
+//
+// Purpose: Specify which features of Wally are enabled and set
+//          configuration parameters
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "BranchPredictorType.vh"
+
+// RV32 or RV64: XLEN = 32 or 64
+localparam XLEN = 32'd64;
+
+// IEEE 754 compliance
+localparam IEEE754 = 0;
+
+// Debug Module implemented                                                                                                          
+localparam logic DEBUG_SUPPORTED = 1'b1;
+
+// RISC-V configuration per specification
+// Base instruction set (defaults to I if E is not supported)
+localparam logic E_SUPPORTED = 0;
+
+// Integer instruction set extensions
+localparam logic ZIFENCEI_SUPPORTED = 1; // Instruction-Fetch fence
+localparam logic ZICSR_SUPPORTED    = 1; // CSR Instructions
+localparam logic ZICCLSM_SUPPORTED  = 1; // Misaligned loads/stores
+localparam logic ZICOND_SUPPORTED   = 1; // Integer conditional operations
+
+// Multiplication & division extensions
+// M implies (and in the configuration file requires) Zmmul
+localparam logic M_SUPPORTED     = 1;
+localparam logic ZMMUL_SUPPORTED = 1;
+
+// Atomic extensions
+// A extension is Zaamo + Zalrsc
+localparam logic ZAAMO_SUPPORTED  = 1;
+localparam logic ZALRSC_SUPPORTED = 1;
+
+// Bit manipulation extensions
+// B extension is Zba + Zbb + Zbs
+localparam logic ZBA_SUPPORTED = 1;
+localparam logic ZBB_SUPPORTED = 1;
+localparam logic ZBS_SUPPORTED = 1;
+localparam logic ZBC_SUPPORTED = 1;
+
+// Scalar crypto extensions
+// Zkn is all 6 of these
+localparam logic ZBKB_SUPPORTED = 1;
+localparam logic ZBKC_SUPPORTED = 1;
+localparam logic ZBKX_SUPPORTED = 1;
+localparam logic ZKND_SUPPORTED = 1;
+localparam logic ZKNE_SUPPORTED = 1;
+localparam logic ZKNH_SUPPORTED = 1;
+
+// Compressed extensions
+// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
+// All compressed extensions require Zca
+localparam logic ZCA_SUPPORTED = 1;
+localparam logic ZCB_SUPPORTED = 1;
+localparam logic ZCF_SUPPORTED = 0; // RV32 only, requires F
+localparam logic ZCD_SUPPORTED = 1; // requires D
+
+// Floating point extensions
+localparam logic F_SUPPORTED   = 1;
+localparam logic D_SUPPORTED   = 1;
+localparam logic Q_SUPPORTED   = 0;
+localparam logic ZFH_SUPPORTED = 1;
+localparam logic ZFA_SUPPORTED = 1;
+
+// privilege modes
+localparam logic S_SUPPORTED = 1; // Supervisor mode
+localparam logic U_SUPPORTED = 1; // User mode
+
+// Supervisor level extensions
+localparam logic SSTC_SUPPORTED = 1; // Supervisor-mode timer interrupts
+
+// Hardware performance counters
+localparam logic ZICNTR_SUPPORTED = 1;
+localparam logic ZIHPM_SUPPORTED  = 1;
+localparam COUNTERS = 12'd32;
+
+// Cache-management operation extensions
+localparam logic ZICBOM_SUPPORTED = 1;
+localparam logic ZICBOZ_SUPPORTED = 1;
+localparam logic ZICBOP_SUPPORTED = 1;
+
+// Virtual memory extensions
+localparam logic SVPBMT_SUPPORTED  = 1;
+localparam logic SVNAPOT_SUPPORTED = 1;
+localparam logic SVINVAL_SUPPORTED = 1;
+localparam logic SVADU_SUPPORTED   = 1;
+
+
+// LSU microarchitectural Features
+localparam logic BUS_SUPPORTED = 1;
+localparam logic DCACHE_SUPPORTED = 1;
+localparam logic ICACHE_SUPPORTED = 1;
+localparam logic VIRTMEM_SUPPORTED = 1;
+localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
+localparam logic BIGENDIAN_SUPPORTED = 1;
+
+// TLB configuration.  Entries should be a power of 2
+localparam ITLB_ENTRIES = 32'd32;
+localparam DTLB_ENTRIES = 32'd32;
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+localparam DCACHE_NUMWAYS = 32'd4;
+localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
+localparam DCACHE_LINELENINBITS = 32'd512;
+localparam ICACHE_NUMWAYS = 32'd4;
+localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
+localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+localparam IDIV_BITSPERCYCLE = 32'd4;
+localparam logic IDIV_ON_FPU = 1;
+
+// Legal number of PMP entries are 0, 16, or 64
+localparam PMP_ENTRIES = 32'd16;
+
+// Address space
+localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000;
+
+// WFI Timeout Wait
+localparam WFI_TIMEOUT_BIT = 32'd16;
+
+// Peripheral Physical Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+localparam logic DTIM_SUPPORTED = 0;
+localparam logic [63:0] DTIM_BASE          = 64'h80000000;
+localparam logic [63:0] DTIM_RANGE         = 64'h007FFFFF;
+localparam logic IROM_SUPPORTED = 0;
+localparam logic [63:0] IROM_BASE          = 64'h80000000;
+localparam logic [63:0] IROM_RANGE         = 64'h007FFFFF;
+localparam logic BOOTROM_SUPPORTED = 1;
+localparam logic [63:0] BOOTROM_BASE       = 64'h00001000;
+localparam logic [63:0] BOOTROM_RANGE      = 64'h00000FFF;
+localparam BOOTROM_PRELOAD = 1'b0;
+localparam logic UNCORE_RAM_SUPPORTED = 1;
+localparam logic [63:0] UNCORE_RAM_BASE    = 64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE   = 64'h07FFFFFF;
+localparam UNCORE_RAM_PRELOAD = 1'b0;
+localparam logic EXT_MEM_SUPPORTED = 1;
+localparam logic [63:0] EXT_MEM_BASE       = 64'h90000000;
+localparam logic [63:0] EXT_MEM_RANGE      = 64'h07FFFFFF;
+localparam logic CLINT_SUPPORTED = 1;
+localparam logic [63:0] CLINT_BASE         = 64'h02000000;
+localparam logic [63:0] CLINT_RANGE        = 64'h0000FFFF;
+localparam logic GPIO_SUPPORTED = 1;
+localparam logic [63:0] GPIO_BASE          = 64'h10060000;
+localparam logic [63:0] GPIO_RANGE         = 64'h000000FF;
+localparam logic UART_SUPPORTED = 1;
+localparam logic [63:0] UART_BASE          = 64'h10000000;
+localparam logic [63:0] UART_RANGE         = 64'h00000007;
+localparam logic PLIC_SUPPORTED = 1;
+localparam logic [63:0] PLIC_BASE          = 64'h0C000000;
+localparam logic [63:0] PLIC_RANGE         = 64'h03FFFFFF;
+localparam logic SDC_SUPPORTED = 0; // Needs to be set to 1 when using actual SDC hardware. Currently setting to 1 immediately breaks simulation
+localparam logic [63:0] SDC_BASE           = 64'h00013000;
+localparam logic [63:0] SDC_RANGE          = 64'h0000007F;
+localparam logic SPI_SUPPORTED = 1;
+localparam logic [63:0] SPI_BASE           = 64'h10040000;
+localparam logic [63:0] SPI_RANGE          = 64'h00000FFF;
+localparam logic PLL_SUPPORTED = 1;
+localparam logic [63:0] PLL_CONF_BASE      = 64'h00020000;
+localparam logic [63:0] PLL_CONF_RANGE     = 64'h000000FF;
+localparam logic BSG_DMC_SUPPORTED = 1;
+localparam logic [63:0] BSG_DMC_CONF_BASE  = 64'h00030000;
+localparam logic [63:0] BSG_DMC_CONF_RANGE = 64'h000000FF;
+// Debug program buffer support is enabled with DEBUG_SUPPORTED
+localparam logic [63:0] PROGBUF_BASE     = 64'h00002000;
+localparam logic [63:0] PROGBUF_RANGE    = 64'h0000000F;
+
+// Bus Interface width
+localparam AHBW = (XLEN);
+
+// Test modes
+
+// AHB 
+localparam RAM_LATENCY = 32'b0;
+localparam logic BURST_EN = 1;
+
+// Tie GPIO outputs back to inputs
+localparam logic GPIO_LOOPBACK_TEST = 1;
+localparam logic SPI_LOOPBACK_TEST  = 1;
+
+// Hardware configuration
+localparam UART_PRESCALE = 32'd1;
+
+// Interrupt configuration
+localparam PLIC_NUM_SRC = 32'd10;
+// comment out the following if >=32 sources
+localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
+localparam PLIC_GPIO_ID = 32'd3;
+localparam PLIC_UART_ID = 32'd10;
+localparam PLIC_SPI_ID = 32'd6;
+localparam PLIC_SDC_ID = 32'd9;
+
+// Branch prediction
+localparam logic BPRED_SUPPORTED = 1;
+localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+localparam BPRED_SIZE = 32'd10;
+localparam BPRED_NUM_LHR = 32'd6;
+localparam BTB_SIZE = 32'd10;
+localparam RAS_SIZE = 32'd16;
+localparam INSTR_CLASS_PRED = 1;
+
+// FPU division architecture
+localparam RADIX = 32'd4;
+localparam DIVCOPIES = 32'd4;
+
+// Memory synthesis configuration
+localparam logic USE_SRAM = 0; // 1 in actual hardware
+
+`include "config-shared.vh"
diff --git a/docs/docker/Dockerfile.builds b/docs/docker/Dockerfile.builds
new file mode 100644
index 000000000..ec157de07
--- /dev/null
+++ b/docs/docker/Dockerfile.builds
@@ -0,0 +1,104 @@
+FROM wallysoc/ubuntu_wally
+
+# SET ENVIRONMENT VARIABLES
+# assume 4 threads are available to speed up
+ARG NUM_THREADS=4
+ENV RISCV=/opt/riscv
+ENV PATH="$PATH:${RISCV}/bin"
+ENV MANPATH="$MANPATH:${RISCV}/share/man"
+
+# this is required by podman
+USER root
+WORKDIR /opt/riscv
+
+# TOOLCHAIN
+RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
+    cd riscv-gnu-toolchain && \
+    sed -i 's/https/git/' .gitmodules && git submodule sync && \
+    ./configure --prefix=${RISCV} --enable-multilib \
+        --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \
+    make --jobs ${NUM_THREADS} && \
+    make install && cd ${RISCV} && \
+    rm -rf ${RISCV}/riscv-gnu-toolchain
+
+# elf2hex
+RUN git clone https://github.com/sifive/elf2hex.git && \
+    cd elf2hex && \
+    autoreconf -i && \
+    ./configure --target=riscv64-unknown-elf --prefix=${RISCV} && \
+    make && \
+    make install && cd ${RISCV} && \
+    rm -rf ${RISCV}/elf2hex
+
+# QEMU
+RUN git clone --recursive https://github.com/qemu/qemu && \
+    cd qemu && \
+    ./configure --target-list=riscv64-softmmu --prefix=${RISCV}  && \
+    make --jobs ${NUM_THREADS} && \
+    make install && cd ${RISCV} && \
+    rm -rf ${RISCV}/qemu
+
+# Spike
+RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \
+    mkdir riscv-isa-sim/build && \
+    cd riscv-isa-sim/build && \
+    ../configure --prefix=$RISCV --enable-commitlog && \
+    make --jobs ${NUM_THREADS} && \
+    make install && cd ${RISCV} && \
+    rm -rf ${RISCV}/riscv-isa-sim
+
+# SAIL
+RUN opam init -y --disable-sandboxing && \
+    opam switch create 5.1.0 && \
+    opam install sail -y && \
+    eval $(opam config env) && \
+    git clone https://github.com/riscv/sail-riscv.git && \
+    cd sail-riscv && \
+    ARCH=RV32 make c_emulator/riscv_sim_RV32 && \
+    ARCH=RV64 make c_emulator/riscv_sim_RV64 && \
+    cp ${RISCV}/sail-riscv/c_emulator/riscv_sim_RV64 ${RISCV}/bin/riscv_sim_RV64 && \
+    cp ${RISCV}/sail-riscv/c_emulator/riscv_sim_RV32 ${RISCV}/bin/riscv_sim_RV32 && \
+    rm -rf ${RISCV}/sail-riscv
+
+COPY ./buildroot-config-src /opt/riscv/buildroot-config-src
+COPY ./testvector-generation /opt/riscv/testvector-generation
+
+# # Buildroot
+RUN git clone https://github.com/buildroot/buildroot.git && \
+    cd buildroot && \
+    git checkout 2021.05 && \
+    cp -r /opt/riscv/buildroot-config-src ./board/wally && \
+    cp ./board/wally/main.config .config && \
+    make --jobs ${NUM_THREADS} && \
+    # generate files for buildroot regression
+    mkdir -p ${RISCV}/linux-testvectors && \
+    cd /opt/riscv/testvector-generation && \
+    curl https://raw.githubusercontent.com/openhwgroup/cvw/main/linux/devicetree/wally-virt.dts --output ${RISCV}/buildroot/output/images/wally-virt.dts && \
+    dtc -I dts -O dtb ${RISCV}/buildroot/output/images/wally-virt.dts > ${RISCV}/buildroot/output/images/wally-virt.dtb && \
+    make && ./genInitMem.sh && \
+    chmod -R a+rw ${RISCV}/linux-testvectors && \
+    rm -rf ${RISCV}/buildroot
+
+RUN pip3 install --no-cache-dir \
+    testresources riscv_config \
+    git+https://github.com/riscv/riscof.git
+
+# Wally needs Verilator 5.021 or later.
+# Verilator needs to be built from scratch to get the latest version
+# apt-get install verilator installs version 4.028 as of 6/8/23
+RUN apt-get install -y \
+    perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g \
+    libfl2  libfl-dev && \
+    apt-get clean
+RUN git clone https://github.com/verilator/verilator && \
+    cd verilator && \
+    git pull && \
+    git checkout v5.022 && \
+    autoconf && \
+    ./configure --prefix=${RISCV} && \
+    make -j ${NUM_THREADS} && \
+    make install && \
+    cd ${RISCV} && rm -rf ${RISCV}/verilator
+
+USER ${USERNAME}
+WORKDIR /home/${USERNAME}/cvw
\ No newline at end of file
diff --git a/docs/docker/Dockerfile.regression b/docs/docker/Dockerfile.regression
new file mode 100644
index 000000000..1bcda8baf
--- /dev/null
+++ b/docs/docker/Dockerfile.regression
@@ -0,0 +1,17 @@
+FROM wallysoc/toolchains_wally
+
+ENV QUESTA=/cad/mentor/questa_sim-xxxx.x_x
+ENV RUN_QUESTA=false
+ENV USERNAME=cad
+
+VOLUME [ "/home/${USERNAME}/cvw" ]
+USER root
+
+COPY --chown=${USERNAME}:${USERNAME} . /home/${USERNAME}
+RUN chown -R ${USERNAME}:${USERNAME} /home/${USERNAME}
+RUN chown -R ${USERNAME}:${USERNAME} /home/${USERNAME}/cvw
+
+USER ${USERNAME}
+WORKDIR /home/${USERNAME}/cvw
+
+CMD [ "/bin/sh", "-c", "/home/${USERNAME}/run_regression.sh" ]
\ No newline at end of file
diff --git a/docs/docker/Dockerfile.ubuntu b/docs/docker/Dockerfile.ubuntu
new file mode 100644
index 000000000..cc98bd5c5
--- /dev/null
+++ b/docs/docker/Dockerfile.ubuntu
@@ -0,0 +1,33 @@
+FROM ubuntu:22.04@sha256:aa772c98400ef833586d1d517d3e8de670f7e712bf581ce6053165081773259d
+
+RUN apt update && \
+    apt install -y \
+        git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev python3-pip pkg-config libglib2.0-dev opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils verilator cpio bc vim emacs gedit nano && \
+    apt-get clean
+
+# COPY requirements.txt /root
+RUN pip3 install --no-cache-dir \
+    sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief
+
+RUN ln -s /usr/bin/python3 /usr/bin/python
+
+# Create a user group 'xyzgroup'
+ENV USERNAME=cad
+ARG USER_UID=1000
+ARG USER_GID=$USER_UID
+
+# Create the user
+RUN groupadd --gid $USER_GID ${USERNAME} \
+    && useradd --uid $USER_UID --gid $USER_GID -m ${USERNAME} \
+    # [Optional] Add sudo support. Omit if you don't need to install software after connecting.
+    && apt-get update \
+    && apt-get install -y sudo \
+    && echo ${USERNAME} ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/${USERNAME} \
+    && chmod 0440 /etc/sudoers.d/${USERNAME}
+
+# Change RISCV user
+RUN chown -Rf cad:cad /opt
+
+# Add cad user
+USER ${USERNAME}
+WORKDIR /home/${USERNAME}
\ No newline at end of file
diff --git a/docs/docker/Makefile b/docs/docker/Makefile
new file mode 100644
index 000000000..82560d8cb
--- /dev/null
+++ b/docs/docker/Makefile
@@ -0,0 +1,32 @@
+QUESTA_HOME?=/cad/mentor/questa_sim-2023.4
+CVW_GIT?=""
+
+commanline:
+	podman run -it --rm \
+	-v cvw_temp:/home/cad/cvw \
+	-v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \
+	--privileged --network=host \
+	wallysoc/regression_wally /bin/bash
+
+regression_openhw_cvw:
+	podman run \
+	-e CVW_GIT=$(CVW_GIT) \
+	-e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 \
+	-v cvw_temp:/home/cad/cvw \
+	-v $(QUESTA_HOME):/cad/mentor/questa_sim-xxxx.x_x \
+	--privileged --network=host \
+	--rm wallysoc/regression_wally
+
+push_hub:
+	podman push wallysoc/ubuntu_wally:latest
+	podman push wallysoc/toolchains_wally:latest
+	podman push wallysoc/regression_wally:latest
+
+update_ubuntu:
+	podman build -t wallysoc/ubuntu_wally -f Dockerfile.ubuntu .
+
+update_toolchains:
+	podman build -t wallysoc/toolchains_wally -f Dockerfile.builds .
+
+update_regression:
+	podman build -t wallysoc/regression_wally -f Dockerfile.regression .
\ No newline at end of file
diff --git a/docs/docker/README.md b/docs/docker/README.md
new file mode 100644
index 000000000..e21e53211
--- /dev/null
+++ b/docs/docker/README.md
@@ -0,0 +1,333 @@
+# Consistant Build of Toolchain for Wally
+
+`Dockerfile.*` contains a ~~multi-stage~~ build for all the toolchains that are required for Wally's open-source features.
+
+Hazards:
+
+- If there is any change in `${CVW_HOME}/linux/buildroot-config-src` folder with main.config, you have to copy it to the current folder to `buildroot-config-src`
+- If there is any change in `${CVW_HOME}/linux/testvector-generation` folder with main.config, you have to copy it to the current folder to `testvector-generation`
+
+If you have any other questions, please read the [troubleshooting]() first.
+
+## TODOs
+
+- [ ] Pinning the tools version
+    - As for the consistent tool build, should we use specific versions of tools in order to avoid bugs at the master branch?
+    - And we will upgrade the versions of tool after a certain period of time to get the latest features and patches while verifying it won’t cause any problem.
+- [x] Mount the ~~EDA Tools~~QuestaSIM and Path
+    - USE_QUESTA and QUESTA for path
+- [x] Enable X11 forwarding for docker
+    - `--network=host` for docker run
+    - `xhost +localhost:${USER}` for host
+- [x] Regression Script
+- [x] Configure the license for Questa
+- [x] Change the condition from empty string to 1
+- [x] Add linux testvector-generation
+    - [x] Estimate the useless building intermediate files
+
+## TL;DR
+
+Steps:
+
+1. Install either Docker Engine or Podman for container support
+2. Run start-up script `docs/docker/start.sh` to start a stateless container to run the toolchains and EDA tool
+
+### Docker Engine or Podman
+
+First and foremost, install either Docker Engine or Podman:
+
+- Docker Engine (More Popular, default): https://docs.docker.com/engine/install/
+- Podman: https://podman.io/docs/installation
+
+Here are some common installation commands (not guarantee to be up to date)
+
+```shell
+# For Ubuntu
+# Add Docker's official GPG key:
+sudo apt-get update
+sudo apt-get install ca-certificates curl
+sudo install -m 0755 -d /etc/apt/keyrings
+sudo curl -fsSL https://download.docker.com/linux/ubuntu/gpg -o /etc/apt/keyrings/docker.asc
+sudo chmod a+r /etc/apt/keyrings/docker.asc
+
+# Add the repository to Apt sources:
+echo \
+  "deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.asc] https://download.docker.com/linux/ubuntu \
+  $(. /etc/os-release && echo "$VERSION_CODENAME") stable" | \
+  sudo tee /etc/apt/sources.list.d/docker.list > /dev/null
+sudo apt-get update
+# Installation
+sudo apt-get install docker-ce docker-ce-cli containerd.io docker-buildx-plugin docker-compose-plugin
+# Hello-World Example
+docker run hello-world
+```
+
+### Use of Start-up Script
+
+Files at this folder can help you to build/fetch environment you need to run wally with the help of Docker.
+
+Here are some common use cases, it will **provides you an environment with RISC-V toolchains** that required by this project:
+
+```shell
+# By default, we assume that you have cloned the cvw respository and running the script at relative path `docs/docker`
+
+# For HMC students, /opt/riscv is available and nothing needs to be built
+TOOLCHAINS_MOUNT=/opt/riscv QUESTA=/cad/mentor/questa_sim-2023.4 ./start.sh
+
+# For those with all the toolchains installed, simply mount the toolchains
+TOOLCHAINS_MOUNT=<path-to-toolchains> ./start.sh
+
+# For those have nothing, fetching the builds are easiest thing
+CVW_MOUNT=<path-to-cvw> ./start.sh
+# if you want to use Podman instead of Docker Engine
+USE_PODMAN=1 ./start.sh
+
+# For other cases, checkout start-up script for building option
+```
+For further usage, please consult the following configuration.
+
+### Regression on Master Branch
+
+The regression script is used by image `wallysoc/regression_wally` to run regressions on the master branch of a specific repository.
+
+If you are using docker, then replace the following podman with docker.
+
+```shell
+# create volume for permanent storage
+podman volume create cvw_temp
+
+# run regression on the OpenHW/cvw
+podman run \
+    -e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 \
+    -v cvw_temp:/home/cad/cvw \
+    -v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x \
+    --privileged --network=host \
+    --rm wallysoc/regression_wally
+
+# run regression on the Karl-Han/cvw
+podman run \
+    -e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 \
+    -e CVW_GIT=https://github.com/Karl-Han/cvw \
+    -v cvw_temp:/home/cad/cvw \
+    -v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x \
+    --privileged --network=host \
+    --rm wallysoc/regression_wally
+
+# get into the container command line to debug or reading files
+podman run -it \
+    -e RUN_QUESTA=1 \
+    -v cvw_temp:/home/cad/cvw \
+    -v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x \
+    --privileged --network=host \
+    wallysoc/regression_wally /bin/bash
+```
+
+## Conventions
+
+- In the container
+    - default user is `cad`
+    - RISCV is defined as `/opt/riscv`
+    - QUESTA is defined as `/cad/mentor/questa_sim-xxxx.x_x`
+        - bin location is in `$QUESTA/questasim/bin`
+    - cvw folder should be mounted on `/home/${USERNAME}/cvw`
+        - as for `cad`, it is `/home/cad/cvw`
+- In the current shell environment: checkout the constants in the following script section
+
+## New Dockerfile Design
+
+There are two parts of the new docker-related design:
+
+- build proper image(s)
+- scripts for different purposes
+
+### Problem Statement
+
+The following 3 problems are to be resolved:
+
+- remove storage of useless files with `Dockerfile`
+    - git build: clean up
+    - packages info
+        - apt: `apt-get clean`
+        - pip: `--no-cache-dir`
+- reuse storage
+    - read-only $RISCV volume across different users with `docker image`
+    - local-built RISCV with `start-up script`
+- use commercial EDA tools: optional environment variable configuration with `start-up script`
+
+### Dockerfiles
+
+There are two Dockerfiles:
+
+- `Dockerfile.ubuntu`: basic ubuntu system setup and produce `ubuntu_wally` image in docker
+    - corresponds to `wallysoc/ubuntu_wally`
+- `Dockerfile.builds`: all the required toolchains are built
+    - corresponds to `wallysoc/toolchains_wally`
+
+Because we are going to use the whole environment of ubuntu to get both executables and python packages, we are not going to use multi-stage builds, which runs only executables.
+
+### Scripts
+
+There are four scripts:
+
+- `start.sh` (most often used): start running the container
+    - if you don't care about toolchains and running regression automatically, this script is only thing you need to know
+- `get_images.sh`: get docker image `wallysoc/ubuntu_wally` or `wallysoc/toolchains_wally`
+- `get_buildroot_testvector.py`: copy buildroot and testvector configuration required by building
+- `run_regression.sh`: run regressions with Verilator (and QuestaSIM) on specific CVW
+    - this script is not intended to be run directly, but inside the container
+    - However, it is a good resource to look into to know what is happening
+- `test.sh`: a test script to facilitate the above three
+
+All the following options in the corresponding scripts should be set by either:
+
+- define it right before the command: `USE_PODMAN=1 ./start.sh` with USE_PODMAN on start-up script
+    - the variable is only effective for the current command, not the following environment
+- declare it globally and use it any time afterwards:
+
+```shell
+# declare it globally in the environment
+export DOCKER_EXEC=$(which docker)
+export UBUNTU_BUILD=1
+
+# run the script with all the above variables
+./get_images.sh
+```
+
+#### Start-up Script: start.sh
+
+There are two settings:
+
+- build/fetch both ubuntu_wally and toolchains in docker image and use it
+- build/fetch only ubuntu_wally and use local toolchains folder
+
+Options:
+
+- USE_PODMAN:
+    - by default, docker is used
+    - set USE_PODMAN=1 otherwise
+- UBUNTU_BUILD:
+    - fetch by default
+    - set UBUNTU_BUILD=1 if you want to build with Dockerfile.ubuntu
+- TOOLCHAINS_BUILD:
+    - fetch by default
+    - set TOOLCHAINS_BUILD=1 if you want to build with Dockerfile.build
+
+#### Image Building Script: get_images.sh
+
+Options (if you want to build the images):
+
+- DOCKER_EXEC:
+    - docker by default
+    - if you want to use podman, then set it to $(which podman)
+- UBUNTU_BUILD:
+    - fetch by default
+    - set it to 1 if you want to build it instead of fetching it
+- TOOLCHAINS_BUILD:
+    - fetch by default
+    - set it to 1 if you want to build it instead of fetching it
+
+#### Regression Script: run_regression.sh
+
+There are two parts for regression:
+
+- Verilator: must be able to run as it is open-sourced
+- Questa: OPTIONAL as it is commercial EDA Tool
+
+
+There are three main knobs:
+
+1. CLEAN_CVW: remove the `/home/${USERNAME}/cvw` inside the container (it can be a volume) and clone the `${CVW_GIT}`.
+2. BUILD_RISCOF: build RISCOF in the `/home/${USERNAME}/cvw`, sometimes you don't want to rebuild if there is no change in the test suite.
+3. RUN_QUESTA: enable the QuestaSIM in regression
+
+Options:
+
+- CVW_GIT: git clone address
+- CLEAN_CVW: clone CVW_GIT if enabled with `-e CLEAN_CVW=1`
+- BUILD_RISCOF: rebuild RISCOF if enabled with `-e BUILD_RISCOF=1`
+- RUN_QUESTA: run vsim to check if enabled with `-e RUN_QUESTA=1`
+    - QUESTA: home folder for mounted QuestaSIM `/cad/mentor/questa_sim-xxxx.x_x` if enabled
+    - for example, if your vsim is in `/cad/mentor/questa_sim-2023.4/questasim/bin/vsim` then your local QuestaSIM folder is `/cad/mentor/questa_sim-2023.4`, so you have to add `-v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x -e RUN_QUESTA=1`
+
+### Commercial EDA Tools
+
+This is kind of tricky, because Docker network is a different network from the host. Therefore, it should be carefully handled in order to use the host's license server while minimizing the access of docker container.
+
+There are at least two ways to solve this problem:
+
+- use `--network=host` in docker-run to use the same network
+- (NOT WORKING) use bridge in docker-run while forwarding docker network's traffic to localhost without setting `X11UseLocalhost no`
+    - this idea is from https://stackoverflow.com/a/64284364/10765798
+
+## Old Dockerfile Analysis
+
+> Refer to https://github.com/openhwgroup/cvw/blob/91919150a94ccf8e750cf7c9eec1c400efaef7f5/docs/Dockerfile
+
+There are stages in the old Dockerfile:
+
+- debian-based package installtion
+    - apt package
+    - python3 package
+- user and its group configuration
+- clone and build toolchain with prefix=$RISCV
+    - riscv-gnu-toolchain: https://github.com/riscv-collab/riscv-gnu-toolchain
+    - elf2hex: https://github.com/sifive/elf2hex
+    - qemu: https://github.com/qemu/qemu
+    - spike: https://github.com/riscv-software-src/riscv-isa-sim
+    - sail: https://github.com/riscv/sail-riscv/commits/master/
+    - buildroot: https://github.com/buildroot/buildroot
+    - verilator: https://github.com/verilator/verilator
+
+### Tool Versions till 20240331
+
+- riscv-gnu-toolchain: `2024.03.01`
+- elf2hex: `f28a3103c06131ed3895052b1341daf4ca0b1c9c`
+- qemu: not tested
+- spike: `3427b459f88d2334368a1abbdf5a3000957f08e8`
+- sail: `f601c866153c79a7ae8404f939dc2d66aa2e41f9`
+- buildroot: `2021.05`
+- verilator: `v5.022`
+
+## Troubleshooting
+
+### Permission Denied for .git
+
+Description: permission problem in `/home/$USERNAME/cvw`.
+
+```text
+$ podman run -v cvw_temp:/home/cad/cvw -e CLEAN_CVW=1 -e BUILD_RISCOF=1 -e RUN_QUESTA=1 -v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x --rm wallysoc/regression_wally                          
+No CVW_GIT is provided                                                                                 
+rm: cannot remove '/home/cad/cvw': Device or resource busy                                             
+Cloning into '/home/cad/cvw'...                                                                        
+/home/cad/cvw/.git: Permission denied                                                                  
+chmod: cannot access '/home/cad/cvw/setup.sh': No such file or directory                               
+chmod: cannot access '/home/cad/cvw/site-setup.sh': No such file or directory                          
+make: *** No rule to make target 'install'.  Stop.                                                     
+make: *** No rule to make target 'verify'.  Stop.                                                      
+make: *** No rule to make target 'coverage'.  Stop.                                                    
+make: *** No rule to make target 'benchmarks'.  Stop.                                                  
+/home/cad/run_regression.sh: line 64: cd: /home/cad/cvw/sim: No such file or directory                 
+/home/cad/run_regression.sh: line 65: /home/cad/cvw/sim/regression_verilator.out: No such file or direc
+tory       
+```
+
+It may be caused by podman and I am not sure why it happens.
+
+Solution: get into the container with interaction as root and change the permission of the folder/volume `/home/$USERNAME/cvw`
+
+```shell
+podman run -it --user root -v cvw_temp:/home/cad/cvw -e RUN_QUESTA= -v /cad/mentor/questa_sim-2023.4:/cad/mentor/questa_sim-xxxx.x_x --net=host --rm --privileged wallysoc/regression_wally /bin/bash
+
+chown -R $USERNAME:$USERNAME /home/$USERNAME
+```
+
+## References
+
+- Dockerfile Docs: https://docs.docker.com/reference/dockerfile/
+- Multi-stage builds: https://docs.docker.com/build/building/multi-stage/
+- Best Practices: https://docs.docker.com/develop/develop-images/guidelines/
+- Chinese Reference: https://yeasy.gitbook.io/docker_practice/
+- Clean Cache
+    - apt cache: https://gist.github.com/marvell/7c812736565928e602c4
+    - pip cache: https://stackoverflow.com/questions/50333650/install-python-package-in-docker-file
+- Docker Network: https://docs.docker.com/network/
diff --git a/docs/docker/get_buildroot_testvector.py b/docs/docker/get_buildroot_testvector.py
new file mode 100644
index 000000000..f2feb0789
--- /dev/null
+++ b/docs/docker/get_buildroot_testvector.py
@@ -0,0 +1,13 @@
+import shutil, os
+
+# if WALLY is defined, then get it
+WALLY_HOME = os.getenv("WALLY")
+if WALLY_HOME is None or WALLY_HOME == "":
+    # otherwise, it is assumed as ../../
+    WALLY_HOME = "../../"
+
+BUILDROOT_SRC = "linux/buildroot-config-src/wally"
+TESTVECTOR_SRC = "linux/testvector-generation"
+
+shutil.copytree(os.path.join(WALLY_HOME, BUILDROOT_SRC), "./buildroot-config-src")
+shutil.copytree(os.path.join(WALLY_HOME, TESTVECTOR_SRC), "./testvector-generation")
\ No newline at end of file
diff --git a/docs/docker/get_images.sh b/docs/docker/get_images.sh
new file mode 100755
index 000000000..2e7b43c0c
--- /dev/null
+++ b/docs/docker/get_images.sh
@@ -0,0 +1,23 @@
+UBUNTU_BUILD=${UBUNTU_BUILD:-0}
+TOOLCHAINS_BUILD=${TOOLCHAINS_BUILD:-0}
+
+if [ -n "$USE_PODMAN" ]; then
+    DOCKER_EXEC=$(which podman)
+else
+    DOCKER_EXEC=$(which docker)
+fi
+
+if [ $UBUNTU_BUILD -eq 1 ]; then
+    ${DOCKER_EXEC} build -t ubuntu_wally -f Dockerfile.ubuntu .
+    ${DOCKER_EXEC} tag ubuntu_wally:latest wallysoc/ubuntu_wally:latest
+else
+    ${DOCKER_EXEC} pull wallysoc/ubuntu_wally
+fi
+
+if [ $TOOLCHAINS_BUILD -eq 1 ]; then
+    `which python` get_buildroot_testvector.py
+    ${DOCKER_EXEC} build -t toolchains_wally -f Dockerfile.builds .
+    ${DOCKER_EXEC} tag toolchains_wally:latest wallysoc/toolchains_wally:latest
+else
+    ${DOCKER_EXEC} pull wallysoc/toolchains_wally
+fi
\ No newline at end of file
diff --git a/docs/docker/run_regression.sh b/docs/docker/run_regression.sh
new file mode 100755
index 000000000..6d125bc7e
--- /dev/null
+++ b/docs/docker/run_regression.sh
@@ -0,0 +1,72 @@
+#!/bin/bash
+# this script is used to run regression inside the Dockerfile.regression
+# of course, you can run it in the current environment as soon as
+#   - RISCV is defined
+#   - QUESTA is defined
+# declare with empty string: export ABC=
+
+# Options:
+# - CVW_GIT: git clone address, only main branch supported
+# - CLEAN_CVW: declared with empty string to clone
+# - BUILD_RISCOF: declared with empty string to rebuild RISCOF
+# - RUN_QUESTA: declared with empty string to run vsim to check
+
+# now only main branch is supported
+if [ -z "${CVW_GIT}" ]; then
+    echo "No CVW_GIT is provided"
+    export CVW_GIT="https://github.com/openhwgroup/cvw"
+else
+    echo "Using customized CVW_GIT: ${CVW_GIT}"
+    # support specific branch now
+    export CVW_GIT=$(echo ${CVW_GIT} | sed -E "s/tree\// -b /g")
+fi
+
+git config --global http.version HTTP/1.1
+
+# if cvw is not available or CLEAN_CVW(empty string) is defined
+if [[ ! -f "/home/${USERNAME}/cvw/setup.sh" ]] || [[ "${CLEAN_CVW}" -eq 1 ]]; then
+    cd /home/${USERNAME} && rm -rf /home/${USERNAME}/cvw
+    git clone --recurse-submodules  ${CVW_GIT} /home/${USERNAME}/cvw
+    # if failed to clone submodules for some reason, please run `git submodule update`
+fi
+
+# Preset Environment Variable
+export PATH="${RISCV}/bin:${PATH}"
+export CVW_HOME="/home/${USERNAME}/cvw"
+export QUESTA="/cad/mentor/questa_sim-xxxx.x_x"
+export PATH="${QUESTA}/questasim/bin:${PATH}"
+
+# cd /home/${USERNAME}/cvw && chmod +x ./setup.sh && ./setup.sh
+chmod +x ${CVW_HOME}/setup.sh && source ${CVW_HOME}/setup.sh
+chmod +x ${CVW_HOME}/site-setup.sh && source ${CVW_HOME}/site-setup.sh
+
+# Overwriting
+export QUESTAPATH=/cad/mentor/questa_sim-xxxx.x_x/questasim/bin
+
+# # if you are making it alone, it works
+# make
+
+cd ${CVW_HOME}
+# build it only if BUILD_RISCOF is defined with empty string
+if [[ "${BUILD_RISCOF}" -eq 1 ]]; then
+    make install && make riscof && make testfloat
+fi
+
+if [[ "${RUN_QUESTA}" -eq 1 ]] ; then
+    if [ ! -f "${QUESTA}/questasim/bin/vsim" ]; then
+        echo "Cannot find vsim with ${QUESTA}/questasim/bin/vsim"
+    else
+        # cd sim && ./regression-wally 2>&1 > ./regression_questa.out && cd ..
+        # make verify
+        regression-wally
+    fi
+fi
+
+make coverage
+make benchmarks
+
+if [[ ! NO_VERILATOR -eq 1 ]]; then
+    make -C sim/verilator run
+    # by default it runs the arch64i on rv64gc
+    cat ${CVW_HOME}/sim/verilator/logs/rv64gc_arch64i.log
+fi
diff --git a/docs/docker/start.sh b/docs/docker/start.sh
new file mode 100755
index 000000000..ce3076574
--- /dev/null
+++ b/docs/docker/start.sh
@@ -0,0 +1,37 @@
+if [ -n "$USE_PODMAN" ]; then
+    DOCKER_EXEC=$(which podman)
+else
+    DOCKER_EXEC=$(which docker)
+fi
+if [ -n "$USE_PODMAN" ]; then
+       CVW_MOUNT=$(pwd)/../../
+fi
+echo ${CVW_MOUNT}
+USERNAME="cad"
+
+UBUNTU_WALLY_HASH=$(${DOCKER_EXEC} images --quiet wallysoc/ubuntu_wally)
+TOOLCHAINS_HASH=$(${DOCKER_EXEC} images --quiet wallysoc/toolchains_wally)
+TOOLCHAINS_MOUNT=${TOOLCHAINS_MOUNT}
+
+if [ -z $UBUNTU_WALLY_HASH ]; then
+    echo "CANNOT FIND wallysoc/ubuntu_wally, please get the image first with \`get_image.sh\`";
+    exit 1
+else
+    echo "Get ${UBUNTU_WALLY_HASH} for ubuntu_wally"
+fi
+
+if [ ! -z $TOOLCHAINS_MOUNT ]; then
+    if [ -n "$QUESTA" ]; then
+        ${DOCKER_EXEC} run -it --rm -v ${TOOLCHAINS_MOUNT}:/opt/riscv -v ${CVW_MOUNT}:/home/${USERNAME}/cvw -v ${QUESTA}:/cad/mentor/questa_sim-xxxx.x_x wallysoc/ubuntu_wally
+    else
+        ${DOCKER_EXEC} run -it --rm -v ${TOOLCHAINS_MOUNT}:/opt/riscv -v ${CVW_MOUNT}:/home/${USERNAME}/cvw wallysoc/ubuntu_wally
+    fi
+elif [ -z $TOOLCHAINS_HASH ]; then
+    echo "CANNOT FIND wallysoc/toolchains_wally, please get the image first with \`get_image.sh\`";
+    exit 1
+else
+    echo "Get ${TOOLCHAINS_HASH} for toolchains_wally"
+    ${DOCKER_EXEC} run --user root -it --rm -v ${CVW_MOUNT}:/home/${USERNAME}/cvw wallysoc/toolchains_wally
+fi
+
+echo "Successfully reach the end"
diff --git a/docs/docker/test.sh b/docs/docker/test.sh
new file mode 100644
index 000000000..fdd4eec85
--- /dev/null
+++ b/docs/docker/test.sh
@@ -0,0 +1,22 @@
+# There are three parts in testing as there are three scripts
+# It is fine to use either docker or podman as they are equivalent in the context
+export USE_PODMAN=1
+
+## build either one of them
+UBUNTU_BUILD=1 ./get_image.sh
+echo "get images is $?"
+
+## mount toolchian and questa
+TOOLCHAINS_MOUNT=/opt/riscv QUESTA=/cad/mentor/questa_sim-2023.4 ./start.sh
+# then run 
+# - `file ${QUESTA}/questasim/vsim` to check if it is properly mount
+# - `file $RISCV/bin/riscv64-unknown-elf-gcc` to check the toolchain
+
+## use internal toolchain
+./start.sh
+# then run 
+# - `file $RISCV/bin/riscv64-unknown-elf-gcc` to check the toolchain
+# - `which verilator | grep riscv` to check the verilator
+
+## mount questa
+RUN_QUESTA=true QUESTA=/cad/mentor/questa_sim-2023.4 ./run_regression.sh
\ No newline at end of file
diff --git a/docs/testplans/testplan.md b/docs/testplans/testplan.md
index 37390a632..95ce72f8b 100644
--- a/docs/testplans/testplan.md
+++ b/docs/testplans/testplan.md
@@ -2,26 +2,21 @@
 
 CORE-V Wally is functionally tested in the following ways.  Each test is run in lock-step against ImperasDV to ensure all architectural state is correct after each instruction.
 
-| Functions      | Coverage Method | Status |
-| ----------- | ----------- |----|
-|  Instructions | riscv-arch-test | Pass   |
-| Privileged Unit   | wally-riscv-arch-test        | Pass   |
-| Virtual Memory | wally-riscv-arch-test | Pass |
-| PMP | wally-riscv-arch-test | Pass
-| Peripherals | wally-riscv-arch-test | Pass |
-| Floating-Point | TestFloat | Pass |
-| General | Code Coverage | 91% |
-| General | Boot Linux in Sim | Pass | 
-| General | Boot Linux on FPGA | Pass |
-
-
-The following performance validation is also run:
-| Function | Method | Status |
-| --- | --- | --- |
-| Overall Performance | embench | Pass|
-| Overall Performance | coremark | Pass |
-| Branch Predictor | *** | Pass |
-| Cache Miss Rate | *** | Pass |
+| Tests               | Section        | TRL3         | TRL5   | Coverage Method       | Status | Command | 
+| ------------------- | -------------- | ------------ | ------ | --------------------- | ------ | ------- |
+| Verilator Lint      | 5.3            | All configs  | rv64gc | lint-wally            | PASS   | regression-wally --nightly |
+| Instructions        | 3.7            | All configs  | rv64gc | riscv-arch-test       | PASS   | regression-wally --nightly |
+| Privileged          | 3.7            | All configs  | rv64gc | wally-riscv-arch-test | PASS   | regression-wally --nightly |
+| Floating-point      | 5.11.7, 16.5.3 | rv{32/64}gc + derived | rv64gc    | TestFloat | FAIL   | regression-wally --nightly |
+| CoreMark            | 21.1           | Many configs | rv64gc | CoreMark              |        | regression-wally --nightly |
+| Embench             | 21.2           | rv32*        | n/a    | Embench               |        | regression-wally --nightly |
+| Cache PV            | 21.3.1         | rv{32/64}gc  | rv64gc | TBD                   | TBD    | TBD |
+| Cache PV            | 21.3.2         | rv{32/64}gc  | rv64gc | TBD                   | TBD    | TBD |
+| Linux Boot          | 22.3.2         | rv64gc       | rv64gc | TBD                   | TBD    | TBD |
+| FPGA Linux Boot     | 23.2           |              | rv64gc | TBD                   | TBD    | TBD |
+| Code Coverage       | 5.11.10        |              | rv64gc | TBD                   | TBD    | TBD |
+| Functional Coverage | 5.11.11        |              | rv64gc | TBD                   | TBD    | TBD |
+
 
 
 
diff --git a/examples/crypto/gfmul/Makefile b/examples/crypto/gfmul/Makefile
new file mode 100644
index 000000000..a501c3775
--- /dev/null
+++ b/examples/crypto/gfmul/Makefile
@@ -0,0 +1,16 @@
+# Makefile
+
+CC     = gcc
+CFLAGS = -O3
+LIBS   = 
+SRCS   = $(wildcard *.c)
+
+PROGS = $(patsubst %.c,%,$(SRCS))
+
+all:	$(PROGS)
+
+%: %.c
+	$(CC) $(CFLAGS) $(IFLAGS) -o $@ $< $(LIBS)
+
+clean: 
+	rm -f $(PROGS)
diff --git a/examples/crypto/gfmul/gfmul.c b/examples/crypto/gfmul/gfmul.c
new file mode 100644
index 000000000..3c4f585f1
--- /dev/null
+++ b/examples/crypto/gfmul/gfmul.c
@@ -0,0 +1,72 @@
+// gfmul.c - Galois Field multiplication
+// James Stine and David Harris 16 May 2024
+
+#include <stdio.h>
+
+/* return ab mod m(x) - long multiplication in GF(2^n) with polynomial m */
+int gfmul(int a, int b, int n, int m) {
+   int result = 0;
+   while (b) {
+     if (b & 1) result = result ^ a; /* if bit of b is set add a */
+     a = a << 1;                     /* multiply a by x */
+     if (a & 1 << n)
+       a = a ^ m;                    /* reduce/sub modulo AES m(x) = 100011011 */
+     //printf("a = %x, b = %x, result = %x\n", a, b, result);
+     b = b >> 1;                     /* get next bit of b */
+   }
+   return result;
+}
+
+void inverses(void) {
+    int i, j, k, num;
+
+    printf("\nTable of inverses in GF(2^8) with polynomial m(x) = 100011011\n");
+    for (i=0; i<16; i++) {
+        for (j=0; j<16; j++) {
+            num = i*16+j;
+            if (num ==0) printf ("00 ");
+            else for (k=1; k<256; k++) {
+                if (gfmul(num, k, 8, 0b100011011) == 1) {
+                    printf("%02x ", k);
+                    break;
+                }
+            }
+        }
+        printf("\n");
+    }
+}
+
+void inverses3(void) {
+    int k, num;
+
+    printf("\nTable of inverses in GF(2^8) with polynomial m(x) = 100011011\n");
+    for (num=0; num<8; num++) {
+        if (num == 0) printf ("0 ");
+        else for (k=1; k<8; k++) {
+            if (gfmul(num, k, 3, 0b1011) == 1) {
+                printf("%d ", k);
+                break;
+            }
+        }
+    }
+    printf("\n");
+}
+
+
+int main() {
+  int a = 0xC5;
+  int b = 0xA1;
+
+  printf("The GF(2^8) result is %x\n", gfmul(a,b, 8, 0b100011011));
+  printf("The GF(2^8) result is %x\n", gfmul(0xC1, 0x28, 8, 0b100011011));
+  inverses();
+
+  // tabulate inverses for GF(2^3)
+  inverses3();
+  // check worked examples
+    printf("The GF(2^3) result is %d\n", gfmul(0b101,0b011, 3, 0b1011));
+    printf("The GF(2^3) result is %d\n", gfmul(0b101,0b010, 3, 0b1011));
+    printf("The GF(2^3) result is %d\n", gfmul(0b101,0b100, 3, 0b1011));
+    printf("The GF(2^3) result is %d\n", gfmul(0b101,0b011, 3, 0b1011));
+ 
+}
diff --git a/examples/fp/fpcalc/Makefile b/examples/fp/fpcalc/Makefile
index 196fdf3d2..e3165231b 100644
--- a/examples/fp/fpcalc/Makefile
+++ b/examples/fp/fpcalc/Makefile
@@ -2,14 +2,12 @@
 
 CC     = gcc
 CFLAGS = -O3 -Wno-format-overflow
-LIBS   = -lm
-LFLAGS = -L. 
 # Link against the riscv-isa-sim version of SoftFloat rather than 
 # the regular version to get RISC-V NaN behavior
 IFLAGS   = -I$(RISCV)/riscv-isa-sim/softfloat
-LIBS   = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a
+LIBS   = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a -lm -lquadmath
 #IFLAGS = -I../../../addins/SoftFloat-3e/source/include/
-#LIBS   = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a
+#LIBS   = ../../../addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
 SRCS   = $(wildcard *.c)
 
 PROGS = $(patsubst %.c,%,$(SRCS))
@@ -17,7 +15,7 @@ PROGS = $(patsubst %.c,%,$(SRCS))
 all:	$(PROGS)
 
 %: %.c
-	$(CC) $(CFLAGS) $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
+	$(CC) $(CFLAGS) -DSOFTFLOAT_FAST_INT64 $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
 
 clean: 
 	rm -f $(PROGS)
diff --git a/examples/fp/fpcalc/fpcalc.c b/examples/fp/fpcalc/fpcalc.c
index 94bfc9ac1..8264b1442 100644
--- a/examples/fp/fpcalc/fpcalc.c
+++ b/examples/fp/fpcalc/fpcalc.c
@@ -7,6 +7,8 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
+#include <inttypes.h>
+#include <quadmath.h> // GCC Quad-Math Library
 #include "softfloat.h"
 #include "softfloat_types.h"
 
@@ -26,6 +28,12 @@ typedef union dp {
   double d;
 } dp;
 
+typedef union qp {
+  uint64_t v64[2];
+  __uint128_t v;
+  __float128 q;
+} qp;
+
 
 int opSize = 0;
 
@@ -140,6 +148,45 @@ void printF64(char *msg, float64_t f) {
   //  msg, conv.v, conv.d, sci, exp, fract); 
 }
 
+void printF128 (char *msg, float128_t q) {
+  qp conv;
+  //__int128_t v128;
+  int i, j;
+  char buf[64];
+  //v128 = q.v[1];
+  //v128 = v128 << 64 | q.v[0]; // use union to convert between hexadecimal and floating-point views
+  //conv.v = v128;
+  conv.v64[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
+  conv.v64[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views  
+  printf("%s: ", msg);  // print out nicely
+
+  // Some compilers can understand %Q for printf on quad precision instead of the
+  // API call of quadmath_snprintf
+  // printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
+  quadmath_snprintf (buf, sizeof buf, "%1.15Qe", conv.q);
+  //printf("0x%032" PRIx12 " = %s\n", q.v, buf);  
+  printf("0x%016" PRIx64 "_%016" PRIx64 " = %s\n", q.v[1], q.v[0], buf);  
+
+}
+
+void printF128val(float128_t q) {
+  qp conv;
+  //__int128_t v128;
+  int i, j;
+  char buf[64];
+  //v128 = q.v[1];
+  //v128 = v128 << 64 | q.v[0]; // use union to convert between hexadecimal and floating-point views
+  //conv.v = v128;
+  conv.v64[0] = q.v[0]; // use union to convert between hexadecimal and floating-point views
+  conv.v64[1] = q.v[1]; // use union to convert between hexadecimal and floating-point views  
+
+  // Some compilers can understand %Q for printf on quad precision instead of the
+  // API call of quadmath_snprintf
+  // printf("0x%016" PRIx64 "_%016" PRIx64 " = %1.15Qe\n", q.v[1], q.v[0], conv.q);
+  //quadmath_snprintf (buf, sizeof buf, "%1.15Qe", conv.q);
+  printf("%016" PRIx64 "%016" PRIx64 "\n", q.v[1], q.v[0]);  
+}
+
 void printFlags(void) {
   int NX = softfloat_exceptionFlags % 2;
   int UF = (softfloat_exceptionFlags >> 1) % 2;
@@ -160,14 +207,32 @@ void softfloatInit(void) {
     softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
 }
 
-uint64_t parseNum(char *num) {
-  uint64_t result;
+__uint128_t strtoul128(char *num, int base) {
+  __uint128_t result = 0;
+  int i;
+  for (i=0; i<strlen(num); i++) {
+    result = result * base;
+    if (num[i] >= '0' && num[i] <= '9') result += num[i] - '0';
+    else if (num[i] >= 'a' && num[i] <= 'f') result += num[i] - 'a' + 10;
+    else if (num[i] >= 'A' && num[i] <= 'F') result += num[i] - 'A' + 10;
+    else {
+      printf("Error: bad character %c in number %s\n", num[i], num);
+      exit(1);
+    }
+  }
+  return result;
+}
+
+__uint128_t parseNum(char *num) {
+//  uint64_t result;
+  __uint128_t result;
   int size; // size of operands in bytes (2= half, 4=single, 8 = double)
   if (strlen(num) < 8) size = 2;
   else if (strlen(num) < 16) size = 4;
-  else if (strlen(num) < 19) size = 8;
+  else if (strlen(num) < 32) size = 8;
+  else if (strlen(num) < 35) size = 16; // *** will need to increase
   else {
-    printf("Error: only half, single, and double precision supported");
+    printf("Error: only half, single, double, or quad precision supported");
     exit(1);
   }
   if (opSize != 0) {
@@ -179,7 +244,7 @@ uint64_t parseNum(char *num) {
     opSize = size;
     //printf ("Operand size is %d\n", opSize);
   }
-  result = (uint64_t)strtoul(num, NULL, 16);
+  result = (__uint128_t)strtoul128(num, 16);
   //printf("Parsed %s as 0x%lx\n", num, result);
   return result;
 }
@@ -206,7 +271,8 @@ char parseRound(char *rnd) {
 
 int main(int argc, char *argv[])
 {
-    uint64_t xn, yn, zn;
+    //uint64_t xn, yn, zn;
+    __uint128_t xn, yn, zn;
     char op1, op2;
     char cmd[200];
 
@@ -217,6 +283,7 @@ int main(int argc, char *argv[])
       exit(1);
     } else {
       softfloat_roundingMode = softfloat_round_near_even;
+      //printf("argv[0] = %s arvg[1] = %s argv[2] = %s argv[3] = %s\n", argv[0], argv[1], argv[2], argv[3]);
       xn = parseNum(argv[1]);
       yn = parseNum(argv[3]);
       op1 = parseOp(argv[2]);
@@ -241,12 +308,22 @@ int main(int argc, char *argv[])
             r = f32_mulAdd(x, y, z);
             printF32("X", x); printF32("Y", y); printF32("Z", z);
             printF32("result = X*Y+Z", r); printFlags();
-          } else { // opSize = 8
+          } else if (opSize == 8) { 
             float64_t x, y, z, r;
             x.v = xn; y.v = yn; z.v = zn;
             r = f64_mulAdd(x, y, z);
             printF64("X", x); printF64("Y", y); printF64("Z", z);
             printF64("result = X*Y+Z", r); printFlags();
+          } else { // opSize = 16
+            float128_t x, y, z, r;
+            qp xc, yc, zc;
+            xc.v = xn; yc.v = yn; zc.v = zn;
+            x.v[0] = xc.v64[0]; x.v[1] = xc.v64[1];
+            y.v[0] = yc.v64[0]; y.v[1] = yc.v64[1];
+            z.v[0] = zc.v64[0]; z.v[1] = zc.v64[1];
+            r = f128_mulAdd(x, y, z);
+            printF128("X", x); printF128("Y", y); printF128("Z", z);
+            printF128("result = X*Y+Z", r); printFlags();
           }
         }
       } else {
@@ -279,7 +356,7 @@ int main(int argc, char *argv[])
           sprintf(cmd, "0x%08x %c 0x%08x", x.v, op1, y.v);
           printF32(cmd, r); printFlags();
 
-        } else { // opSize = 8
+        } else if (opSize == 8) { // opSize = 8
           float64_t x, y, r;
           x.v = xn; y.v = yn;
           switch (op1) {
@@ -293,7 +370,25 @@ int main(int argc, char *argv[])
           printF64("X", x); printF64("Y", y); 
           sprintf(cmd, "0x%016lx %c 0x%016lx", x.v, op1, y.v);
           printF64(cmd, r); printFlags();
-
+        } else { // opSize = 16
+          float128_t x, y, r;
+          qp xc, yc;
+          xc.v = xn; yc.v = yn;
+          x.v[0] = xc.v64[0]; x.v[1] = xc.v64[1];
+          y.v[0] = yc.v64[0]; y.v[1] = yc.v64[1];
+          //x.v = xn; y.v = yn;
+          switch (op1) {
+            case 'x': r = f128_mul(x, y); break;
+            case '+': r = f128_add(x, y); break;
+            case '-': r = f128_sub(x, y); break;
+            case '/': r = f128_div(x, y); break;
+            case '%': r = f128_rem(x, y); break;
+            default: printf("Unknown op %c\n", op1); exit(1);
+          }
+          printF128("X", x); printF128("Y", y); 
+          //sprintf(cmd, "0x%016lx %c 0x%016lx", x.v, op1, y.v);
+          printF128(cmd, r); printFlags();
+          printF128val(r); 
         }
       }
     }
diff --git a/examples/link/link.ld b/examples/link/link.ld
index 1e20a7a13..174b0e6d8 100644
--- a/examples/link/link.ld
+++ b/examples/link/link.ld
@@ -4,7 +4,7 @@ ENTRY(rvtest_entry_point)
 SECTIONS
 {
   . = 0x80000000;
-  .text : { *(.text.init) }
+  .text : { *(.text.init) *(.text) }
   . = ALIGN(0x1000);
   .tohost : { *(.tohost) }
   . = ALIGN(0x1000);
diff --git a/examples/verilog/fulladder/fulladder.sv b/examples/verilog/fulladder/fulladder.sv
index 478c3db82..156bec3f9 100644
--- a/examples/verilog/fulladder/fulladder.sv
+++ b/examples/verilog/fulladder/fulladder.sv
@@ -19,6 +19,8 @@ module testbench();
   // at start of test, load vectors and pulse reset
   initial
     begin
+      $dumpfile("fulladder.vcd");
+      $dumpvars;
       $readmemb("fulladder.tv", testvectors);
       cycle = 0;
       vectornum = 0; errors = 0;
@@ -47,6 +49,7 @@ module testbench();
         $finish;
       end
     end
+
 endmodule
 
 module fulladder(input  logic a, b, c,
diff --git a/examples/verilog/fulladder/verilate b/examples/verilog/fulladder/verilate
index 2b6d7908d..f1efcc74c 100755
--- a/examples/verilog/fulladder/verilate
+++ b/examples/verilog/fulladder/verilate
@@ -1,5 +1,3 @@
-#verilator --timescale "1ns/1ns" --timing -cc --exe --build --top-module testbench fulladder.sv
-#verilator --timescale "1ns/1ns" --timing -cc --exe --top-module testbench fulladder.sv
-#verilator --binary --top-module testbench fulladder.sv
-verilator --timescale "1ns/1ns" --timing --binary --top-module testbench fulladder.sv
+verilator --binary --top-module testbench --trace fulladder.sv
+obj_dir/Vtestbench
 
diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc
index 6fc660e8d..39495d0be 100644
--- a/fpga/constraints/constraints-ArtyA7.xdc
+++ b/fpga/constraints/constraints-ArtyA7.xdc
@@ -71,6 +71,12 @@ set_property PACKAGE_PIN D9 [get_ports {south_reset}]
 set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}]
 
 
+##### JTAG Port #####
+set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports tck]
+set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports tdo]
+set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports tms]
+set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS33} [get_ports tdi]
+
 
 ##### SD Card I/O #####
 #***** may have to switch to Pmod JB or JC.
diff --git a/fpga/constraints/debug6.xdc b/fpga/constraints/debug6.xdc
new file mode 100644
index 000000000..88ae08ef8
--- /dev/null
+++ b/fpga/constraints/debug6.xdc
@@ -0,0 +1,549 @@
+create_debug_core u_ila_0 ila
+
+set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+startgroup 
+set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
+set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
+set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
+endgroup
+connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
+set_property port_width 64 [get_debug_ports u_ila_0/probe0]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe1]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/core/HRDATA[0]} {wallypipelinedsoc/core/HRDATA[1]} {wallypipelinedsoc/core/HRDATA[2]} {wallypipelinedsoc/core/HRDATA[3]} {wallypipelinedsoc/core/HRDATA[4]} {wallypipelinedsoc/core/HRDATA[5]} {wallypipelinedsoc/core/HRDATA[6]} {wallypipelinedsoc/core/HRDATA[7]} {wallypipelinedsoc/core/HRDATA[8]} {wallypipelinedsoc/core/HRDATA[9]} {wallypipelinedsoc/core/HRDATA[10]} {wallypipelinedsoc/core/HRDATA[11]} {wallypipelinedsoc/core/HRDATA[12]} {wallypipelinedsoc/core/HRDATA[13]} {wallypipelinedsoc/core/HRDATA[14]} {wallypipelinedsoc/core/HRDATA[15]} {wallypipelinedsoc/core/HRDATA[16]} {wallypipelinedsoc/core/HRDATA[17]} {wallypipelinedsoc/core/HRDATA[18]} {wallypipelinedsoc/core/HRDATA[19]} {wallypipelinedsoc/core/HRDATA[20]} {wallypipelinedsoc/core/HRDATA[21]} {wallypipelinedsoc/core/HRDATA[22]} {wallypipelinedsoc/core/HRDATA[23]} {wallypipelinedsoc/core/HRDATA[24]} {wallypipelinedsoc/core/HRDATA[25]} {wallypipelinedsoc/core/HRDATA[26]} {wallypipelinedsoc/core/HRDATA[27]} {wallypipelinedsoc/core/HRDATA[28]} {wallypipelinedsoc/core/HRDATA[29]} {wallypipelinedsoc/core/HRDATA[30]} {wallypipelinedsoc/core/HRDATA[31]} {wallypipelinedsoc/core/HRDATA[32]} {wallypipelinedsoc/core/HRDATA[33]} {wallypipelinedsoc/core/HRDATA[34]} {wallypipelinedsoc/core/HRDATA[35]} {wallypipelinedsoc/core/HRDATA[36]} {wallypipelinedsoc/core/HRDATA[37]} {wallypipelinedsoc/core/HRDATA[38]} {wallypipelinedsoc/core/HRDATA[39]} {wallypipelinedsoc/core/HRDATA[40]} {wallypipelinedsoc/core/HRDATA[41]} {wallypipelinedsoc/core/HRDATA[42]} {wallypipelinedsoc/core/HRDATA[43]} {wallypipelinedsoc/core/HRDATA[44]} {wallypipelinedsoc/core/HRDATA[45]} {wallypipelinedsoc/core/HRDATA[46]} {wallypipelinedsoc/core/HRDATA[47]} {wallypipelinedsoc/core/HRDATA[48]} {wallypipelinedsoc/core/HRDATA[49]} {wallypipelinedsoc/core/HRDATA[50]} {wallypipelinedsoc/core/HRDATA[51]} {wallypipelinedsoc/core/HRDATA[52]} {wallypipelinedsoc/core/HRDATA[53]} {wallypipelinedsoc/core/HRDATA[54]} {wallypipelinedsoc/core/HRDATA[55]} {wallypipelinedsoc/core/HRDATA[56]} {wallypipelinedsoc/core/HRDATA[57]} {wallypipelinedsoc/core/HRDATA[58]} {wallypipelinedsoc/core/HRDATA[59]} {wallypipelinedsoc/core/HRDATA[60]} {wallypipelinedsoc/core/HRDATA[61]} {wallypipelinedsoc/core/HRDATA[62]} {wallypipelinedsoc/core/HRDATA[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe2]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 6 [get_debug_ports u_ila_0/probe3]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe4]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe5]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe6]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe7]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe8]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsoc/core/IEUAdrM[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe9]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 2 [get_debug_ports u_ila_0/probe10]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsoc/core/MemRWM[1]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 6 [get_debug_ports u_ila_0/probe11]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe12]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 6 [get_debug_ports u_ila_0/probe13]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 4 [get_debug_ports u_ila_0/probe14]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe15]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe16]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe17]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe18]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 6 [get_debug_ports u_ila_0/probe19]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 2 [get_debug_ports u_ila_0/probe20]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHSIZE[0]} {wallypipelinedsoc/core/lsu/LSUHSIZE[1]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe21]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe22]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list wallypipelinedsoc/core/lsu/LSUHWRITE ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 3 [get_debug_ports u_ila_0/probe23]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHBURST[0]} wallypipelinedsoc/core/lsu/LSUHBURST[1] wallypipelinedsoc/core/lsu/LSUHBURST[2] ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe24]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe25]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe26]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
+connect_debug_port u_ila_0/probe26 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe27]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
+connect_debug_port u_ila_0/probe27 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe28]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
+connect_debug_port u_ila_0/probe28 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe29]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
+connect_debug_port u_ila_0/probe29 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe30]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
+connect_debug_port u_ila_0/probe30 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe31]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
+connect_debug_port u_ila_0/probe31 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe32]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
+connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe33]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
+connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe34]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
+connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe35]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
+connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe36]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
+connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/core/TrapM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe37]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
+connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/core/hzu/BPWrongE ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe38]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
+connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/core/hzu/CSRWriteFenceM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe39]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
+connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/core/hzu/RetM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe40]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
+connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/core/TrapM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe41]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
+connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/core/hzu/LSUStallM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe42]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
+connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/core/hzu/IFUStallF ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe43]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
+connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 7 [get_debug_ports u_ila_0/probe44]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
+connect_debug_port u_ila_0/probe44 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][7]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe45]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
+connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/core/hzu/FDivBusyE ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe46]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
+connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/core/hzu/StallF ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe47]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
+connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/core/hzu/StallDCause]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe48]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
+connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/core/hzu/StallE ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe49]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
+connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]]
+
+# StallW is StallM.  trying to connect to StallW causes issues.
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe50]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
+connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe51]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
+connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/core/hzu/FlushD ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe52]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
+connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/core/hzu/FlushE ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe53]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
+connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/core/hzu/FlushM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe54]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
+connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/hzu/FlushW ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 4 [get_debug_ports u_ila_0/probe55]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
+connect_debug_port u_ila_0/probe55 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 2 [get_debug_ports u_ila_0/probe56]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
+connect_debug_port u_ila_0/probe56 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe57]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
+connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/core/ifu/IFUHREADY ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe58]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
+connect_debug_port u_ila_0/probe58 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHADDR[0]} {wallypipelinedsoc/core/ifu/IFUHADDR[1]} {wallypipelinedsoc/core/ifu/IFUHADDR[2]} {wallypipelinedsoc/core/ifu/IFUHADDR[3]} {wallypipelinedsoc/core/ifu/IFUHADDR[4]} {wallypipelinedsoc/core/ifu/IFUHADDR[5]} {wallypipelinedsoc/core/ifu/IFUHADDR[6]} {wallypipelinedsoc/core/ifu/IFUHADDR[7]} {wallypipelinedsoc/core/ifu/IFUHADDR[8]} {wallypipelinedsoc/core/ifu/IFUHADDR[9]} {wallypipelinedsoc/core/ifu/IFUHADDR[10]} {wallypipelinedsoc/core/ifu/IFUHADDR[11]} {wallypipelinedsoc/core/ifu/IFUHADDR[12]} {wallypipelinedsoc/core/ifu/IFUHADDR[13]} {wallypipelinedsoc/core/ifu/IFUHADDR[14]} {wallypipelinedsoc/core/ifu/IFUHADDR[15]} {wallypipelinedsoc/core/ifu/IFUHADDR[16]} {wallypipelinedsoc/core/ifu/IFUHADDR[17]} {wallypipelinedsoc/core/ifu/IFUHADDR[18]} {wallypipelinedsoc/core/ifu/IFUHADDR[19]} {wallypipelinedsoc/core/ifu/IFUHADDR[20]} {wallypipelinedsoc/core/ifu/IFUHADDR[21]} {wallypipelinedsoc/core/ifu/IFUHADDR[22]} {wallypipelinedsoc/core/ifu/IFUHADDR[23]} {wallypipelinedsoc/core/ifu/IFUHADDR[24]} {wallypipelinedsoc/core/ifu/IFUHADDR[25]} {wallypipelinedsoc/core/ifu/IFUHADDR[26]} {wallypipelinedsoc/core/ifu/IFUHADDR[27]} {wallypipelinedsoc/core/ifu/IFUHADDR[28]} {wallypipelinedsoc/core/ifu/IFUHADDR[29]} {wallypipelinedsoc/core/ifu/IFUHADDR[30]} {wallypipelinedsoc/core/ifu/IFUHADDR[31]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 2 [get_debug_ports u_ila_0/probe59]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
+connect_debug_port u_ila_0/probe59 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHTRANS[0]} {wallypipelinedsoc/core/ifu/IFUHTRANS[0]}]]
+
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 2 [get_debug_ports u_ila_0/probe60]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
+connect_debug_port u_ila_0/probe60 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 53 [get_debug_ports u_ila_0/probe61]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
+connect_debug_port u_ila_0/probe61 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][53]} ]]
+
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe62]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
+connect_debug_port u_ila_0/probe62 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe63]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
+connect_debug_port u_ila_0/probe63 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HREADY}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe64]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
+connect_debug_port u_ila_0/probe64 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HRESP}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe65]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
+connect_debug_port u_ila_0/probe65 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HWRITE}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 3 [get_debug_ports u_ila_0/probe66]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
+connect_debug_port u_ila_0/probe66 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 3 [get_debug_ports u_ila_0/probe67]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
+connect_debug_port u_ila_0/probe67 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 4 [get_debug_ports u_ila_0/probe68]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
+connect_debug_port u_ila_0/probe68 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe69]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
+connect_debug_port u_ila_0/probe69 [get_nets [list {wallypipelinedsoc/core/priv.priv/InterruptM}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe70]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
+connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/core/lsu/ITLBMissF]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe71]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71]
+connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/core/lsu/DTLBMissM]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe72]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72]
+connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsoc/core/lsu/ITLBWriteF]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe73]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73]
+connect_debug_port u_ila_0/probe73 [get_nets [list wallypipelinedsoc/core/lsu/DTLBWriteM]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 4 [get_debug_ports u_ila_0/probe74]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74]
+connect_debug_port u_ila_0/probe74 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[0]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[1]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[2]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe75]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75]
+connect_debug_port u_ila_0/probe75 [get_nets [list {wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsoc/core/SrcAM[63]}]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 56 [get_debug_ports u_ila_0/probe76]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76]
+connect_debug_port u_ila_0/probe76 [get_nets [list {wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsoc/core/ifu/PCPF[55]} ]]
+
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 3 [get_debug_ports u_ila_0/probe77]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe77]
+connect_debug_port u_ila_0/probe77 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe78]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe78]
+connect_debug_port u_ila_0/probe78 [get_nets [list wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 3 [get_debug_ports u_ila_0/probe79]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe79]
+connect_debug_port u_ila_0/probe79 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 7 [get_debug_ports u_ila_0/probe80]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe80]
+connect_debug_port u_ila_0/probe80 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][7]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe81]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe81]
+connect_debug_port u_ila_0/probe81 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe82]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe82]
+connect_debug_port u_ila_0/probe82 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe83]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83]
+connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe84]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84]
+connect_debug_port u_ila_0/probe84 [get_nets [list wallypipelinedsoc/core/ieu/dp/RegWriteW]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe85]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe85]
+connect_debug_port u_ila_0/probe85 [get_nets [list {wallypipelinedsoc/core/priv.priv/CSRWriteM} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe86]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe86]
+connect_debug_port u_ila_0/probe86 [get_nets [list {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe87]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe87]
+connect_debug_port u_ila_0/probe87 [get_nets [list {wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsoc/core/ifu/PCNextF[63]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe88]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88]
+connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe89]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe89]
+connect_debug_port u_ila_0/probe89 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe90]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe90]
+connect_debug_port u_ila_0/probe90 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe91]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe91]
+connect_debug_port u_ila_0/probe91 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 12 [get_debug_ports u_ila_0/probe92]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92]
+connect_debug_port u_ila_0/probe92 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 12 [get_debug_ports u_ila_0/probe93]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93]
+connect_debug_port u_ila_0/probe93 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe94]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94]
+connect_debug_port u_ila_0/probe94 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe95]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe95]
+connect_debug_port u_ila_0/probe95 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe96]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe96]
+connect_debug_port u_ila_0/probe96 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe97]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe97]
+connect_debug_port u_ila_0/probe97 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe98]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe98]
+connect_debug_port u_ila_0/probe98 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe99]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
+connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 49 [get_debug_ports u_ila_0/probe100]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100]
+connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/core/lsu/PTE[0]}  {wallypipelinedsoc/core/lsu/PTE[3]} {wallypipelinedsoc/core/lsu/PTE[4]} {wallypipelinedsoc/core/lsu/PTE[5]} {wallypipelinedsoc/core/lsu/PTE[6]} {wallypipelinedsoc/core/lsu/PTE[10]} {wallypipelinedsoc/core/lsu/PTE[11]} {wallypipelinedsoc/core/lsu/PTE[12]} {wallypipelinedsoc/core/lsu/PTE[13]} {wallypipelinedsoc/core/lsu/PTE[14]} {wallypipelinedsoc/core/lsu/PTE[15]} {wallypipelinedsoc/core/lsu/PTE[16]} {wallypipelinedsoc/core/lsu/PTE[17]} {wallypipelinedsoc/core/lsu/PTE[18]} {wallypipelinedsoc/core/lsu/PTE[19]} {wallypipelinedsoc/core/lsu/PTE[20]} {wallypipelinedsoc/core/lsu/PTE[21]} {wallypipelinedsoc/core/lsu/PTE[22]} {wallypipelinedsoc/core/lsu/PTE[23]} {wallypipelinedsoc/core/lsu/PTE[24]} {wallypipelinedsoc/core/lsu/PTE[25]} {wallypipelinedsoc/core/lsu/PTE[26]} {wallypipelinedsoc/core/lsu/PTE[27]} {wallypipelinedsoc/core/lsu/PTE[28]} {wallypipelinedsoc/core/lsu/PTE[29]} {wallypipelinedsoc/core/lsu/PTE[30]} {wallypipelinedsoc/core/lsu/PTE[31]} {wallypipelinedsoc/core/lsu/PTE[32]} {wallypipelinedsoc/core/lsu/PTE[33]} {wallypipelinedsoc/core/lsu/PTE[34]} {wallypipelinedsoc/core/lsu/PTE[35]} {wallypipelinedsoc/core/lsu/PTE[36]} {wallypipelinedsoc/core/lsu/PTE[37]} {wallypipelinedsoc/core/lsu/PTE[38]} {wallypipelinedsoc/core/lsu/PTE[39]} {wallypipelinedsoc/core/lsu/PTE[40]} {wallypipelinedsoc/core/lsu/PTE[41]} {wallypipelinedsoc/core/lsu/PTE[42]} {wallypipelinedsoc/core/lsu/PTE[43]} {wallypipelinedsoc/core/lsu/PTE[44]} {wallypipelinedsoc/core/lsu/PTE[45]} {wallypipelinedsoc/core/lsu/PTE[46]} {wallypipelinedsoc/core/lsu/PTE[47]} {wallypipelinedsoc/core/lsu/PTE[48]} {wallypipelinedsoc/core/lsu/PTE[49]} {wallypipelinedsoc/core/lsu/PTE[50]} {wallypipelinedsoc/core/lsu/PTE[51]} {wallypipelinedsoc/core/lsu/PTE[52]} {wallypipelinedsoc/core/lsu/PTE[53]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe101]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101]
+connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/ValidNonLeafPTE}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe102]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102]
+connect_debug_port u_ila_0/probe102 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/ValidLeafPTE}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe103]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103]
+connect_debug_port u_ila_0/probe103 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/ValidPTE}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe104]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104]
+connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/LeafPTE}]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 48 [get_debug_ports u_ila_0/probe105]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105]
+connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[0]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[1]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[2]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[3]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[4]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[5]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[6]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[7]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[8]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[9]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[10]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[11]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[12]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[13]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[14]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[15]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[16]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[17]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[18]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[19]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[20]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[21]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[22]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[23]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[24]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[25]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[26]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[27]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[28]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[29]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[30]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[31]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[32]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[33]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[34]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[35]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[36]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[37]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[38]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[39]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[40]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[41]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[42]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[43]}  {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[60]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[61]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[62]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[63]}]]
diff --git a/fpga/constraints/marked_debug_all.txt b/fpga/constraints/marked_debug_all.txt
index 3973fc451..1ddec51c9 100644
--- a/fpga/constraints/marked_debug_all.txt
+++ b/fpga/constraints/marked_debug_all.txt
@@ -45,6 +45,7 @@ ifu/ifu.sv: logic            PCPF
 ifu/ifu.sv: logic     PostSpillInstrRawF
 mmu/hptw.sv: logic	   ITLBWriteF
 mmu/hptw.sv:	 statetype WalkerState
+mmu/hptw.sv: logic  ValidPTE
 privileged/csrs.sv: logic        CSRSReadValM
 privileged/csrs.sv: logic        SEPC_REGW
 privileged/csrs.sv: logic        MIP_REGW
diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index e6807a6a6..df4ed0e2a 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -57,7 +57,8 @@ PreProcessFiles:
 	# modify config  *** RT: eventually setup for variably defined sized memory
 	#sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
 	# This line allows the Bootloader to be loaded in a Block RAM on the FPGA
-	sed -i "s/logic \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
+	sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
+	sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
 
 $(dst)/%.log: %.tcl
 	mkdir -p IP
diff --git a/fpga/generator/insert_debug_comment.sh b/fpga/generator/insert_debug_comment.sh
index 35fa05a02..5f8e3fce1 100755
--- a/fpga/generator/insert_debug_comment.sh
+++ b/fpga/generator/insert_debug_comment.sh
@@ -2,9 +2,9 @@
 ###########################################
 ## insert_debug_comment.sh
 ##
-## Written: Ross Thompson ross1728@gmail.com
+## Written: Rose Thompson ross1728@gmail.com
 ## Created: 20 January 2023
-## Modified: 20 January 2023
+## Modified: 22 April 2024
 ##
 ## A component of the CORE-V-WALLY configurable RISC-V project.
 ## https://github.com/openhwgroup/cvw
@@ -34,6 +34,7 @@ while read line; do
     signal=`echo "${StrArray[1]}" | awk '{$1=$1};1'`
     readarray -d " " -t SigArray <<< $signal
     sigType=`echo "${SigArray[0]}" | awk '{$1=$1};1'`
-    sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1'`
-    find $copiedDir -wholename $file | xargs sed -i "s/\(.*${sigType}.*${sigName}\)/(\* mark_debug = \"true\" \*)\1/g" 
+    sigName=`echo "${SigArray[1]}" | awk '{$1=$1};1' | tr -d "\015"`
+    filepath=`find $copiedDir -wholename $file`
+    sed -i "s/\(.*${sigType}.*${sigName}.*\)/(\* mark_debug = \"true\" \*)\1/g" $filepath
 done < ../constraints/marked_debug.txt
diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index 4939881a9..eff0a6cb9 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -19,7 +19,7 @@ read_verilog -sv  ../src/CopiedFiles_do_not_add_to_repo/cvw.sv
 if {$board=="ArtyA7"} {
     read_verilog  {../src/fpgaTopArtyA7.sv}
 } else {
-    read_verilog  {../src/fpgaTop.v}
+    read_verilog  {../src/fpgaTop.sv}
 }
 
 # read in ip
@@ -93,7 +93,7 @@ if {$board=="ArtyA7"} {
 
 } else {
     # source ../constraints/vcu-small-debug.xdc
-    source ../constraints/debug4.xdc
+    source ../constraints/debug6.xdc
 }
 
 
diff --git a/fpga/renumber.py b/fpga/renumber.py
new file mode 100755
index 000000000..adf625920
--- /dev/null
+++ b/fpga/renumber.py
@@ -0,0 +1,33 @@
+#!/usr/bin/python3
+import sys
+import re
+
+def usage():
+    print("Usage: ./renumber.py <input xdc file> <output xdc file>")
+
+def main(args):
+    if (len(args) != 2):
+        usage()
+        exit()
+
+    probenum = 0
+    countLines = 1
+        
+    with open(args[0],'r') as xdcfile, open(args[1], 'w') as outfile:
+        Lines = xdcfile.readlines()
+        for line in Lines:
+            t = re.sub("probe[0-9]+", f"probe{probenum}",line)
+            
+            if line.find("probe") >= 0:
+                countLines = countLines + 1
+                
+            if countLines == 4:
+                countLines = 0
+                probenum = probenum + 1
+
+            outfile.write(t)
+
+
+
+if __name__ == '__main__':
+    main(sys.argv[1:])
diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.sv
similarity index 95%
rename from fpga/src/fpgaTop.v
rename to fpga/src/fpgaTop.sv
index 6038bb677..20ffd4b08 100644
--- a/fpga/src/fpgaTop.v
+++ b/fpga/src/fpgaTop.sv
@@ -24,6 +24,10 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
+`include "config.vh"
+
+import cvw::*;
+
 module fpgaTop 
   (input           default_250mhz_clk1_0_n,
    input           default_250mhz_clk1_0_p, 
@@ -76,8 +80,9 @@ module fpgaTop
   wire 			   HRESPEXT;
   (* mark_debug = "true" *) wire 			   HSELEXT;
   (* mark_debug = "true" *) wire             HSELEXTSDC; // TEMP BOOT SIGNAL - JACOB
-  wire [31:0] 	   HADDR;
+  wire [55:0] 	   HADDR;
   wire [64-1:0]    HWDATA;
+  wire [64/8-1:0]  HWSTRB;
   wire 			   HWRITE;
   wire [2:0] 	   HSIZE;
   wire [2:0] 	   HBURST;
@@ -478,45 +483,55 @@ module fpgaTop
      .peripheral_reset(peripheral_reset), //open
      .interconnect_aresetn(interconnect_aresetn), //open
      .peripheral_aresetn(peripheral_aresetn));
+
+  `include "parameter-defs.vh"
+
+  wallypipelinedsoc  #(P) 
+  wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(), 
+                    .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT,
+                    .HSELEXTSDC, .HCLK(HCLKOpen), .HRESETn(HRESETnOpen), 
+                    .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+                    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), 
+                    .GPIOIN, .GPIOOUT, .GPIOEN,
+                    .UARTSin, .UARTSout, .SDCIntr); 
   
 
-  // wally
-  // *** FIXME add sdc interrupt and HSELEXTSDC, remove old sdc
-  wallypipelinedsocwrapper wallypipelinedsocwrapper
-    (.clk(CPUCLK),
-     .reset_ext(bus_struct_reset),
-     // bus interface
-     .HRDATAEXT(HRDATAEXT),
-     .HREADYEXT(HREADYEXT),
-     .HRESPEXT(HRESPEXT),
-     .HSELEXT(HSELEXT),
-     .HSELEXTSDC(HSELEXTSDC),
-     .HCLK(HCLKOpen), // open
-     .HRESETn(HRESETnOpen), // open
-     .HADDR(HADDR),
-     .HWDATA(HWDATA),
-     .HWRITE(HWRITE),
-     .HSIZE(HSIZE),
-     .HBURST(HBURST),
-     .HPROT(HPROT),
-     .HTRANS(HTRANS),
-     .HMASTLOCK(HMASTLOCK),
-     .HREADY(HREADY),
-     // GPIO
-     .GPIOIN(GPIOIN),
-     .GPIOOUT(GPIOOUT),
-     .GPIOEN(GPIOEN),
-     // UART
-     .UARTSin(UARTSin),
-     .UARTSout(UARTSout),
-     .SDCIntr(SDCIntr)
-     // SD Card   
-     /*.SDCDatIn(SDCDatIn),
-     .SDCCmdIn(SDCCmdIn),     
-     .SDCCmdOut(SDCCmdOut),
-     .SDCCmdOE(SDCCmdOE),
-     .SDCCLK(SDCCLK));*/
-     );
+  // RT and JP: FIXME add sdc interrupt and HSELEXTSDC, remove old sdc after the new sdc ahb version is implemented
+  // wallypipelinedsocwrapper wallypipelinedsocwrapper
+  //   (.clk(CPUCLK),
+  //    .reset_ext(bus_struct_reset),
+  //    // bus interface
+  //    .HRDATAEXT(HRDATAEXT),
+  //    .HREADYEXT(HREADYEXT),
+  //    .HRESPEXT(HRESPEXT),
+  //    .HSELEXT(HSELEXT),
+  //    .HSELEXTSDC(HSELEXTSDC),
+  //    .HCLK(HCLKOpen), // open
+  //    .HRESETn(HRESETnOpen), // open
+  //    .HADDR(HADDR),
+  //    .HWDATA(HWDATA),
+  //    .HWRITE(HWRITE),
+  //    .HSIZE(HSIZE),
+  //    .HBURST(HBURST),
+  //    .HPROT(HPROT),
+  //    .HTRANS(HTRANS),
+  //    .HMASTLOCK(HMASTLOCK),
+  //    .HREADY(HREADY),
+  //    // GPIO
+  //    .GPIOIN(GPIOIN),
+  //    .GPIOOUT(GPIOOUT),
+  //    .GPIOEN(GPIOEN),
+  //    // UART
+  //    .UARTSin(UARTSin),
+  //    .UARTSout(UARTSout),
+  //    .SDCIntr(SDCIntr)
+  //    // SD Card   
+  //    /*.SDCDatIn(SDCDatIn),
+  //    .SDCCmdIn(SDCCmdIn),     
+  //    .SDCCmdOut(SDCCmdOut),
+  //    .SDCCmdOE(SDCCmdOE),
+  //    .SDCCLK(SDCCLK));*/
+  //    );
   
   // ahb lite to axi bridge
   xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0
diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv
index 20e8adb81..796106a0e 100644
--- a/fpga/src/fpgaTopArtyA7.sv
+++ b/fpga/src/fpgaTopArtyA7.sv
@@ -58,7 +58,12 @@ module fpgaTop
    output [0:0]    ddr3_cke,
    output [0:0]    ddr3_cs_n,
    output [1:0]    ddr3_dm,
-   output [0:0]    ddr3_odt
+   output [0:0]    ddr3_odt,
+   // JTAG signals
+   input           tck,
+   input           tdi,
+   input           tms,
+   output          tdo
    );
 
   wire 			   CPUCLK;
@@ -485,12 +490,12 @@ module fpgaTop
      .peripheral_aresetn(peripheral_aresetn));
 
   // wally
-  // *** FIXME add sdc interrupt and HSELEXTSDC, remove old sdc
+  // RT and JP: FIXME add sdc interrupt and HSELEXTSDC, remove old sdc after the new sdc ahb version is implemented
 
   `include "parameter-defs.vh"
 
   wallypipelinedsoc  #(P) 
-  wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(), 
+  wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(), .tck, .tdi, .tms, .tdo,
                     .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT,
                     .HSELEXTSDC, .HCLK(HCLKOpen), .HRESETn(HRESETnOpen), 
                     .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
@@ -1048,7 +1053,6 @@ module fpgaTop
      .sys_rst(resetn),    // omg. this is active low?!?!?? 
      .mmcm_locked(mmcm_locked),
 
-     // *** What are these? 
      .app_sr_req(1'b0),  // reserved command
      .app_ref_req(1'b0), // refresh command
      .app_zq_req(1'b0),  // recalibrate command
diff --git a/fpga/zsbl/Makefile b/fpga/zsbl/Makefile
index bd30033fc..37323b813 100644
--- a/fpga/zsbl/Makefile
+++ b/fpga/zsbl/Makefile
@@ -16,7 +16,7 @@ OBJECTS		:= $(OBJECTS:.$(CPPEXT)=.$(OBJEXT))
 OBJECTS		:= $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS))
 
 TARGETDIR	:= bin
-TARGET		:= $(TARGETDIR)/fpga-test-sdc
+TARGET		:= $(TARGETDIR)/boot
 ROOT		:= ..
 LIBRARY_DIRS	:= 
 LIBRARY_FILES	:=
@@ -24,11 +24,13 @@ LIBRARY_FILES	:=
 MARCH           :=-march=rv64imfdc_zifencei
 MABI            :=-mabi=lp64d
 LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles
-LINKER		:=linker.x
+LINKER		:=linker1000.x
 
 
 AFLAGS =$(MARCH) $(MABI) -W
-CFLAGS =$(MARCH) $(MABI) -mcmodel=medany  -O2
+# Override directive allows us to prepend other options on the command line
+# e.g. $ make CFLAGS=-g
+override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 -g
 AS=riscv64-unknown-elf-as
 CC=riscv64-unknown-elf-gcc
 AR=riscv64-unknown-elf-ar
@@ -104,7 +106,7 @@ $(BUILDDIR)/%.$(OBJEXT): $(SRCDIR)/%.$(CPPEXT)
 # convert to hex
 $(TARGET).memfile: $(TARGET)
 	@echo 'Making object dump file.'
-	@riscv64-unknown-elf-objdump -D $< > $<.objdump
+	riscv64-unknown-elf-objdump -DS $< > $<.objdump
 	@echo 'Making memory file'
 	riscv64-unknown-elf-elf2hex --bit-width 64 --input $^ --output $@
 	extractFunctionRadix.sh $<.objdump
diff --git a/fpga/zsbl/bios.s b/fpga/zsbl/bios.s
index 7954eab7a..9a5d6e21f 100644
--- a/fpga/zsbl/bios.s
+++ b/fpga/zsbl/bios.s
@@ -49,7 +49,12 @@ _start:
 	# set the stack pointer to the top of memory - 8 bytes (pointer size)
 	li sp, 0x87FFFFF8
 
-	jal ra, main
+	li a0, 0x00000000
+	li a1, 0x80000000
+	#li a2, 128*1024*1024/512 # copy 128MB
+	li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra)
+	#li a2, 800 # copy 400KB
+	jal ra, copyFlash
 	
 	fence.i
 	# now toggle led so we know the copy completed.
@@ -81,18 +86,16 @@ delay2:
 	# now that the card is copied and the led toggled we
 	# jump to the copied contents of the sd card.
 
-jumpToLinux:
-	csrr a0, mhartid
-        li s0, 0x80000000
-        la a1, _dtb
-        jr s0
-end_of_bios:	
+jumpToLinux:	
+	csrrs	a0, 0xF14, x0   # copy hart ID to a0
+	li	a1, 0x87000000  # end of memory? not 100% sure on this but it's 112MB
+	la	a2, end_of_bios
+	li	t0, 0x80000000  # start of code
+	
+	jalr	x0, t0, 0
 
+end_of_bios:	
 
+	
 
-.section .rodata
-.globl _dtb
-.align 4, 0
-_dtb:
-#.incbin "wally-vcu118.dtb"
 
diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c
new file mode 100644
index 000000000..6e4780f55
--- /dev/null
+++ b/fpga/zsbl/boot.c
@@ -0,0 +1,422 @@
+#include <stddef.h>
+#include "boot.h"
+#include "gpt.h"
+
+/* Card type flags (card_type) */
+#define CT_MMC          0x01            /* MMC ver 3 */
+#define CT_SD1          0x02            /* SD ver 1 */
+#define CT_SD2          0x04            /* SD ver 2 */
+#define CT_SDC          (CT_SD1|CT_SD2) /* SD */
+#define CT_BLOCK        0x08            /* Block addressing */
+
+#define CMD0    (0)             /* GO_IDLE_STATE */
+#define CMD1    (1)             /* SEND_OP_COND */
+#define CMD2    (2)             /* SEND_CID */
+#define CMD3    (3)             /* RELATIVE_ADDR */
+#define CMD4    (4)
+#define CMD5    (5)             /* SLEEP_WAKE (SDC) */
+#define CMD6    (6)             /* SWITCH_FUNC */
+#define CMD7    (7)             /* SELECT */
+#define CMD8    (8)             /* SEND_IF_COND */
+#define CMD9    (9)             /* SEND_CSD */
+#define CMD10   (10)            /* SEND_CID */
+#define CMD11   (11)
+#define CMD12   (12)            /* STOP_TRANSMISSION */
+#define CMD13   (13)
+#define CMD15   (15)
+#define CMD16   (16)            /* SET_BLOCKLEN */
+#define CMD17   (17)            /* READ_SINGLE_BLOCK */
+#define CMD18   (18)            /* READ_MULTIPLE_BLOCK */
+#define CMD19   (19)
+#define CMD20   (20)
+#define CMD23   (23)
+#define CMD24   (24)
+#define CMD25   (25)
+#define CMD27   (27)
+#define CMD28   (28)
+#define CMD29   (29)
+#define CMD30   (30)
+#define CMD32   (32)
+#define CMD33   (33)
+#define CMD38   (38)
+#define CMD42   (42)
+#define CMD55   (55)            /* APP_CMD */
+#define CMD56   (56)
+#define ACMD6   (0x80+6)        /* define the data bus width */
+#define ACMD41  (0x80+41)       /* SEND_OP_COND (ACMD) */
+
+// Capability bits
+#define SDC_CAPABILITY_SD_4BIT  0x0001
+#define SDC_CAPABILITY_SD_RESET 0x0002
+#define SDC_CAPABILITY_ADDR     0xff00
+
+// Control bits
+#define SDC_CONTROL_SD_4BIT     0x0001
+#define SDC_CONTROL_SD_RESET    0x0002
+
+// Card detect bits
+#define SDC_CARD_INSERT_INT_EN  0x0001
+#define SDC_CARD_INSERT_INT_REQ 0x0002
+#define SDC_CARD_REMOVE_INT_EN  0x0004
+#define SDC_CARD_REMOVE_INT_REQ 0x0008
+
+// Command status bits
+#define SDC_CMD_INT_STATUS_CC   0x0001  // Command complete
+#define SDC_CMD_INT_STATUS_EI   0x0002  // Any error
+#define SDC_CMD_INT_STATUS_CTE  0x0004  // Timeout
+#define SDC_CMD_INT_STATUS_CCRC 0x0008  // CRC error
+#define SDC_CMD_INT_STATUS_CIE  0x0010  // Command code check error
+
+// Data status bits
+#define SDC_DAT_INT_STATUS_TRS  0x0001  // Transfer complete
+#define SDC_DAT_INT_STATUS_ERR  0x0002  // Any error
+#define SDC_DAT_INT_STATUS_CTE  0x0004  // Timeout
+#define SDC_DAT_INT_STATUS_CRC  0x0008  // CRC error
+#define SDC_DAT_INT_STATUS_CFE  0x0010  // Data FIFO underrun or overrun
+
+
+#define ERR_EOF             30
+#define ERR_NOT_ELF         31
+#define ERR_ELF_BITS        32
+#define ERR_ELF_ENDIANNESS  33
+#define ERR_CMD_CRC         34
+#define ERR_CMD_CHECK       35
+#define ERR_DATA_CRC        36
+#define ERR_DATA_FIFO       37
+#define ERR_BUF_ALIGNMENT   38
+#define FR_DISK_ERR         39
+#define FR_TIMEOUT          40
+
+struct sdc_regs {
+    volatile uint32_t argument;
+    volatile uint32_t command;
+    volatile uint32_t response1;
+    volatile uint32_t response2;
+    volatile uint32_t response3;
+    volatile uint32_t response4;
+    volatile uint32_t data_timeout;
+    volatile uint32_t control;
+    volatile uint32_t cmd_timeout;
+    volatile uint32_t clock_divider;
+    volatile uint32_t software_reset;
+    volatile uint32_t power_control;
+    volatile uint32_t capability;
+    volatile uint32_t cmd_int_status;
+    volatile uint32_t cmd_int_enable;
+    volatile uint32_t dat_int_status;
+    volatile uint32_t dat_int_enable;
+    volatile uint32_t block_size;
+    volatile uint32_t block_count;
+    volatile uint32_t card_detect;
+    volatile uint32_t res_50;
+    volatile uint32_t res_54;
+    volatile uint32_t res_58;
+    volatile uint32_t res_5c;
+    volatile uint64_t dma_addres;
+};
+
+#define MAX_BLOCK_CNT 0x1000
+
+#define SDC 0x00013000;
+
+// static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013000;
+
+// static int errno __attribute__((section(".bss")));
+// static DSTATUS drv_status __attribute__((section(".bss")));
+// static BYTE card_type __attribute__((section(".bss")));
+// static uint32_t response[4] __attribute__((section(".bss")));
+// static int alt_mem __attribute__((section(".bss")));
+
+/*static const char * errno_to_str(void) {
+    switch (errno) {
+    case ERR_EOF: return "Unexpected EOF";
+    case ERR_NOT_ELF: return "Not an ELF file";
+    case ERR_ELF_BITS: return "Wrong ELF word size";
+    case ERR_ELF_ENDIANNESS: return "Wrong ELF endianness";
+    case ERR_CMD_CRC: return "Command CRC error";
+    case ERR_CMD_CHECK: return "Command code check error";
+    case ERR_DATA_CRC: return "Data CRC error";
+    case ERR_DATA_FIFO: return "Data FIFO error";
+    case ERR_BUF_ALIGNMENT: return "Bad buffer alignment";
+    case FR_DISK_ERR: return "Disk error";
+    case FR_TIMEOUT: return "Timeout";
+    }
+    return "Unknown error code";
+    }*/
+
+static void usleep(unsigned us) {
+    uintptr_t cycles0;
+    uintptr_t cycles1;
+    asm volatile ("csrr %0, 0xB00" : "=r" (cycles0));
+    for (;;) {
+        asm volatile ("csrr %0, 0xB00" : "=r" (cycles1));
+        if (cycles1 - cycles0 >= us * 100) break;
+    }
+}
+
+static int sdc_cmd_finish(unsigned cmd, uint32_t * response) {
+  struct sdc_regs * regs = (struct sdc_regs *)SDC;
+  
+    while (1) {
+        unsigned status = regs->cmd_int_status;
+        if (status) {
+            // clear interrupts
+            regs->cmd_int_status = 0;
+            while (regs->software_reset != 0) {}
+            if (status == SDC_CMD_INT_STATUS_CC) {
+                // get response
+                response[0] = regs->response1;
+                response[1] = regs->response2;
+                response[2] = regs->response3;
+                response[3] = regs->response4;
+                return 0;
+            }
+            /* errno = FR_DISK_ERR;
+            if (status & SDC_CMD_INT_STATUS_CTE) errno = FR_TIMEOUT;
+            if (status & SDC_CMD_INT_STATUS_CCRC) errno = ERR_CMD_CRC;
+            if (status & SDC_CMD_INT_STATUS_CIE) errno = ERR_CMD_CHECK;*/
+            break;
+        }
+    }
+    return -1;
+}
+
+static int sdc_data_finish(void) {
+    int status;
+    struct sdc_regs * regs = (struct sdc_regs *)SDC;
+    
+    while ((status = regs->dat_int_status) == 0) {}
+    regs->dat_int_status = 0;
+    while (regs->software_reset != 0) {}
+
+    if (status == SDC_DAT_INT_STATUS_TRS) return 0;
+    /* errno = FR_DISK_ERR;
+    if (status & SDC_DAT_INT_STATUS_CTE) errno = FR_TIMEOUT;
+    if (status & SDC_DAT_INT_STATUS_CRC) errno = ERR_DATA_CRC;
+    if (status & SDC_DAT_INT_STATUS_CFE) errno = ERR_DATA_FIFO;*/
+    return -1;
+}
+
+static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks, uint32_t * response) {
+  struct sdc_regs * regs = (struct sdc_regs *)SDC;
+  
+  unsigned command = (cmd & 0x3f) << 8;
+    switch (cmd) {
+    case CMD0:
+    case CMD4:
+    case CMD15:
+        // No responce
+        break;
+    case CMD11:
+    case CMD13:
+    case CMD16:
+    case CMD17:
+    case CMD18:
+    case CMD19:
+    case CMD23:
+    case CMD24:
+    case CMD25:
+    case CMD27:
+    case CMD30:
+    case CMD32:
+    case CMD33:
+    case CMD42:
+    case CMD55:
+    case CMD56:
+    case ACMD6:
+        // R1
+        command |= 1; // 48 bits
+        command |= 1 << 3; // resp CRC
+        command |= 1 << 4; // resp OPCODE
+        break;
+    case CMD7:
+    case CMD12:
+    case CMD20:
+    case CMD28:
+    case CMD29:
+    case CMD38:
+        // R1b
+        command |= 1; // 48 bits
+        command |= 1 << 2; // busy
+        command |= 1 << 3; // resp CRC
+        command |= 1 << 4; // resp OPCODE
+        break;
+    case CMD2:
+    case CMD9:
+    case CMD10:
+         // R2
+        command |= 2; // 136 bits
+        command |= 1 << 3; // resp CRC
+        break;
+    case ACMD41:
+        // R3
+        command |= 1; // 48 bits
+        break;
+    case CMD3:
+        // R6
+        command |= 1; // 48 bits
+        command |= 1 << 2; // busy
+        command |= 1 << 3; // resp CRC
+        command |= 1 << 4; // resp OPCODE
+        break;
+    case CMD8:
+        // R7
+        command |= 1; // 48 bits
+        command |= 1 << 3; // resp CRC
+        command |= 1 << 4; // resp OPCODE
+        break;
+    }
+
+    if (blocks) {
+        command |= 1 << 5;
+        if ((intptr_t)buf & 3) {
+          // errno = ERR_BUF_ALIGNMENT;
+            return -1;
+        }
+        regs->dma_addres = (uint64_t)(intptr_t)buf;
+        regs->block_size = 511;
+        regs->block_count = blocks - 1;
+        regs->data_timeout = 0x1FFFFFF;
+    }
+
+    regs->command = command;
+    regs->cmd_timeout = 0xFFFFF;
+    regs->argument = arg;
+
+    if (sdc_cmd_finish(cmd, response) < 0) return -1;
+    if (blocks) return sdc_data_finish();
+
+    return 0;
+}
+
+#define send_cmd(cmd, arg, response) send_data_cmd(cmd, arg, NULL, 0, response)
+
+static BYTE ini_sd(void) {
+  struct sdc_regs * regs = (struct sdc_regs *)SDC;
+    unsigned rca;
+    BYTE card_type;
+    uint32_t response[4];
+
+    /* Reset controller */
+    regs->software_reset = 1;
+    while ((regs->software_reset & 1) == 0) {}
+
+    // This clock divider is meant to initialize the card at
+    // 400kHz
+
+    // 22MHz/400kHz = 55 (base 10) = 0x37 - 0x01 = 0x36
+    regs->clock_divider = 0x36;
+    regs->software_reset = 0;
+    while (regs->software_reset) {}
+    usleep(5000);
+
+    card_type = 0;
+    // drv_status = STA_NOINIT;
+
+    if (regs->capability & SDC_CAPABILITY_SD_RESET) {
+        /* Power cycle SD card */
+        regs->control |= SDC_CONTROL_SD_RESET;
+        usleep(1000000);
+        regs->control &= ~SDC_CONTROL_SD_RESET;
+        usleep(100000);
+    }
+
+    /* Enter Idle state */
+    send_cmd(CMD0, 0, response);
+
+    card_type = CT_SD1;
+    if (send_cmd(CMD8, 0x1AA, response) == 0) {
+        if ((response[0] & 0xfff) != 0x1AA) {
+            // errno = ERR_CMD_CHECK;
+            return -1;
+        }
+        card_type = CT_SD2;
+    }
+
+    /* Wait for leaving idle state (ACMD41 with HCS bit) */
+    while (1) {
+        /* ACMD41, Set Operating Conditions: Host High Capacity & 3.3V */
+      if (send_cmd(CMD55, 0, response) < 0 || send_cmd(ACMD41, 0x40300000, response) < 0) return -1;
+        if (response[0] & (1 << 31)) {
+            if (response[0] & (1 << 30)) card_type |= CT_BLOCK;
+            break;
+        }
+    }
+
+    /* Enter Identification state */
+    if (send_cmd(CMD2, 0, response) < 0) return -1;
+
+    /* Get RCA (Relative Card Address) */
+    rca = 0x1234;
+    if (send_cmd(CMD3, rca << 16, response) < 0) return -1;
+    rca = response[0] >> 16;
+
+    /* Select card */
+    if (send_cmd(CMD7, rca << 16, response) < 0) return -1;
+
+    /* Clock 25MHz */
+    // 22Mhz/2 = 11Mhz
+    regs->clock_divider = 1;
+    usleep(10000);
+
+    /* Bus width 1-bit */
+    regs->control = 0;
+    if (send_cmd(CMD55, rca << 16, response) < 0 || send_cmd(ACMD6, 0, response) < 0) return -1;
+
+    /* Set R/W block length to 512 */
+    if (send_cmd(CMD16, 512, response) < 0) return -1;
+
+    // drv_status &= ~STA_NOINIT;
+    return card_type;
+}
+
+int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type) {
+
+  /* This is not needed. This has everything to do with the FAT
+     filesystem stuff that I'm not including. All I need to do is
+     initialize the SD card and read from it. Anything in here that is
+     checking for potential errors, I'm going to have to temporarily
+     do without.
+   */
+  // if (!count) return RES_PARERR;
+    /* if (drv_status & STA_NOINIT) return RES_NOTRDY; */
+
+  uint32_t response[4];
+  struct sdc_regs * regs = (struct sdc_regs *)SDC;
+  
+    /* Convert LBA to byte address if needed */
+    if (!(card_type & CT_BLOCK)) sector *= 512;
+    while (count > 0) {
+        UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count;
+        unsigned bytes = bcnt * 512;
+        if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt, response) < 0) return 1;
+        if (bcnt > 1 && send_cmd(CMD12, 0, response) < 0) return 1;
+        sector += (card_type & CT_BLOCK) ? bcnt : bytes;
+        count -= bcnt;
+        buf += bytes;
+    }
+
+    return 0;;
+}
+
+void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) {
+  BYTE card_type;
+  int ret = 0;
+  
+  card_type = ini_sd();
+
+  // BYTE * buf = (BYTE *)Dst;
+    
+  // if (disk_read(buf, (LBA_t)address, (UINT)numBlocks, card_type) < 0) /* UART Print function?*/;
+  
+  ret = gpt_load_partitions(card_type);
+}
+
+/*
+int main() {
+  ini_sd();
+  
+  
+  return 0;
+}
+*/
diff --git a/fpga/zsbl/boot.h b/fpga/zsbl/boot.h
new file mode 100644
index 000000000..77d403145
--- /dev/null
+++ b/fpga/zsbl/boot.h
@@ -0,0 +1,26 @@
+#ifndef WALLYBOOT
+#define WALLYBOOT 10000
+
+#include <stdint.h>
+typedef unsigned int    UINT;   /* int must be 16-bit or 32-bit */
+typedef unsigned char   BYTE;   /* char must be 8-bit */
+typedef uint16_t        WORD;   /* 16-bit unsigned integer */
+typedef uint32_t        DWORD;  /* 32-bit unsigned integer */
+typedef uint64_t        QWORD;  /* 64-bit unsigned integer */
+typedef WORD            WCHAR;
+
+typedef QWORD LBA_t;
+
+// Define memory locations of boot images =====================
+// These locations are copied from the generic configuration
+// of OpenSBI. These addresses can be found in:
+// buildroot/output/build/opensbi-0.9/platform/generic/config.mk
+#define FDT_ADDRESS 0x87000000          // FW_JUMP_FDT_ADDR
+#define OPENSBI_ADDRESS 0x80000000      // FW_TEXT_START
+#define KERNEL_ADDRESS 0x80200000       // FW_JUMP_ADDR
+
+// Export disk_read
+int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type);
+
+#endif // WALLYBOOT
+
diff --git a/fpga/zsbl/copyFlash.c b/fpga/zsbl/copyFlash.c
deleted file mode 100644
index 4165fe21c..000000000
--- a/fpga/zsbl/copyFlash.c
+++ /dev/null
@@ -1,40 +0,0 @@
-///////////////////////////////////////////
-// copyFlash.sv
-//
-// Written: Ross Thompson September 25, 2021
-// Modified: 
-//
-// Purpose: copies flash card into memory
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "sdcDriver.h"
-
-void copyFlash(long int blockAddr, long int * Dst, int numBlocks) {
-
-  setSDCCLK(4); // must be even, 1 gives no division.
-  waitInitSDC();
-
-  int index;
-
-  for(index = 0; index < numBlocks; index++) {
-    copySDC512(blockAddr+(index*512), Dst+(index*512/8));
-  }
-  
-    
-}
diff --git a/fpga/zsbl/gpt.c b/fpga/zsbl/gpt.c
index 0c645d70e..97e3e4e46 100644
--- a/fpga/zsbl/gpt.c
+++ b/fpga/zsbl/gpt.c
@@ -1,119 +1,46 @@
 #include "gpt.h"
-
-#include "sdcDriver.h"
-
-#include "uart.h"
+#include "boot.h"
 #include <stddef.h>
 
-int gpt_find_boot_partition(long int* dest, uint32_t size)
-{
-  //int ret = init_sd();
-  int ret;
-  setSDCCLK(4); // must be even, 1 gives no division.
-  waitInitSDC();
-  ret = 0;
-    if (ret != 0) {
-        print_uart("could not initialize sd... exiting\r\n");
-        return -1;
-    }
-
-    print_uart("sd initialized!\r\n");
-
-    // load LBA1
-    size_t block_size = 512/8;
-    long int lba1_buf[block_size];
-
-    //int res = sd_copy(lba1_buf, 1, 1);
-    int res;
-    copySDC512(1, lba1_buf);
-    res = 0;
+/* PSUEDOCODE
 
-    if (res != 0)
-    {
-        print_uart("SD card failed!\r\n");
-        print_uart("sd copy return value: ");
-        print_uart_addr(res);
-        print_uart("\r\n");
-        return -2;
-    }
+   Need to load GPT LBA 1 and read through the partition entries.
+   I need to find each of the relevant partition entries, possibly
+   by their partition names.
+   
+*/
 
-    gpt_pth_t *lba1 = (gpt_pth_t *)lba1_buf;
+int gpt_load_partitions(BYTE card_type) {
+  // In this version of the GPT partition code
+  // I'm going to assume that the SD card is already initialized.
 
-    print_uart("gpt partition table header:");
-    print_uart("\r\n\tsignature:\t");
-    print_uart_addr(lba1->signature);
-    print_uart("\r\n\trevision:\t");
-    print_uart_int(lba1->revision);
-    print_uart("\r\n\tsize:\t\t");
-    print_uart_int(lba1->header_size);
-    print_uart("\r\n\tcrc_header:\t");
-    print_uart_int(lba1->crc_header);
-    print_uart("\r\n\treserved:\t");
-    print_uart_int(lba1->reserved);
-    print_uart("\r\n\tcurrent lba:\t");
-    print_uart_addr(lba1->current_lba);
-    print_uart("\r\n\tbackup lda:\t");
-    print_uart_addr(lba1->backup_lba);
-    print_uart("\r\n\tpartition entries lba:   \t");
-    print_uart_addr(lba1->partition_entries_lba);
-    print_uart("\r\n\tnumber partition entries:\t");
-    print_uart_int(lba1->nr_partition_entries);
-    print_uart("\r\n\tsize partition entries:  \t");
-    print_uart_int(lba1->size_partition_entry);
-    print_uart("\r\n");
+  // size_t block_size = 512/8;
+  // long int lba1_buf[block_size];
 
-    long int lba2_buf[block_size];
+  BYTE lba1_buf[512];
+  
+  int ret = 0;
+  //ret = disk_read(/* BYTE * buf, LBA_t sector, UINT count, BYTE card_type */);
+  ret = disk_read(lba1_buf, 1, 1, card_type);
 
-    //res = sd_copy(lba2_buf, lba1->partition_entries_lba, 1);
-    copySDC512(lba1->partition_entries_lba, lba2_buf);
-    res = 0;
+  /* Possible error handling with UART message
+  if ( ret != 0 ) {
+    
+  }*/
 
-    if (res != 0)
-    {
-        print_uart("SD card failed!\r\n");
-        print_uart("sd copy return value: ");
-        print_uart_addr(res);
-        print_uart("\r\n");
-        return -2;
-    }
+  gpt_pth_t *lba1 = (gpt_pth_t *)lba1_buf;
 
-    for (int i = 0; i < 4; i++)
-    {
-        partition_entries_t *part_entry = (partition_entries_t *)(lba2_buf + (i * 128));
-        print_uart("gpt partition entry ");
-        print_uart_byte(i);
-        print_uart("\r\n\tpartition type guid:\t");
-        for (int j = 0; j < 16; j++)
-            print_uart_byte(part_entry->partition_type_guid[j]);
-        print_uart("\r\n\tpartition guid:     \t");
-        for (int j = 0; j < 16; j++)
-            print_uart_byte(part_entry->partition_guid[j]);
-        print_uart("\r\n\tfirst lba:\t");
-        print_uart_addr(part_entry->first_lba);
-        print_uart("\r\n\tlast lba:\t");
-        print_uart_addr(part_entry->last_lba);
-        print_uart("\r\n\tattributes:\t");
-        print_uart_addr(part_entry->attributes);
-        print_uart("\r\n\tname:\t");
-        for (int j = 0; j < 72; j++)
-            print_uart_byte(part_entry->name[j]);
-        print_uart("\r\n");
-    }
+  BYTE lba2_buf[512];
+  ret = disk_read(lba2_buf, (LBA_t)lba1->partition_entries_lba, 1, card_type);
 
-    partition_entries_t *boot = (partition_entries_t *)(lba2_buf);
-    print_uart("copying boot image ");
-    //res = sd_copy(dest, boot->first_lba, boot->last_lba - boot->first_lba + 1);
-    copyFlash(boot->first_lba, dest, boot->last_lba - boot->first_lba + 1);
+  // Load parition entries for the relevant boot partitions.
+  partition_entries_t *fdt = (partition_entries_t *)(lba2_buf);
+  partition_entries_t *opensbi = (partition_entries_t *)(lba2_buf + 128);
+  partition_entries_t *kernel = (partition_entries_t *)(lba2_buf + 256);
 
-    if (res != 0)
-    {
-        print_uart("SD card failed!\r\n");
-        print_uart("sd copy return value: ");
-        print_uart_addr(res);
-        print_uart("\r\n");
-        return -2;
-    }
+  ret = disk_read((BYTE *)FDT_ADDRESS, fdt->first_lba, fdt->last_lba - fdt->first_lba + 1, card_type);
+  ret = disk_read((BYTE *)OPENSBI_ADDRESS, opensbi->first_lba, opensbi->last_lba - opensbi->first_lba + 1, card_type);
+  ret = disk_read((BYTE *)KERNEL_ADDRESS, kernel->first_lba,kernel->last_lba - kernel->first_lba + 1, card_type);
 
-    print_uart(" done!\r\n");
-    return 0;
+  return 0;
 }
diff --git a/fpga/zsbl/gpt.h b/fpga/zsbl/gpt.h
index dcc27ae8a..4aefae229 100644
--- a/fpga/zsbl/gpt.h
+++ b/fpga/zsbl/gpt.h
@@ -1,6 +1,7 @@
 #pragma once
 
 #include <stdint.h>
+#include "boot.h"
 
 // LBA 0: Protective MBR
 // ignored here
@@ -36,4 +37,4 @@ typedef struct partition_entries
 } partition_entries_t;
 
 // Find boot partition and load it to the destination
-int gpt_find_boot_partition(long int* dest, uint32_t size);
+int gpt_load_partitions(BYTE card_type);
diff --git a/fpga/zsbl/linker1000.x b/fpga/zsbl/linker1000.x
new file mode 100644
index 000000000..6d9e948a6
--- /dev/null
+++ b/fpga/zsbl/linker1000.x
@@ -0,0 +1,245 @@
+OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv",
+	      "elf64-littleriscv")
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+SEARCH_DIR("/opt/riscv/riscv64-unknown-elf/lib");
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  /* init segment to ensure we get a consistent start routine*/
+  . = 0x0000000000001000; 
+  . = ALIGN(0x0); 
+  .init : {  
+  	*(.init) 
+  } 
+  _start_end = .;
+  
+  PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x0)); . = SEGMENT_START("text-segment", _start_end);
+  .interp         : { *(.interp) }
+  .note.gnu.build-id  : { *(.note.gnu.build-id) }
+  .hash           : { *(.hash) }
+  .gnu.hash       : { *(.gnu.hash) }
+  .dynsym         : { *(.dynsym) }
+  .dynstr         : { *(.dynstr) }
+  .gnu.version    : { *(.gnu.version) }
+  .gnu.version_d  : { *(.gnu.version_d) }
+  .gnu.version_r  : { *(.gnu.version_r) }
+  .rela.dyn       :
+    {
+      *(.rela.init)
+      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+      *(.rela.fini)
+      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+      *(.rela.ctors)
+      *(.rela.dtors)
+      *(.rela.got)
+      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+      PROVIDE_HIDDEN (__rela_iplt_start = .);
+      *(.rela.iplt)
+      PROVIDE_HIDDEN (__rela_iplt_end = .);
+    }
+  .rela.plt       :
+    {
+      *(.rela.plt)
+    }
+  .init           :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  }
+  .plt            : { *(.plt) }
+  .iplt           : { *(.iplt) }
+  .text           :
+  {
+    *(.text.unlikely .text.*_unlikely .text.unlikely.*)
+    *(.text.exit .text.exit.*)
+    *(.text.startup .text.startup.*)
+    *(.text.hot .text.hot.*)
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    /* .gnu.warning sections are handled specially by elf64.em.  */
+    *(.gnu.warning)
+  }
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  }
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  . = 0x0000000000002000;
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
+  .rodata1        : { *(.rodata1) }
+  .sdata2         :
+  {
+    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+  }
+  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
+  .eh_frame_hdr   : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) }
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) *(.eh_frame.*) }
+  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }
+  .gnu_extab   : ONLY_IF_RO { *(.gnu_extab*) }
+  /* These sections are generated by the Sun/Oracle C++ compiler.  */
+  .exception_ranges   : ONLY_IF_RO { *(.exception_ranges*) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) }
+  .gnu_extab      : ONLY_IF_RW { *(.gnu_extab) }
+  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
+  .exception_ranges   : ONLY_IF_RW { *(.exception_ranges*) }
+  /* Thread Local Storage sections  */
+  .tdata	  :
+   {
+     PROVIDE_HIDDEN (__tdata_start = .);
+     *(.tdata .tdata.* .gnu.linkonce.td.*)
+   }
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
+  .preinit_array    :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  }
+  .init_array    :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  }
+  .fini_array    :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  }
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  }
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  }
+  .jcr            : { KEEP (*(.jcr)) }
+  .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) }
+  .dynamic        : { *(.dynamic) }
+  . = DATA_SEGMENT_RELRO_END (0, .);
+  .data           :
+  {
+    __DATA_BEGIN__ = .;
+    *(.data .data.* .gnu.linkonce.d.*)
+    SORT(CONSTRUCTORS)
+  }
+  .data1          : { *(.data1) }
+  .got            : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata          :
+  {
+    __SDATA_BEGIN__ = .;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+  _edata = .; PROVIDE (edata = .);
+  . = .;
+  __bss_start = .;
+  .sbss           :
+  {
+    *(.dynsbss)
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss            :
+  {
+   *(.dynbss)
+   *(.bss .bss.* .gnu.linkonce.b.*)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.
+      FIXME: Why do we need it? When there is no .bss section, we do not
+      pad the .data section.  */
+   . = ALIGN(. != 0 ? 64 / 8 : 1);
+  }
+  . = ALIGN(64 / 8);
+  . = SEGMENT_START("ldata-segment", .);
+  . = ALIGN(64 / 8);
+  __BSS_END__ = .;
+    __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,
+		            MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800));
+  _end = .; PROVIDE (end = .);
+  . = DATA_SEGMENT_END (.);
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  /* DWARF 3 */
+  .debug_pubtypes 0 : { *(.debug_pubtypes) }
+  .debug_ranges   0 : { *(.debug_ranges) }
+  /* DWARF Extension.  */
+  .debug_macro    0 : { *(.debug_macro) }
+  .debug_addr     0 : { *(.debug_addr) }
+  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}
diff --git a/fpga/zsbl/main.c b/fpga/zsbl/main.c
deleted file mode 100644
index 898025c30..000000000
--- a/fpga/zsbl/main.c
+++ /dev/null
@@ -1,26 +0,0 @@
-#include "uart.h"
-#include "sdcDriver.h"
-#include "gpt.h"
-
-int main()
-{
-    init_uart(30000000, 115200);
-    print_uart("Hello World!\r\n");
-
-    int res = gpt_find_boot_partition((long int *)0x80000000UL, 2 * 16384);
-
-    if (res == 0)
-    {
-      return 0;
-    }
-
-    while (1)
-    {
-        // do nothing
-    }
-}
-
-void handle_trap(void)
-{
-    // print_uart("trap\r\n");
-}
diff --git a/fpga/zsbl/sdcDriver.c b/fpga/zsbl/sdcDriver.c
deleted file mode 100644
index 45caa42fa..000000000
--- a/fpga/zsbl/sdcDriver.c
+++ /dev/null
@@ -1,69 +0,0 @@
-///////////////////////////////////////////
-// SDC.sv
-//
-// Written: Rose Thompson September 25, 2021
-// Modified: 
-//
-// Purpose: driver for sdc reader.
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-
-#include "sdcDriver.h"
-
-#define SDC_MAIL_BOX 0x12100
-
-void copySDC512(long int blockAddr, long int * Dst) {
-
-  waitInitSDC();
-
-  volatile long int * mailBoxAddr;
-  volatile int * mailBoxCmd;
-  volatile int * mailBoxStatus;
-  volatile long int * mailBoxReadData;
-  mailBoxStatus = (int *) (SDC_MAIL_BOX + 0x4);  
-  mailBoxCmd = (int *) (SDC_MAIL_BOX + 0x8);
-  mailBoxAddr = (long int *) (SDC_MAIL_BOX + 0x10);
-  mailBoxReadData = (long int *) (SDC_MAIL_BOX + 0x18);  
-  
-  // write the SDC address register with the blockAddr
-  *mailBoxAddr = blockAddr;
-  *mailBoxCmd = 0x4;
-
-  // wait until the mailbox has valid data
-  // this occurs when status[1] = 0
-  while((*mailBoxStatus & 0x2) == 0x2);
-
-  int index;
-  for(index = 0; index < 512/8; index++) {
-    Dst[index] = *mailBoxReadData;
-  }
-}
-
-volatile void waitInitSDC(){
-  volatile int * mailBoxStatus;
-  mailBoxStatus = (int *) (SDC_MAIL_BOX + 0x4);
-  while((*mailBoxStatus & 0x1) != 0x1);
-}
-
-void setSDCCLK(int divider){
-  divider = (1 - (divider >> 1));
-  volatile int * mailBoxCLK;
-  mailBoxCLK = (int *) (SDC_MAIL_BOX + 0x0);
-  *mailBoxCLK = divider;
-}
diff --git a/fpga/zsbl/sdcDriver.h b/fpga/zsbl/sdcDriver.h
deleted file mode 100644
index 3e7381837..000000000
--- a/fpga/zsbl/sdcDriver.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __SDCDRIVER_H
-#define __SDCDRIVER_H
-
-
-void copySDC512(long int, long int *);
-volatile void waitInitSDC();
-void setSDCCLK(int);
-void copyFlash(long int, long int *, int);
-
-#endif
diff --git a/fpga/zsbl/smp.h b/fpga/zsbl/smp.h
deleted file mode 100644
index bb037755d..000000000
--- a/fpga/zsbl/smp.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#pragma once
-
-// The hart that non-SMP tests should run on
-#ifndef NONSMP_HART
-#define NONSMP_HART 0
-#endif
-
-// The maximum number of HARTs this code supports
-#define CLINT_CTRL_ADDR 0x2000000
-#ifndef MAX_HARTS
-#define MAX_HARTS 256
-#endif
-#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS * 4)
-
-/* If your test needs to temporarily block multiple-threads, do this:
- *    smp_pause(reg1, reg2)
- *    ... single-threaded work ...
- *    smp_resume(reg1, reg2)
- *    ... multi-threaded work ...
- */
-
-#define smp_pause(reg1, reg2) \
-    li reg2, 0x8;             \
-    csrw mie, reg2;           \
-    li reg1, NONSMP_HART;     \
-    csrr reg2, mhartid;       \
-    bne reg1, reg2, 42f
-
-#define smp_resume(reg1, reg2)   \
-    li reg1, CLINT_CTRL_ADDR;    \
-    41:;                         \
-    li reg2, 1;                  \
-    sw reg2, 0(reg1);            \
-    addi reg1, reg1, 4;          \
-    li reg2, CLINT_END_HART_IPI; \
-    blt reg1, reg2, 41b;         \
-    42:;                         \
-    wfi;                         \
-    csrr reg2, mip;              \
-    andi reg2, reg2, 0x8;        \
-    beqz reg2, 42b;              \
-    li reg1, CLINT_CTRL_ADDR;    \
-    csrr reg2, mhartid;          \
-    slli reg2, reg2, 2;          \
-    add reg2, reg2, reg1;        \
-    sw zero, 0(reg2);            \
-    41:;                         \
-    lw reg2, 0(reg1);            \
-    bnez reg2, 41b;              \
-    addi reg1, reg1, 4;          \
-    li reg2, CLINT_END_HART_IPI; \
-    blt reg1, reg2, 41b
diff --git a/fpga/zsbl/uart.c b/fpga/zsbl/uart.c
deleted file mode 100644
index a8084ee5e..000000000
--- a/fpga/zsbl/uart.c
+++ /dev/null
@@ -1,91 +0,0 @@
-#include "uart.h"
-
-void write_reg_u8(uintptr_t addr, uint8_t value)
-{
-    volatile uint8_t *loc_addr = (volatile uint8_t *)addr;
-    *loc_addr = value;
-}
-
-uint8_t read_reg_u8(uintptr_t addr)
-{
-    return *(volatile uint8_t *)addr;
-}
-
-int is_transmit_empty()
-{
-    return read_reg_u8(UART_LINE_STATUS) & 0x20;
-}
-
-void write_serial(char a)
-{
-    while (is_transmit_empty() == 0) {};
-
-    write_reg_u8(UART_THR, a);
-}
-
-void init_uart(uint32_t freq, uint32_t baud)
-{
-    uint32_t divisor = freq / (baud << 4);
-
-    write_reg_u8(UART_INTERRUPT_ENABLE, 0x00); // Disable all interrupts
-    write_reg_u8(UART_LINE_CONTROL, 0x80);     // Enable DLAB (set baud rate divisor)
-    write_reg_u8(UART_DLAB_LSB, divisor);         // divisor (lo byte)
-    write_reg_u8(UART_DLAB_MSB, (divisor >> 8) & 0xFF);  // divisor (hi byte)
-    write_reg_u8(UART_LINE_CONTROL, 0x03);     // 8 bits, no parity, one stop bit
-    write_reg_u8(UART_FIFO_CONTROL, 0xC7);     // Enable FIFO, clear them, with 14-byte threshold
-    write_reg_u8(UART_MODEM_CONTROL, 0x20);    // Autoflow mode
-}
-
-void print_uart(const char *str)
-{
-    const char *cur = &str[0];
-    while (*cur != '\0')
-    {
-        write_serial((uint8_t)*cur);
-        ++cur;
-    }
-}
-
-uint8_t bin_to_hex_table[16] = {
-    '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'};
-
-void bin_to_hex(uint8_t inp, uint8_t res[2])
-{
-    res[1] = bin_to_hex_table[inp & 0xf];
-    res[0] = bin_to_hex_table[(inp >> 4) & 0xf];
-    return;
-}
-
-void print_uart_int(uint32_t addr)
-{
-    int i;
-    for (i = 3; i > -1; i--)
-    {
-        uint8_t cur = (addr >> (i * 8)) & 0xff;
-        uint8_t hex[2];
-        bin_to_hex(cur, hex);
-        write_serial(hex[0]);
-        write_serial(hex[1]);
-    }
-}
-
-void print_uart_addr(uint64_t addr)
-{
-    int i;
-    for (i = 7; i > -1; i--)
-    {
-        uint8_t cur = (addr >> (i * 8)) & 0xff;
-        uint8_t hex[2];
-        bin_to_hex(cur, hex);
-        write_serial(hex[0]);
-        write_serial(hex[1]);
-    }
-}
-
-void print_uart_byte(uint8_t byte)
-{
-    uint8_t hex[2];
-    bin_to_hex(byte, hex);
-    write_serial(hex[0]);
-    write_serial(hex[1]);
-}
diff --git a/fpga/zsbl/uart.h b/fpga/zsbl/uart.h
deleted file mode 100644
index df3aef9c8..000000000
--- a/fpga/zsbl/uart.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#pragma once
-
-#include <stdint.h>
-
-#define UART_BASE 0x10000000
-
-#define UART_RBR UART_BASE + 0
-#define UART_THR UART_BASE + 0
-#define UART_INTERRUPT_ENABLE UART_BASE + 4
-#define UART_INTERRUPT_IDENT UART_BASE + 8
-#define UART_FIFO_CONTROL UART_BASE + 8
-#define UART_LINE_CONTROL UART_BASE + 12
-#define UART_MODEM_CONTROL UART_BASE + 16
-#define UART_LINE_STATUS UART_BASE + 20
-#define UART_MODEM_STATUS UART_BASE + 24
-#define UART_DLAB_LSB UART_BASE + 0
-#define UART_DLAB_MSB UART_BASE + 4
-
-void init_uart();
-
-void print_uart(const char* str);
-
-void print_uart_int(uint32_t addr);
-
-void print_uart_addr(uint64_t addr);
-
-void print_uart_byte(uint8_t byte);
diff --git a/linux/buildroot-config-src/buildroot-2023.05.1/main.config b/linux/buildroot-config-src/buildroot-2023.05.1/main.config
index 348922670..3ea431c02 100644
--- a/linux/buildroot-config-src/buildroot-2023.05.1/main.config
+++ b/linux/buildroot-config-src/buildroot-2023.05.1/main.config
@@ -134,7 +134,7 @@ BR2_GCC_VERSION_12_X=y
 BR2_GCC_VERSION="12.3.0"
 BR2_EXTRA_GCC_CONFIG_OPTIONS=""
 BR2_TOOLCHAIN_BUILDROOT_CXX=y
-# BR2_TOOLCHAIN_BUILDROOT_FORTRAN is not set
+BR2_TOOLCHAIN_BUILDROOT_FORTRAN=y
 # BR2_GCC_ENABLE_OPENMP is not set
 # BR2_GCC_ENABLE_GRAPHITE is not set
 BR2_PACKAGE_HOST_GDB_ARCH_SUPPORTS=y
@@ -152,6 +152,7 @@ BR2_TOOLCHAIN_SUPPORTS_VARIADIC_MI_THUNK=y
 BR2_USE_WCHAR=y
 BR2_ENABLE_LOCALE=y
 BR2_INSTALL_LIBSTDCPP=y
+BR2_TOOLCHAIN_HAS_FORTRAN=y
 BR2_TOOLCHAIN_HAS_THREADS=y
 BR2_TOOLCHAIN_HAS_THREADS_DEBUG=y
 BR2_TOOLCHAIN_HAS_THREADS_NPTL=y
@@ -1086,10 +1087,6 @@ BR2_PACKAGE_PROVIDES_HOST_LUAINTERPRETER="host-lua"
 # BR2_PACKAGE_MICROPYTHON is not set
 # BR2_PACKAGE_MOARVM is not set
 BR2_PACKAGE_HOST_MONO_ARCH_SUPPORTS=y
-
-#
-# octave needs a toolchain w/ C++ and fortran, gcc >= 4.8
-#
 BR2_PACKAGE_HOST_OPENJDK_BIN_ARCH_SUPPORTS=y
 # BR2_PACKAGE_PERL is not set
 BR2_PACKAGE_PHP_ARCH_SUPPORTS=y
@@ -1731,10 +1728,7 @@ BR2_PACKAGE_LIBCAMERA_ARCH_SUPPORTS=y
 # BR2_PACKAGE_ACE is not set
 # BR2_PACKAGE_APR is not set
 # BR2_PACKAGE_APR_UTIL is not set
-
-#
-# armadillo needs a toolchain w/ fortran, C++
-#
+# BR2_PACKAGE_ARMADILLO is not set
 # BR2_PACKAGE_ATF is not set
 # BR2_PACKAGE_AVRO_C is not set
 # BR2_PACKAGE_BCTOOLBOX is not set
@@ -1782,10 +1776,7 @@ BR2_PACKAGE_GOBJECT_INTROSPECTION_ARCH_SUPPORTS=y
 BR2_PACKAGE_JEMALLOC_ARCH_SUPPORTS=y
 # BR2_PACKAGE_JEMALLOC is not set
 BR2_PACKAGE_LAPACK_ARCH_SUPPORTS=y
-
-#
-# lapack/blas needs a toolchain w/ fortran
-#
+# BR2_PACKAGE_LAPACK is not set
 BR2_PACKAGE_LIBABSEIL_CPP_ARCH_SUPPORTS=y
 # BR2_PACKAGE_LIBABSEIL_CPP is not set
 # BR2_PACKAGE_LIBARGTABLE2 is not set
diff --git a/openocd.cfg b/openocd.cfg
new file mode 100644
index 000000000..6ac36ae4a
--- /dev/null
+++ b/openocd.cfg
@@ -0,0 +1,30 @@
+# OpenOCD config file for Core V Wally
+# Users can find example material in /usr/share/openocd/scripts/
+
+adapter driver ftdi
+
+# when multiple adapters with the same vid_pid are connected (ex: arty-a7 and usb-jtag)
+# need to specify which usb port to drive
+# find numerical path using command "lsusb -t" (<bus>-<port>)
+adapter usb location 1-4
+
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 0
+
+#TODO: figure out which of these bits need to be set
+# data MSB..LSB       direction (1:out) MSB..LSB
+# 0000'0000'0011'0000 0000'0000'0011'1011
+ftdi layout_init 0x0030 0x003b
+
+transport select jtag
+adapter speed 1000
+
+set _CHIPNAME cvw
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1002ac05
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+init
+# this is useful for manual debugging, but breaks gdb
+poll off
diff --git a/setup.sh b/setup.sh
index d8063b2aa..656fed5a6 100644
--- a/setup.sh
+++ b/setup.sh
@@ -24,7 +24,7 @@ echo \$WALLY set to ${WALLY}
 export PATH=$WALLY/bin:$PATH    
 
 # Verilator needs a larger stack to simulate CORE-V Wally
-ulimit -s 100000
+ulimit -c 234613
 
 # load site licenses and tool locations
 if [ -f ${RISCV}/site-setup.sh ]; then
diff --git a/sim/Makefile b/sim/Makefile
index 0cae5053e..09d417124 100644
--- a/sim/Makefile
+++ b/sim/Makefile
@@ -17,28 +17,28 @@ all: riscoftests memfiles coveragetests deriv
 
 wally-riscv-arch-test: wallyriscoftests memfiles
 
-coverage: cov/rv64gc_arch64i.ucdb 
+QuestaCoverage: questa/cov/rv64gc_arch64i.ucdb 
 	#iter-elf.bash --cover --search ../tests/coverage
-	vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb -logfile cov/log
-#	vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb cov/buildroot_buildroot.ucdb riscv.ucdb -logfile cov/log
-	vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt
-	vcover report cov/cov.ucdb -details -instance=/core/ebu. > cov/rv64gc_coverage_ebu.rpt
-	vcover report cov/cov.ucdb -details -instance=/core/priv. > cov/rv64gc_coverage_priv.rpt
-	vcover report cov/cov.ucdb -details -instance=/core/ifu. > cov/rv64gc_coverage_ifu.rpt
-	vcover report cov/cov.ucdb -details -instance=/core/lsu. > cov/rv64gc_coverage_lsu.rpt
-	vcover report cov/cov.ucdb -details -instance=/core/fpu. > cov/rv64gc_coverage_fpu.rpt
-	vcover report cov/cov.ucdb -details -instance=/core/ieu. > cov/rv64gc_coverage_ieu.rpt
-	vcover report cov/cov.ucdb -below 100 -details -instance=/core/ebu. > cov/rv64gc_uncovered_ebu.rpt
-	vcover report cov/cov.ucdb -below 100 -details -instance=/core/priv. > cov/rv64gc_uncovered_priv.rpt
-	vcover report cov/cov.ucdb -below 100 -details -instance=/core/ifu. > cov/rv64gc_uncovered_ifu.rpt
-	vcover report cov/cov.ucdb -below 100 -details -instance=/core/lsu. > cov/rv64gc_uncovered_lsu.rpt
-	vcover report cov/cov.ucdb -below 100 -details -instance=/core/fpu. > cov/rv64gc_uncovered_fpu.rpt
-	vcover report cov/cov.ucdb -below 100 -details -instance=/core/ieu. > cov/rv64gc_uncovered_ieu.rpt
-	vcover report -hierarchical cov/cov.ucdb > cov/rv64gc_coverage_hierarchical.rpt
-	vcover report -below 100 -hierarchical cov/cov.ucdb > cov/rv64gc_uncovered_hierarchical.rpt
-#	vcover report -below 100 cov/cov.ucdb > cov/rv64gc_coverage.rpt
-#	vcover report -recursive cov/cov.ucdb > cov/rv64gc_recursive.rpt
-	vcover report -details -threshH 100 -html cov/cov.ucdb
+	vcover merge -out questa/cov/cov.ucdb questa/cov/rv64gc_arch64i.ucdb questa/cov/rv64gc*.ucdb -logfile questa/cov/log
+#	vcover merge -out questa/cov/cov.ucdb questa/cov/rv64gc_arch64i.ucdb questa/cov/rv64gc*.ucdb questa/cov/buildroot_buildroot.ucdb riscv.ucdb -logfile questa/cov/log
+	vcover report -details questa/cov/cov.ucdb > questa/cov/rv64gc_coverage_details.rpt
+	vcover report questa/cov/cov.ucdb -details -instance=/core/ebu. > questa/cov/rv64gc_coverage_ebu.rpt
+	vcover report questa/cov/cov.ucdb -details -instance=/core/priv. > questa/cov/rv64gc_coverage_priv.rpt
+	vcover report questa/cov/cov.ucdb -details -instance=/core/ifu. > questa/cov/rv64gc_coverage_ifu.rpt
+	vcover report questa/cov/cov.ucdb -details -instance=/core/lsu. > questa/cov/rv64gc_coverage_lsu.rpt
+	vcover report questa/cov/cov.ucdb -details -instance=/core/fpu. > questa/cov/rv64gc_coverage_fpu.rpt
+	vcover report questa/cov/cov.ucdb -details -instance=/core/ieu. > questa/cov/rv64gc_coverage_ieu.rpt
+	vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/ebu. > questa/cov/rv64gc_uncovered_ebu.rpt
+	vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/priv. > questa/cov/rv64gc_uncovered_priv.rpt
+	vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/ifu. > questa/cov/rv64gc_uncovered_ifu.rpt
+	vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/lsu. > questa/cov/rv64gc_uncovered_lsu.rpt
+	vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/fpu. > questa/cov/rv64gc_uncovered_fpu.rpt
+	vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/ieu. > questa/cov/rv64gc_uncovered_ieu.rpt
+	vcover report -hierarchical questa/cov/cov.ucdb > questa/cov/rv64gc_coverage_hierarchical.rpt
+	vcover report -below 100 -hierarchical questa/cov/cov.ucdb > questa/cov/rv64gc_uncovered_hierarchical.rpt
+#	vcover report -below 100 questa/cov/cov.ucdb > questa/cov/rv64gc_coverage.rpt
+#	vcover report -recursive questa/cov/cov.ucdb > questa/cov/rv64gc_recursive.rpt
+	vcover report -details -threshH 100 -html questa/cov/cov.ucdb
 
 allclean: clean all
 
diff --git a/sim/questa/coverage-exclusions-rv64gc.do b/sim/questa/coverage-exclusions-rv64gc.do
index 3331c4574..5dc94d50e 100644
--- a/sim/questa/coverage-exclusions-rv64gc.do
+++ b/sim/questa/coverage-exclusions-rv64gc.do
@@ -64,7 +64,7 @@ coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [G
 # This is cleaner than trying to set an I$-specific pragma in cachefsm.sv (which would exclude it for the D$ instance too)
 # Also exclude the write line to ready transition for the I$ since we can't get a flush during this operation.
 coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -fstate CurrState STATE_FLUSH STATE_FLUSH_WRITEBACK STATE_FLUSH_WRITEBACK STATE_WRITEBACK
-coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -ftrans CurrState STATE_WRITE_LINE->STATE_READY STATE_FETCH->STATE_READY
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -ftrans CurrState STATE_WRITE_LINE->STATE_ACCESS STATE_FETCH->STATE_ACCESS
 # exclude unused transitions from case statement. Unfortunately the whole branch needs to be excluded I think. Expression coverage should still work.
 coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache state-case"] -item b 1
 # I$ does not flush
@@ -151,7 +151,7 @@ for {set i 0} {$i < $numcacheways} {incr i} {
 # Not right; other ways can get flushed and dirtied simultaneously    coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache UpdateDirty"] -item c 1 -feccondrow 6
 }
 # D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush
-coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY 
+coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_ACCESS STATE_FLUSH->STATE_ACCESS STATE_WRITE_LINE->STATE_ACCESS STATE_FLUSH_WRITEBACK->STATE_ACCESS 
 
 ####################
 # Unused / illegal peripheral accesses
diff --git a/sim/questa/imperas.ic b/sim/questa/imperas.ic
new file mode 100644
index 000000000..51344b75a
--- /dev/null
+++ b/sim/questa/imperas.ic
@@ -0,0 +1,115 @@
+#--mpdconsole
+#--gdbconsole
+#--showoverrides
+#--showcommands
+
+# Core settings
+--override cpu/priv_version=1.12 
+--override cpu/user_version=20191213
+# arch
+--override cpu/mimpid=0x100
+--override cpu/mvendorid=0x602
+--override cpu/marchid=0x24
+--override refRoot/cpu/tvec_align=64
+--override refRoot/cpu/envcfg_mask=1   # dh 1/26/24 this should be deleted when ImperasDV is updated to allow envcfg.FIOM to be written
+
+# bit manipulation
+--override cpu/add_Extensions=B 
+#--override cpu/add_implicit_Extensions=B 
+--override cpu/bitmanip_version=1.0.0
+
+# More extensions
+--override cpu/Zcb=T
+--override cpu/Zicond=T
+--override cpu/Zfh=T
+--override cpu/Zfa=T
+
+# Cache block operations
+--override cpu/Zicbom=T
+--override cpu/Zicbop=T
+--override cpu/Zicboz=T
+--override cmomp_bytes=64  # Zic64b
+--override cmoz_bytes=64   # Zic64b
+--override lr_sc_grain=8   # Za64rs requires <=64; we use native word size
+
+# 64 KiB continuous huge pages supported
+--override cpu/Svpbmt=T
+--override cpu/Svnapot_page_mask=65536
+
+# SV39 and SV48 supported
+--override cpu/Sv_modes=768
+
+--override cpu/Svinval=T
+
+
+#  clarify
+#--override refRoot/cpu/mtvec_sext=F
+
+--override cpu/tval_ii_code=T
+
+#--override cpu/time_undefined=T
+#--override cpu/cycle_undefined=T
+#--override cpu/instret_undefined=T
+#--override cpu/hpmcounter_undefined=T
+
+--override cpu/reset_address=0x80000000
+
+--override cpu/unaligned=T  # Zicclsm (should be true)
+--override cpu/ignore_non_leaf_DAU=1
+--override cpu/wfi_is_nop=T
+--override cpu/misa_Extensions_mask=0x0 # MISA not writable
+--override cpu/Sstc=T
+
+# unsuccessfully attempt to add B extension (DH 12/21/23)
+#--override cpu/add_Extensions="B"
+#--override cpu/misa_Extensions=0x0014112F
+
+# Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1
+--override cpu/Svadu=T
+#--override cpu/updatePTEA=F
+#--override cpu/updatePTED=F
+
+
+# THIS NEEDS FIXING to 16
+--override cpu/PMP_registers=16
+--override cpu/PMP_undefined=T
+
+# PMA Settings 
+# 'r': read access allowed
+# 'w': write access allowed
+# 'x': execute access allowed
+# 'a': aligned access required
+# 'A': atomic instructions NOT allowed (actually USER1 privilege needed)
+# 'P': push/pop instructions NOT allowed (actually USER2 privilege needed)
+# '1': 1-byte accesses allowed
+# '2': 2-byte accesses allowed
+# '4': 4-byte accesses allowed
+# '8': 8-byte accesses allowed
+# '-', space: ignored (use for input string formatting).
+#
+# SVxx Memory 0x0000000000 0x7FFFFFFFFF
+#
+--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ---a-- ---- " # INITIAL
+--callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM
+--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC
+--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT
+--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC
+--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0 error - 0x10000000 - 0x100000FF
+--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO  error - 0x10069000 - 0x100600FF
+--callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI   error - 0x10040000 - 0x10040FFF
+#--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwxaA- 1248 " # UNCORE_RAM
+--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM
+
+# Enable the Imperas instruction coverage
+#-extlib    refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
+#-override  refRoot/cpu/cv/cover=basic
+#-override  refRoot/cpu/cv/extensions=RV32I
+
+# Add Imperas simulator application instruction tracing
+--verbose
+#--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 300000000
+--override cpu/debugflags=6 --override cpu/verbose=1
+--override cpu/show_c_prefix=T
+
+# Store simulator output to logfile
+--output imperas.log
diff --git a/sim/run-imperas-linux.sh b/sim/questa/run-imperas-linux.sh
similarity index 75%
rename from sim/run-imperas-linux.sh
rename to sim/questa/run-imperas-linux.sh
index 65e4826fb..aebf6b9d0 100755
--- a/sim/run-imperas-linux.sh
+++ b/sim/questa/run-imperas-linux.sh
@@ -7,4 +7,4 @@ export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=100"
 #export OTHERFLAGS="+TRACE2LOG_ENABLE=1  +TRACE2LOG_AFTER=10500000"
 #export OTHERFLAGS=""
 
-vsim -c -do "do wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0"
+vsim -do "do wally.do buildroot buildroot testbench --lockstep +acc -GDEBUG=1"
diff --git a/sim/questa/sim-testfloat-verilator b/sim/questa/sim-testfloat-verilator
index c08484275..6470837f9 100755
--- a/sim/questa/sim-testfloat-verilator
+++ b/sim/questa/sim-testfloat-verilator
@@ -16,11 +16,7 @@
 # sqrt   - test square root
 # all    - test everything
 
-#vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1"
-
-verilator -GTEST="\"all\"" -GTEST_SIZE="\"all\"" --timescale "1ns/1ns" --timing --binary --top-module testbenchfp "-I../config/shared" "-I../config/deriv/fdqh_ieee_rv64gc" ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv --relative-includes
-
-#vlog +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 
+wsim fdqh_ieee_rv64gc add --tb testbench_fp --sim verilator
 
 # Change TEST_SIZE to only test certain FP width
 # values are QP, DP, SP, HP or all for all tests
diff --git a/sim/questa/wally-imperas-cov.do b/sim/questa/wally-imperas-cov.do
index 5cc56529e..1b83950d0 100644
--- a/sim/questa/wally-imperas-cov.do
+++ b/sim/questa/wally-imperas-cov.do
@@ -24,10 +24,19 @@ vlib work
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
         # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN.  For now just live with the warnings.
-vlog +incdir+../config/$1 \
-     +incdir+../config/shared \
+vlog +incdir+$env(WALLY)/config/$1 \
+     +incdir+$env(WALLY)/config/deriv/$1 \
+     +incdir+$env(WALLY)/config/shared \
      +define+USE_IMPERAS_DV \
      +define+IDV_INCLUDE_TRACE2COV \
+     +define+INCLUDE_TRACE2COV +define+COVER_BASE_RV64I +define+COVER_LEVEL_DV_PR_EXT \
+       +define+COVER_RV64I \
+       +define+COVER_RV64M \
+       +define+COVER_RV64A \
+       +define+COVER_RV64F \
+       +define+COVER_RV64D \
+       +define+COVER_RV64ZICSR \
+       +define+COVER_RV64C \
      +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
      +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
      $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv    \
@@ -38,27 +47,23 @@ vlog +incdir+../config/$1 \
      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv  \
      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv  \
      \
-     +define+INCLUDE_TRACE2COV +define+COVER_BASE_RV64I +define+COVER_LEVEL_DV_PR_EXT \
-       +define+COVER_RV64I \
-       +define+COVER_RV64C \
-       +define+COVER_RV64M \
      +incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \
      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv  \
     \
-    ../src/cvw.sv \
-     ../testbench/testbench-imperas.sv \
-     ../testbench/common/*.sv   \
-     ../src/*/*.sv \
-     ../src/*/*/*.sv \
+     $env(WALLY)/src/cvw.sv \
+     $env(WALLY)/testbench/testbench.sv \
+     $env(WALLY)/testbench/common/*.sv   \
+     $env(WALLY)/src/*/*.sv \
+     $env(WALLY)/src/*/*/*.sv \
      -suppress 2583 \
      -suppress 7063  \
      +acc
 vopt +acc work.testbench -G DEBUG=1 -o workopt 
 eval vsim workopt +nowarn3829  -fatal 7 \
      -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
-     +testDir=$env(TESTDIR) $env(OTHERFLAGS) +TRACE2COV_ENABLE=1
+     +ElfFile=$env(TESTDIR)/ref/ref.elf $env(OTHERFLAGS) +TRACE2COV_ENABLE=1
 
-coverage save -onexit ./riscv.ucdb
+coverage save -onexit $env(WALLY)/sim/questa/riscv.ucdb
 
 
 view wave
@@ -68,7 +73,7 @@ view wave
 
 run -all
 
-noview ../testbench/testbench-imperas.sv
+noview $env(WALLY)/testbench/testbench-imperas.sv
 view wave
 
-quit -f
+#quit -f
diff --git a/sim/questa/wally-linux-imperas.do b/sim/questa/wally-linux-imperas.do
deleted file mode 100644
index 1165676a0..000000000
--- a/sim/questa/wally-linux-imperas.do
+++ /dev/null
@@ -1,84 +0,0 @@
-# wally.do 
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-#
-# Modification by Oklahoma State University & Harvey Mudd College
-# Use with Testbench 
-# James Stine, 2008; David Harris 2021
-# Go Cowboys!!!!!!
-#
-# Takes 1:10 to run RV64IC tests using gui
-
-# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
-
-# Use this wally-pipelined.do file to run this example.
-# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
-#     do wally.do
-# or, to run from a shell, type the following at the shell prompt:
-#     vsim -do wally.do -c
-# (omit the "-c" to see the GUI while running from the shell)
-
-onbreak {resume}
-
-# create library
-if [file exists work] {
-    vdel -all
-}
-vlib work
-
-# compile source files
-# suppress spurious warnngs about 
-# "Extra checking for conflicts with always_comb done at vopt time"
-# because vsim will run vopt
-
-# start and run simulation
-# remove +acc flag for faster sim during regressions if there is no need to access internal signals
-if {$2 eq "buildroot"} {
-    vlog -lint -work work_${1}_${2} \
-      +define+USE_IMPERAS_DV \
-      +incdir+../config/deriv/$1 \
-      +incdir+../config/shared \
-      +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
-      +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
-      $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv    \
-      $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv      \
-      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv  \
-      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv   \
-      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
-      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv  \
-      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv  \
-      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv  \
-      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv  \
-      ../src/cvw.sv \
-       ../testbench/testbench.sv \
-       ../testbench/common/*.sv ../src/*/*.sv \
-       ../src/*/*/*.sv -suppress 2583
-
-    #
-    # start and run simulation
-    # for profiling add
-    # vopt -fprofile
-    # vsim -fprofile+perf
-    # visualizer -fprofile+perf+dir=fprofile
-    #
-    eval vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 \
-         -G TEST=$2 -o testbenchopt 
-    eval vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286  -fatal 7 \
-        -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
-        $env(OTHERFLAGS)
-
-    #-- Run the Simulation
-    echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
-    echo "Don't forget to change DEBUG_LEVEL = 0."
-    echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
-    #run 100 ns
-    #force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
-    #force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
-    run 9800 ms
-    add log -recursive /testbench/dut/*
-    do wave.do
-    run 200 ms
-    #run -all
-
-    exec ./slack-notifier/slack-notifier.py
-
-}
diff --git a/sim/questa/wally.do b/sim/questa/wally.do
index 184da43d0..7d6f7f62f 100644
--- a/sim/questa/wally.do
+++ b/sim/questa/wally.do
@@ -1,4 +1,4 @@
-# wally-batch.do 
+# wally.do 
 # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 #
 # Modification by Oklahoma State University & Harvey Mudd College
@@ -8,17 +8,20 @@
 #
 # Takes 1:10 to run RV64IC tests using gui
 
-# Usage: do wally-batch.do <config> <testcases> <testbench> [-coverage] [+acc] [any number of +value] [any number of -G VAR=VAL]
-# Example: do wally-batch.do rv64gc arch64i testbench
+# Usage: do wally.do <config> <testcases> <testbench> [-coverage] [+acc] [any number of +value] [any number of -G VAR=VAL]
+# Example: do wally.do rv64gc arch64i testbench
 
-# Use this wally-batch.do file to run this example.
+# Use this wally.do file to run this example.
 # Either bring up ModelSim and type the following at the "ModelSim>" prompt:
-#     do wally-batch.do
+#     do wally.do
 # or, to run from a shell, type the following at the shell prompt:
-#     vsim -do wally-batch.do -c
+#     vsim -do wally.do -c
 # (omit the "-c" to see the GUI while running from the shell)
 
+set DEBUG 1
+
 onbreak {resume}
+onerror {quit -f}
 
 set CFG ${1}
 set TESTSUITE ${2}
@@ -41,6 +44,36 @@ set coverage 0
 set CoverageVoptArg ""
 set CoverageVsimArg ""
 
+set FunctCoverage 0
+set riscvISACOVsrc ""
+set FCdefineINCLUDE_TRACE2COV ""
+set FCdefineCOVER_BASE_RV64I ""
+set FCdefineCOVER_LEVEL_DV_PR_EXT  ""
+set FCdefineCOVER_RV64I ""
+set FCdefineCOVER_RV64M ""
+set FCdefineCOVER_RV64A ""
+set FCdefineCOVER_RV64F ""
+set FCdefineCOVER_RV64D ""
+set FCdefineCOVER_RV64ZICSR ""
+set FCdefineCOVER_RV64C ""
+set FCdefineIDV_INCLUDE_TRACE2COV ""
+
+set lockstep 0
+# ok this is annoying. vlog, vopt, and vsim are very picky about how arguments are passed.
+# unforunately it won't allow these to be grouped as one argument per command so they are broken
+# apart. 
+set lockstepvoptstring ""
+set SVLib ""
+set SVLibPath ""
+#set OtherFlags ""
+set ImperasPubInc ""
+set ImperasPrivInc ""
+set rvviFiles ""
+set idvFiles ""
+
+set GUI 0
+set accFlag ""
+
 # Need to be able to pass arguments to vopt.  Unforunately argv does not work because
 # it takes on different values if vsim and the do file are called from the command line or
 # if the do file isd called from questa sim directly.  This chunk of code uses the $4 through $n
@@ -49,10 +82,9 @@ set tbArgs ""
 set from 4
 set step 1
 set lst {}
-set GUI 0
+
 set PlusArgs {}
 set ParamArgs {}
-set accFlag ""
 for {set i 0} true {incr i} {
     set x [expr {$i*$step + $from}]
     if {$x > $argc} break
@@ -60,54 +92,120 @@ for {set i 0} true {incr i} {
     lappend lst $arg
 }
 
-if {$argc >= 3} {
-    if {[lindex $lst [expr { [llength $lst] -1 } ]] eq "+acc"} {
-        set GUI 1
-        set accFlag "+acc"
-        set tbArgs [lrange $lst 0 end-1]
-    } else {
-        set tbArgs $lst
+echo "number of args = $argc"
+echo "lst = $lst"
+
+# if +acc found set flag and remove from list
+set AccIndex [lsearch -exact $lst "+acc"]
+if {$AccIndex >= 0} {
+    set GUI 1
+    set accFlag "+acc"
+    set lst [lreplace $lst $AccIndex $AccIndex]
+}
+
+# if +coverage found set flag and remove from list
+set CoverageIndex [lsearch -exact $lst "--coverage"]
+if {$CoverageIndex >= 0} {
+    set coverage 1
+    set CoverageVoptArg "+cover=sbecf"
+    set CoverageVsimArg "-coverage"
+    set lst [lreplace $lst $CoverageIndex $CoverageIndex]
+}
+
+# if +coverage found set flag and remove from list
+set FunctCoverageIndex [lsearch -exact $lst "--fcov"]
+if {$FunctCoverageIndex >= 0} {
+    set FunctCoverage 1
+    set riscvISACOVsrc +incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source
+
+    set FCdefineINCLUDE_TRACE2COV "+define+INCLUDE_TRACE2COV"
+    set FCdefineCOVER_BASE_RV64I "+define+COVER_BASE_RV64I"
+    set FCdefineCOVER_LEVEL_DV_PR_EXT  "+define+COVER_LEVEL_DV_PR_EXT"
+    set FCdefineCOVER_RV64I "+define+COVER_RV64I"
+    set FCdefineCOVER_RV64M "+define+COVER_RV64M"
+    set FCdefineCOVER_RV64A "+define+COVER_RV64A"
+    set FCdefineCOVER_RV64F "+define+COVER_RV64F"
+    set FCdefineCOVER_RV64D "+define+COVER_RV64D"
+    set FCdefineCOVER_RV64ZICSR "+define+COVER_RV64ZICSR"
+    set FCdefineCOVER_RV64C "+define+COVER_RV64C"
+    set FCdefineIDV_INCLUDE_TRACE2COV "+define+IDV_INCLUDE_TRACE2COV"
+
+    set lst [lreplace $lst $FunctCoverageIndex $FunctCoverageIndex]
+}
+
+set LockStepIndex [lsearch -exact $lst "--lockstep"]
+# ugh.  can't have more than 9 arguments passed to vsim. why? I'll have to remove --lockstep when running
+# functional coverage and imply it.
+if {$LockStepIndex >= 0 || $FunctCoverageIndex >= 0} {
+    set lockstep 1
+
+    # ideally this would all be one or two variables, but questa is having a real hard time
+    # with this.  For now they have to be separate.
+    set lockstepvoptstring "+define+USE_IMPERAS_DV"
+    set ImperasPubInc +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host
+    set ImperasPrivInc +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host
+    set rvviFiles       $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/*.sv
+    set idvFiles $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/*.sv
+    set SVLib "-sv_lib"
+    set SVLibPath $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model
+    #set OtherFlags $env(OTHERFLAGS)
+
+    if {$LockStepIndex >= 0} {
+        set lst [lreplace $lst $LockStepIndex $LockStepIndex]
     }
-    set tbArgsLst [split $lst " "]
-    # separate the +args from the -G parameters
-    foreach otherArg $tbArgsLst {
-        if {[string index $otherArg 0] eq "+"} {
-            lappend PlusArgs $otherArg
-        } else {
-            lappend ParamArgs $otherArg
-        }
+}
+
+# separate the +args from the -G parameters
+foreach otherArg $lst {
+    if {[string index $otherArg 0] eq "+"} {
+        lappend PlusArgs $otherArg
+    } else {
+        lappend ParamArgs $otherArg
     }
-    #echo "PlusArgs"
-    #echo $PlusArgs
-    #echo "ParamArgs"
-    #echo $ParamArgs
-    #echo "accFlag"
-    #echo $accFlag
-
-    #if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} {
-    #    set coverage 1
-    #    set CoverageVoptArg "+cover=sbecf"
-    #    set CoverageVsimArg "-coverage"
-    #} elseif {$3 eq "tbArgs"} {
-    #    set tbArgs $lst
-    #    puts $tbArgs
-    #}
 }
 
-# compile source files
-# suppress spurious warnngs about 
-# "Extra checking for conflicts with always_comb done at vopt time"
-# because vsim will run vopt
+if {$DEBUG > 0} {
+    echo "GUI = $GUI"
+    echo "coverage = $coverage"
+    echo "lockstep = $lockstep"
+    echo "FunctCoverage = $FunctCoverage"
+    echo "remaining list = $lst"
+    echo "Extra +args = $PlusArgs"
+    echo "Extra -args = $ParamArgs"
+}
 
-vlog -lint -work ${WKDIR} +incdir+${CONFIG}/$1 +incdir+${CONFIG}/deriv/$1 +incdir+${CONFIG}/shared ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv  ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
+foreach x $PlusArgs {
+    echo "Element is $x"
+}
+
+# need a better solution this is really ugly
+# Questa really don't like passing $PlusArgs on the command line to vsim.  It treats the whole things
+# as one string rather than mutliple separate +args.  Is there an automated way to pass these?
+set temp0 [lindex $PlusArgs 0]
+set temp1 [lindex $PlusArgs 1]
+set temp2 [lindex $PlusArgs 2]
+set temp3 [lindex $PlusArgs 3]
+
+# compile source files
+if {${CFG} eq "soc"} {
+    set BSG ${WALLY}/soc/src/basejump_stl
+    set BSG_DEFINES den2048Mb+sg5+x16+FULL_MEM
+    set BSG_INCDIRS ${BSG}/bsg_clk_gen+${BSG}/bsg_dmc+${BSG}/bsg_misc+${BSG}/bsg_noc+${BSG}/bsg_tag+${BSG}/testing/bsg_dmc/lpddr_verilog_model
+    vlog -lint -work ${WKDIR} +define+${BSG_DEFINES} +incdir+${BSG_INCDIRS} ${BSG}/bsg_misc/bsg_defines.sv ${BSG}/*/*_pkg.sv ${BSG}/*/*.sv ${BSG}/testing/bsg_dmc/lpddr_verilog_model/*.sv -suppress 2583,2596,2605,2902,7063,8885,13286,13314,13388
+    vlog -lint -work ${WKDIR} +define+USE_BSG +incdir+${CONFIG}/$1 +incdir+${CONFIG}/shared +incdir+${BSG_INCDIRS} ${lockstepvoptstring} ${FCdefineIDV_INCLUDE_TRACE2COV} ${FCdefineINCLUDE_TRACE2COV} ${ImperasPubInc} ${ImperasPrivInc} ${rvviFiles} ${idvFiles} ${FCdefineCOVER_BASE_RV64I} ${FCdefineCOVER_LEVEL_DV_PR_EXT} ${FCdefineCOVER_RV64I} ${FCdefineCOVER_RV64M} ${FCdefineCOVER_RV64A} ${FCdefineCOVER_RV64F} ${FCdefineCOVER_RV64D} ${FCdefineCOVER_RV64ZICSR} ${FCdefineCOVER_RV64C} ${riscvISACOVsrc} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${WALLY}/soc/src/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583,2596,2605,2902,7063,8885,13286,13314,13388
+
+} else {
+    vlog -lint -work ${WKDIR} +incdir+${CONFIG}/$1 +incdir+${CONFIG}/deriv/$1 +incdir+${CONFIG}/shared ${lockstepvoptstring} ${FCdefineIDV_INCLUDE_TRACE2COV} ${FCdefineINCLUDE_TRACE2COV} ${ImperasPubInc} ${ImperasPrivInc} ${rvviFiles} ${idvFiles} ${FCdefineCOVER_BASE_RV64I} ${FCdefineCOVER_LEVEL_DV_PR_EXT} ${FCdefineCOVER_RV64I} ${FCdefineCOVER_RV64M} ${FCdefineCOVER_RV64A} ${FCdefineCOVER_RV64F} ${FCdefineCOVER_RV64D} ${FCdefineCOVER_RV64ZICSR} ${FCdefineCOVER_RV64C} ${riscvISACOVsrc} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583,7063,2596,13286
+}
 
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
-vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${tbArgs} -o testbenchopt ${CoverageVoptArg}
-#  *** tbArgs producees a warning that TEST not found in design when running sim-testfloat-batch.  Need to separate -G and + arguments to pass separately to vopt and vsim
-vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 -suppress 3829 ${CoverageVsimArg} 
+vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${ParamArgs} -o testbenchopt ${CoverageVoptArg} -suppress 8885
+
+#vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 ${SVLib} ${SVLibPath} ${OtherFlags} +TRACE2COV_ENABLE=1 -suppress 3829 ${CoverageVsimArg}
+#vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 ${SVLib} ${SVLibPath} +IDV_TRACE2COV=1 +TRACE2COV_ENABLE=1 -suppress 3829 ${CoverageVsimArg}
+vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} $temp0 $temp1 $temp2 $temp3 -fatal 7 ${SVLib} ${SVLibPath} -suppress 3009,3829,3999,8386,8885 ${CoverageVsimArg}
 
-#    vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3829
 # power add generates the logging necessary for said generation.
 # power add -r /dut/core/*
 if { ${GUI} } {
@@ -122,9 +220,8 @@ if { ${GUI} } {
 run -all
 # power off -r /dut/core/*
 
-
-if {$coverage} {
-    set UCDB cov/${CFG}_${TESTSUITE}.ucdb
+if {$coverage || $FunctCoverage} {
+    set UCDB ${WALLY}/sim/questa/cov/${CFG}_${TESTSUITE}.ucdb
     echo "Saving coverage to ${UCDB}"
     do coverage-exclusions-rv64gc.do  # beware: this assumes testing the rv64gc configuration
     coverage save -instance /testbench/dut/core ${UCDB}
diff --git a/sim/questa/wave.do b/sim/questa/wave.do
index bb6b1d54b..c6cc26f9c 100644
--- a/sim/questa/wave.do
+++ b/sim/questa/wave.do
@@ -73,7 +73,6 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpre
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillNextF
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSpillF
 add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
-add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} -label PHT /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/mem
 add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[5]}
 add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[4]}
 add wave -noupdate -group ifu -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/RASPredictor/memory[3]}
@@ -91,7 +90,7 @@ add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF
 add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState
 add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF
 add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallF
-add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF
+add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissOrUpdateAF
 add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF
 add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
 add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
@@ -123,50 +122,50 @@ add wave -noupdate -group ifu -group icache -expand -group lru {/testbench/dut/c
 add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/CurrLRU
 add wave -noupdate -group ifu -group icache -expand -group lru /testbench/dut/core/ifu/bus/icache/icache/vict/cacheLRU/LRUMemory
 add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/SelectedWriteWordEn}
-add wave -noupdate -group ifu -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/RAM}
+add wave -noupdate -group ifu -group icache -group way3 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/CacheTagMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/ValidBits}
 add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/SelectedWriteWordEn}
-add wave -noupdate -group ifu -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/RAM}
+add wave -noupdate -group ifu -group icache -group way2 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/CacheTagMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/ValidBits}
 add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way2 -expand -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/HitWay}
 add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/SelectedWriteWordEn}
-add wave -noupdate -group ifu -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/RAM}
+add wave -noupdate -group ifu -group icache -group way1 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/CacheTagMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/ValidBits}
 add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/SelectedWriteWordEn}
-add wave -noupdate -group ifu -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/RAM}
+add wave -noupdate -group ifu -group icache -group way0 -label tag {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/CacheTagMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/ValidBits}
 add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way0 -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way0 -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/dout}
-add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -group ifu -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
 add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
 add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr
@@ -205,6 +204,7 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE
 add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE
 add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE
 add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW
+add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
@@ -239,7 +239,7 @@ add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/z
 add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/ByteMaskSpillM
 add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataM
 add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/LSUWriteDataSpillM
-add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
+add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteData
 add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/ByteMask
 add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/BlankByteMask
 add wave -noupdate -expand -group lsu -group alignment /testbench/dut/core/lsu/bus/dcache/dcache/WriteSelLogic/DemuxedByteMask
@@ -281,7 +281,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement
 add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
 add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
 add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
 add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
 add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
 add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
@@ -296,68 +295,67 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearValidWay}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/we}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/bwe}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/we}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/bwe}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/we}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/bwe}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ce}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/we}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/bwe}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelNonHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ClearValidWay}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/wordram/CacheDataMem/we}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ClearValidWay}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/wordram/CacheDataMem/we}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ClearValidWay}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/wordram/CacheDataMem/we}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/wordram/CacheDataMem/ram/RAM}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
@@ -386,7 +384,7 @@ add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/d
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBHit
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
 add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
 add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
@@ -416,7 +414,6 @@ add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hp
 add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
 add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
 add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
-add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
 add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
 add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
 add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
@@ -471,88 +468,88 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
-add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HADDR
-add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HTRANS
-add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HREADY
-add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions
-add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD
-add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD
-add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA
-add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
-add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
-add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
-add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/SExtInt
-add wave -noupdate -group uncore -group plic /testbench/dut/uncore/uncore/plic/plic/Dout
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intEn
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intInProgress
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPending
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPriority
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intThreshold
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/nextIntPending
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/requests
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqMatrix
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/priorities_with_irqs
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority
-add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask
-add wave -noupdate -group uncore -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME
-add wave -noupdate -group uncore -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSEL
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PADDR
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWDATA
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSTRB
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWRITE
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PENABLE
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PRDATA
-add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PREADY
-add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LSR
-add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MCR
-add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MSR
-add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/RBR
-add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/TXHR
-add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LCR
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/intrID
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/INTR
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxstate
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txstate
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitssent
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitsexpected
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsreceived
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsexpected
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdata
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxoverrunerr
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataready
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataavailintr
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/RXBR
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/squashRXerrIP
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxshiftreg
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/SOUTbit
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/SINsync
-add wave -noupdate -group uncore -group uart /testbench/dut/uncore/uncore/uart/uart/u/txsr
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SIN
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SOUT
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RTSb
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DTRb
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT1b
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT2b
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DSRb
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DCDb
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/CTSb
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/TXRDYb
-add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RXRDYb
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIN
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOOUT
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOEN
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB
-add wave -noupdate -group uncore -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE
+add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HADDR
+add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HTRANS
+add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HREADY
+add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELRegions
+add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELNoneD
+add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HSELPLICD
+add wave -noupdate -group uncore /testbench/dut/uncoregen/uncore/HRDATA
+add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/UARTIntr
+add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/GPIOIntr
+add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/MExtInt
+add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/SExtInt
+add wave -noupdate -group uncore -group plic /testbench/dut/uncoregen/uncore/plic/plic/Dout
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intClaim
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intEn
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intInProgress
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intPending
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intPriority
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/intThreshold
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/nextIntPending
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/requests
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/irqMatrix
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/priorities_with_irqs
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/max_priority_with_irqs
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/irqs_at_max_priority
+add wave -noupdate -group uncore -group plic -expand -group internals /testbench/dut/uncoregen/uncore/plic/plic/threshMask
+add wave -noupdate -group uncore -group CLINT /testbench/dut/uncoregen/uncore/clint/clint/MTIME
+add wave -noupdate -group uncore -group CLINT /testbench/dut/uncoregen/uncore/clint/clint/MTIMECMP
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PSEL
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PADDR
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PWDATA
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PSTRB
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PWRITE
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PENABLE
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PRDATA
+add wave -noupdate -group uncore -group CLINT -expand -group {clint bus} /testbench/dut/uncoregen/uncore/clint/clint/PREADY
+add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/LSR
+add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/MCR
+add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/MSR
+add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/RBR
+add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/TXHR
+add wave -noupdate -group uncore -group uart -expand -group Registers /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/LCR
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/intrID
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/INTR
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxstate
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txstate
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txbitssent
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txbitsexpected
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxbitsreceived
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxbitsexpected
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdata
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxoverrunerr
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdataready
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxdataavailintr
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/RXBR
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/squashRXerrIP
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/rxshiftreg
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/SOUTbit
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/SINsync
+add wave -noupdate -group uncore -group uart /testbench/dut/uncoregen/uncore/uartgen/uart/uartPC/txsr
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/SIN
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/SOUT
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/RTSb
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DTRb
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/OUT1b
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/OUT2b
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DSRb
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/DCDb
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/CTSb
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/TXRDYb
+add wave -noupdate -group uncore -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncoregen/uncore/uartgen/uart/RXRDYb
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOIN
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOOUT
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOEN
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/GPIOIntr
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PSEL
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PADDR
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PWRITE
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PRDATA
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PREADY
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PWDATA
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PSTRB
+add wave -noupdate -group uncore -group GPIO /testbench/dut/uncoregen/uncore/gpio/gpio/PENABLE
 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rf
 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
@@ -661,7 +658,7 @@ add wave -noupdate -expand -group testbench /testbench/DCacheFlushStart
 add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFault
 add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFaultDelay
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {6586 ns} 1} {{Cursor 4} {11656 ns} 0} {{Cursor 3} {403021 ns} 1}
+WaveRestoreCursors {{Cursor 4} {6586 ns} 1} {{Cursor 4} {2112952 ns} 0} {{Cursor 3} {403021 ns} 1}
 quietly wave cursor active 2
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -677,4 +674,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {0 ns} {284634 ns}
+WaveRestoreZoom {2039338 ns} {2323972 ns}
diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs
new file mode 100755
index 000000000..5601e57b2
--- /dev/null
+++ b/sim/vcs/run_vcs
@@ -0,0 +1,118 @@
+#!/bin/bash
+# VCS Compilation for WALLY
+# Divya Kohli, Rose Thompson, David Harris 2024
+# Note: VCS produces warning about unsupported Linux Version, but runs successfully
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+# Color Definitions
+RED='\033[0;31m'
+GREEN='\033[0;32m'
+YELLOW='\033[1;33m'
+NC='\033[0m' # No Color
+
+# Directories
+CFG="${WALLY}/config"
+SRC="${WALLY}/src"
+TB="${WALLY}/testbench"
+
+# Set CONFIG_VARIANT from the first script argument
+CONFIG_VARIANT=${1}
+# Set TESTSUITE from the second script argument
+TESTSUITE=$2
+
+WKDIR="wkdir/${1}_${2}"
+COV="cov/${1}_${2}"
+LOGS="logs"
+
+if [ ${TESTSUITE} = "buildroot" ]; then
+	shift 2
+	PLUSARGS="$*"
+fi
+
+clean_logs() {
+    echo -e "${YELLOW}Cleaning up workspace...${NC}"
+    rm -rf wkdir logs cov
+}
+clean_simprofile() {
+    echo -e "${YELLOW}Cleaning up simprofile_dir...${NC}"
+    rm -rf simprofile_dir* profileReport*  
+}
+
+#clean_simprofile
+#clean_logs
+# Function to create a directory if it does not exist
+create_directory() {
+    local dir=$1  # Local variable for directory name
+
+    if [ ! -d "$dir" ]; then
+        mkdir -p "$dir"
+        if [ $? -eq 0 ]; then
+            echo "Directory $dir created successfully."
+        else
+            echo "Failed to create directory $dir."
+            exit 1
+        fi
+    else
+        echo "Directory $dir already exists."
+    fi
+}
+
+# Create or verify WKDIR, COV, and LOGS directories
+create_directory "$WKDIR"
+create_directory "$COV"
+create_directory "$LOGS"
+
+# Ensure the working directory exists
+if [ ! -d "$WKDIR" ]; then
+    echo -e "${YELLOW}Directory $WKDIR does not exist. Creating it now...${NC}"
+    mkdir -p "$WKDIR" && echo -e "${GREEN}Directory $WKDIR created successfully.${NC}" || {
+        echo -e "${RED}Failed to create directory $WKDIR.${NC}"
+        exit 1
+    }
+else
+    echo -e "${GREEN}Directory $WKDIR already exists.${NC}"
+fi
+
+# GUI option handling
+GUI=""
+if [ "$3" = "gui" ]; then
+    GUI="-gui"
+else
+    GUI=""
+fi
+
+# Collect include directories
+INCLUDE_DIRS=$(find ${SRC} -type d | xargs -I {} echo -n "{} ")
+INCLUDE_PATH="+incdir+${CFG}/${CONFIG_VARIANT} +incdir+${CFG}/deriv/${CONFIG_VARIANT} +incdir+${CFG}/shared +incdir+../../tests +define+ +incdir+${TB} ${SRC}/cvw.sv +incdir+${SRC}"
+
+# Prepare RTL files avoiding certain paths
+RTL_FILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x64.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x32.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_2048x64.sv")  ${TB}/testbench.sv $(find ${TB}/common -name "*.sv" ! -path "${TB}/common/wallyTracer.sv")"
+
+# Simulation and Coverage Commands
+OUTPUT="sim_out"
+VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF +vcs+vcdpluson -suppress +warn -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse  -ntb_opts sensitive_dyn +define+SIM_VCS ${INCLUDE_PATH} $RTL_FILES"
+SIMV_CMD="./${WKDIR}/$OUTPUT +TEST=${TESTSUITE} ${PLUSARGS}" 
+COV_FILES="${TB}/coverage/test_pmp_coverage.sv"
+COV_OPTIONS="-cm line+cond+branch+fsm+tgl -cm_log ${WKDIR}/coverage.log -cm_dir ${WKDIR}/COVERAGE"
+### CODE COVERAGE REPORT in IndividualCovReport in XML format
+#COV_RUN="urg -dir ${WKDIR}/COVERAGE.vdb -report IndividualCovReport/${CONFIG_VARIANT}_${TESTSUITE}" 
+### CODE COVERAGE REPORT in IndividualCovReport in text format
+COV_RUN="urg -dir ./${WKDIR}/COVERAGE.vdb -format text -report IndividualCovReport/${CONFIG_VARIANT}_${TESTSUITE}"
+
+
+# Clean and run simulation with VCS
+
+if [ "$3" = "coverage" ]; then
+    echo -e "${YELLOW}#### Running VCS Simulation with Coverage ####${NC}"
+    # Code Coverage.
+    $VCS_CMD -Mdir=${WKDIR} $COV_OPTIONS -o ${WKDIR}/$OUTPUT -Mlib ${WKDIR} -work ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log"
+    $SIMV_CMD $COV_OPTIONS
+    $COV_RUN
+    #cp -rf urgReport $COV
+
+else
+    echo -e "${YELLOW}#### Running VCS Simulation ####${NC}"
+    $VCS_CMD -Mdir=${WKDIR} -o ${WKDIR}/$OUTPUT -work ${WKDIR} -Mlib ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log"
+    $SIMV_CMD 
+fi
+
diff --git a/sim/vcs/run_vcs.sh b/sim/vcs/run_vcs.sh
deleted file mode 100755
index ef9d84e45..000000000
--- a/sim/vcs/run_vcs.sh
+++ /dev/null
@@ -1,25 +0,0 @@
-#!/bin/bash
-
-
-# Set CONFIG_VARIANT from the first script argument
-#CONFIG_VARIANT=${1:-rv64i}
-CONFIG_VARIANT=${1}
-# Set TESTSUITE from the second script argument
-TESTSUITE=$2
-INCLUDE_DIRS=$(find ../src -type d | xargs -I {} echo -n "{} ")
-SOURCE_PATH="+incdir+../config/${CONFIG_VARIANT} +incdir+../config/deriv/${CONFIG_VARIANT} +incdir+../config/shared +define+ +define+P.XLEN=64  +define+FPGA=0 +incdir+../testbench ../src/cvw.sv +incdir+../src" 
-
-SIMFILES="$INCLUDE_DIRS $(find ../src -name "*.sv" ! -path "../src/generic/clockgater.sv" ! -path "../src/generic/mem/rom1p1r_128x64.sv" ! -path "../src/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "../src/generic/mem/rom1p1r_128x32.sv" ! -path "../src/generic/mem/ram2p1r1wbe_512x64.sv")  ../testbench/testbench.sv $(find ../testbench/common -name "*.sv" ! -path "../testbench/common/wallyTracer.sv")" 
-OUTPUT="sim_out"
-
-clean() {
-    rm -rf obj_dir work transcript vsim.wlf $OUTPUT *.vcd csrc ucli.key vc_hdrs.h program.out
-    rm -rf simv* *.daidir dve *.vpd *.dump DVEfiles/ verdi* novas* *fsdb* *.vg *.rep *.db *.chk *.log *.out profileReport* simprofile_dir*
-}
-
-# Clean and run simulation with VCS
-clean
-#vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate  ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
-vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate  ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
-./$OUTPUT | tee program.out
-
diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile
new file mode 100644
index 000000000..576ecf2b7
--- /dev/null
+++ b/sim/verilator/Makefile
@@ -0,0 +1,83 @@
+# Verilator Makefile for WALLY
+# Kunlin Han, Rose Thompson, David Harris 2024
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+SHELL := /bin/bash
+.PHONY: profile run questa clean
+
+# verilator configurations
+OPT=
+PARAMS?=-DVERILATOR=1 --no-trace-top
+NONPROF?=--stats
+VERILATOR_DIR=${WALLY}/sim/verilator
+SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/config/${WALLYCONF} ${WALLY}/config/deriv/${WALLYCONF} ${WALLY}/src/cvw.sv ${WALLY}/testbench/*.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
+EXTRA_ARGS=
+
+
+WALLYCONF?=rv64gc
+TEST?=arch64i
+TESTBENCH?=testbench 	
+
+# constants
+# assume WALLY variable is correctly configured in the shell environment
+WORKING_DIR=${WALLY}/sim/verilator
+TARGET=$(WORKING_DIR)/target
+# INCLUDE_PATH are pathes that Verilator should search for files it needs
+INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)"
+# SOURCES are source files
+SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/${TESTBENCH}.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
+# DEPENDENCIES are configuration files and source files, which leads to recompilation of executables
+DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
+
+# regular testbench requires a wrapper defining getenvval
+ifeq ($(TESTBENCH), testbench)
+	WRAPPER=${WALLY}/sim/verilator/wrapper.c
+	GTEST=
+	ARGTEST=+TEST=$(TEST)
+else
+	WRAPPER=
+	GTEST=-GTEST="\"${TEST}\"" 
+	ARGTEST=
+endif
+
+default: run
+
+run: wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH}
+	mkdir -p $(VERILATOR_DIR)/logs
+	wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH} ${ARGTEST} $(EXTRA_ARGS) 
+
+profile: obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF)
+	$(VERILATOR_DIR)/obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF) ${ARGTEST}
+	mv gmon.out gmon_$(WALLYCONF).out
+	gprof $(VERILATOR_DIR)/obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF) gmon_$(WALLYCONF).out > gmon_$(WALLYCONF).log
+	verilator_profcfunc gmon_$(WALLYCONF).log > gmon_$(WALLYCONF).log2
+	mkdir -p $(VERILATOR_DIR)/logs_profiling
+	mv gmon_$(WALLYCONF)* $(VERILATOR_DIR)/logs_profiling
+	echo "Please check $(VERILATOR_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files."
+
+wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH}: $(DEPENDENCIES)
+	mkdir -p wkdir/$(WALLYCONF)_$(TEST)
+	verilator \
+	--Mdir wkdir/$(WALLYCONF)_$(TEST) -o V${TESTBENCH} \
+	--binary --trace \
+	$(OPT) $(PARAMS) $(NONPROF) \
+	--top-module ${TESTBENCH}  --relative-includes \
+	$(INCLUDE_PATH) \
+	${WRAPPER} \
+	${GTEST} \
+	$(SOURCES)
+
+obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF): $(DEPENDENCIES)
+	mkdir -p obj_dir_profiling
+	verilator \
+	--Mdir obj_dir_profiling -o V${TESTBENCH}_$(WALLYCONF) \
+	--binary \
+	--prof-cfuncs $(OPT) $(PARAMS) \
+	--top-module ${TESTBENCH}  --relative-includes \
+	$(INCLUDE_PATH) \
+	${WRAPPER} \
+	${GTEST} \
+	$(SOURCES)
+
+clean:
+	rm -rf $(VERILATOR_DIR)/wkdir $(VERILATOR_DIR)/obj_dir_profiling $(VERILATOR_DIR)/logs $(VERILATOR_DIR)/logs_profiling
diff --git a/sim/verilator/README.md b/sim/verilator/README.md
new file mode 100644
index 000000000..5fd1b57b3
--- /dev/null
+++ b/sim/verilator/README.md
@@ -0,0 +1,32 @@
+# Simulation with Verilator
+
+Different executables will be built for different architecture configurations, e.g., rv64gc, rv32i. A executable can run all the test suites that it can run with `+TEST=<testsuite>`.
+
+Demand:
+
+- Avoid unnecessary compilation by sharing the same executable for a specific configuration
+    - executables are stored in `obj_dir_non_profiling` and `obj_dir_profiling` correspondingly
+- Wsim should support `-s verilator` option and run simulation with Verilator.
+
+## Folder Structure
+
+This folder contains the following files that help the simulation of Wally with Verilator:
+
+- Makefile: simplify the usage with Verialtor
+- executables
+    - `obj_dir_non_profiling`: non-profiling executables for different configurations
+    - `obj_dir_profiling`: profiling executables for different configurations
+- logs in `logs` and `logs_profiling` correspondingly
+- [NOT WORKING] `logs`: contains all the logs
+
+## Examples
+
+```shell
+# non-profiling mode
+make WALLYCONF=rv64gc TEST=arch64i run
+# profiling mode
+make WALLYCONF=rv64gc TEST=arch64i profile
+
+# remove all the temporary files, including executables and logs
+make clean
+```
\ No newline at end of file
diff --git a/sim/verilator/sim-wally-batch b/sim/verilator/sim-wally-batch
new file mode 100755
index 000000000..63b4a4cba
--- /dev/null
+++ b/sim/verilator/sim-wally-batch
@@ -0,0 +1 @@
+wsim -s verilator rv64gc arch64i
diff --git a/sim/verilator/verilate b/sim/verilator/verilate
deleted file mode 100755
index 23eb115e1..000000000
--- a/sim/verilator/verilate
+++ /dev/null
@@ -1,42 +0,0 @@
-#!/bin/bash
-# simulate with Verilator
-
-export PATH=$PATH:/usr/local/bin/
-verilator=`which verilator`
-
-basepath=$(dirname $0)/..
-#for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
-
-# define associateive array of tests to run
-declare -A suites
-rv64gccases=("arch64zba" "arch64zbb" "arch64zbc" "arch64zbs" "arch64i" "arch64m" "arch64a" "arch64f" "arch64d" "arch64c" "arch64f_fma" "arch64d_fma" "wally64priv")
-suites["rv64gc"]=${rv64gccases[@]}
-rv64icases=("arch64i")
-suites["rv64i"]=${rv32icases[@]}
-rv32gccases=("arch32zba" "arch32zbb" "arch32zbc" "arch32zbs" "arch32i" "arch32m" "arch32a" "arch32f" "arch32d" "arch32c" "arch64f_fma" "arch64d_fma" "wally32priv")
-suites["rv32gc"]=${rv32gccases[@]}
-rv32imccases=("arch32i" "arch32m" "arch32c")
-suites["rv32imc"]=${rv32imccases[@]}
-rv32icases=("arch32i")
-suites["rv32i"]=${rv32icases[@]}
-rv32ecases=("arch32e")
-suites["rv32e"]=${rv32ecases[@]}
-
-for config in ${!suites[@]}; do
-    for suite in ${suites[${config}]}; do
-        echo "Verilating ${config} ${suite}"
-        if !($verilator --timescale "1ns/1ns" --timing --binary "$@" -GTEST="\"${suite}\"" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv   $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
-            echo "Exiting after ${config} ${suite} verilation due to errors or warnings"
-            exit 1
-        fi
-        ./obj_dir/Vtestbench 
-    done
-done
-echo "Verilation complete"
-
-# command line to invoke Verilator on rv64gc arch64i
-# verilator -GTEST="\"arch64i\"" --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
-
-# command line with debugging to address core dumps
-# verilator -CFLAGS -DVL_DEBUG -CFLAGS -D_GLIBCXX_DEBUG -CFLAGS -ggdb -LDFLAGS -ggdb -CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
-
diff --git a/sim/verilator/wrapper.c b/sim/verilator/wrapper.c
new file mode 100644
index 000000000..572acaa55
--- /dev/null
+++ b/sim/verilator/wrapper.c
@@ -0,0 +1,11 @@
+#include <stdlib.h>
+
+#include "Vtestbench__Dpi.h"
+
+const char *getenvval(const char *pszName) {
+    const char *pszValue = getenv(pszName);
+    if (pszValue == NULL) {
+        return "";
+    }
+    return ((const char *) getenv(pszName));
+}
\ No newline at end of file
diff --git a/sim/wally-soc.do b/sim/wally-soc.do
deleted file mode 100644
index 176950ae0..000000000
--- a/sim/wally-soc.do
+++ /dev/null
@@ -1,94 +0,0 @@
-# wally-batch.do 
-# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-#
-# Modification by Oklahoma State University & Harvey Mudd College
-# Use with Testbench 
-# James Stine, 2008; David Harris 2021
-# Go Cowboys!!!!!!
-#
-# Takes 1:10 to run RV64IC tests using gui
-
-# Usage: do wally-batch.do <config> <testcases>
-# Example: do wally-batch.do rv32imc imperas-32i
-
-# Use this wally-batch.do file to run this example.
-# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
-#     do wally-batch.do
-# or, to run from a shell, type the following at the shell prompt:
-#     vsim -do wally-batch.do -c
-# (omit the "-c" to see the GUI while running from the shell)
-
-onbreak {resume}
-
-# create library
-if [file exists wkdir/work_${1}_${2}] {
-    vdel -lib wkdir/work_${1}_${2} -all
-}
-vlib wkdir/work_${1}_${2}
-# Create directory for coverage data
-mkdir -p cov
-
-set coverage 0
-set CoverageVoptArg ""
-set CoverageVsimArg ""
-
-# Need to be able to pass arguments to vopt.  Unforunately argv does not work because
-# it takes on different values if vsim and the do file are called from the command line or
-# if the do file isd called from questa sim directly.  This chunk of code uses the $4 through $n
-# variables and compacts into a single list for passing to vopt.
-set configOptions ""
-set from 4
-set step 1
-set lst {}
-for {set i 0} true {incr i} {
-    set x [expr {$i*$step + $from}]
-    if {$x > $argc} break
-    set arg [expr "$$x"]
-    lappend lst $arg
-}
-
-if {$argc >= 3} {
-    if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} {
-        set coverage 1
-        set CoverageVoptArg "+cover=sbecf"
-        set CoverageVsimArg "-coverage"
-    } elseif {$3 eq "configOptions"} {
-        set configOptions $lst
-        puts $configOptions
-    }
-}
-
-# compile source files
-# suppress spurious warnngs about 
-# "Extra checking for conflicts with always_comb done at vopt time"
-# because vsim will run vopt
-
-# default to config/rv64ic, but allow this to be overridden at the command line.  For example:
-# do wally-pipelined-batch.do ../config/rv32imc rv32imc
-
-# Compile bsg files, then wally
-set bsg_dir ../soc/src/basejump_stl
-vlog -lint -work wkdir/work_${1}_${2} +define+den2048Mb +define+sg5 +define+x32 +incdir+$bsg_dir/bsg_clk_gen +incdir+$bsg_dir/bsg_dmc +incdir+$bsg_dir/bsg_noc +incdir+$bsg_dir/bsg_tag +incdir+$bsg_dir/testing/bsg_dmc/lpddr_verilog_model +incdir+$bsg_dir/bsg_misc +incdir+$bsg_dir/testing/bsg_dmc/lpddr_verilog_model $bsg_dir/bsg_misc/bsg_defines.sv $bsg_dir/bsg_tag/bsg_tag_pkg.sv $bsg_dir/bsg_dmc/bsg_dmc_pkg.sv $bsg_dir/bsg_noc/bsg_noc_pkg.sv $bsg_dir/bsg_noc/bsg_mesh_router_pkg.sv $bsg_dir/bsg_noc/bsg_wormhole_router_pkg.sv $bsg_dir/*/*.sv $bsg_dir/testing/bsg_dmc/lpddr_verilog_model/*.sv -suppress 2583,2596,2605,2902,7063,8885,13286,13314,13388
-vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared +incdir+$bsg_dir/bsg_clk_gen +incdir+$bsg_dir/bsg_dmc +incdir+$bsg_dir/dmc_misc +incdir+$bsg_dir/bsg_misc +incdir+$bsg_dir/bsg_tag +incdir+$bsg_dir/testing/bsg_dmc/lpddr_verilog_model ../src/cvw.sv ../testbench/testbench-soc.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../soc/src/fifo/*.sv ../soc/src/*.sv -suppress 2583,2596,2605,2902,7063,8885,13286,13314,13388
-
-# start and run simulation
-# remove +acc flag for faster sim during regressions if there is no need to access internal signals
-vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 ${configOptions} -o testbenchopt ${CoverageVoptArg}
-vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3009,3829,8885 ${CoverageVsimArg}
-
-# power add generates the logging necessary for said generation.
-# power add -r /dut/core/*
-run -all
-# power off -r /dut/core/*
-
-
-if {$coverage} {
-    echo "Saving coverage to ${1}_${2}.ucdb"
-    do coverage-exclusions-rv64gc.do  # beware: this assumes testing the rv64gc configuration
-    coverage save -instance /testbench/dut/core cov/${1}_${2}.ucdb
-}
-
-# These aren't doing anything helpful
-#profile report -calltree -file wally-calltree.rpt -cutoff 2
-#power report -all -bsaif power.saif
-quit
diff --git a/site-setup.sh b/site-setup.sh
index 1ffca5fd4..acda541aa 100755
--- a/site-setup.sh
+++ b/site-setup.sh
@@ -21,7 +21,6 @@ export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH
 
 # GCC
 export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
-export PATH=$PATH:$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin      # GCC tools
 
 # Spike
 export LD_LIBRARY_PATH=$RISCV/lib:$LD_LIBRARY_PATH
@@ -30,6 +29,11 @@ export PATH=$PATH:$RISCV/bin
 # Verilator
 export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator
 
+# environment variables needed for RISCV-DV
+export RISCV_GCC=`which riscv64-unknown-elf-gcc`		            # Copy this as it is
+export RISCV_OBJCOPY=`which riscv64-unknown-elf-objcopy`	        # Copy this as it is
+export SPIKE_PATH=/usr/bin											# Change this for your path to riscv-isa-sim (spike)
+
 # Imperas OVPsim; put this in if you are using it
 #export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH  
 #export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH
@@ -45,3 +49,4 @@ if [ -e "$IDV" ]; then
     export PATH=$IDV/scripts/cvw:$PATH
 fi
 
+
diff --git a/soc/fsbl/Makefile b/soc/fsbl/Makefile
new file mode 100644
index 000000000..f406c35bc
--- /dev/null
+++ b/soc/fsbl/Makefile
@@ -0,0 +1,27 @@
+TARGETDIR	:= bin
+TARGET		:= $(TARGETDIR)/fsbl
+ROOT		:= ../../tests/custom
+LIBRARY_DIRS	:= 
+LIBRARY_FILES	:=
+
+MARCH			:=-march=rv64imfdc
+MABI            :=-mabi=lp64d
+LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles
+LINKER			:=$(ROOT)/linker.x
+
+AFLAGS =$(MARCH) $(MABI) -W
+CFLAGS =$(MARCH) $(MABI) -mcmodel=medany -O2
+AS=riscv64-unknown-elf-as
+CC=riscv64-unknown-elf-gcc
+AR=riscv64-unknown-elf-ar
+
+all: libfsbl.a
+
+%.o: %.s
+	${AS} ${AFLAGS} -c $< -o $@
+
+libfsbl.a: config_bsg_dmc.o config_pll.o
+	${AR} -r $@ $^
+
+clean:
+	rm -rf *.a *.o
diff --git a/soc/fsbl/config_bsg_dmc.s b/soc/fsbl/config_bsg_dmc.s
new file mode 100644
index 000000000..8585379e2
--- /dev/null
+++ b/soc/fsbl/config_bsg_dmc.s
@@ -0,0 +1,100 @@
+.section .text
+.globl config_bsg_dmc
+.type config_bsg_dmc, @function
+
+config_bsg_dmc:
+    # Configure memory-mapped registers for bsg_dmc memory sizing,
+    # timing parameters, and initialization sequence
+    # These values work with Micron LPDDR model provided by BSG
+
+    # trefi
+    li t1, 0x00030000
+    li t2, 0x3ff
+    sd t2, 0(t1)
+
+    # tmrd
+    addi t1, t1, 8
+    li t2, 0x1
+    sd t2, 0(t1)
+
+    # trfc
+    addi t1, t1, 8
+    li t2, 0xf
+    sd t2, 0(t1)
+
+    # trc
+    addi t1, t1, 8
+    li t2, 0xa
+    sd t2, 0(t1)
+
+    # trp
+    addi t1, t1, 8
+    li t2, 0x2
+    sd t2, 0(t1)
+
+    # tras
+    addi t1, t1, 8
+    li t2, 0x7
+    sd t2, 0(t1)
+
+    # trrd
+    addi t1, t1, 8
+    li t2, 0x1
+    sd t2, 0(t1)
+
+    # trcd
+    addi t1, t1, 8
+    li t2, 0x2
+    sd t2, 0(t1)
+
+    # twr
+    addi t1, t1, 8
+    li t2, 0xa
+    sd t2, 0(t1)
+
+    # twtr
+    addi t1, t1, 8
+    li t2, 0x7
+    sd t2, 0(t1)
+
+    # trtp
+    addi t1, t1, 8
+    li t2, 0xa
+    sd t2, 0(t1)
+
+    # tcas
+    addi t1, t1, 8
+    li t2, 0x3
+    sd t2, 0(t1)
+
+    # col_width
+    addi t1, t1, 8
+    li t2, 0xb
+    sd t2, 0(t1)
+
+    # row_width
+    addi t1, t1, 8
+    li t2, 0xe
+    sd t2, 0(t1)
+
+    # bank_width
+    addi t1, t1, 8
+    li t2, 0x2
+    sd t2, 0(t1)
+
+    # bank_pos
+    addi t1, t1, 8
+    li t2, 0x19
+    sd t2, 0(t1)
+
+    # dqs_sel_cal
+    addi t1, t1, 8
+    li t2, 0x3
+    sd t2, 0(t1)
+
+    # init_cycles
+    addi t1, t1, 8
+    li t2, 0x9c4a
+    sd t2, 0(t1)
+
+    ret
diff --git a/soc/fsbl/config_pll.s b/soc/fsbl/config_pll.s
new file mode 100644
index 000000000..b47982b6c
--- /dev/null
+++ b/soc/fsbl/config_pll.s
@@ -0,0 +1,46 @@
+.section .text
+.globl config_pll
+.type config_pll, @function
+
+config_pll:
+    # Configure memory-mapped registers for PLL clock generation
+    # This config generates a 2GHz clock at the PLL output, which we divide down
+
+    # clkr
+    li t1, 0x00020000
+    li t2, 0x00
+    sd t2, 0(t1)
+
+    # clkf
+    addi t1, t1, 8
+    li t2, 0x0027
+    sd t2, 0(t1)
+
+    # clkod
+    addi t1, t1, 8
+    li t2, 0x0
+    sd t2, 0(t1)
+
+    # bwadj
+    addi t1, t1, 8
+    li t2, 0x13
+    sd t2, 0(t1)
+
+    # test
+    addi t1, t1, 8
+    li t2, 0x0
+    sd t2, 0(t1)
+
+    # fasten
+    addi t1, t1, 8
+    li t2, 0x0
+    sd t2, 0(t1)
+
+    # wait for lock
+    addi t1, t1, 8
+    ld t2, 0(t1)
+wait_until_pll_locked:
+    bne t2, zero, pll_locked
+    ld t2, 0(t1)
+pll_locked:
+    ret
diff --git a/soc/src/ahbburstctrl.sv b/soc/src/ahbburstctrl.sv
new file mode 100644
index 000000000..940a1870e
--- /dev/null
+++ b/soc/src/ahbburstctrl.sv
@@ -0,0 +1,223 @@
+///////////////////////////////////////////
+// ahbburstctrl.sv
+//
+// Written: infinitymdm@gmail.com 20 May 2024
+// Modified: infinitymdm@gmail.com 25 May 2024
+//
+// Purpose: AHB burst management FSM for AHB to UI converter
+// 
+// Documentation: 
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module ahbburstctrl #(parameter BURST_LEN = 8) (
+  input  logic clk,
+  input  logic reset,
+  input  logic op_ready,            // Manager has valid address phase signals on the AHB bus
+  input  logic cmd_full,            // Subordinate cannot accept a command right now
+  input  logic new_addr,            // Manager is addressing a new location in memory
+  input  logic [3:0] word_addr,     // Lower bits of the write address
+  input  logic write,               // Manager has issued a write operation
+  input  logic new_burst,           // Manager has initiated a new burst
+  input  logic resp_valid,          // Subordinate has response data ready
+  output logic capture_op,          // Capture the current AHB op so we can issue it to the subordinate
+  output logic record_op,           // Store the current AHB op so we have the option of issuing it to the subordinate later
+  output logic select_recorded_op,  // Mux the recorded op to the subordinate
+  output logic mask_write,          // Mask off all bytes in this write op
+  output logic issue_op,            // Commit the selected op to the subordinate
+  output logic drop_resp,           // Discard response data from the subordinate
+  output logic readyout             // Manager can send more commands
+);
+  // State Definitions
+  typedef enum logic [4:0] {
+    IDLE=0, // Ready to start the next burst (default)
+    DLYR,   // Delay Read burst until subordinate is ready
+    DLYPR,  // Delay Read burst until subordinate is ready, then pad until word aligned
+    RBIP,   // Read Burst In Progress
+    DROP,   // Read burst response received, check & drop aligned read commands
+    DRPR,   // Drop unaligned read responses, then start new Read burst
+    DRPPR,  // Drop remaining read responses, then start new Read burst by way of PADR
+    DRPW,   // Drop remaining read responses, then start new Write burst
+    DRPPW,  // Drop remaining read responses, then start new Write burst by way of PADW
+    PADR,   // Read burst issued, but read command is not word aligned. Realign by dropping unaligned responses
+    RPTR,   // Repeat last write op to complete a burst, then start new Read burst
+    RPTPR,  // Repeat last write op to complete a burst, then start new Read burst by way of PADR
+    RPTW,   // Repeat last write op to complete a burst, then start new Write burst
+    RPTPW,  // Repeat last write op to complete a burst, then start new Write burst by way of PADW
+    WBIP,   // Write Burst In Progress
+    DLYW,   // Delay Write burst until subordinate is ready
+    DLYPW,  // Delay write burst until subordinate is ready, then pad until word aligned
+    PADW    // Pad Write burst by issuing masked writes until word aligned
+  } state;
+
+  logic [$clog2(BURST_LEN)-1:0] op_count;
+  logic inc_op_count;
+  logic first_op, last_op;
+  logic word_aligned, word_zero;
+  state current_state, next_state;
+  logic [7:0] outputs;
+  logic record_op_next, mask_write_next, issue_op_next, ready_next, ready;
+
+  // Op counter
+  counter #($clog2(BURST_LEN)) op_counter (clk, reset, inc_op_count, op_count);
+
+  // Aliases/shorthands for readability
+  assign first_op = ~|op_count; // true when op_count is all 0s
+  assign last_op = &op_count; // true when op_count is all 1s
+  assign word_aligned = (word_addr == {op_count, 1'b0}); // word_addr == 2*op_count // FIXME: If BURST_LEN != 8, op_count is the wrong size
+  assign word_zero = ~|word_addr; // word_addr == 4'b0000
+
+  // State transition logic
+  flopr #(5) statereg (clk, reset, next_state, current_state);
+  always_comb begin
+    case (current_state)
+      IDLE: casez ({op_ready, cmd_full, write, word_aligned})
+              4'b0???: {next_state, outputs} = {IDLE,  8'b00000010}; // Wait for command
+              4'b1000: {next_state, outputs} = {PADR,  8'b10001000}; // We have a misaligned read. Issue read burst and drop responses until realigned.
+              4'b1001: {next_state, outputs} = {RBIP,  8'b10001100}; // We have an aligned read. Issue read burst and wait for response. Precount the first response beat.
+              4'b1010: {next_state, outputs} = {PADW,  8'b11011100}; // We have a misaligned write. Pad write burst with masked writes until aligned with the incoming word.
+              4'b1011: {next_state, outputs} = {WBIP,  8'b11001110}; // We have an aligned write. Issue write and wait for next write in burst.
+              4'b1100: {next_state, outputs} = {DLYPR, 8'b11000000}; // We have a misaligned write, and the command queue is full Record op and wait for a spot in the queue, then pad read. 
+              4'b1101: {next_state, outputs} = {DLYR,  8'b11000000}; // We have an aligned read, but the command queue is full. Record op and wait for a spot in the queue, then issue read.
+              4'b1110: {next_state, outputs} = {DLYPW, 8'b11000000}; // We have a misaligned write, and the command queue is full. Record op and wait for a spot in the queue, then pad write.
+              4'b1111: {next_state, outputs} = {DLYW,  8'b11000000}; // We have an aligned write, but the command queue is full. Record op and wait for a spot in the queue, then issue write.
+            endcase
+      DLYR: case (cmd_full)
+              1'b0: {next_state, outputs} = {RBIP, 8'b00101100}; // Subordinate is ready for command. Issue read and wait for response.
+              1'b1: {next_state, outputs} = {DLYR, 8'b00000000}; // Wait until subordinate is ready for command
+            endcase
+      DLYPR:case (cmd_full)
+              1'b0: {next_state, outputs} = {PADR,  8'b00101100}; // Subordinate is ready for command. Issue read and drop responses until aligned.
+              1'b1: {next_state, outputs} = {DLYPR, 8'b00000000}; // Wait until subordinate is ready for command
+            endcase
+      RBIP: casez ({resp_valid, op_ready, write, new_addr, word_aligned, word_zero})
+              6'b0?????: {next_state, outputs} = {RBIP,  8'b00000000}; // Wait for response data from subordinate
+              6'b10????: {next_state, outputs} = {DROP,  8'b00000010}; // Response rx'd. Wait for next read in burst.
+              6'b11000?: {next_state, outputs} = {PADR,  8'b11000000}; // Response rx'd, but next read op is misaligned. Realign by dropping responses.
+              6'b11001?: {next_state, outputs} = {DROP,  8'b00000110}; // Response rx'd. Drop the aligned read op on the bus.
+              6'b1101?0: {next_state, outputs} = {DRPPR, 8'b11000000}; // Response rx'd, but we have a misaligned read targeting a new address. Drop remaining responses then pad out the new read.
+              6'b1101?1: {next_state, outputs} = {DRPR,  8'b11000000}; // Response rx'd, but we have a read targeting a new address. Drop remaining responses then issue the new read.
+              6'b111??0: {next_state, outputs} = {DRPPW, 8'b11000000}; // Response rx'd, but we have a misaligned write. Drop remaining responses then pad out the new write.
+              6'b111??1: {next_state, outputs} = {DRPW,  8'b11000000}; // Response rx'd, but we have a write. Drop remaining responses then issue the new write.
+            endcase
+      DROP: casez ({op_ready, write, new_addr, word_aligned, last_op, word_zero})
+              6'b0?????: {next_state, outputs} = {DROP,  8'b00000010}; // Wait for manager to send the next beat in the read burst
+              6'b1000??: {next_state, outputs} = {PADR,  8'b11000000}; // We have a misaligned read op. Realign by dropping responses.
+              6'b10010?: {next_state, outputs} = {DROP,  8'b00000110}; // We have an aligned read op. Ignore the op since we already have the response data, then wait for the next beat.
+              6'b10011?: {next_state, outputs} = {IDLE,  8'b00000110}; // We have an aligned read op. Ignore the op since we already have the response data, then wait for a new op.
+              6'b101??0: {next_state, outputs} = {DRPPR, 8'b11000000}; // We have a misaligned read targeting a new address. Drop remaining responses then pad out the new read.
+              6'b101??1: {next_state, outputs} = {DRPR,  8'b11000000}; // We have an aligned read targeting a new address. Drop remaining responses then issue the new read.
+              6'b11???0: {next_state, outputs} = {DRPPW, 8'b11000000}; // We have a misaligned write. Drop remaining responses then pad out the new write.
+              6'b11???1: {next_state, outputs} = {DRPW,  8'b11000000}; // We have an aligned write. Drop remaining responses then issue the new write.
+            endcase
+      DRPR: casez ({resp_valid, cmd_full})
+              2'b00: {next_state, outputs} = {RBIP, 8'b00101100}; // We've dropped all read responses and subordinate is ready for command. Issue read and wait for response.
+              2'b01: {next_state, outputs} = {DLYPR, 8'b00000000}; // We've dropped all read responses. Wait until subordinate is ready for command.
+              2'b1?: {next_state, outputs} = {DRPR, 8'b00000101}; // Drop this beat of the read response.
+            endcase
+      DRPPR:casez ({resp_valid, cmd_full})
+              2'b00: {next_state, outputs} = {PADR,  8'b00101100}; // We've dropped all read responses and subordinate is ready for command. Pad read.
+              2'b01: {next_state, outputs} = {DLYPR, 8'b00000000}; // We've dropped all read responses. Wait until subordinate is ready for command.
+              2'b1?: {next_state, outputs} = {DRPR,  8'b00000101}; // Drop this beat of the read response.
+            endcase
+      DRPW: casez ({resp_valid, cmd_full})
+              2'b00: {next_state, outputs} = {WBIP,  8'b00101110}; // We've dropped all read responses and subordinate is ready for command. Issue write and wait for next beat in burst.
+              2'b01: {next_state, outputs} = {DLYPW, 8'b00000000}; // We've dropped all read responses. Wait until subordinate is ready for command.
+              2'b1?: {next_state, outputs} = {DRPW,  8'b00000101}; // Drop this beat of the read response.
+            endcase
+      DRPPW:casez ({resp_valid, cmd_full})
+              2'b00: {next_state, outputs} = {PADW,  8'b00111110}; // We've dropped all read responses and subordinate is ready for command. Pad write.
+              2'b01: {next_state, outputs} = {DLYPW, 8'b00000000}; // We've dropped all read responses. Wait until subordinate is ready for command.
+              2'b1?: {next_state, outputs} = {DRPPW, 8'b00000101}; // Drop this beat of the read response.
+            endcase
+      PADR: casez ({resp_valid, word_aligned, first_op, cmd_full})
+              4'b0?0?: {next_state, outputs} = {PADR, 8'b00000000}; // Wait for response data
+              4'b0?10: {next_state, outputs} = {PADR, 8'b00101100}; // We dropped all remaining beats of the burst without realigning. Issue a new read and wait for data. Precount the first beat. (NOTE: This should only happen if we have a misordered read burst, e.g. 0x08 followed by 0x00)
+              4'b0?11: {next_state, outputs} = {PADR, 8'b00000000}; // We are out of response data, but queue is full. Wait for queue to open up.
+              4'b10??: {next_state, outputs} = {PADR, 8'b00000101}; // Response is misaligned. Drop this beat of response data.
+              4'b11??: {next_state, outputs} = {DROP, 8'b00000110}; // Response is now realigned with the read burst. Return to normal read burst handling.
+            endcase
+      RPTR: casez ({cmd_full, first_op})
+              2'b00: {next_state, outputs} = {RPTR, 8'b00111100}; // Subordinate is ready for command, and write burst is incomplete. Mask and reissue the write op.
+              2'b01: {next_state, outputs} = {RBIP, 8'b00101100}; // Subordinate is ready for command, and write burst is complete. Issue the captured read burst.
+              2'b1?: {next_state, outputs} = {RPTR, 8'b00000000}; // Wait until subordinate is ready for command
+            endcase
+      RPTPR:casez ({cmd_full, first_op})
+              2'b00: {next_state, outputs} = {RPTPR, 8'b00111100}; // Subordinate is ready for command, and write burst is incomplete. Mask and reissue the write op.
+              2'b01: {next_state, outputs} = {PADR,  8'b01101100}; // Subordinate is ready for command, and write burst is complete. Issue the captured read burst and drop responses until aligned.
+              2'b1?: {next_state, outputs} = {RPTPR, 8'b00000000}; // Wait until subordinate is ready for command
+            endcase
+      RPTW: casez ({cmd_full, first_op})
+              2'b00: {next_state, outputs} = {RPTW, 8'b00111100}; // Subordinate is ready for command, and write burst is incomplete. Mask and reissue the write op.
+              2'b01: {next_state, outputs} = {WBIP, 8'b00101110}; // Subordinate is ready for command, and write burst is complete. Issue the captured write burst.
+              2'b1?: {next_state, outputs} = {RPTW, 8'b00000000}; // Wait until subordinate is ready for command
+            endcase
+      RPTPW:casez ({cmd_full, first_op})
+              2'b00: {next_state, outputs} = {RPTPW, 8'b00111100}; // Subordinate is ready for command, and write burst is incomplete. Mask and reissue the write op.
+              2'b01: {next_state, outputs} = {PADW,  8'b01111110}; // Subordinate is ready for command, and write burst is complete. Pad out the captured write burst.
+              2'b1?: {next_state, outputs} = {RPTPW, 8'b00000000}; // Wait until subordinate is ready for command
+            endcase
+      WBIP: casez ({op_ready, cmd_full, write, new_burst, new_addr, word_aligned, word_zero, last_op})
+              8'b0???????: {next_state, outputs} = {WBIP,  8'b00000010}; // Wait for command
+              8'b100???0?: {next_state, outputs} = {RPTPR, 8'b10111100}; // We have a misaligned read. Repeat write op until burst is complete, then issue read and drop responses until aligned.
+              8'b100???1?: {next_state, outputs} = {RPTR,  8'b10111100}; // We have an aligned read. Repeat write op until burst is complete, then issue read.
+              8'b101000??: {next_state, outputs} = {PADW,  8'b11011100}; // We have a misaligned write. Pad until realigned.
+              8'b101001?0: {next_state, outputs} = {WBIP,  8'b11001110}; // We have an aligned write, and the burst is not complete. Issue write, then wait for next write in burst.
+              8'b101001?1: {next_state, outputs} = {IDLE,  8'b10001110}; // We have an aligned write that will complete the burst. Issue the write and wait for new op.
+              8'b10101?0?: {next_state, outputs} = {RPTPW, 8'b10111100}; // We have a misaligned write targeting a new address. Repeat write op until burst is complete, then pad new write.
+              8'b10101?1?: {next_state, outputs} = {RPTW,  8'b10111100}; // We have an aligned write targeting a new address. Repeat write op until burst is complete, then issue new write.
+              8'b1011??0?: {next_state, outputs} = {RPTPW, 8'b10111100}; // We have a misaligned write starting a new burst. Repeat write op until burst is complete, then pad new write.
+              8'b1011??1?: {next_state, outputs} = {RPTW,  8'b10111100}; // We have an aligned write starting a new burst. Repeat write op until burst is complete, then issue new write.
+              8'b110???0?: {next_state, outputs} = {RPTPR, 8'b10000000}; // We have a misaligned read, but queue is full. Wait on the queue, then repeat write until burst complete, then issue read and drop responses until aligned.
+              8'b110???1?: {next_state, outputs} = {RPTR,  8'b10000000}; // We have an aligned read, but queue is full. Wait on the queue, then repeat write until burst complete, then issue read.
+              8'b111000??: {next_state, outputs} = {DLYPW, 8'b10000000}; // We have a misaligned write, but the queue is full. Wait on the queue, then pad the write.
+              8'b111001??: {next_state, outputs} = {DLYW,  8'b10000000}; // We have an aligned write, but the queue is full. Wait on the queue, then issue the write.
+              8'b11101?0?: {next_state, outputs} = {RPTPW, 8'b10000000}; // We have a misaligned write targeting a new address. Wait on the queue, then repeat write until burst complete, then pad new write.
+              8'b11101?1?: {next_state, outputs} = {RPTW,  8'b10000000}; // We have an aligned write targeting a new address. Wait on the queue, then repeat write until burst complete, then issue new write.
+              8'b1111??0?: {next_state, outputs} = {RPTPW, 8'b10000000}; // We have a misaligned write starting a new burst. Wait on the queue, then repeat write until burst complete, then pad new write.
+              8'b1111??1?: {next_state, outputs} = {RPTW,  8'b10000000}; // We have an aligned write starting a new burst. Wait on the queue, then repeat write until burst complete, then issue new write.
+            endcase
+      DLYW: casez ({cmd_full, last_op})
+              2'b00: {next_state, outputs} = {WBIP, 8'b00101110}; // Subordinate is ready for command, and write burst is incomplete. Issue write and wait for next write in burst.
+              2'b01: {next_state, outputs} = {IDLE, 8'b00101110}; // Subordinate is ready for command, and this write completes the burst. Issue write and wait for new op.
+              2'b1?: {next_state, outputs} = {DLYW, 8'b00000000}; // Wait until subordinate is ready for command
+            endcase
+      DLYPW:case (cmd_full)
+              1'b0: {next_state, outputs} = {PADW,  8'b00111110}; // Subordinate is ready for command. Pad write until realigned.
+              1'b1: {next_state, outputs} = {DLYPW, 8'b00000000}; // Wait until subordinate is ready for command
+            endcase
+      PADW: casez ({cmd_full, word_aligned, last_op})
+              3'b00?: {next_state, outputs} = {PADW, 8'b00111100}; // Subordinate is ready for command. Issue masked write to realign burst.
+              3'b010: {next_state, outputs} = {WBIP, 8'b00101110}; // Subordinate is ready for command and burst is aligned. Issue and wait for next write in burst.
+              3'b011: {next_state, outputs} = {IDLE, 8'b00101110}; // Subordinate is ready for command, burst is aligned, and this write completes the burst. Issue and wait for next op.
+              3'b1??: {next_state, outputs} = {PADW, 8'b00000000}; // Wait until subordinate is ready for command
+            endcase
+    endcase
+  end
+  assign {capture_op, record_op_next, select_recorded_op, mask_write_next, issue_op_next, inc_op_count, ready_next, drop_resp} = outputs;
+
+  // Delay signals to align with ops
+  flopr #(1) recordreg (clk, reset, record_op_next,  record_op);
+  flopr #(1) maskreg   (clk, reset, mask_write_next, mask_write);
+  flopr #(1) issuereg  (clk, reset, issue_op_next,   issue_op);
+  flopr #(1) readyreg  (clk, reset, ready_next,      ready);
+  assign readyout = ready_next & ready;  // Deassert readyout immediately, but assert synchronously
+
+endmodule
diff --git a/soc/src/ahbxuiconverter.sv b/soc/src/ahbxuiconverter.sv
index 2d672a796..221f32137 100644
--- a/soc/src/ahbxuiconverter.sv
+++ b/soc/src/ahbxuiconverter.sv
@@ -2,6 +2,7 @@
 // ahbxuiconverter.sv
 //
 // Written: infinitymdm@gmail.com 29 February 2024
+// Modified: infinitymdm@gmail.com 02 April 2024
 //
 // Purpose: AHB to Xilinx UI converter
 // 
@@ -26,8 +27,12 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module ahbxuiconverter #(parameter ADDR_SIZE = 31,
-                         parameter DATA_SIZE = 64) (
+module ahbxuiconverter 
+#(
+  parameter ADDR_SIZE = 31,
+  parameter DATA_SIZE = 64,
+  parameter BURST_LEN = 8
+) (
   // AHB signals
   input  logic                   HCLK,
   input  logic                   HRESETn,
@@ -37,6 +42,7 @@ module ahbxuiconverter #(parameter ADDR_SIZE = 31,
   input  logic [DATA_SIZE/8-1:0] HWSTRB,
   input  logic                   HWRITE,
   input  logic [1:0]             HTRANS,
+  input  logic [2:0]             HBURST,
   input  logic                   HREADY,
   output logic [DATA_SIZE-1:0]   HRDATA,
   output logic                   HRESP,
@@ -46,7 +52,7 @@ module ahbxuiconverter #(parameter ADDR_SIZE = 31,
   output logic                   sys_reset,
   input  logic                   ui_clk, // from PLL
   input  logic                   ui_clk_sync_rst,
-  output logic [ADDR_SIZE-1:0]   app_addr, // Double check this width
+  output logic [ADDR_SIZE-1:0]   app_addr,
   output logic [2:0]             app_cmd,
   output logic                   app_en,
   input  logic                   app_rdy,
@@ -61,54 +67,124 @@ module ahbxuiconverter #(parameter ADDR_SIZE = 31,
   input  logic                   init_calib_complete
 );
 
+  localparam BURST_CNTR_SIZE = $clog2(BURST_LEN);
+  localparam MASK_SIZE = DATA_SIZE >> 3;
+  localparam OP_SIZE = 1 + ADDR_SIZE-4 + DATA_SIZE + MASK_SIZE; // wren + addr (minus last nibble) + data + mask
+
+  logic [ADDR_SIZE-1:0]       addr;
+  logic                       ahb_wren;
+  logic [ADDR_SIZE-1:4]       ahb_addr;
+  logic [1:0]                 ahb_burst;
+  
+  logic                       op_ready;
+  logic                       new_addr;
+  logic                       new_burst;
+  logic                       record_op;
+  logic                       select_recorded_op;
+  logic                       mask_write;
+  logic                       drop_resp;
+  
+  logic [OP_SIZE-1:0]         op;
+  logic [OP_SIZE-1:0]         recorded_op;
+  logic                       capture_op;
+  logic [OP_SIZE-1:MASK_SIZE] selected_op;
+  logic [MASK_SIZE-1:0]       mask;
+  logic [MASK_SIZE-1:0]       selected_mask;
+
+  logic                       cmd_w_full;
+  logic                       cmd_r_valid;
+  logic                       cmd_enq;
+  logic                       cmd_deq;
+
+  logic                       ui_initialized;
+  logic                       write;
+
+  logic                       resp_w_full;
+  logic                       resp_r_valid;
+  logic                       resp_enq;
+  logic                       resp_deq;
+
   assign sys_reset = ~HRESETn;
 
-  // Enable this peripheral when:
-  // a) selected, AND
-  // b) a transfer is started, AND
-  // c) the bus is ready
-  logic ahbEnable;
-  assign ahbEnable = HSEL & HTRANS[1] & HREADY;
-
-  // UI is ready for a command when initialized and ready to read and write
-  logic uiReady;
-  assign uiReady = app_rdy & app_wdf_rdy & init_calib_complete;
-
-  // Buffer the input down to ui_clk speed
-  logic [ADDR_SIZE-1:0]   addr;
-  logic [DATA_SIZE-1:0]   data;
-  logic [DATA_SIZE/8-1:0] mask;
-  logic                   cmdEnable, cmdWrite;
-  logic                   cmdwfull, cmdrempty;
-  // FIFO needs addr + (data + mask) + (enable + write)
-  fifo #(ADDR_SIZE + 9*DATA_SIZE/8 + 2, 32) cmdfifo (
-    .wdata({HADDR, HWDATA, HWSTRB, ahbEnable, HWRITE}),
-    .winc(ahbEnable), .wclk(HCLK), .wrst_n(HRESETn),
-    .rinc(uiReady), .rclk(ui_clk), .rrst_n(~ui_clk_sync_rst),
-    .rdata({addr, data, mask, cmdEnable, cmdWrite}),
-    .wfull(cmdwfull), .rempty(cmdrempty)
+  // Wally uses byte addressing, but DDR gives us 32 bits per address
+  // Compensate for this with a bit of address translation - just divide by 4
+  assign addr = HADDR >> 2;
+
+  // We use an FSM to line up AHB commands into bursts for the UI
+  assign op_ready = HSEL & HTRANS[1] & HREADY;
+  assign new_addr = ~(ahb_addr == addr[ADDR_SIZE-1:4]);
+  assign new_burst = ~(ahb_burst == HBURST);
+  ahbburstctrl #(BURST_LEN) ahbctrl (
+    .clk(HCLK), .reset(~HRESETn),
+    .op_ready, .cmd_full(cmd_w_full),
+    .new_addr, .word_addr(addr[3:0]),
+    .write(HWRITE), .new_burst,
+    .resp_valid(resp_r_valid),
+    .capture_op, .record_op,
+    .select_recorded_op, .mask_write,
+    .issue_op(cmd_enq), .drop_resp,
+    .readyout(HREADYOUT)
   );
 
-  // Delay transactions 1 clk so we can set wren on the cycle after write commands
-  flopen  #(ADDR_SIZE)   addrreg  (ui_clk, uiReady, addr, app_addr);
-  flopenr #(3)           cmdreg   (ui_clk, ui_clk_sync_rst, uiReady, {2'b0, ~cmdWrite}, app_cmd);
-  flopenr #(1)           cmdenreg (ui_clk, ui_clk_sync_rst, uiReady, cmdEnable, app_en);
-  flopenr #(1)           wrenreg  (ui_clk, ui_clk_sync_rst, uiReady, ~app_cmd[0], app_wdf_wren);
-  flopenr #(DATA_SIZE)   datareg  (ui_clk, ui_clk_sync_rst, uiReady, data, app_wdf_data);
-  flopenr #(DATA_SIZE/8) maskreg  (ui_clk, ui_clk_sync_rst, uiReady, mask, app_wdf_mask);
-  assign app_wdf_end = app_wdf_wren; // Since AHB will always put data on the bus after a write cmd, this is always valid
-  
-  // Return read data at HCLK speed TODO: Double check that rinc is correct
-  logic respwfull, resprempty;
-  fifo #(DATA_SIZE, 16) respfifo (
-    .wdata(app_rd_data),
-    .winc(app_rd_data_valid), .wclk(ui_clk), .wrst_n(~ui_clk_sync_rst),
-    .rinc(ahbEnable), .rclk(HCLK), .rrst_n(HRESETn),
-    .rdata(HRDATA),
-    .wfull(respwfull), .rempty(resprempty)
+  // Delay AHB address phase signals. Only capture if indicated by control logic
+  flopenr #(1)           ahbwrenreg (HCLK, ~HRESETn, capture_op, HWRITE,              ahb_wren);
+  flopenr #(ADDR_SIZE-4) ahbaddrreg (HCLK, ~HRESETn, capture_op, addr[ADDR_SIZE-1:4], ahb_addr); // The last nibble to UI will always be 'h0, so no need to store it
+  flopenr #(2)           ahbbrstreg (HCLK, ~HRESETn, capture_op, HBURST[2:1],         ahb_burst);
+  assign op = {ahb_wren, ahb_addr, HWDATA, ~HWSTRB};
+
+  // Store a previously captured op for later if requested by control logic
+  flopenr #(OP_SIZE) recordedopreg (HCLK, ~HRESETn, record_op, op, recorded_op);
+
+  // Select signals according to control logic
+  mux2 #(OP_SIZE)   opselect   (op,   recorded_op,       select_recorded_op, {selected_op, mask});
+  mux2 #(MASK_SIZE) maskselect (mask, {MASK_SIZE{1'b1}}, mask_write,         selected_mask);
+
+  // Buffer input down to ui_clk speed
+  bsg_async_fifo #(
+    .width_p(OP_SIZE),
+    .lg_size_p(5),
+    .and_data_with_valid_p(1)
+  ) cmdfifo (
+    .w_data_i({selected_op, selected_mask}),
+    .w_enq_i(cmd_enq), .w_clk_i(HCLK), .w_reset_i(~HRESETn),
+    .r_deq_i(cmd_deq), .r_clk_i(ui_clk), .r_reset_i(ui_clk_sync_rst),
+    .r_data_o({write, app_addr[ADDR_SIZE-1:4], app_wdf_data, app_wdf_mask}),
+    .w_full_o(cmd_w_full), .r_valid_o(cmd_r_valid)
   );
-  
-  assign HRESP = 0; // do not indicate errors
-  assign HREADYOUT = uiReady & ~cmdwfull; // TODO: Double check
+  assign app_addr[3:0] = 4'b0;
+
+  // Synchronize ui init flag
+  flopr #(1) initreg (ui_clk, sys_reset, init_calib_complete, ui_initialized);
+
+  // Use an FSM to issue UI bursts
+  uiburstctrl #(BURST_LEN) uictrl (
+    .clk(ui_clk), .reset(ui_clk_sync_rst),
+    .ui_initialized, .app_rdy, .app_wdf_rdy,
+    .write, .op_ready(cmd_r_valid),
+    .app_en, .app_cmd0(app_cmd[0]), .app_wdf_wren, .app_wdf_end,
+    .dequeue_op(cmd_deq)
+  );
+  assign app_cmd[2:1] = {2'b0};
+
+  // Return read data at HCLK speed
+  // There is no mechanism to stall the UI in the event that the FIFO is full during a read burst,
+  // so we need to ensure that never occurs. In theory, since the FSM in ahbburstctrl ensures we
+  // never issue a command while a read is in progress, we should never have the read FIFO fill up.
+  assign resp_enq = app_rd_data_valid & ~resp_w_full;
+  assign resp_deq = (HSEL & resp_r_valid) | drop_resp;
+  bsg_async_fifo #(
+    .width_p(DATA_SIZE),
+    .lg_size_p(4),
+    .and_data_with_valid_p(1)
+  ) respfifo (
+    .w_data_i(app_rd_data),
+    .w_enq_i(resp_enq), .w_clk_i(ui_clk), .w_reset_i(ui_clk_sync_rst),
+    .r_deq_i(resp_deq), .r_clk_i(HCLK), .r_reset_i(~HRESETn),
+    .r_data_o(HRDATA),
+    .w_full_o(resp_w_full), .r_valid_o(resp_r_valid)
+  );
+
+  // do not indicate errors
+  assign HRESP = 0;
 
 endmodule
diff --git a/soc/src/bsg_dmc_ahb.sv b/soc/src/bsg_dmc_ahb.sv
index 25045823f..115af1cda 100644
--- a/soc/src/bsg_dmc_ahb.sv
+++ b/soc/src/bsg_dmc_ahb.sv
@@ -3,7 +3,7 @@
 //
 // Written: infinitymdm@gmail.com 29 February 2024
 //
-// Purpose: BSG controller and LPDDRDRAM presenting an AHB interface
+// Purpose: BSG memory controller presenting an AHB interface
 // 
 // Documentation: 
 //
@@ -34,44 +34,46 @@ module bsg_dmc_ahb
 #(
   parameter AHB_ADDR_SIZE = 28,
   parameter AHB_DATA_SIZE = 64,
-  parameter DDR_DATA_SIZE = 32,
-  parameter BURST_LENGTH  = 8,
-  parameter FIFO_DEPTH    = 4
+  parameter DQ_DATA_SIZE  = 32,
+  parameter BURST_LEN     = 8, // bsg_dmc supports 4- or 8-beat bursts
+  parameter FIFO_DEPTH    = 8
 ) (
+  input  bsg_dmc_s                   dmc_config,
+  input  logic                       dmc_config_changed,
   input  logic                       HCLK, HRESETn,
   input  logic                       HSEL,
   input  logic [AHB_ADDR_SIZE-1:0]   HADDR,
   input  logic [AHB_DATA_SIZE-1:0]   HWDATA,
   input  logic [AHB_DATA_SIZE/8-1:0] HWSTRB,
+  input  logic [2:0]                 HBURST,
   input  logic                       HWRITE,
   input  logic [1:0]                 HTRANS,
   input  logic                       HREADY,
   output logic [AHB_DATA_SIZE-1:0]   HRDATA,
   output logic                       HRESP, HREADYOUT,
-  //input  logic                       ui_clk, // Add this once PLL is integrated
-  output logic                       ddr_ck_p, ddr_ck_n, ddr_cke,
-  output logic [2:0]                 ddr_ba,
-  output logic [13:0]                ddr_addr,
-  output logic                       ddr_cs, ddr_ras, ddr_cas,
-  output logic                       ddr_we, ddr_reset, ddr_odt,
-  output logic [DDR_DATA_SIZE/8-1:0] ddr_dm_oen, ddr_dm,
-  output logic [DDR_DATA_SIZE/8-1:0] ddr_dqs_p_oen, ddr_dqs_p_ien, ddr_dqs_p_out,
-  input  logic [DDR_DATA_SIZE/8-1:0] ddr_dqs_p_in,
-  output logic [DDR_DATA_SIZE/8-1:0] ddr_dqs_n_oen, ddr_dqs_n_ien, ddr_dqs_n_out,
-  input  logic [DDR_DATA_SIZE/8-1:0] ddr_dqs_n_in,
-  output logic [DDR_DATA_SIZE-1:0]   ddr_dq_oen, ddr_dq_out,
-  input  logic [DDR_DATA_SIZE-1:0]   ddr_dq_in,
-  input  logic                       dfi_clk_2x,
-  output logic                       dfi_clk_1x
+  input  logic                       ui_clk,
+  output                             ddr_ck_p_o, ddr_ck_n_o, ddr_cke_o,
+  output       [2:0]                 ddr_ba_o,
+  output       [15:0]                ddr_addr_o,
+  output                             ddr_cs_n_o, ddr_ras_n_o, ddr_cas_n_o,
+  output                             ddr_we_n_o, ddr_reset_n_o, ddr_odt_o,
+  output       [DQ_DATA_SIZE/8-1:0]  ddr_dm_oen_o, ddr_dm_o,
+  output       [DQ_DATA_SIZE/8-1:0]  ddr_dqs_p_oen_o, ddr_dqs_p_ien_o, ddr_dqs_p_o,
+  input        [DQ_DATA_SIZE/8-1:0]  ddr_dqs_p_i,
+  output       [DQ_DATA_SIZE/8-1:0]  ddr_dqs_n_oen_o, ddr_dqs_n_ien_o, ddr_dqs_n_o,
+  input        [DQ_DATA_SIZE/8-1:0]  ddr_dqs_n_i,
+  output       [DQ_DATA_SIZE-1:0]    ddr_dq_oen_o, ddr_dq_o,
+  input        [DQ_DATA_SIZE-1:0]    ddr_dq_i,
+  input  logic                       dfi_clk_2x_i,
+  output logic                       dfi_clk_1x_o
 );
 
   // Global async reset
   logic sys_reset;
 
   // Memory controller config
-  bsg_tag_s       dmc_rst_tag, dmc_ds_tag;
-  bsg_tag_s [3:0] dmc_dly_tag, dmc_dly_trigger_tag;
-  bsg_dmc_s       dmc_config;
+  bsg_tag_s                      dmc_rst_tag, dmc_ds_tag;
+  bsg_tag_s [DQ_DATA_SIZE/8-1:0] dmc_dly_tag, dmc_dly_trigger_tag;
 
   // UI signals
   logic                       ui_clk_sync_rst;
@@ -83,43 +85,17 @@ module bsg_dmc_ahb
   logic                       app_wdf_end, app_wdf_rdy;
   logic [AHB_DATA_SIZE-1:0]   app_rd_data;
   logic                       app_rd_data_end, app_rd_data_valid;
-  logic                       app_ref_ack, app_zq_ack, app_sr_active; // Sink unused UI signals
+  logic                       app_ref_ack_o, app_zq_ack_o, app_sr_active_o; // Sink unused UI signals
   logic                       init_calib_complete;
   logic [11:0]                device_temp; // Reserved
 
-  // Use a /6 clock divider until PLL is integrated. TODO: Replace
-  logic ui_clk;
-  integer clk_counter;
-  always @(posedge HCLK) begin
-    clk_counter <= clk_counter + 1;
-    if (clk_counter >= 6) clk_counter <= 0;
-    ui_clk <= (clk_counter >= 3);
-  end
-
-  // TODO: Figure out how to initialize dmc_config correctly
-  always_comb begin: bsg_dmc_config
-    dmc_config.trefi = 1023;
-    dmc_config.tmrd = 1;
-    dmc_config.trfc = 15;
-    dmc_config.trc = 10;
-    dmc_config.trp = 2;
-    dmc_config.tras = 7;
-    dmc_config.trrd = 1;
-    dmc_config.trcd = 2;
-    dmc_config.twr = 10;
-    dmc_config.twtr = 7;
-    dmc_config.trtp = 10;
-    dmc_config.tcas = 3;
-    dmc_config.col_width = 11;
-    dmc_config.row_width = 14;
-    dmc_config.bank_width = 2;
-    dmc_config.dqs_sel_cal = 3;
-    dmc_config.init_cycles = 40010;
-    dmc_config.bank_pos = 25;
-  end
-
-  ahbxuiconverter #(AHB_ADDR_SIZE, AHB_DATA_SIZE) bsg_dmc_ahb_ui_converter (
-    .HCLK, .HRESETn, .HSEL, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, .HRDATA, .HRESP, .HREADYOUT,
+  ahbxuiconverter #(
+    AHB_ADDR_SIZE,
+    AHB_DATA_SIZE,
+    BURST_LEN
+  ) bsg_dmc_ahb_ui_converter (
+    .HCLK, .HRESETn(HRESETn & ~dmc_config_changed), // Allow changes to dmc_config to reset the converter FSM and reinit bsg_dmc
+    .HSEL, .HADDR, .HWDATA, .HWSTRB, .HBURST, .HWRITE, .HTRANS, .HREADY, .HRDATA, .HRESP, .HREADYOUT,
     .sys_reset, .ui_clk, .ui_clk_sync_rst,
     .app_addr, .app_cmd, .app_en, .app_rdy,
     .app_wdf_wren, .app_wdf_data, .app_wdf_mask, .app_wdf_end, .app_wdf_rdy,
@@ -131,8 +107,8 @@ module bsg_dmc_ahb
     .num_adgs_p(1),
     .ui_addr_width_p(AHB_ADDR_SIZE),
     .ui_data_width_p(AHB_DATA_SIZE),
-    .burst_data_width_p(AHB_DATA_SIZE * BURST_LENGTH),
-    .dq_data_width_p(DDR_DATA_SIZE),
+    .burst_data_width_p(AHB_DATA_SIZE * BURST_LEN),
+    .dq_data_width_p(DQ_DATA_SIZE),
     .cmd_afifo_depth_p(FIFO_DEPTH),
     .cmd_sfifo_depth_p(FIFO_DEPTH)
   ) dmc (
@@ -143,19 +119,19 @@ module bsg_dmc_ahb
     .app_addr_i(app_addr), .app_cmd_i(app_cmd), .app_en_i(app_en), .app_rdy_o(app_rdy),
     .app_wdf_wren_i(app_wdf_wren), .app_wdf_data_i(app_wdf_data), .app_wdf_mask_i(app_wdf_mask), .app_wdf_end_i(app_wdf_end), .app_wdf_rdy_o(app_wdf_rdy),
     .app_rd_data_valid_o(app_rd_data_valid), .app_rd_data_o(app_rd_data), .app_rd_data_end_o(app_rd_data_end),
-    .app_ref_req_i(1'b0), .app_ref_ack_o(app_ref_ack),
-    .app_zq_req_i(1'b0), .app_zq_ack_o(app_zq_ack),
-    .app_sr_req_i(1'b0), .app_sr_active_o(app_sr_active),
+    .app_ref_req_i(1'b0), .app_ref_ack_o,
+    .app_zq_req_i(1'b0), .app_zq_ack_o,
+    .app_sr_req_i(1'b0), .app_sr_active_o,
     .init_calib_complete_o(init_calib_complete),
-    .ddr_ck_p_o(ddr_ck_p), .ddr_ck_n_o(ddr_ck_n), .ddr_cke_o(ddr_cke),
-    .ddr_ba_o(ddr_ba), .ddr_addr_o(ddr_addr), .ddr_cs_n_o(ddr_cs), .ddr_ras_n_o(ddr_ras), .ddr_cas_n_o(ddr_cas),
-    .ddr_we_n_o(ddr_we), .ddr_reset_n_o(ddr_reset), .ddr_odt_o(ddr_odt),
-    .ddr_dm_oen_o(ddr_dm_oen), .ddr_dm_o(ddr_dm),
-    .ddr_dqs_p_oen_o(ddr_dqs_p_oen), .ddr_dqs_p_ien_o(ddr_dqs_p_ien), .ddr_dqs_p_o(ddr_dqs_p_out), .ddr_dqs_p_i(ddr_dqs_p_in),
-    .ddr_dqs_n_oen_o(ddr_dqs_n_oen), .ddr_dqs_n_ien_o(ddr_dqs_n_ien), .ddr_dqs_n_o(ddr_dqs_n_out), .ddr_dqs_n_i(ddr_dqs_n_in),
-    .ddr_dq_oen_o(ddr_dq_oen), .ddr_dq_o(ddr_dq_out), .ddr_dq_i(ddr_dq_in),
+    .ddr_ck_p_o, .ddr_ck_n_o, .ddr_cke_o,
+    .ddr_ba_o, .ddr_addr_o, .ddr_cs_n_o, .ddr_ras_n_o, .ddr_cas_n_o,
+    .ddr_we_n_o, .ddr_reset_n_o, .ddr_odt_o,
+    .ddr_dm_oen_o, .ddr_dm_o,
+    .ddr_dqs_p_oen_o, .ddr_dqs_p_ien_o, .ddr_dqs_p_o, .ddr_dqs_p_i,
+    .ddr_dqs_n_oen_o, .ddr_dqs_n_ien_o, .ddr_dqs_n_o, .ddr_dqs_n_i,
+    .ddr_dq_oen_o, .ddr_dq_o, .ddr_dq_i,
     .ui_clk_i(ui_clk),
-    .dfi_clk_2x_i(dfi_clk_2x), .dfi_clk_1x_o(dfi_clk_1x),
+    .dfi_clk_2x_i, .dfi_clk_1x_o,
     .ui_clk_sync_rst_o(ui_clk_sync_rst),
     .device_temp_o(device_temp)
   );
diff --git a/soc/src/uiburstctrl.sv b/soc/src/uiburstctrl.sv
new file mode 100644
index 000000000..a39478a29
--- /dev/null
+++ b/soc/src/uiburstctrl.sv
@@ -0,0 +1,85 @@
+///////////////////////////////////////////
+// uiburstctrl.sv
+//
+// Written: infinitymdm@gmail.com 24 March 2024
+//
+// Purpose: UI burst management for AHB to UI converter
+// 
+// Documentation: 
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module uiburstctrl #(parameter BURST_LEN = 8) (
+  input  logic clk,
+  input  logic reset,
+  input  logic ui_initialized,
+  input  logic app_rdy,
+  input  logic app_wdf_rdy,
+  input  logic write,
+  input  logic op_ready,
+  output logic app_en,
+  output logic app_cmd0,
+  output logic app_wdf_wren,
+  output logic app_wdf_end,
+  output logic dequeue_op
+);
+  // State Definitions
+  // IDLE: Ready for next command (default)
+  // WBIP: Write Burst In Progress: write addr issued, waiting for write data
+  typedef enum logic {IDLE=0, WBIP} state;
+
+  logic [$clog2(BURST_LEN)-1:0] op_count;
+  logic inc_op_count;
+  logic last_op;
+  state current_state, next_state;
+  logic [4:0] inputs;
+  logic [5:0] outputs;
+
+  // Op counter - used to track # reads or writes issued
+  counter #($clog2(BURST_LEN)) op_counter (clk, reset, inc_op_count, op_count);
+  assign last_op = &op_count;
+
+  // State transition logic
+  flopr #(1) statereg (clk, reset, next_state, current_state);
+  always_comb begin
+    inputs = {ui_initialized, app_rdy, app_wdf_rdy, write, op_ready};
+    case (current_state)
+      IDLE: casez (inputs)
+              5'b0????: {next_state, outputs} = {IDLE, 6'b000000}; // Wait for init
+              5'b1???0: {next_state, outputs} = {IDLE, 6'b001000}; // Wait for commands, assuming read
+              5'b10?01: {next_state, outputs} = {IDLE, 6'b011000}; // Issue read w/o dequeuing
+              5'b11?01: {next_state, outputs} = {IDLE, 6'b111000}; // Issue read and dequeue
+              5'b10?11: {next_state, outputs} = {IDLE, 6'b010000}; // Prepare to write
+              5'b11011: {next_state, outputs} = {WBIP, 6'b010000}; // Issue write addr w/o data
+              5'b11111: {next_state, outputs} = {WBIP, 6'b110101}; // Issue write addr and data
+            endcase
+      WBIP: casez (inputs)
+              5'b0????:              {next_state, outputs} = {IDLE, 6'b000000}; // This should never happen unless reset
+              5'b1???0:              {next_state, outputs} = {WBIP, 6'b000000}; // Wait for more write data
+              5'b1??01:              {next_state, outputs} = {WBIP, 6'b000000}; // This should never happen as long as ahbburstctrl works correctly
+              5'b1?011:              {next_state, outputs} = {WBIP, 6'b000000}; // Wait until UI is ready for write data
+              5'b1?111: if (last_op) {next_state, outputs} = {IDLE, 6'b100111}; // Issue write data and end the burst
+                        else         {next_state, outputs} = {WBIP, 6'b100101}; // Issue write data
+            endcase
+    endcase
+  end
+  assign {dequeue_op, app_en, app_cmd0, app_wdf_wren, app_wdf_end, inc_op_count} = outputs;
+
+endmodule
diff --git a/src/cache/cache.sv b/src/cache/cache.sv
index 2edf867e2..44966f03c 100644
--- a/src/cache/cache.sv
+++ b/src/cache/cache.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Implements the I$ and D$. Interfaces with requests from IEU and HPTW and ahbcacheinterface
 //
-// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.10, and 7.19)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -29,7 +29,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module cache import cvw::*; #(parameter cvw_t P,
-                              parameter PA_BITS, XLEN, LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
+                              parameter PA_BITS, XLEN, LINELEN,  NUMSETS,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
   input  logic                   clk,
   input  logic                   reset,
   input  logic                   Stall,             // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
@@ -42,7 +42,7 @@ module cache import cvw::*; #(parameter cvw_t P,
   input  logic [11:0]            NextSet,           // Virtual address, but we only use the lower 12 bits.
   input  logic [PA_BITS-1:0]     PAdr,              // Physical address
   input  logic [(WORDLEN-1)/8:0] ByteMask,          // Which bytes to write (D$ only)
-  input  logic [WORDLEN-1:0]     CacheWriteData,    // Data to write to cache (D$ only)
+  input  logic [WORDLEN-1:0]     WriteData,    // Data to write to cache (D$ only)
   output logic                   CacheCommitted,    // Cache has started bus operation that shouldn't be interrupted
   output logic                   CacheStall,        // Cache stalls pipeline during multicycle operation
   output logic [WORDLEN-1:0]     ReadDataWord,      // Word read from cache (goes to CPU and bus)
@@ -63,12 +63,12 @@ module cache import cvw::*; #(parameter cvw_t P,
   // Cache parameters
   localparam                     LINEBYTELEN = LINELEN/8;            // Line length in bytes
   localparam                     OFFSETLEN = $clog2(LINEBYTELEN);    // Number of bits in offset field
-  localparam                     SETLEN = $clog2(NUMLINES);          // Number of set bits
+  localparam                     SETLEN = $clog2(NUMSETS);          // Number of set bits
   localparam                     SETTOP = SETLEN+OFFSETLEN;          // Number of set plus offset bits
   localparam                     TAGLEN = PA_BITS - SETTOP;          // Number of tag bits
   localparam                     CACHEWORDSPERLINE = LINELEN/WORDLEN;// Number of words in cache line
   localparam                     LOGCWPL = $clog2(CACHEWORDSPERLINE);// Log2 of ^
-  localparam                     FLUSHADRTHRESHOLD = NUMLINES - 1;   // Used to determine when flush is complete
+  localparam                     FLUSHADRTHRESHOLD = NUMSETS - 1;   // Used to determine when flush is complete
   localparam                     LOGLLENBYTES = $clog2(WORDLEN/8);   // Number of bits to address a word
 
 
@@ -87,14 +87,13 @@ module cache import cvw::*; #(parameter cvw_t P,
   logic                          LineDirty, HitLineDirty;
   logic [TAGLEN-1:0]             TagWay [NUMWAYS-1:0];
   logic [TAGLEN-1:0]             Tag;
-  logic [SETLEN-1:0]             FlushAdr, NextFlushAdr, FlushAdrP1;
+  logic [SETLEN-1:0]             FlushAdr;
   logic                          FlushAdrCntEn, FlushCntRst;
   logic                          FlushAdrFlag, FlushWayFlag;
   logic [NUMWAYS-1:0]            FlushWay, NextFlushWay;
   logic                          FlushWayCntEn;
   logic                          SelWriteback;
   logic                          LRUWriteEn;
-  logic                          ResetOrFlushCntRst;
   logic [LINELEN-1:0]            ReadDataLine, ReadDataLineCache;
   logic                          SelFetchBuffer;
   logic                          CacheEn;
@@ -119,16 +118,16 @@ module cache import cvw::*; #(parameter cvw_t P,
     AdrSelMuxSelTag, CacheSetTag);
 
   // Array of cache ways, along with victim, hit, dirty, and read merging logic
-  cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
+  cacheway #(P, PA_BITS, XLEN, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
     .clk, .reset, .CacheEn, .CacheSetData, .CacheSetTag, .PAdr, .LineWriteData, .LineByteMask, .SelVictim,
     .SetValid, .ClearValid, .SetDirty, .ClearDirty, .VictimWay,
     .FlushWay, .FlushCache, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitDirtyWay, .TagWay, .FlushStage, .InvalidateCache);
 
   // Select victim way for associative caches
   if(NUMWAYS > 1) begin:vict
-    cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU(
-      .clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetData, .CacheSetTag, .LRUWriteEn,
-      .SetValid, .ClearValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache);
+    cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMSETS) cacheLRU(
+      .clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetTag, .LRUWriteEn,
+      .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache);
   end else 
     assign VictimWay = 1'b1; // one hot.
 
@@ -184,7 +183,7 @@ module cache import cvw::*; #(parameter cvw_t P,
 
     // Merge write data into fetched cache line for store miss
     for(index = 0; index < LINELEN/8; index++) begin
-      mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
+      mux2 #(8) WriteDataMux(.d0(WriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
         .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index] & ~CMOpM[3]), .y(LineWriteData[8*index+7:8*index]));
     end
     assign LineByteMask = SetDirty ? DemuxedByteMask : '1;
@@ -201,6 +200,9 @@ module cache import cvw::*; #(parameter cvw_t P,
   /////////////////////////////////////////////////////////////////////////////////////////////
 
   if (!READ_ONLY_CACHE) begin:flushlogic // D$ can be flushed
+    logic                          ResetOrFlushCntRst;
+    logic [SETLEN-1:0]             NextFlushAdr, FlushAdrP1;
+
     // Flush address (line number)
     assign ResetOrFlushCntRst = reset | FlushCntRst;
     flopenr #(SETLEN) FlushAdrReg(clk, ResetOrFlushCntRst, FlushAdrCntEn, FlushAdrP1, NextFlushAdr);
@@ -215,9 +217,10 @@ module cache import cvw::*; #(parameter cvw_t P,
     assign FlushWayFlag = FlushWay[NUMWAYS-1];
   end // block: flushlogic
   else begin:flushlogic // I$ is never flushed because it is never dirty
-    assign FlushWay = 0;
-    assign FlushWayFlag = 0;
-    assign FlushAdrFlag = 0;
+    assign FlushWay = '0;
+    assign FlushWayFlag = 1'b0;
+    assign FlushAdrFlag = 1'b0;
+    assign FlushAdr = '0;
   end
    
   /////////////////////////////////////////////////////////////////////////////////////////////
diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv
index 0af178c94..79b277a03 100644
--- a/src/cache/cacheLRU.sv
+++ b/src/cache/cacheLRU.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Implements Pseudo LRU. Tested for Powers of 2.
 //
-// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.15 to 7.18)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -29,32 +29,30 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module cacheLRU
-  #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128) (
+  #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMSETS = 128) (
   input  logic                clk, 
   input  logic                reset,
   input  logic                FlushStage,
   input  logic                CacheEn,         // Enable the cache memory arrays.  Disable hold read data constant
   input  logic [NUMWAYS-1:0]  HitWay,          // Which way is valid and matches PAdr's tag
   input  logic [NUMWAYS-1:0]  ValidWay,        // Which ways for a particular set are valid, ignores tag
-  input  logic [SETLEN-1:0]   CacheSetData,    // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
   input  logic [SETLEN-1:0]   CacheSetTag,     // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
   input  logic [SETLEN-1:0]   PAdr,            // Physical address 
   input  logic                LRUWriteEn,      // Update the LRU state
   input  logic                SetValid,        // Set the dirty bit in the selected way and set
-  input  logic                ClearValid,      // Clear the dirty bit in the selected way and set
   input  logic                InvalidateCache, // Clear all valid bits
   output logic [NUMWAYS-1:0]  VictimWay        // LRU selects a victim to evict
 );
 
   localparam                           LOGNUMWAYS = $clog2(NUMWAYS);
 
-  logic [NUMWAYS-2:0]                  LRUMemory [NUMLINES-1:0];
-  logic [NUMWAYS-2:0]                  CurrLRU;
-  logic [NUMWAYS-2:0]                  NextLRU;
+  logic [NUMWAYS-2:0]                  LRUMemory [NUMSETS-1:0];
+  logic [NUMWAYS-2:0]                  CurrLRU, NextLRU, ReadLRU, BypassedLRU;
   logic [LOGNUMWAYS-1:0]               HitWayEncoded, Way;
   logic [NUMWAYS-2:0]                  WayExpanded;
   logic                                AllValid;
-  
+  logic                                ForwardLRU;
+ 
   genvar                               row;
 
   /* verilator lint_off UNOPTFLAT */
@@ -132,29 +130,22 @@ module cacheLRU
     assign Intermediate[node] = CurrLRU[node] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0];
   end
 
-  
   priorityonehot #(NUMWAYS) FirstZeroEncoder(~ValidWay, FirstZero);
   binencoder #(NUMWAYS) FirstZeroWayEncoder(FirstZero, FirstZeroWay);
   mux2 #(LOGNUMWAYS) VictimMux(FirstZeroWay, Intermediate[NUMWAYS-2], AllValid, VictimWayEnc);
   decoder #(LOGNUMWAYS) decoder (VictimWayEnc, VictimWay);
 
-  // LRU storage must be reset for modelsim to run. However the reset value does not actually matter in practice.
-  // This is a two port memory.
-  // Every cycle must read from CacheSetData and each load/store must write the new LRU.
-
-  // note: Verilator lint doesn't like <= for array initialization (https://verilator.org/warn/BLKLOOPINIT?v=5.021)
-  // Move to = to keep Verilator happy and simulator running fast
-  always_ff @(posedge clk) begin
+  // LRU memory must be reset for Questa to run. The reset value does not matter but it is best to be deterministc.
+  always_ff @(posedge clk)
     if (reset | (InvalidateCache & ~FlushStage)) 
-      for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = 0; // exclusion-tag: initialize
-    else if(CacheEn) begin
-      // Because we are using blocking assignments, change to LRUMemory must occur after LRUMemory is used so we get the proper value
-      if(LRUWriteEn & (PAdr == CacheSetTag)) CurrLRU = NextLRU;
-      else                                   CurrLRU = LRUMemory[CacheSetTag];
-      if(LRUWriteEn)                         LRUMemory[PAdr] = NextLRU;
-    end
-  end
-
+      for (int set = 0; set < NUMSETS; set++) LRUMemory[set] <= '0; // exclusion-tag: initialize
+    else if (CacheEn & LRUWriteEn) LRUMemory[PAdr] <= NextLRU;
+
+  // LRU read path with write forwarding
+  assign ReadLRU = LRUMemory[CacheSetTag];
+  assign ForwardLRU = LRUWriteEn & (PAdr == CacheSetTag);
+  mux2 #(NUMWAYS-1) ReadLRUmux(ReadLRU, NextLRU, ForwardLRU, BypassedLRU);
+  flop #(NUMWAYS-1) CurrLRUReg(clk, BypassedLRU, CurrLRU);
 endmodule
 
 
diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index b3dc17024..64084f863 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Controller for the cache fsm
 //
-// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -102,7 +102,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
 
   // outputs for the performance counters.
   assign CacheAccess = (|CacheRW) & ((CurrState == STATE_ACCESS & ~Stall & ~FlushStage) | (CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
-  assign CacheMiss = CacheAccess & ~Hit;
+  assign CacheMiss = CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage;
 
   // special case on reset. When the fsm first exists reset twayhe
   // PCNextF will no longer be pointing to the correct address.
diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv
index 8f647fff2..fb9d39f41 100644
--- a/src/cache/cacheway.sv
+++ b/src/cache/cacheway.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -29,14 +29,14 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module cacheway import cvw::*; #(parameter cvw_t P, 
-                  parameter PA_BITS, XLEN, NUMLINES=512, LINELEN = 256, TAGLEN = 26,
+                  parameter PA_BITS, XLEN, NUMSETS=512, LINELEN = 256, TAGLEN = 26,
                   OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) (
   input  logic                        clk,
   input  logic                        reset,
   input  logic                        FlushStage,     // Pipeline flush of second stage (prevent writes and bus operations)
   input  logic                        CacheEn,        // Enable the cache memory arrays.  Disable hold read data constant
-  input  logic [$clog2(NUMLINES)-1:0] CacheSetData,       // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
-  input  logic [$clog2(NUMLINES)-1:0] CacheSetTag,       // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
+  input  logic [$clog2(NUMSETS)-1:0]  CacheSetData,       // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
+  input  logic [$clog2(NUMSETS)-1:0]  CacheSetTag,       // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
   input  logic [PA_BITS-1:0]          PAdr,           // Physical address 
   input  logic [LINELEN-1:0]          LineWriteData,  // Final data written to cache (D$ only)
   input  logic                        SetValid,       // Set the valid bit in the selected way and set
@@ -63,8 +63,8 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   localparam                          LOGXLENBYTES = $clog2(XLEN/8);
   localparam                          BYTESPERWORD = XLEN/8;
 
-  logic [NUMLINES-1:0]                ValidBits;
-  logic [NUMLINES-1:0]                DirtyBits;
+  logic [NUMSETS-1:0]                ValidBits;
+  logic [NUMSETS-1:0]                DirtyBits;
   logic [LINELEN-1:0]                 ReadDataLine;
   logic [TAGLEN-1:0]                  ReadTag;
   logic                               Dirty;
@@ -76,7 +76,6 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   logic                               ClearValidWay;
   logic                               SetDirtyWay;
   logic                               ClearDirtyWay;
-  logic                               SelNonHit;
   logic                               SelectedWay;
   logic                               InvalidateCacheDelay;
   
@@ -112,7 +111,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   // Tag Array
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn),
+  ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMSETS), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn),
     .addr(CacheSetTag), .dout(ReadTag),
     .din(PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
 
@@ -135,33 +134,33 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   localparam           LOGNUMSRAM = $clog2(NUMSRAM);
   
   for(words = 0; words < NUMSRAM; words++) begin: word
-    if (!READ_ONLY_CACHE) begin:wordram
-      ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
+    if (READ_ONLY_CACHE) begin:wordram // no byte-enable needed for i$.
+      ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMSETS), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
       .dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
       .din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
-      .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
-    end else begin:wordram // no byte-enable needed for i$.
-      ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
+      .we(SelectedWriteWordEn));
+    end else begin:wordram // D$ needs byte enables
+     ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMSETS), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
       .dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
       .din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
-      .we(SelectedWriteWordEn));
-    end
+      .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
+     end
   end
 
   // AND portion of distributed read multiplexers
-  assign ReadDataLineWay = SelectedWay ? ReadDataLine : 0;  // AND part of AO mux.
+  assign ReadDataLineWay = SelectedWay ? ReadDataLine : '0;  // AND part of AO mux.
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Valid Bits
   /////////////////////////////////////////////////////////////////////////////////////////////
   
   always_ff @(posedge clk) begin // Valid bit array, 
-    if (reset) ValidBits        <= 0;
+    if (reset) ValidBits        <= '0;
     if(CacheEn) begin 
       ValidWay <= ValidBits[CacheSetTag];
-      if(InvalidateCache)                    ValidBits <= 0; // exclusion-tag: dcache invalidateway
+      if(InvalidateCache)                    ValidBits <= '0; // exclusion-tag: dcache invalidateway
       else if (SetValidEN) ValidBits[CacheSetData] <= SetValidWay;
-      else if (ClearValidEN) ValidBits[CacheSetData] <= 0; // exclusion-tag: icache ClearValidBits
+      else if (ClearValidEN) ValidBits[CacheSetData] <= '0; // exclusion-tag: icache ClearValidBits
     end
   end
 
@@ -173,7 +172,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   if (!READ_ONLY_CACHE) begin:dirty
     always_ff @(posedge clk) begin
       // reset is optional.  Consider merging with TAG array in the future.
-      //if (reset) DirtyBits <= {NUMLINES{1'b0}}; 
+      //if (reset) DirtyBits <= {NUMSETS{1'b0}}; 
       if(CacheEn) begin
         Dirty <= DirtyBits[CacheSetTag];
         if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CacheSetData] <= SetDirtyWay; // exclusion-tag: cache UpdateDirty
diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv
index 95920ec7e..3e9718c27 100644
--- a/src/cache/subcachelineread.sv
+++ b/src/cache/subcachelineread.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Muxes the cache line down to the word size.  Also include possible save/restore registers/muxes.
 //
-// Documentation: RISC-V System on Chip Design Chapter 7
+// Documentation: RISC-V System on Chip Design
 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/cvw.sv b/src/cvw.sv
index 21b55c55e..922bcfaa8 100644
--- a/src/cvw.sv
+++ b/src/cvw.sv
@@ -37,12 +37,12 @@ package cvw;
   `include "BranchPredictorType.vh"
 
 typedef struct packed {
-  int           XLEN;     // Machine width (32 or 64)
-  logic         IEEE754;  // IEEE754 NaN handling (0 = use RISC-V NaN propagation instead)
-  int           MISA;     // Machine Instruction Set Architecture
-  int           AHBW;     // AHB bus width (usually = XLEN)
-  int           RAM_LATENCY; // Latency to stress AHB 
-  logic         BURST_EN; // Support AHB Burst Mode
+  int           XLEN;                // Machine width (32 or 64)
+  logic         IEEE754;             // IEEE754 NaN handling (0 = use RISC-V NaN propagation instead)
+  int           MISA;                // Machine Instruction Set Architecture
+  int           AHBW;                // AHB bus width (usually = XLEN)
+  int           RAM_LATENCY;         // Latency to stress AHB 
+  logic         BURST_EN;            // Support AHB Burst Mode
 
   // RISC-V Features
   logic         ZICSR_SUPPORTED;
@@ -66,18 +66,20 @@ typedef struct packed {
   logic         SVPBMT_SUPPORTED;
   logic         SVNAPOT_SUPPORTED;
   logic         SVINVAL_SUPPORTED;
+  logic         ZAAMO_SUPPORTED;
+  logic         ZALRSC_SUPPORTED;
 
   // Microarchitectural Features
   logic         BUS_SUPPORTED;
   logic         DCACHE_SUPPORTED;
   logic         ICACHE_SUPPORTED;
 
-// TLB configuration.  Entries should be a power of 2
+  // TLB configuration.  Entries should be a power of 2
   int           ITLB_ENTRIES;
   int           DTLB_ENTRIES;
 
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 ints per way, 256 bit or more lines
+  // Cache configuration.  Sizes should be a power of two
+  // typical configuration 4 ways, 4096 ints per way, 256 bit or more lines
   int           DCACHE_NUMWAYS;
   int           DCACHE_WAYSIZEINBYTES;
   int           DCACHE_LINELENINBITS;
@@ -86,23 +88,23 @@ typedef struct packed {
   int           ICACHE_LINELENINBITS;
   int           CACHE_SRAMLEN;
 
-// Integer Divider Configuration
-// IDIV_BITSPERCYCLE must be 1, 2, or 4
+  // Integer Divider Configuration
+  // IDIV_BITSPERCYCLE must be 1, 2, or 4
   int           IDIV_BITSPERCYCLE;
   logic         IDIV_ON_FPU;
 
-// Legal number of PMP entries are 0, 16, or 64
+  // Legal number of PMP entries are 0, 16, or 64
   int           PMP_ENTRIES;
 
-// Address space
+  // Address space
   logic [63:0]  RESET_VECTOR;
 
-// WFI Timeout Wait
+  // WFI Timeout Wait
   int           WFI_TIMEOUT_BIT;
 
-// Peripheral Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+  // Peripheral Addresses
+  // Peripheral memory space extends from BASE to BASE+RANGE
+  // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
   logic         DTIM_SUPPORTED;
   logic [63:0]  DTIM_BASE;
   logic [63:0]  DTIM_RANGE;
@@ -138,17 +140,26 @@ typedef struct packed {
   logic         SPI_SUPPORTED;
   logic [63:0]  SPI_BASE;
   logic [63:0]  SPI_RANGE;
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
+  logic         PLL_SUPPORTED;
+  logic [63:0]  PLL_CONF_BASE;
+  logic [63:0]  PLL_CONF_RANGE;
+  logic         BSG_DMC_SUPPORTED;
+  logic [63:0]  BSG_DMC_CONF_BASE;
+  logic [63:0]  BSG_DMC_CONF_RANGE;
+  // Debug program buffer support is enabled with DEBUG_SUPPORTED
+  logic [63:0]  PROGBUF_BASE;
+  logic [63:0]  PROGBUF_RANGE;
+
+  // Test modes
+
+  // Tie GPIO outputs back to inputs
   logic         GPIO_LOOPBACK_TEST;
   logic         SPI_LOOPBACK_TEST;
-
-// Hardware configuration
+  
+  // Hardware configuration
   int           UART_PRESCALE ;
 
-// Interrupt configuration
+  // Interrupt configuration
   int           PLIC_NUM_SRC;
   logic         PLIC_NUM_SRC_LT_32;
   int           PLIC_GPIO_ID;
@@ -156,144 +167,145 @@ typedef struct packed {
   int           PLIC_SPI_ID;
   int           PLIC_SDC_ID;
 
-  logic                BPRED_SUPPORTED;
-  logic [31:0]         BPRED_TYPE;
-  int                  BPRED_NUM_LHR;
-  int                  BPRED_SIZE;
-  int                  BTB_SIZE;
-  int                  RAS_SIZE;
-  logic                INSTR_CLASS_PRED; // is class predictor enabled
+  logic         BPRED_SUPPORTED;
+  logic [31:0]  BPRED_TYPE;
+  int           BPRED_NUM_LHR;
+  int           BPRED_SIZE;
+  int           BTB_SIZE;
+  int           RAS_SIZE;
+  logic         INSTR_CLASS_PRED;    // is class predictor enabled
 
-// FPU division architecture
+  // FPU division architecture
   int           RADIX;
   int           DIVCOPIES;
 
-// bit manipulation
+  // bit manipulation
   logic         ZBA_SUPPORTED;
   logic         ZBB_SUPPORTED;
   logic         ZBC_SUPPORTED;
   logic         ZBS_SUPPORTED;
 
-// compressed
+  // compressed
   logic         ZCA_SUPPORTED;
   logic         ZCB_SUPPORTED;
   logic         ZCD_SUPPORTED;
   logic         ZCF_SUPPORTED;
 
-// Cryptography
+  // Cryptography
   logic         ZBKB_SUPPORTED;
   logic         ZBKC_SUPPORTED;
   logic         ZBKX_SUPPORTED;
   logic         ZKND_SUPPORTED;
   logic         ZKNE_SUPPORTED;
   logic         ZKNH_SUPPORTED;
-  logic         ZK_SUPPORTED;
+  logic         ZKN_SUPPORTED;
 
-// Memory synthesis configuration
+  // Memory synthesis configuration
   logic         USE_SRAM;
 
-// constants defining different privilege modes
-// defined in Table 1.1 of the privileged spec
-  logic [1:0] M_MODE ;
-  logic [1:0] S_MODE ;
-  logic [1:0] U_MODE ;
-
-// Virtual Memory Constants
-  int VPN_SEGMENT_BITS;
-  int VPN_BITS;
-  int PPN_BITS;
-  int PA_BITS;
-  int SVMODE_BITS;
-  int ASID_BASE;
-  int ASID_BITS;
-
-// constants to check SATP_MODE against
-// defined in Table 4.3 of the privileged spec
-  logic [3:0] NO_TRANSLATE;
-  logic [3:0] SV32; 
-  logic [3:0] SV39;
-  logic [3:0] SV48;
-
-// macros to define supported modes
-  logic A_SUPPORTED;
-  logic B_SUPPORTED;
-  logic C_SUPPORTED;
-  logic COMPRESSED_SUPPORTED;  // C or ZCA
-  logic D_SUPPORTED;
-  logic E_SUPPORTED;
-  logic F_SUPPORTED;
-  logic I_SUPPORTED;
-  logic K_SUPPORTED;
-  logic M_SUPPORTED;
-  logic Q_SUPPORTED;
-  logic S_SUPPORTED;
-  logic U_SUPPORTED;
+  // constants defining different privilege modes
+  // defined in Table 1.1 of the privileged spec
+  logic [1:0]   M_MODE ;
+  logic [1:0]   S_MODE ;
+  logic [1:0]   U_MODE ;
+
+  // Virtual Memory Constants
+  int           VPN_SEGMENT_BITS;
+  int           VPN_BITS;
+  int           PPN_BITS;
+  int           PA_BITS;
+  int           SVMODE_BITS;
+  int           ASID_BASE;
+  int           ASID_BITS;
+
+  // constants to check SATP_MODE against
+  // defined in Table 4.3 of the privileged spec
+  logic [3:0]   NO_TRANSLATE;
+  logic [3:0]   SV32; 
+  logic [3:0]   SV39;
+  logic [3:0]   SV48;
+
+  // macros to define supported modes
+  logic         A_SUPPORTED;
+  logic         B_SUPPORTED;
+  logic         C_SUPPORTED;
+  logic         D_SUPPORTED;
+  logic         E_SUPPORTED;
+  logic         F_SUPPORTED;
+  logic         I_SUPPORTED;
+  logic         M_SUPPORTED;
+  logic         Q_SUPPORTED;
+  logic         S_SUPPORTED;
+  logic         U_SUPPORTED;
   
-// logarithm of XLEN, used for number of index bits to select
-  int LOG_XLEN;
-
-// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
-  int PMPCFG_ENTRIES;
-
-// Floating point constants for Quad, Double, Single, and Half precisions
-  int         Q_LEN;
-  int         Q_NE;
-  int         Q_NF;
-  int         Q_BIAS;
-  logic [1:0] Q_FMT;
-  int         D_LEN;
-  int         D_NE;
-  int         D_NF;
-  int         D_BIAS;
-  logic [1:0] D_FMT;
-  int         S_LEN;
-  int         S_NE;
-  int         S_NF;
-  int         S_BIAS;
-  logic [1:0] S_FMT;
-  int         H_LEN;
-  int         H_NE;
-  int         H_NF;
-  int         H_BIAS;
-  logic [1:0] H_FMT;
-
-// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
-  int FLEN;
-  int         NE  ;
-  int         NF  ;
-  logic [1:0] FMT ;
-  int         BIAS;
-
-// Floating point constants needed for FPU paramerterization
-  int         FPSIZES;
-  int         FMTBITS;
-  int         LEN1 ;
-  int         NE1  ;
-  int         NF1  ;
-  logic [1:0] FMT1 ;
-  int         BIAS1;
-  int         LEN2 ;
-  int         NE2  ;
-  int         NF2  ;
-  logic [1:0] FMT2 ;
-  int         BIAS2;
-
-// largest length in IEU/FPU
-  int CVTLEN;
-  int LLEN;
-  int LOGCVTLEN;
-  int NORMSHIFTSZ;
-  int LOGNORMSHIFTSZ;
-  int CORRSHIFTSZ;
-
-// division constants
-  int LOGR       ;
-  int RK         ;
-  int FPDUR      ;
-  int DURLEN     ;
-  int DIVb       ;
-  int DIVBLEN    ;
-
+  // logarithm of XLEN, used for number of index bits to select
+  int           LOG_XLEN;
+
+  // Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
+  int           PMPCFG_ENTRIES;
+
+  // Floating point constants for Quad, Double, Single, and Half precisions
+  int           Q_LEN;
+  int           Q_NE;
+  int           Q_NF;
+  int           Q_BIAS;
+  logic [1:0]   Q_FMT;
+  int           D_LEN;
+  int           D_NE;
+  int           D_NF;
+  int           D_BIAS;
+  logic [1:0]   D_FMT;
+  int           S_LEN;
+  int           S_NE;
+  int           S_NF;
+  int           S_BIAS;
+  logic [1:0]   S_FMT;
+  int           H_LEN;
+  int           H_NE;
+  int           H_NF;
+  int           H_BIAS;
+  logic [1:0]   H_FMT;
+
+  // Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
+  int           FLEN;
+  int           LOGFLEN;
+  int           NE;
+  int           NF;
+  logic [1:0]   FMT;
+  int           BIAS;
+
+  // Floating point constants needed for FPU paramerterization
+  int           FPSIZES;
+  int           FMTBITS;
+  int           LEN1;
+  int           NE1;
+  int           NF1;
+  logic [1:0]   FMT1;
+  int           BIAS1;
+  int           LEN2;
+  int           NE2;
+  int           NF2;
+  logic [1:0]   FMT2;
+  int           BIAS2;
+
+  // largest length in IEU/FPU
+  int           CVTLEN;
+  int           LLEN;
+  int           LOGCVTLEN;
+  int           NORMSHIFTSZ;
+  int           LOGNORMSHIFTSZ;
+  int           FMALEN;
+
+  // division constants
+  int           LOGR;
+  int           RK;
+  int           FPDUR;
+  int           DURLEN;
+  int           DIVb;
+  int           DIVBLEN;
+
+  // Debug Module
+  logic         DEBUG_SUPPORTED;
 } cvw_t;
 
 endpackage
diff --git a/src/debug/dm.sv b/src/debug/dm.sv
new file mode 100644
index 000000000..410a47c4c
--- /dev/null
+++ b/src/debug/dm.sv
@@ -0,0 +1,526 @@
+///////////////////////////////////////////
+// dm.sv
+//
+// Written: matthew.n.otto@okstate.edu, james.stine@okstate.edu
+// Created: 15 March 2024
+//
+// Purpose: Main debug module (dm) for Debug Specification
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License Version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// TODO List:
+// Ignore wfi instructions in debug mode (overwrite with NOP?)
+// mask all interrupts/ignore all traps (except ebreak) in debug mode
+// capture CSR read/write failures as convert them to cmderr
+
+
+module dm import cvw::*; #(parameter cvw_t P) (
+  input  logic            clk, 
+  input  logic            rst,
+
+  // External JTAG signals
+  input  logic            tck,
+  input  logic            tdi,
+  input  logic            tms,
+  output logic            tdo,
+
+  // Platform reset signal
+  output logic            NdmReset,
+  // Core control signals
+  input  logic            ResumeAck,      // Signals Hart has been resumed
+  input  logic            HaveReset,      // Signals Hart has been reset
+  input  logic            DebugStall,     // Signals core is halted
+  output logic            HaltReq,        // Initiates core halt
+  output logic            ResumeReq,      // Initiates core resume
+  output logic            HaltOnReset,    // Halts core immediately on hart reset
+  output logic            AckHaveReset,   // Clears HaveReset status
+
+  // Scan Chain
+  output logic            DebugScanEn,    // puts scannable flops into scan mode
+  input  logic            DebugScanIn,    // (misc) scan chain data in
+  input  logic            GPRScanIn,      // (GPR) scan chain data in
+  input  logic            FPRScanIn,      // (FPR) scan chain data in
+  input  logic            CSRScanIn,      // (CSR) scan chain data in
+  output logic            DebugScanOut,   // scan chain data out
+  output logic            MiscSel,        // selects general scan chain
+  output logic            GPRSel,         // selects GPR scan chain
+  output logic            FPRSel,         // selects FPR scan chain
+  output logic            CSRSel,         // selects CSR scan chain
+  output logic [11:0]     RegAddr,        // address for scanable regfiles (GPR, FPR, CSR)
+  output logic            DebugCapture,   // latches values into scan register before scanning out
+  output logic            DebugRegUpdate, // writes values from scan register after scanning in			
+  
+  // Program Buffer
+  output logic [P.XLEN-1:0] ProgBufAddr,
+  output logic            ProgBuffScanEn,
+  output logic            ExecProgBuf
+);
+  `include "debug.vh"
+
+  localparam PROGBUF_SIZE = (P.PROGBUF_RANGE+1)/4;
+  localparam DATA_COUNT = (P.LLEN/32);
+  localparam AARSIZE_ENC = $clog2(P.LLEN/8);
+
+  // DMI Signals
+  logic                       ReqReady;
+  logic                       ReqValid;
+  logic [`DMI_ADDR_WIDTH-1:0] ReqAddress;
+  logic [31:0]                ReqData;
+  logic [1:0]                 ReqOP;
+  logic                       RspReady;
+  logic                       RspValid;
+  logic [31:0]                RspData;
+  logic [1:0]                 RspOP;
+  logic [P.XLEN-`DMI_ADDR_WIDTH-1:0] UpperReqAddr;
+
+  // JTAG ID for Wally:  
+  // Version [31:28] = 0x1 : 0001
+  // PartNumber [27:12] = 0x2A : Wally (00000000_00101010)
+  // JEDEC number [11:1] = 0x602 : Bank 13 (1100) Open HW Group (0000010) 
+  // [0] = 1
+  localparam JTAG_DEVICE_ID = 32'h1002AC05; 
+
+  dtm #(`DMI_ADDR_WIDTH, JTAG_DEVICE_ID) dtm (.clk, .rst, .tck, .tdi, .tms, .tdo,
+    .ReqReady, .ReqValid, .ReqAddress, .ReqData, .ReqOP, .RspReady,
+    .RspValid, .RspData, .RspOP);
+
+  enum logic [3:0] {INACTIVE, IDLE, ACK, R_DATA, W_DATA, DMSTATUS, W_DMCONTROL, R_DMCONTROL, 
+		    W_ABSTRACTCS, R_ABSTRACTCS, ABST_COMMAND, R_SYSBUSCS, W_PROGBUF, READ_ZERO,
+		    INVALID, EXEC_PROGBUF} State;
+
+  enum logic [2:0] {AC_IDLE, AC_UPDATE, AC_SCAN, AC_CAPTURE, PROGBUFF_WRITE} AcState, NewAcState;
+
+  // AbsCmd internal state
+  logic              AcWrite;        // Abstract Command write state
+  logic [P.LLEN:0]   ScanReg;        // The part of the debug scan chain located within DM
+  logic [P.LLEN-1:0] ScanNext;       // New ScanReg value
+  logic [P.LLEN-1:0] ARMask;         // Masks which bits of the ScanReg get updated
+  logic [P.LLEN-1:0] PackedDataReg;  // Combines DataX msg registers into a single LLEN wide register
+  logic [P.LLEN-1:0] MaskedScanReg;  // Masks which bits of the ScanReg get written to DataX
+  logic [9:0]        ShiftCount;     // Position of the selected register on the debug scan chain
+  logic [9:0]        ScanChainLen;   // Total length of currently selected scan chain
+  logic [9:0]        Cycle;          // DM's current position in the scan chain
+  logic              InvalidRegNo;   // Requested RegNo is invalid
+  logic              RegReadOnly;    // Current RegNo points to a readonly register
+  logic              MiscRegNo;      // Requested RegNo is on the Misc scan chain
+  logic              GPRegNo;        // Requested RegNo is a GPR
+  logic              FPRegNo;        // Requested RegNo is a FPR
+  logic              CSRegNo;        // Requested RegNo is a CSR
+  logic              StoreScanChain; // Store current value of ScanReg into DataX
+  logic              WriteMsgReg;    // Write to DataX
+  logic              WriteScanReg;   // Insert data from DataX into ScanReg
+  logic              WriteProgBuff;  // Insert data from DMI into ScanReg
+  logic [31:0]       Data0Wr;        // Muxed inputs to DataX regs
+  logic [31:0]       Data1Wr;        // Muxed inputs to DataX regs
+  logic [31:0]       Data2Wr;        // Muxed inputs to DataX regs
+  logic [31:0]       Data3Wr;        // Muxed inputs to DataX regs
+  // message registers
+  logic [31:0]       Data0;          // 0x04
+  logic [31:0]       Data1;          // 0x05
+  logic [31:0]       Data2;          // 0x06
+  logic [31:0]       Data3;          // 0x07
+
+  // debug module registers
+  logic [31:0]       DMControl;      // 0x10
+  logic [31:0]       DMStatus;       // 0x11
+  logic [31:0]       AbstractCS;     // 0x16
+  logic [31:0]       SysBusCS;       // 0x38
+
+  //// DM register fields
+  // DMControl
+  logic              AckUnavail;
+  logic              DmActive;       // This bit is used to (de)activate the DM. Toggling off-on acts as reset
+  // DMStatus
+  const logic        NdmResetPending = 0;
+  const logic        StickyUnavail = 0;
+  const logic        ImpEBreak = 0;
+  logic              AllHaveReset;
+  logic              AnyHaveReset;
+  logic              AllResumeAck;
+  logic              AnyResumeAck;
+  const logic        AllNonExistent = 0;
+  const logic        AnyNonExistent = 0;
+  const logic        AllUnavail = 0;
+  const logic        AnyUnavail = 0;
+  logic              AllRunning;
+  logic              AnyRunning;
+  logic              AllHalted;
+  logic              AnyHalted;
+  const logic        Authenticated = 1;
+  const logic        AuthBusy = 0;
+  const logic        HasResetHaltReq = 1;
+  const logic        ConfStrPtrValid = 0; // Used with SysBusAccess
+  const logic [3:0]  Version = 3;    // DM Version
+  // AbstractCS
+  const logic [4:0]  ProgBufSize = PROGBUF_SIZE[4:0];
+  logic              Busy;
+  const logic        RelaxedPriv = 1;
+  logic [2:0]        CmdErr;
+  const logic [3:0]  DataCount = DATA_COUNT[3:0];
+
+  assign UpperReqAddr = '0;
+
+  // Core control signals
+  assign AllHaveReset = HaveReset;
+  assign AnyHaveReset = HaveReset;
+  assign AnyHalted = DebugStall;
+  assign AllHalted = DebugStall;
+  assign AnyRunning = ~DebugStall;
+  assign AllRunning = ~DebugStall;
+  // I believe resumeack is used to determine when a resume is requested but never completes
+  // It's pretty worthless in this implementation (complain to the riscv debug working group)
+  assign AllResumeAck = ResumeAck;
+  assign AnyResumeAck = ResumeAck;
+  
+  assign DMControl = {2'b0, 1'b0, 2'b0, 1'b0, 10'b0, 10'b0, 4'b0, NdmReset, DmActive};
+
+  assign DMStatus = {7'b0, NdmResetPending, StickyUnavail, ImpEBreak, 2'b0, 
+    AllHaveReset, AnyHaveReset, AllResumeAck, AnyResumeAck, AllNonExistent, 
+    AnyNonExistent, AllUnavail, AnyUnavail, AllRunning, AnyRunning, AllHalted, 
+    AnyHalted, Authenticated, AuthBusy, HasResetHaltReq, ConfStrPtrValid, Version};
+
+  assign AbstractCS = {3'b0, ProgBufSize, 11'b0, Busy, RelaxedPriv, CmdErr, 4'b0, DataCount};
+
+  assign SysBusCS = 32'h20000000; // SBVersion = 1
+
+  assign RspValid = (State == ACK);
+  assign ReqReady = (State != ACK);
+
+  always_ff @(posedge clk) begin
+    if (rst) begin
+      DmActive <= 0;
+      State <= INACTIVE;
+    end else begin
+      case (State)
+        default : begin  // INACTIVE
+          // Reset Values
+          {HaltReq, ResumeReq, AckHaveReset, HaltOnReset, NdmReset} <= 0;
+          RspData <= 0;
+          CmdErr <= 0;
+          if (ReqValid) begin
+            if (ReqAddress == `DMCONTROL & ReqOP == `OP_WRITE & ReqData[`DMACTIVE]) begin
+              DmActive <= ReqData[`DMACTIVE];
+              RspOP <= `OP_SUCCESS;
+            end
+            State <= ACK; // acknowledge all Reqs even if they don't activate DM
+          end
+        end
+
+        ACK : begin
+          NewAcState <= AC_IDLE;
+          ResumeReq <= 0;
+          AckHaveReset <= 0;
+          if (~ReqValid)
+            State <= ~DmActive ? INACTIVE : IDLE;
+        end
+
+        IDLE : begin
+          if (ReqValid)
+            case ({ReqOP, ReqAddress}) inside
+              {`OP_WRITE,`DATA0}                            : State <= W_DATA;
+              {`OP_READ,`DATA0}                             : State <= R_DATA;
+              {`OP_WRITE,`DATA1}                            : State <= (P.LLEN >= 64) ? W_DATA : INVALID;
+              {`OP_READ,`DATA1}                             : State <= (P.LLEN >= 64) ? R_DATA : INVALID;
+              [{`OP_WRITE,`DATA2}:{`OP_WRITE,`DATA3}]       : State <= (P.LLEN >= 128) ? W_DATA : INVALID;
+              [{`OP_READ,`DATA2}:{`OP_READ,`DATA3}]         : State <= (P.LLEN >= 128) ? R_DATA : INVALID;
+              {`OP_WRITE,`DMCONTROL}                        : State <= W_DMCONTROL;
+              {`OP_READ,`DMCONTROL}                         : State <= R_DMCONTROL;
+              {`OP_READ,`DMSTATUS}                          : State <= DMSTATUS;
+              {`OP_WRITE,`ABSTRACTCS}                       : State <= W_ABSTRACTCS;
+              {`OP_READ,`ABSTRACTCS}                        : State <= R_ABSTRACTCS;
+              {`OP_WRITE,`COMMAND}                          : State <= ABST_COMMAND;
+              {`OP_READ,`COMMAND}                           : State <= READ_ZERO;
+              {`OP_WRITE,`SBCS}                             : State <= READ_ZERO;
+              {`OP_READ,`SBCS}                              : State <= R_SYSBUSCS;
+              [{`OP_WRITE,`PROGBUF0}:{`OP_WRITE,`PROGBUF3}] : State <= W_PROGBUF; // TODO: update decode range dynamically using PROGBUF_RANGE
+              [{`OP_READ,`PROGBUF0}:{`OP_READ,`PROGBUFF}],
+              {2'b??,`HARTINFO},
+              {2'b??,`ABSTRACTAUTO},
+              {2'b??,`NEXTDM}                               : State <= READ_ZERO;
+              default                                       : State <= INVALID;
+            endcase
+        end
+
+        R_DATA : begin
+          if (Busy)
+            CmdErr <= ~|CmdErr ? `CMDERR_BUSY : CmdErr;
+          case (ReqAddress)
+            `DATA0  : RspData <= Data0;
+            `DATA1  : RspData <= Data1;
+            `DATA2  : RspData <= Data2;
+            `DATA3  : RspData <= Data3;
+            default : RspData <= 32'b0;
+          endcase
+          RspOP <= `OP_SUCCESS;
+          State <= ACK;
+        end
+
+        W_DATA : begin
+          if (Busy)
+            CmdErr <= ~|CmdErr ? `CMDERR_BUSY : CmdErr;
+          RspOP <= `OP_SUCCESS;
+          State <= ACK;
+        end
+
+        W_DMCONTROL : begin
+          // While an abstract command is executing (busy in abstractcs is high), a debugger must not change
+          // hartsel, and must not write 1 to haltreq, resumereq, ackhavereset, setresethaltreq, or clrresethaltreq
+          if (Busy & (ReqData[`HALTREQ] | ReqData[`RESUMEREQ] | ReqData[`ACKHAVERESET] | ReqData[`SETRESETHALTREQ] | ReqData[`CLRRESETHALTREQ]))
+            CmdErr <= ~|CmdErr ? `CMDERR_BUSY : CmdErr;
+          else begin
+            HaltReq <= ReqData[`HALTREQ];
+            AckUnavail <= ReqData[`ACKUNAVAIL];
+            NdmReset <= ReqData[`NDMRESET];
+            DmActive <= ReqData[`DMACTIVE]; // Writing 0 here resets the DM
+            
+            // On any given write, a debugger may only write 1 to at most one of the following bits: resumereq,
+            //  hartreset, ackhavereset, setresethaltreq, and clrresethaltreq. The others must be written 0
+            case ({ReqData[`RESUMEREQ],ReqData[`ACKHAVERESET],ReqData[`SETRESETHALTREQ],ReqData[`CLRRESETHALTREQ]})
+              4'b0000 :; // None
+              4'b1000 : ResumeReq <= ~ReqData[`HALTREQ]; // Ignore ResumeReq if HaltReq
+              4'b0100 : AckHaveReset <= 1;
+              4'b0010 : HaltOnReset <= 1;
+              4'b0001 : HaltOnReset <= 0;
+              default : begin // Invalid (not onehot), dont write any changes
+                HaltReq <= HaltReq;
+                AckUnavail <= AckUnavail;
+                NdmReset <= NdmReset;
+                DmActive <= DmActive;
+              end
+            endcase
+          end
+        
+          RspOP <= `OP_SUCCESS;
+          State <= ACK;
+        end
+
+        R_DMCONTROL : begin
+          RspData <= DMControl;
+          RspOP <= `OP_SUCCESS;
+          State <= ACK;
+        end
+
+        DMSTATUS : begin
+          RspData <= DMStatus;
+          RspOP <= `OP_SUCCESS;
+          State <= ACK;
+        end
+
+        W_ABSTRACTCS : begin
+          if (Busy)
+            CmdErr <= ~|CmdErr ? `CMDERR_BUSY : CmdErr;
+          else
+            CmdErr <= |ReqData[`CMDERR] ? `CMDERR_NONE : CmdErr; // clear CmdErr
+          RspOP <= `OP_SUCCESS;
+          State <= ACK;
+        end
+
+        R_ABSTRACTCS : begin
+          RspData <= AbstractCS;
+          RspOP <= `OP_SUCCESS;
+          State <= ACK;
+        end
+
+        ABST_COMMAND : begin
+          RspOP <= `OP_SUCCESS;
+          State <= ACK;
+
+          if (CmdErr != `CMDERR_NONE); // If CmdErr, do nothing
+          else if (Busy)
+            CmdErr <= `CMDERR_BUSY; // If Busy, set CmdErr, do nothing
+          else if (~DebugStall)
+            CmdErr <= `CMDERR_HALTRESUME; // If not halted, set CmdErr, do nothing
+          else begin
+            case (ReqData[`CMDTYPE])
+              `ACCESS_REGISTER : begin
+                if (~ReqData[`TRANSFER])
+                  State <= ReqData[`POSTEXEC] ? EXEC_PROGBUF : ACK;  // If not transfer, exec progbuf or do nothing
+                else if (ReqData[`AARSIZE] > AARSIZE_ENC[2:0])
+                  CmdErr <= `CMDERR_BUS;                             // If AARSIZE (encoded) is greater than P.LLEN, set CmdErr, do nothing
+                else if (InvalidRegNo)
+                  CmdErr <= `CMDERR_EXCEPTION;                       // If InvalidRegNo, set CmdErr, do nothing
+                else if (ReqData[`AARWRITE] & RegReadOnly)
+                  CmdErr <= `CMDERR_NOT_SUPPORTED;                   // If writing to a read only register, set CmdErr, do nothing
+                else begin
+                  AcWrite <= ReqData[`AARWRITE];
+                  NewAcState <= ~ReqData[`AARWRITE] ? AC_CAPTURE : AC_SCAN;
+                  State <= ReqData[`POSTEXEC] ? EXEC_PROGBUF : ACK;
+                end
+              end
+              //`QUICK_ACCESS : State <= QUICK_ACCESS;
+              //`ACCESS_MEMORY : State <= ACCESS_MEMORY;
+              default : CmdErr <= `CMDERR_NOT_SUPPORTED;
+            endcase
+          end
+        end
+
+        W_PROGBUF : begin
+          if (Busy)
+            CmdErr <= ~|CmdErr ? `CMDERR_BUSY : CmdErr;
+          else begin
+            NewAcState <= PROGBUFF_WRITE;
+            ProgBufAddr <= {UpperReqAddr, ReqAddress};
+          end
+          RspOP <= `OP_SUCCESS;
+          State <= ACK;
+        end
+
+        R_SYSBUSCS : begin
+          RspData <= SysBusCS;
+          RspOP <= `OP_SUCCESS;
+          State <= ACK;
+        end
+
+        READ_ZERO : begin // Writes ignored, Read Zero
+          RspData <= 0;
+          RspOP <= `OP_SUCCESS;
+          State <= ACK;
+        end
+
+        INVALID : begin
+          RspOP <= `OP_SUCCESS;  // openocd cannot recover from `OP_FAILED;
+          State <= ACK;
+        end
+
+        EXEC_PROGBUF : begin
+          NewAcState <= AC_IDLE;
+          if (~Busy)
+            State <= ACK;
+        end
+      endcase
+    end
+  end
+
+  // Abstract command engine
+  // Due to length of the register scan chain,
+  // abstract commands execute independently of other DM operations
+  always_ff @(posedge clk) begin
+    if (rst)
+      AcState <= AC_IDLE;
+    else begin
+      case (AcState)
+        AC_IDLE : begin
+          Cycle <= 0;
+          AcState <= NewAcState;
+        end
+
+        AC_CAPTURE : begin
+          AcState <= AC_SCAN;
+        end
+
+        AC_SCAN : begin
+          if (~MiscRegNo & AcWrite & (Cycle == ScanChainLen)) // Writes to CSR/GPR/FPR are shifted in len(CSR/GPR) or len(FPR) cycles
+            AcState <= AC_UPDATE;
+          else if (~MiscRegNo & ~AcWrite & (Cycle == P.LLEN[9:0])) // Reads from CSR/GPR/FPR are shifted in len(ScanReg) cycles
+            AcState <= AC_IDLE;
+          else if (MiscRegNo & (Cycle == ScanChainLen)) // Misc scanchain must be scanned completely
+            AcState <= AC_IDLE;
+          else
+            Cycle <= Cycle + 1;
+        end
+
+        AC_UPDATE : begin
+          AcState <= AC_IDLE;
+        end
+
+        PROGBUFF_WRITE : begin
+          if (Cycle == 32)
+            AcState <= AC_IDLE;
+          else
+            Cycle <= Cycle + 1;
+        end
+
+        default:;
+      endcase
+    end
+  end
+
+  assign Busy = ~(AcState == AC_IDLE);
+  assign ExecProgBuf = (State == EXEC_PROGBUF) & ~Busy;
+
+  // Program Buffer
+  assign ProgBuffScanEn = (AcState == PROGBUFF_WRITE);
+
+  // Scan Chain
+  assign DebugScanOut = ScanReg[0];
+  assign DebugScanEn = (AcState == AC_SCAN);
+  assign DebugCapture = (AcState == AC_CAPTURE);
+  assign DebugRegUpdate = (AcState == AC_UPDATE);
+
+  assign MiscRegNo = ~(CSRegNo | GPRegNo | FPRegNo);
+  assign MiscSel = MiscRegNo & (AcState != AC_IDLE);
+  assign CSRSel = CSRegNo & (AcState != AC_IDLE);
+  assign GPRSel = GPRegNo & (AcState != AC_IDLE);
+  assign FPRSel = FPRegNo & (AcState != AC_IDLE);
+
+
+  always_comb begin
+    case ({CSRSel, GPRSel, FPRSel})
+      3'b100  : ScanReg[P.LLEN] = CSRScanIn;
+      3'b010  : ScanReg[P.LLEN] = GPRScanIn;
+      3'b001  : ScanReg[P.LLEN] = FPRScanIn;
+      default : ScanReg[P.LLEN] = DebugScanIn;
+    endcase
+  end
+  
+  if (P.LLEN == 32)
+    assign PackedDataReg = Data0;
+  else if (P.LLEN == 64)
+    assign PackedDataReg = {Data1,Data0};
+  else if (P.LLEN == 128)
+    assign PackedDataReg = {Data3,Data2,Data1,Data0};
+  
+  // Load data from DMI into scan chain
+  assign WriteProgBuff = (AcState == PROGBUFF_WRITE) & (Cycle == 0);
+  // Load data from message registers into scan chain
+  assign WriteScanReg = AcWrite & (MiscRegNo & (Cycle == ShiftCount) | ~MiscRegNo & (Cycle == 0));
+  genvar i;
+  for (i=0; i<P.LLEN; i=i+1) begin
+    // ARMask is used as write enable for subword overwrites (basic mask would overwrite neighbors in the chain)
+    if (i < 32)
+      assign ScanNext[i] = WriteProgBuff ? ReqData[i] : WriteScanReg & ARMask[i] ? PackedDataReg[i] : ScanReg[i+1];
+    else
+      assign ScanNext[i] = WriteScanReg & ARMask[i] ? PackedDataReg[i] : ScanReg[i+1];
+    flopenr #(1) scanreg (.clk, .reset(rst), .en(DebugScanEn | ProgBuffScanEn), .d(ScanNext[i]), .q(ScanReg[i]));
+  end
+  
+  // Message Registers
+  assign MaskedScanReg = ARMask & ScanReg[P.LLEN:1];
+  assign WriteMsgReg = (State == W_DATA) & ~Busy;
+  assign StoreScanChain = (AcState == AC_SCAN) & (Cycle == ShiftCount) & ~AcWrite;
+  
+  assign Data0Wr = WriteMsgReg ? ReqData : MaskedScanReg[31:0];
+  flopenr #(32) data0reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA0)), .d(Data0Wr), .q(Data0));
+  if (P.LLEN >= 64) begin
+    assign Data1Wr = WriteMsgReg ? ReqData : MaskedScanReg[63:32];
+    flopenr #(32) data1reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA1)), .d(Data1Wr), .q(Data1));
+  end else
+    assign Data1 = '0;
+  if (P.LLEN == 128) begin
+    assign Data2Wr = WriteMsgReg ? ReqData : MaskedScanReg[95:64];
+    assign Data3Wr = WriteMsgReg ? ReqData : MaskedScanReg[127:96];
+    flopenr #(32) data2reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA2)), .d(Data2Wr), .q(Data2));
+    flopenr #(32) data3reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA3)), .d(Data3Wr), .q(Data3));
+  end else
+    assign {Data3,Data2} = '0;
+
+  rad #(P) regnodecode(.AarSize(ReqData[`AARSIZE]),.Regno(ReqData[`REGNO]),.CSRegNo,.GPRegNo,.FPRegNo,.ScanChainLen,.ShiftCount,.InvalidRegNo,.RegReadOnly,.RegAddr,.ARMask);
+
+endmodule
diff --git a/src/debug/dmc.sv b/src/debug/dmc.sv
new file mode 100644
index 000000000..d94b536b4
--- /dev/null
+++ b/src/debug/dmc.sv
@@ -0,0 +1,128 @@
+///////////////////////////////////////////
+// dmc.sv
+//
+// Written: matthew.n.otto@okstate.edu 10 May 2024
+// Modified: 
+//
+// Purpose: Controls pipeline during Debug Mode
+// 
+// Documentation: RISC-V System on Chip Design 
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+
+// TODO:
+// Calculate correct cycle timing for step
+// Test progbuf
+
+module dmc (
+  input  logic       clk, reset,
+  input  logic       Step,
+  input  logic       ebreakM,      // ebreak instruction
+  input  logic       ebreakEn,     // DCSR: enter debug mode on ebreak
+  input  logic       HaltReq,      // Initiates core halt
+  input  logic       ResumeReq,    // Initiates core resume
+  input  logic       HaltOnReset,  // Halts core immediately on hart reset
+  input  logic       AckHaveReset, // Clears HaveReset status
+  input  logic       ExecProgBuf,  // Updates PC to progbuf and resumes core
+
+  output logic       DebugMode,      // Sets state in DM and controls masking of interrupts
+  output logic [2:0] DebugCause,     // Reason Hart entered debug mode
+  output logic       ResumeAck,      // Signals Hart has been resumed
+  output logic       HaveReset,      // Signals Hart has been reset
+  output logic       DebugStall,     // Stall signal goes to hazard unit
+
+  output logic       DCall,          // Store PCNextF in DPC when entering Debug Mode
+  output logic       DRet,           // Updates PCNextF with the current value of DPC
+  output logic       ForceBreakPoint // Causes artificial ebreak that puts core in debug mode
+);
+  `include "debug.vh"
+
+  enum logic [1:0] {RUNNING, EXECPROGBUF, HALTED, STEP} State;
+
+  localparam E2M_CYCLE_COUNT = 4;
+  logic [$clog2(E2M_CYCLE_COUNT+1)-1:0] Counter;
+
+  always_ff @(posedge clk) begin
+    if (reset)
+      HaveReset <= 1;
+    else if (AckHaveReset)
+      HaveReset <= 0;
+  end
+
+  assign ForceBreakPoint = (State == RUNNING) & HaltReq | (State == STEP) & ~|Counter;
+
+  assign DebugMode = (State != RUNNING);
+  assign DebugStall = (State == HALTED);
+
+  assign DCall = ((State == RUNNING) | (State == EXECPROGBUF)) & ((ebreakM & ebreakEn) | ForceBreakPoint);
+  assign DRet = (State == HALTED) & (ResumeReq | ExecProgBuf);
+
+  always_ff @(posedge clk) begin
+    if (reset) begin
+      State <= HaltOnReset ? HALTED : RUNNING;
+      DebugCause <= HaltOnReset ? `CAUSE_RESETHALTREQ : 0;
+    end else begin
+      case (State)
+        RUNNING : begin
+          if (HaltReq) begin
+            State <= HALTED;
+            DebugCause <= `CAUSE_HALTREQ;
+          end else if (ebreakM & ebreakEn) begin
+            State <= HALTED;
+            DebugCause <= `CAUSE_EBREAK;
+          end
+        end
+
+        // Similar to RUNNING, but DebugMode isn't deasserted
+        EXECPROGBUF : begin
+          if (ebreakM & ebreakEn) begin
+            State <= HALTED;
+            DebugCause <= `CAUSE_EBREAK;
+          end
+        end
+
+        HALTED : begin
+          if (ResumeReq) begin
+            if (Step) begin
+              Counter <= E2M_CYCLE_COUNT;
+              State <= STEP;
+            end else begin
+              State <= RUNNING;
+              ResumeAck <= 1;
+            end
+          end else if (ExecProgBuf) begin
+            State <= EXECPROGBUF;
+            ResumeAck <= 1;
+          end
+        end
+
+        STEP : begin
+          if (~|Counter) begin
+            DebugCause <= `CAUSE_STEP;
+            State <= HALTED;
+          end else
+            Counter <= Counter - 1;
+        end
+        default: ; // empty defualt case to make the linter happy
+      endcase
+    end
+  end
+endmodule
diff --git a/src/debug/dtm.sv b/src/debug/dtm.sv
new file mode 100644
index 000000000..2feced8b8
--- /dev/null
+++ b/src/debug/dtm.sv
@@ -0,0 +1,164 @@
+///////////////////////////////////////////
+// dtm.sv
+//
+// Written: matthew.n.otto@okstate.edu, james.stine@okstate.edu
+// Created: 15 March 2024
+//
+// Purpose: debug transport module (dtm) : allows external debugger to communicate with dm
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+//
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+// either express or implied. See the License for the specific language governing permissions
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// To recovert from a core reset, DTM will need to DtmHardReset (or trstn / tms zeroscan).
+//    This is mentioned in spec
+// To recover from DTM reset, core will probably need to be reset
+
+module dtm #(parameter ADDR_WIDTH, parameter JTAG_DEVICE_ID) (
+  // System clock
+  input  logic                  clk, rst,
+  // External JTAG signals
+  input  logic                  tck,
+  input  logic                  tdi,
+  input  logic                  tms,
+  output logic                  tdo,
+
+  // DMI signals
+  input  logic                  ReqReady,
+  output logic                  ReqValid,
+  output logic [ADDR_WIDTH-1:0] ReqAddress,
+  output logic [31:0]           ReqData,
+  output logic [1:0]            ReqOP,
+  output logic                  RspReady,
+  input  logic                  RspValid,
+  input  logic [31:0]           RspData,
+  input  logic [1:0]            RspOP
+);
+  `include "debug.vh"
+
+  enum logic [1:0] {IDLE, START, WAIT, COMPLETE} DMIState;
+
+  // Clock Domain Crossing
+  logic                     tcks; // Synchronized JTAG clock
+  logic                     resetn; // TODO: reset DM (but not hart)
+  logic                     UpdateDtmcs;
+  logic [31:0]              DtmcsIn;
+  logic [31:0]              DtmcsOut;
+  logic                     UpdateDmi;
+  logic                     CaptureDmi;
+  logic [34+ADDR_WIDTH-1:0] DmiIn;
+  logic [34+ADDR_WIDTH-1:0] DmiOut;
+
+  // DTMCS Register
+  const logic [2:0]         ErrInfo = 0;
+  logic                     DtmHardReset;
+  logic                     DmiReset;
+  const logic [2:0]         Idle = 0;
+  logic [1:0]               DmiStat;
+  const logic [5:0]         ABits = ADDR_WIDTH;
+  const logic [3:0]         Version = 1; // DTM spec version 1
+
+  logic [31:0]              ValRspData;
+  logic [1:0]               ValRspOP;
+  logic                     Sticky;
+
+  assign DmiOut = {ReqAddress, ValRspData, ValRspOP};
+  assign DmiStat = ValRspOP;
+
+  // Synchronize the edges of tck to the system clock
+  synchronizer clksync (.clk(clk), .d(tck), .q(tcks));
+
+  jtag #(.ADDR_WIDTH(ADDR_WIDTH), .DEVICE_ID(JTAG_DEVICE_ID)) jtag (.tck(tcks), .tdi, .tms, .tdo,
+    .resetn, .UpdateDtmcs, .DtmcsIn, .DtmcsOut, .CaptureDmi, .UpdateDmi, .DmiIn, .DmiOut);
+
+
+  // DTMCS
+  assign DtmcsOut = {11'b0, ErrInfo, 3'b0, Idle, DmiStat, ABits, Version};
+  always @(posedge clk) begin
+    if (rst | ~resetn | DtmHardReset) begin
+      DtmHardReset <= 0;
+      DmiReset <= 0;
+    end else if (UpdateDtmcs) begin
+      DtmHardReset <= DtmcsIn[17];
+      DmiReset <= DtmcsIn[16];
+    end else if (DmiReset) begin
+      DmiReset <= 0;
+    end
+  end
+
+  // DMI
+  always_ff @(posedge clk) begin
+    if (rst | ~resetn | DtmHardReset) begin
+      ValRspData <= 0;
+      ValRspOP <= `OP_SUCCESS;
+      //ErrInfo <= 4;
+      Sticky <= 0;
+      DMIState <= IDLE;
+    end else if (DmiReset) begin
+      ValRspOP <= `OP_SUCCESS;
+      //ErrInfo <= 4;
+      Sticky <= 0;
+    end else
+      case (DMIState)
+        IDLE : begin
+          if (UpdateDmi & ~Sticky & DmiIn[1:0] != `OP_NOP) begin
+            {ReqAddress, ReqData, ReqOP} <= DmiIn;
+            ReqValid <= 1;
+            // DmiOut is captured immediately on CaptureDmi
+            // this preemptively sets BUSY for next capture unless overwritten
+            ValRspOP <= `OP_BUSY;
+            DMIState <= START;
+          end else begin
+            ReqValid <= 0;
+            if (~Sticky)
+              ValRspOP <= `OP_SUCCESS;
+          end
+        end
+
+        START : begin
+          if (ReqReady) begin
+            ReqValid <= 0;
+            RspReady <= 1;
+            DMIState <= WAIT;
+          end
+        end
+
+        WAIT : begin
+          if (RspValid) begin
+            ValRspData <= RspData;
+            if (~Sticky) // update OP if it isn't currently a sticky value
+              ValRspOP <= RspOP;
+            if (RspOP == `OP_FAILED | RspOP == `OP_BUSY)
+              Sticky <= 1;
+            //if (RspOP == `OP_FAILED)
+            //  ErrInfo <= 3;
+            DMIState <= COMPLETE;
+          end else if (CaptureDmi)
+            Sticky <= 1;
+        end
+
+        COMPLETE : begin
+          if (CaptureDmi) begin
+            RspReady <= 0;
+            DMIState <= IDLE;
+          end
+        end
+      endcase
+  end
+
+endmodule
diff --git a/src/generic/clockgater.sv b/src/debug/idreg.sv
old mode 100644
new mode 100755
similarity index 55%
rename from src/generic/clockgater.sv
rename to src/debug/idreg.sv
index 48282ccfa..602262051
--- a/src/generic/clockgater.sv
+++ b/src/debug/idreg.sv
@@ -1,15 +1,15 @@
 ///////////////////////////////////////////
-// clockgater.sv
+// idreg.sv
 //
-// Written: Ross Thompson 9 January 2021
-// Modified: 
+// Written: matthew.n.otto@okstate.edu, james.stine@okstate.edu
+// Created: 15 March 2024
+//
+// Purpose: JTAG device identification register
 //
-// Purpose: Clock gater model. Must use standard cell for synthesis.
-// 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
 // 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
 //
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
@@ -25,26 +25,24 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module clockgater #(parameter FPGA) (
-  input  logic E,
-  input  logic SE,
-  input  logic CLK,
-  output logic ECLK
+module idreg #(parameter DEVICE_ID) (
+    input  logic tdi,
+    input  logic clockDR,
+    input  logic captureDR,
+    output logic tdo
 );
 
-  if (FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK));
-  else begin
-    // *** BUG 
-    // VERY IMPORTANT.
-    // This part functionally models a clock gater, but does not necessarily meet the timing constrains a real standard cell would.
-    // Do not use this in synthesis!
-    logic   enable_q;
-    always_latch begin
-      if(~CLK) begin
-        enable_q <= E | SE;
-      end
-    end
-    assign ECLK = enable_q & CLK;
-  end    
+    logic [32:0] ShiftReg;
+    assign ShiftReg[32] = tdi;
+    assign tdo = ShiftReg[0];
 
+    genvar i;
+    for (i = 0; i < 32; i = i + 1) begin
+        always @(posedge clockDR) begin
+            if (i > 0)
+                ShiftReg[i] <= captureDR ? DEVICE_ID[i] : ShiftReg[i+1];
+            else
+                ShiftReg[0] <= captureDR ? 1'b1 : ShiftReg[i+1];
+        end
+    end
 endmodule
diff --git a/src/debug/ir.sv b/src/debug/ir.sv
new file mode 100644
index 000000000..6c5f80b6e
--- /dev/null
+++ b/src/debug/ir.sv
@@ -0,0 +1,78 @@
+///////////////////////////////////////////
+// ir.sv
+//
+// Written: matthew.n.otto@okstate.edu, james.stine@okstate.edu
+// Created: 15 March 2024
+//
+// Purpose: JTAG instruction register
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module ir (
+  input  logic clockIR,
+  input  logic tdi,
+  input  logic resetn, 
+  input  logic captureIR,
+  input  logic updateIR,
+  output logic tdo,
+  output logic BypassInstr,
+  output logic IDCodeInstr,
+  output logic DtmcsIntrs,
+  output logic DmiInstr
+);
+
+  localparam INST_REG_WIDTH = 5;
+
+  logic [INST_REG_WIDTH:0] shift_reg;
+  logic [3:0]              decoded;
+
+
+  assign shift_reg[INST_REG_WIDTH] = tdi;
+  assign tdo = shift_reg[0];
+
+  // Shift register
+  flop #(1) shift_regmsb (.clk(clockIR), .d(shift_reg[1] | captureIR), .q(shift_reg[0]));
+  genvar i;
+  for (i = INST_REG_WIDTH; i > 1; i = i - 1)
+    flop #(1) shift_regi (.clk(clockIR), .d(shift_reg[i] & ~captureIR), .q(shift_reg[i-1]));
+
+  // Instruction decoder
+  // 6.1.2
+  always_comb begin
+    unique case (shift_reg[INST_REG_WIDTH-1:0])
+      5'h00   : decoded = 4'b1000; // bypass
+      5'h01   : decoded = 4'b0100; // idcode
+      5'h10   : decoded = 4'b0010; // dtmcs
+      5'h11   : decoded = 4'b0001; // dmi
+      5'h1F   : decoded = 4'b1000; // bypass
+      default : decoded = 4'b1000; // bypass
+    endcase
+  end
+
+  // Flop decoded instruction to minimizes switching during shiftIR
+  /* verilator lint_off SYNCASYNCNET */
+  always @(posedge updateIR or negedge resetn) begin
+    if (~resetn)
+      {BypassInstr, IDCodeInstr, DtmcsIntrs, DmiInstr} <= 4'b0100;
+    else if (updateIR)
+      {BypassInstr, IDCodeInstr, DtmcsIntrs, DmiInstr} <= decoded;
+  end
+  /* verilator lint_on SYNCASYNCNET */
+endmodule
diff --git a/src/debug/jtag.sv b/src/debug/jtag.sv
new file mode 100644
index 000000000..6ea994e17
--- /dev/null
+++ b/src/debug/jtag.sv
@@ -0,0 +1,125 @@
+///////////////////////////////////////////
+// jtag.sv
+//
+// Written: matthew.n.otto@okstate.edu, james.stine@okstate.edu
+// Created: 15 March 2024
+//
+// Purpose: JTAG portion of DTM
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+//
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+// either express or implied. See the License for the specific language governing permissions
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module jtag #(parameter ADDR_WIDTH, parameter DEVICE_ID) (
+  // JTAG signals
+  input  logic                     tck,
+  input  logic                     tdi,
+  input  logic                     tms,
+  output logic                     tdo,
+  output logic                     resetn,
+
+  // DTM signals
+  output logic                     UpdateDtmcs,
+  output logic [31:0]              DtmcsIn,
+  input  logic [31:0]              DtmcsOut,
+
+  output logic                     CaptureDmi,
+  output logic                     UpdateDmi,
+  output logic [34+ADDR_WIDTH-1:0] DmiIn,
+  input  logic [34+ADDR_WIDTH-1:0] DmiOut
+);
+
+  genvar i;
+
+  // Data signals
+  logic                            tdi_ir, tdi_dr;
+  logic                            tdo_ir, tdo_dr;
+  logic                            tdo_bypass;
+  logic                            tdo_idcode;
+  logic                            tdo_dtmcs;
+  logic                            tdo_dmi;
+
+  // TAP controller logic
+  logic                            tdo_en;
+  logic                            captureIR;
+  logic                            clockIR;
+  logic                            updateIR;
+  logic                            shiftDR;
+  logic                            captureDR;
+  logic                            clockDR;
+  logic                            updateDR;
+  logic                            select;
+
+  // Instruction signals
+  logic                            BypassInstr;
+  logic                            IDCodeInstr;
+  logic                            DtmcsIntrs;
+  logic                            DmiInstr;
+
+  logic [32:0]                     DtmcsShiftReg;
+  logic [34+ADDR_WIDTH:0]          DmiShiftReg;
+
+  assign UpdateDtmcs = updateDR & DtmcsIntrs;
+
+  assign CaptureDmi = captureDR & DmiInstr;
+  assign UpdateDmi = updateDR & DmiInstr;
+
+  tap tap (.tck, .tms, .resetn, .tdo_en, .captureIR,
+    .clockIR, .updateIR, .shiftDR, .captureDR, .clockDR, .updateDR, .select);
+
+  // IR/DR input demux
+  assign tdi_ir = select ? tdi : 1'bz;
+  assign tdi_dr = select ? 1'bz : tdi;
+  // IR/DR output mux
+  assign tdo = ~tdo_en ? 1'bz :
+         select ? tdo_ir : tdo_dr;
+
+  ir ir (.clockIR,  .tdi(tdi_ir), .resetn, .captureIR, .updateIR, .tdo(tdo_ir),
+    .BypassInstr, .IDCodeInstr, .DtmcsIntrs, .DmiInstr);
+
+  // DR demux
+  always_comb begin
+    unique case ({BypassInstr, IDCodeInstr, DtmcsIntrs, DmiInstr})
+      4'b1000 : tdo_dr = tdo_bypass;
+      4'b0100 : tdo_dr = tdo_idcode;
+      4'b0010 : tdo_dr = tdo_dtmcs;
+      4'b0001 : tdo_dr = tdo_dmi;
+      default : tdo_dr = tdo_bypass;
+    endcase
+  end
+
+  flop #(32) dtmcsreg (.clk(UpdateDtmcs), .d(DtmcsShiftReg[31:0]), .q(DtmcsIn));
+  flop #(34+ADDR_WIDTH) dmireg (.clk(UpdateDmi), .d(DmiShiftReg[34+ADDR_WIDTH-1:0]), .q(DmiIn));
+
+  assign DtmcsShiftReg[32] = tdi_dr;
+  assign tdo_dtmcs = DtmcsShiftReg[0];
+  for (i = 0; i < 32; i = i + 1)
+    flop #(1) dtmcsshiftreg (.clk(clockDR), .d(captureDR ? DtmcsOut[i] : DtmcsShiftReg[i+1]), .q(DtmcsShiftReg[i]));
+
+  assign DmiShiftReg[34+ADDR_WIDTH] = tdi_dr;
+  assign tdo_dmi = DmiShiftReg[0];
+  for (i = 0; i < 34+ADDR_WIDTH; i = i + 1)
+    flop #(1) dmishiftreg (.clk(clockDR), .d(captureDR ? DmiOut[i] : DmiShiftReg[i+1]), .q(DmiShiftReg[i]));
+
+  // jtag id register
+  idreg #(DEVICE_ID) id (.tdi(tdi_dr), .clockDR, .captureDR, .tdo(tdo_idcode));
+
+  // bypass register
+  flop #(1) bypassreg (.clk(clockDR), .d(tdi_dr & shiftDR), .q(tdo_bypass));
+
+endmodule
diff --git a/src/debug/notes.txt b/src/debug/notes.txt
new file mode 100755
index 000000000..c191927d2
--- /dev/null
+++ b/src/debug/notes.txt
@@ -0,0 +1,49 @@
+Connect JTAG adapter (SiPEED) to  FPGA (Arty-A7)
+
+Using Pmod JA (side closest to ethernet port)
+Connect 5 jumpers on the top row beginning with GND
+The order of the wires matches the order of the USB Adapter
+GND TDI TMS TDO TCK
+(see jtag_pinout.jpg)
+
+To debug Wally using OpenOCD:
+
+1. Select correct jtag adapter
+
+If using "SiPEED" adapters, openocd.cfg already contains the correct adapter ftdi
+with vid_pid 0x0403 0x6010
+
+If there are multiple ft2232 chips connected to the same system (ex: Arty-A7), 
+you will need to tell OpenOCD which one to use.
+
+On linux:
+list your USB devices usign the command: "lsusb -t"
+example output:
+/:  Bus 001.Port 001: Dev 001, Class=root_hub, Driver=xhci_hcd/10p, 480M
+    |__ Port 003: Dev 002, If 0, Class=Vendor Specific Class, Driver=usbfs, 480M
+    |__ Port 003: Dev 002, If 1, Class=Vendor Specific Class, Driver=ftdi_sio, 480M
+    |__ Port 004: Dev 004, If 0, Class=Vendor Specific Class, Driver=usbfs, 12M
+    |__ Port 004: Dev 004, If 1, Class=Vendor Specific Class, Driver=ftdi_sio, 12M   <- This is my JTAG adapter
+
+In the openOCD config, add the line: "adapter usb location 1-4"
+where the numbers 1-4 correspond to <bus_num>-<port_num>
+
+
+
+2. Run openocd 
+run openocd using the command "openocd -f openocd.cfg"
+where openocd.cfg is the path of the config file
+If everything is working corretly, OpenOCD should start without any errors and begin listening for telnet and gdb connections
+connect to openocd via telnet (telnet 127.0.0.1 4444) to send commands via the command line
+
+3. read and write to the DMI bus
+the riscv debug module can be controlled by writing to various registers via the DMI.
+We can access these registers using the two commands:
+  riscv dmi_read <address>
+  riscv dmi_write <address> <value>
+
+4. Initialize the DM
+The debug module starts in an inactive state. In this state, it will not respond to any commands
+To activate it, write 0x1 to the DMCONTROL register (0x10):
+"riscv dmi_write 0x10 0x1"
+Now you should have full control over the debug module.
diff --git a/src/debug/rad.sv b/src/debug/rad.sv
new file mode 100644
index 000000000..ecbd0bd0e
--- /dev/null
+++ b/src/debug/rad.sv
@@ -0,0 +1,188 @@
+///////////////////////////////////////////
+// rad.sv
+//
+// Written: matthew.n.otto@okstate.edu
+// Created: 28 April 2024
+//
+// Purpose: Decodes the register address and generates various control signals 
+//          required to access target register on the debug scan chain
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License Version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module rad import cvw::*; #(parameter cvw_t P) (
+  input  logic [2:0]        AarSize,
+  input  logic [15:0]       Regno,
+  output logic              GPRegNo,
+  output logic              FPRegNo,
+  output logic              CSRegNo,
+  output logic [9:0]        ScanChainLen,
+  output logic [9:0]        ShiftCount,
+  output logic              InvalidRegNo,
+  output logic              RegReadOnly,
+  output logic [11:0]       RegAddr,
+  output logic [P.LLEN-1:0] ARMask
+);
+  `include "debug.vh"
+
+  localparam TRAPMLEN = P.ZICSR_SUPPORTED ? 1 : 0;
+  localparam PCMLEN = (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED) ? P.XLEN : 0;
+  localparam INSTRMLEN = (P.ZICSR_SUPPORTED | P.A_SUPPORTED) ? 32 : 0;
+  localparam MEMRWMLEN = 2;
+  localparam INSTRVALIDMLEN = 1;
+  localparam WRITEDATAMLEN = P.XLEN;
+  localparam IEUADRMLEN = P.XLEN;
+  localparam READDATAMLEN = P.LLEN;
+  localparam SCANCHAINLEN = P.LLEN 
+    + TRAPMLEN + PCMLEN + INSTRMLEN
+    + MEMRWMLEN + INSTRVALIDMLEN + WRITEDATAMLEN
+    + IEUADRMLEN + READDATAMLEN;
+
+  localparam TRAPM_IDX = TRAPMLEN;
+  localparam PCM_IDX = TRAPM_IDX + PCMLEN;
+  localparam INSTRM_IDX = PCM_IDX + INSTRMLEN;
+  localparam MEMRWM_IDX = INSTRM_IDX + MEMRWMLEN;
+  localparam INSTRVALIDM_IDX = MEMRWM_IDX + INSTRVALIDMLEN;
+  localparam WRITEDATAM_IDX = INSTRVALIDM_IDX + WRITEDATAMLEN;
+  localparam IEUADRM_IDX = WRITEDATAM_IDX + IEUADRMLEN;
+  localparam READDATAM_IDX = IEUADRM_IDX + READDATAMLEN;
+
+  logic [P.LLEN-1:0] Mask;
+
+  assign RegAddr = Regno[11:0];
+  assign ScanChainLen = (CSRegNo | GPRegNo) ? P.XLEN[9:0] : FPRegNo ? P.FLEN[9:0] : SCANCHAINLEN[9:0];
+
+  // Register decoder
+  always_comb begin
+    InvalidRegNo = 0;
+    RegReadOnly = 0;
+    CSRegNo = 0;
+    GPRegNo = 0;
+    FPRegNo = 0;
+    case (Regno) inside
+      [`DCSR_REGNO:`DPC_REGNO] : begin
+        ShiftCount = P.LLEN[9:0] - 1;
+        CSRegNo = 1;
+      end
+
+      [`FFLAGS_REGNO:`FCSR_REGNO],
+      [`MSTATUS_REGNO:`MCOUNTEREN_REGNO], //  InvalidRegNo = ~P.ZICSR_SUPPORTED;
+      `MENVCFG_REGNO,
+      `MSTATUSH_REGNO,
+      `MENVCFGH_REGNO,
+      `MCOUNTINHIBIT_REGNO,
+      [`MSCRATCH_REGNO:`MIP_REGNO],
+      [`PMPCFG0_REGNO:`PMPADDR3F_REGNO], // TODO This is variable len (P.PA_BITS)?
+      [`TSELECT_REGNO:`TDATA3_REGNO],
+      `SIP_REGNO,
+      `MIP_REGNO,
+      `MHPMEVENTBASE_REGNO,
+      `MHPMCOUNTERBASE_REGNO,
+      `MHPMCOUNTERHBASE_REGNO,
+      [`HPMCOUNTERBASE_REGNO:`TIME_REGNO],
+      [`HPMCOUNTERHBASE_REGNO:`TIMEH_REGNO],
+      `SSTATUS_REGNO,
+      [`SIE_REGNO:`SCOUNTEREN_REGNO],
+      `SENVCFG_REGNO,
+      [`SSCRATCH_REGNO:`SIP_REGNO],
+      `STIMECMP_REGNO,
+      `STIMECMPH_REGNO,
+      `SATP_REGNO,
+      `SIE_REGNO,
+      `SIP_REGNO,
+      `MIE_REGNO,
+      `MIP_REGNO : begin
+        ShiftCount = P.LLEN[9:0] - 1'b1;
+        CSRegNo = 1;
+	// Comment out because gives error on openocd
+	// This value cause the csrs to all go read-only
+	// which openocd doesnt like
+        //RegReadOnly = 1;
+      end
+
+      [`HPMCOUNTERBASE_REGNO:`TIME_REGNO],
+      [`HPMCOUNTERHBASE_REGNO:`TIMEH_REGNO],
+      [`MVENDORID_REGNO:`MCONFIGPTR_REGNO] : begin
+        ShiftCount = P.LLEN[9:0] - 1;
+        CSRegNo = 1;
+        RegReadOnly = 1;
+      end
+
+      [`X0_REGNO:`X15_REGNO] : begin
+        ShiftCount = P.LLEN[9:0] - 1;
+        GPRegNo = 1;
+      end
+      [`X16_REGNO:`X31_REGNO] : begin
+        ShiftCount = P.LLEN[9:0] - 1;
+        InvalidRegNo = P.E_SUPPORTED;
+        GPRegNo = 1;
+      end
+      [`FP0_REGNO:`FP31_REGNO] : begin
+        ShiftCount = P.LLEN[9:0] - 1;
+        InvalidRegNo = ~(P.F_SUPPORTED | P.D_SUPPORTED | P.Q_SUPPORTED);
+        FPRegNo = 1;
+      end
+      `TRAPM_REGNO : begin
+        ShiftCount = SCANCHAINLEN[9:0] - TRAPM_IDX[9:0];
+        InvalidRegNo = ~P.ZICSR_SUPPORTED;
+        RegReadOnly = 1;
+      end
+      `PCM_REGNO : begin
+        ShiftCount = SCANCHAINLEN[9:0] - PCM_IDX[9:0];
+        InvalidRegNo = ~(P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED);
+      end
+      `INSTRM_REGNO : begin
+        ShiftCount = SCANCHAINLEN[9:0] - INSTRM_IDX[9:0];
+        InvalidRegNo = ~(P.ZICSR_SUPPORTED | P.A_SUPPORTED);
+      end
+      `MEMRWM_REGNO      : ShiftCount = SCANCHAINLEN[9:0] - MEMRWM_IDX[9:0];
+      `INSTRVALIDM_REGNO : ShiftCount = SCANCHAINLEN[9:0] - INSTRVALIDM_IDX[9:0];
+      `WRITEDATAM_REGNO  : ShiftCount = SCANCHAINLEN[9:0] - WRITEDATAM_IDX[9:0];
+      `IEUADRM_REGNO     : ShiftCount = SCANCHAINLEN[9:0] - IEUADRM_IDX[9:0];
+      `READDATAM_REGNO : begin
+        ShiftCount = SCANCHAINLEN[9:0] - READDATAM_IDX[9:0];
+        RegReadOnly = 1;
+      end
+      default : begin
+        ShiftCount = 0;
+        InvalidRegNo = 1;
+      end
+    endcase
+  end
+
+  // Mask calculator
+  always_comb begin
+    case (Regno) inside
+      `TRAPM_REGNO             : Mask = {{P.LLEN-1{1'b0}}, 1'b1};
+      `INSTRM_REGNO            : Mask = {{P.LLEN-32{1'b0}}, {32{1'b1}}};
+      `MEMRWM_REGNO            : Mask = {{P.LLEN-2{1'b0}}, 2'b11};
+      `INSTRVALIDM_REGNO       : Mask = {{P.LLEN-1{1'b0}}, 1'b1};
+      `READDATAM_REGNO         : Mask = {P.LLEN{1'b1}};
+      [`FP0_REGNO:`FP31_REGNO] : Mask = {{P.LLEN-P.FLEN{1'b0}}, {P.FLEN{1'b1}}};
+      default                  : Mask = {{P.LLEN-P.XLEN{1'b0}}, {P.XLEN{1'b1}}};
+    endcase
+  end
+
+  assign ARMask[31:0] = Mask[31:0];
+  if (P.LLEN >= 64)
+    assign ARMask[63:32] = (AarSize == 3'b011 | AarSize == 3'b100) ? Mask[63:32] : '0;
+  if (P.LLEN == 128)
+    assign ARMask[127:64] = (AarSize == 3'b100) ? Mask[127:64] : '0;
+
+endmodule
diff --git a/src/debug/tap.sv b/src/debug/tap.sv
new file mode 100644
index 000000000..9514b1056
--- /dev/null
+++ b/src/debug/tap.sv
@@ -0,0 +1,99 @@
+///////////////////////////////////////////
+// tap.sv
+//
+// Written: matthew.n.otto@okstate.edu, james.stine@okstate.edu
+// Created: 15 March 2024
+//
+// Purpose: JTAG tap controller
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module tap (
+  input  logic tck,
+  input  logic tms,
+  output logic resetn,
+  output logic tdo_en,
+  output logic captureIR,
+  output logic clockIR,
+  output logic updateIR,
+  output logic shiftDR,
+  output logic captureDR,
+  output logic clockDR,
+  output logic updateDR,
+  output logic select
+);
+
+  logic tckn;
+
+  enum logic [3:0] {
+    Exit2DR     = 4'h0,
+    Exit1DR     = 4'h1,
+    ShiftDR     = 4'h2,
+    PauseDR     = 4'h3,
+    SelectIR    = 4'h4,
+    UpdateDR    = 4'h5,
+    CaptureDR   = 4'h6,
+    SelectDR    = 4'h7,
+    Exit2IR     = 4'h8,
+    Exit1IR     = 4'h9,
+    ShiftIR     = 4'hA,
+    PauseIR     = 4'hB,
+    RunTestIdle = 4'hC,
+    UpdateIR    = 4'hD,
+    CaptureIR   = 4'hE,
+    TLReset     = 4'hF
+  } State;
+
+  always @(posedge tck) begin
+    case (State)
+      TLReset     : State <= tms ? TLReset : RunTestIdle;
+      RunTestIdle : State <= tms ? SelectDR : RunTestIdle;
+      SelectDR    : State <= tms ? SelectIR : CaptureDR;
+      CaptureDR   : State <= tms ? Exit1DR : ShiftDR;
+      ShiftDR     : State <= tms ? Exit1DR : ShiftDR;
+      Exit1DR     : State <= tms ? UpdateDR : PauseDR;
+      PauseDR     : State <= tms ? Exit2DR : PauseDR;
+      Exit2DR     : State <= tms ? UpdateDR : ShiftDR;
+      UpdateDR    : State <= tms ? SelectDR : RunTestIdle;
+      SelectIR    : State <= tms ? TLReset : CaptureIR;
+      CaptureIR   : State <= tms ? Exit1IR : ShiftIR;
+      ShiftIR     : State <= tms ? Exit1IR : ShiftIR;
+      Exit1IR     : State <= tms ? UpdateIR : PauseIR;
+      PauseIR     : State <= tms ? Exit2IR : PauseIR;
+      Exit2IR     : State <= tms ? UpdateIR : ShiftIR;
+      UpdateIR    : State <= tms ? SelectDR : RunTestIdle;
+    endcase
+  end
+  
+  assign tckn = ~tck;
+
+  flop #(1) resetnreg    (.clk(tckn), .d(~(State == TLReset)), .q(resetn));
+  flop #(1) tdo_enreg    (.clk(tckn), .d(State == ShiftIR | State == ShiftDR), .q(tdo_en));
+  flop #(1) captureIRreg (.clk(tckn), .d(State == CaptureIR), .q(captureIR));
+  flop #(1) updateIRreg  (.clk(tckn), .d(State == UpdateIR), .q(updateIR));
+  flop #(1) shiftDRreg   (.clk(tckn), .d(State == ShiftDR), .q(shiftDR));
+  flop #(1) captureDRreg (.clk(tckn), .d(State == CaptureDR), .q(captureDR));
+  flop #(1) updateDRreg  (.clk(tckn), .d(State == UpdateDR), .q(updateDR));
+
+  assign clockIR = tck | State[0] | ~State[1] | ~State[3];
+  assign clockDR = tck | State[0] | ~State[1] | State[3];
+  assign select = State[3];
+
+endmodule
diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv
index f033b40cc..2e6973ba5 100644
--- a/src/ebu/ahbcacheinterface.sv
+++ b/src/ebu/ahbcacheinterface.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Translates cache bus requests and uncached ieu memory requests into AHB transactions.
 //
-// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.8)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -79,8 +79,7 @@ module ahbcacheinterface import cvw::*; #(
   logic [P.PA_BITS-1:0]         LocalHADDR;                             // Address after selecting between cached and uncached operation
   logic [AHBWLOGBWPL-1:0]     BeatCountDelayed;                       // Beat within the cache line in the second (Data) cache stage
   logic                       CaptureEn;                              // Enable updating the Fetch buffer with valid data from HRDATA
-  logic [P.AHBW/8-1:0]          BusByteMaskM;                           // Byte enables within a word. For cache request all 1s
-  logic [P.AHBW-1:0]            PreHWDATA;                              // AHB Address phase write data
+ logic [P.AHBW-1:0]            PreHWDATA;                              // AHB Address phase write data
   logic [P.PA_BITS-1:0]         PAdrZero;
 
   genvar                      index;
@@ -114,11 +113,14 @@ module ahbcacheinterface import cvw::*; #(
     .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
   flopen #(P.AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
 
-  // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
-  // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
-  swbytemask #(P.AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(P.AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended());
-  
-  flopen #(P.AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[P.AHBW/8-1:0], HWSTRB);
+  if (READ_ONLY_CACHE) begin
+    assign HWSTRB = '0;
+  end else begin // compute byte mask for AHB transaction based on size and address.  AHBW may be different than LLEN
+    logic [P.AHBW/8-1:0]          BusByteMaskM;                           // Byte enables within a word. For cache request all 1s
+     
+    swbytemask #(P.AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(P.AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended());
+    flopen #(P.AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[P.AHBW/8-1:0], HWSTRB);
+  end
   
   buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE, P.BURST_EN) AHBBuscachefsm(
     .HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv
index 2f4944303..a9bf8f497 100644
--- a/src/ebu/ahbinterface.sv
+++ b/src/ebu/ahbinterface.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Translates LSU simple memory requests into AHB transactions (NON_SEQ).
 // 
-// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.21)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -62,8 +62,8 @@ module ahbinterface #(
     flop #(XLEN)   wdreg(HCLK, WriteData, HWDATA); 
     flop #(XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB);
   end else begin
-    assign HWDATA = 0;
-    assign HWSTRB = 0;
+    assign HWDATA = '0;
+    assign HWSTRB = '0;
   end    
 
   busfsm #(~LSU) busfsm(.HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic,
diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv
index b0f28966e..623d17975 100644
--- a/src/ebu/buscachefsm.sv
+++ b/src/ebu/buscachefsm.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Controller for cache to AHB bus interface
 // 
-// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.9)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -128,7 +128,6 @@ module buscachefsm #(
   assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK;
 
   assign BusStall = (CurrState == ADR_PHASE & ((|BusRW) | (|CacheBusRW) | BusCMOZero)) |
-                    //(CurrState == DATA_PHASE & ~BusRW[0]) |  // *** replace the next line with this.  Fails uart test but i think it's a test problem not a hardware problem.
                     (CurrState == DATA_PHASE) | 
                     (CurrState == ATOMIC_PHASE) |
                     (CurrState == ATOMIC_READ_DATA_PHASE) |
diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv
index 11ba896e4..8aa640673 100644
--- a/src/ebu/busfsm.sv
+++ b/src/ebu/busfsm.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Simple NON_SEQ (no burst) AHB controller.
 //
-// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.23)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv
index 67e4795a6..97ea0d5b4 100644
--- a/src/ebu/controllerinput.sv
+++ b/src/ebu/controllerinput.sv
@@ -11,7 +11,7 @@
 //          Connects core to peripherals and I/O pins on SOC
 //          Bus width presently matches XLEN
 // 
-// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.25)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv
index 356f955f3..2eec7db58 100644
--- a/src/ebu/ebu.sv
+++ b/src/ebu/ebu.sv
@@ -11,7 +11,7 @@
 //          Connects core to peripherals and I/O pins on SOC
 //          Bus width presently matches XLEN
 // 
-// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -110,14 +110,14 @@ module ebu import cvw::*;  #(parameter cvw_t P) (
     .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
     .HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYIn(HREADY));
 
-  // output mux //*** switch to structural implementation
-  assign HADDR = LSUSelect ? LSUHADDROut : IFUSelect ? IFUHADDROut : 0;
-  assign HSIZE = LSUSelect ? LSUHSIZEOut : IFUSelect ? IFUHSIZEOut: 0; 
-  assign HBURST = LSUSelect ? LSUHBURSTOut : IFUSelect ? IFUHBURSTOut : 0; // If doing memory accesses, use LSUburst, else use Instruction burst.
-  assign HTRANS = LSUSelect ? LSUHTRANSOut : IFUSelect ? IFUHTRANSOut: 0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
-  assign HWRITE = LSUSelect ? LSUHWRITEOut : 0;
+  // output mux 
+  assign HADDR = LSUSelect ? LSUHADDROut : IFUSelect ? IFUHADDROut : '0;
+  assign HSIZE = LSUSelect ? LSUHSIZEOut : IFUSelect ? IFUHSIZEOut: '0; 
+  assign HBURST = LSUSelect ? LSUHBURSTOut : IFUSelect ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst.
+  assign HTRANS = LSUSelect ? LSUHTRANSOut : IFUSelect ? IFUHTRANSOut: '0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
+  assign HWRITE = LSUSelect ? LSUHWRITEOut : '0;
   assign HPROT = 4'b0011; // not used; see Section 3.7
-  assign HMASTLOCK = 0; // no locking supported
+  assign HMASTLOCK = 1'b0; // no locking supported
 
   // data phase muxing.  This would be a mux if IFU wrote data.
   assign HWDATA = LSUHWDATA;
diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv
index 571bdcc63..daf3da1e8 100644
--- a/src/ebu/ebufsmarb.sv
+++ b/src/ebu/ebufsmarb.sv
@@ -8,7 +8,7 @@
 // Purpose: Arbitrates requests from instruction and data streams
 //          LSU has priority.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/fclassify.sv b/src/fpu/fclassify.sv
index f35f71869..6f52b0eae 100644
--- a/src/fpu/fclassify.sv
+++ b/src/fpu/fclassify.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Floating-point classify unit
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/fcmp.sv b/src/fpu/fcmp.sv
index 0944090fc..d1baac3b8 100755
--- a/src/fpu/fcmp.sv
+++ b/src/fpu/fcmp.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Floating-point comparison unit
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv
index a6c761494..8595fd29e 100755
--- a/src/fpu/fctrl.sv
+++ b/src/fpu/fctrl.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: floating-point control unit
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -48,7 +48,7 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
   output logic                 XEnE, YEnE, ZEnE,                   // enable inputs
   // operation mux selections                                    
   output logic                 FCvtIntE, FCvtIntW,                 // convert to integer operation
-  output logic [2:0]           FrmM,                               // FP rounding mode
+  output logic [2:0]           FrmE, FrmM,                          // FP rounding mode
   output logic [P.FMTBITS-1:0] FmtE, FmtM,                         // FP format
   output logic [2:0]           OpCtrlE, OpCtrlM,                   // Select which operation to do in each component
   output logic                 FpLoadStoreM,                       // FP load or store instruction
@@ -56,6 +56,7 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
   output logic [1:0]           FResSelE, FResSelM, FResSelW,       // Select one of the results that finish in the memory stage
   output logic                 FPUActiveE,                         // FP instruction being executed
   output logic                 ZfaE, ZfaM,                         // Zfa variants of instructions (fli, fminm, fmaxm, fround, froundnx, fleq, fltq, fmvh, fmvp, fcvtmod)
+  output logic                 ZfaFRoundNXE,                       // Zfa froundnx instruction
   // register control signals
   output logic                 FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable
   output logic                 FWriteIntE, FWriteIntM,             // Write to integer register
@@ -66,7 +67,7 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
   output logic                 FDivStartE, IDivStartE              // Start division or squareroot
   );
 
-  `define FCTRLW 13
+  `define FCTRLW 14
 
   logic [`FCTRLW-1:0]          ControlsD;                          // control signals
   logic                        FRegWriteD;                         // FP register write enable
@@ -75,13 +76,14 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
   logic [2:0]                  OpCtrlD;                            // Select which operation to do in each component
   logic [1:0]                  PostProcSelD;                       // select result in the post processing unit
   logic [1:0]                  FResSelD;                           // Select one of the results that finish in the memory stage
-  logic [2:0]                  FrmD, FrmE;                         // FP rounding mode
+  logic [2:0]                  FrmD;                               // FP rounding mode
   logic [P.FMTBITS-1:0]        FmtD;                               // FP format
   logic [1:0]                  Fmt, Fmt2;                          // format - before possible reduction
   logic                        SupportedFmt;                       // is the format supported
   logic                        SupportedFmt2;                      // is the source format supported for fp -> fp
   logic                        FCvtIntD, FCvtIntM;                 // convert to integer operation
   logic                        ZfaD;                               // Zfa variants of instructions
+  logic                        ZfaFRoundNXD;                       // Zfa froundnx instruction
 
   // FPU Instruction Decoder
   assign Fmt = Funct7D[1:0];
@@ -93,156 +95,156 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
                          (Fmt2 == 2'b10 & P.ZFH_SUPPORTED) | (Fmt2 == 2'b11 & P.Q_SUPPORTED));
 
   // decode the instruction                       
-  // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt_Zfa
+  // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt_Zfa_FroundNX
   always_comb
     if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled
-      ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0;
+      ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0_0;
     else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt) 
-      ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0; // for anything other than loads and stores, check for supported format
+      ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0_0; // for anything other than loads and stores, check for supported format
     else begin 
-      ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0; // default: non-implemented instruction
+      ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0_0; // default: non-implemented instruction
       /* verilator lint_off CASEINCOMPLETE */   // default value above has priority so no other default needed
       case(OpD)
         7'b0000111: case(Funct3D)
-                      3'b010:                       ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0_0; // flw
-                      3'b011:  if (P.D_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0_0; // fld
-                      3'b100:  if (P.Q_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0_0; // flq
-                      3'b001:  if (P.ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0_0; // flh
+                      3'b010:                       ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0_0_0; // flw
+                      3'b011:  if (P.D_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0_0_0; // fld
+                      3'b100:  if (P.Q_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0_0_0; // flq
+                      3'b001:  if (P.ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0_0_0; // flh
                     endcase
         7'b0100111: case(Funct3D)
-                      3'b010:                       ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0_0; // fsw
-                      3'b011:  if (P.D_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0_0; // fsd
-                      3'b100:  if (P.Q_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0_0; // fsq
-                      3'b001:  if (P.ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0_0; // fsh
+                      3'b010:                       ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0_0_0; // fsw
+                      3'b011:  if (P.D_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0_0_0; // fsd
+                      3'b100:  if (P.Q_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0_0_0; // fsq
+                      3'b001:  if (P.ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0_0_0; // fsh
                     endcase
-        7'b1000011:   ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0_0; // fmadd
-        7'b1000111:   ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0_0; // fmsub
-        7'b1001011:   ControlsD = `FCTRLW'b1_0_01_10_010_0_0_0_0; // fnmsub
-        7'b1001111:   ControlsD = `FCTRLW'b1_0_01_10_011_0_0_0_0; // fnmadd
+        7'b1000011:   ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0_0_0; // fmadd
+        7'b1000111:   ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0_0_0; // fmsub
+        7'b1001011:   ControlsD = `FCTRLW'b1_0_01_10_010_0_0_0_0_0; // fnmsub
+        7'b1001111:   ControlsD = `FCTRLW'b1_0_01_10_011_0_0_0_0_0; // fnmadd
         7'b1010011: casez(Funct7D)
-                      7'b00000??: ControlsD = `FCTRLW'b1_0_01_10_110_0_0_0_0; // fadd
-                      7'b00001??: ControlsD = `FCTRLW'b1_0_01_10_111_0_0_0_0; // fsub
-                      7'b00010??: ControlsD = `FCTRLW'b1_0_01_10_100_0_0_0_0; // fmul
-                      7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0_0_0; // fdiv
-                      7'b01011??: if (Rs2D == 5'b0000) ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0_0_0; // fsqrt
+                      7'b00000??: ControlsD = `FCTRLW'b1_0_01_10_110_0_0_0_0_0; // fadd
+                      7'b00001??: ControlsD = `FCTRLW'b1_0_01_10_111_0_0_0_0_0; // fsub
+                      7'b00010??: ControlsD = `FCTRLW'b1_0_01_10_100_0_0_0_0_0; // fmul
+                      7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0_0_0_0; // fdiv
+                      7'b01011??: if (Rs2D == 5'b0000) ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0_0_0_0; // fsqrt
                       7'b00100??: case(Funct3D)
-                                    3'b000:  ControlsD = `FCTRLW'b1_0_00_00_000_0_0_0_0; // fsgnj
-                                    3'b001:  ControlsD = `FCTRLW'b1_0_00_00_001_0_0_0_0; // fsgnjn
-                                    3'b010:  ControlsD = `FCTRLW'b1_0_00_00_010_0_0_0_0; // fsgnjx
+                                    3'b000:  ControlsD = `FCTRLW'b1_0_00_00_000_0_0_0_0_0; // fsgnj
+                                    3'b001:  ControlsD = `FCTRLW'b1_0_00_00_001_0_0_0_0_0; // fsgnjn
+                                    3'b010:  ControlsD = `FCTRLW'b1_0_00_00_010_0_0_0_0_0; // fsgnjx
                                   endcase
                       7'b00101??: case(Funct3D)
-                                    3'b000:  ControlsD = `FCTRLW'b1_0_00_00_110_0_0_0_0; // fmin
-                                    3'b001:  ControlsD = `FCTRLW'b1_0_00_00_101_0_0_0_0; // fmax
-                                    3'b010:  if (P.ZFA_SUPPORTED) ControlsD = `FCTRLW'b1_0_00_00_110_0_0_0_1; // fminm  (Zfa)
-                                    3'b011:  if (P.ZFA_SUPPORTED) ControlsD = `FCTRLW'b1_0_00_00_101_0_0_0_1; // fmaxm  (Zfa)
+                                    3'b000:  ControlsD = `FCTRLW'b1_0_00_00_110_0_0_0_0_0; // fmin
+                                    3'b001:  ControlsD = `FCTRLW'b1_0_00_00_101_0_0_0_0_0; // fmax
+                                    3'b010:  if (P.ZFA_SUPPORTED) ControlsD = `FCTRLW'b1_0_00_00_110_0_0_0_1_0; // fminm  (Zfa)
+                                    3'b011:  if (P.ZFA_SUPPORTED) ControlsD = `FCTRLW'b1_0_00_00_101_0_0_0_1_0; // fmaxm  (Zfa)
                                   endcase
                       7'b10100??: case(Funct3D)
-                                    3'b000:  ControlsD = `FCTRLW'b0_1_00_00_011_0_0_0_0; // fle
-                                    3'b001:  ControlsD = `FCTRLW'b0_1_00_00_001_0_0_0_0; // flt
-                                    3'b010:  ControlsD = `FCTRLW'b0_1_00_00_010_0_0_0_0; // feq
-                                    3'b100:  if (P.ZFA_SUPPORTED) ControlsD = `FCTRLW'b0_1_00_00_011_0_0_0_1; // fleq  (Zfa)
-                                    3'b101:  if (P.ZFA_SUPPORTED) ControlsD = `FCTRLW'b0_1_00_00_001_0_0_0_1; // fltq  (Zfa)
+                                    3'b000:  ControlsD = `FCTRLW'b0_1_00_00_011_0_0_0_0_0; // fle
+                                    3'b001:  ControlsD = `FCTRLW'b0_1_00_00_001_0_0_0_0_0; // flt
+                                    3'b010:  ControlsD = `FCTRLW'b0_1_00_00_010_0_0_0_0_0; // feq
+                                    3'b100:  if (P.ZFA_SUPPORTED) ControlsD = `FCTRLW'b0_1_00_00_011_0_0_0_1_0; // fleq  (Zfa)
+                                    3'b101:  if (P.ZFA_SUPPORTED) ControlsD = `FCTRLW'b0_1_00_00_001_0_0_0_1_0; // fltq  (Zfa)
                                   endcase
                       7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)          
-                                                ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0_0; // fclass
+                                                ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0_0_0; // fclass
                                   else if (Funct3D == 3'b000 & Rs2D == 5'b00000) 
-                                                ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_0; // fmv.x.w/d/h/q  fp to int register
+                                                ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_0_0; // fmv.x.w/d/h/q  fp to int register
                                   else if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct7D[1:0] == 2'b01 & Funct3D == 3'b000 & Rs2D == 5'b00001) 
-                                                  ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1; // fmvh.x.d  (Zfa) 
+                                                  ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.d  (Zfa) 
                                   //  Q not supported in RV64GC
                                   // coverage off   
                                   else if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct7D[1:0] == 2'b11 & Funct3D == 3'b000 & Rs2D == 5'b00001) 
-                                                  ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1; // fmvh.x.q  (Zfa)
+                                                  ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1_0; // fmvh.x.q  (Zfa)
                                   // coverage on
                       7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000) 
-                                                ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_0; // fmv.w/d/h/q.x  int to fp reg
+                                                ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_0_0; // fmv.w/d/h/q.x  int to fp reg
                                   else if (P.ZFA_SUPPORTED & Funct3D == 3'b000 & Rs2D == 5'b00001) 
-                                                ControlsD = `FCTRLW'b1_0_00_00_111_0_0_0_1; // fli  (Zfa)
+                                                ControlsD = `FCTRLW'b1_0_00_00_111_0_0_0_1_0; // fli  (Zfa)
                       7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00)
-                                                ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0_0; // fcvt.s.(d/q/h)
+                                                ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0_0_0; // fcvt.s.(d/q/h)
                                   else if (Rs2D == 5'b00100 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0_1; // fround.s  (Zfa) *** needs ctrl for all rounds
+                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // fround.s  (Zfa) 
                                   else if (Rs2D == 5'b00101 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0_1; // froundnx.s  (Zfa) *** needs ctrl for all rounds
+                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_1; // froundnx.s  (Zfa) 
                       7'b0100001: if (Rs2D[4:2] == 3'b000  & SupportedFmt2 & Rs2D[1:0] != 2'b01)
-                                                ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0_0; // fcvt.d.(s/h/q)
+                                                ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0_0_0; // fcvt.d.(s/h/q)
                                   else if (Rs2D == 5'b00100 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0_1; // fround.d  (Zfa)
+                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // fround.d  (Zfa)
                                   else if (Rs2D == 5'b00101 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0_1; // froundnx.d  (Zfa)
+                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_1; // froundnx.d  (Zfa)
                       7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10)
-                                                ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0_0; // fcvt.h.(s/d/q)
+                                                ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0_0_0; // fcvt.h.(s/d/q)
                                   else if (Rs2D == 5'b00100 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0_1; // fround.h  (Zfa)
+                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // fround.h  (Zfa)
                                   else if (Rs2D == 5'b00101 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0_1; // froundnx.h  (Zfa)
+                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_1; // froundnx.h  (Zfa)
                       // coverage off
                       // Not covered in testing because rv64gc does not support quad precision
                       7'b0100011: if (Rs2D[4:2] == 3'b000  & SupportedFmt2 & Rs2D[1:0] != 2'b11)
-                                                ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0_0; // fcvt.q.(s/h/d)
+                                                ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0_0_0; // fcvt.q.(s/h/d)
                                   else if (Rs2D == 5'b00100 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0_1; // fround.q  (Zfa)
+                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_0; // fround.q  (Zfa)
                                   else if (Rs2D == 5'b00101 & P.ZFA_SUPPORTED)
-                                                ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0_1; // froundnx.q  (Zfa)
+                                                ControlsD = `FCTRLW'b1_0_00_00_100_0_0_0_1_1; // froundnx.q  (Zfa)
                       // coverage on
                       7'b1101000: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fcvt.s.w   w->s
-                                    5'b00001:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0; // fcvt.s.wu wu->s
-                                    5'b00010:    ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0; // fcvt.s.l   l->s
-                                    5'b00011:    ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0; // fcvt.s.lu lu->s
+                                    5'b00000:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.s.w   w->s
+                                    5'b00001:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.s.wu wu->s
+                                    5'b00010:    ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.s.l   l->s
+                                    5'b00011:    ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.s.lu lu->s
                                   endcase
                       7'b1100000: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0; // fcvt.w.s   s->w
-                                    5'b00001:    ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0; // fcvt.wu.s  s->wu
-                                    5'b00010:    ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0; // fcvt.l.s   s->l
-                                    5'b00011:    ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0; // fcvt.lu.s  s->lu
+                                    5'b00000:    ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.s   s->w
+                                    5'b00001:    ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.s  s->wu
+                                    5'b00010:    ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.s   s->l
+                                    5'b00011:    ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.s  s->lu
                                   endcase
                       7'b1101001: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fcvt.d.w   w->d
-                                    5'b00001:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0; // fcvt.d.wu wu->d
-                                    5'b00010:    ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0; // fcvt.d.l   l->d
-                                    5'b00011:    ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0; // fcvt.d.lu lu->d
+                                    5'b00000:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.d.w   w->d
+                                    5'b00001:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.d.wu wu->d
+                                    5'b00010:    ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.d.l   l->d
+                                    5'b00011:    ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.d.lu lu->d
                                   endcase
                       7'b1100001: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0; // fcvt.w.d   d->w
-                                    5'b00001:    ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0; // fcvt.wu.d  d->wu
-                                    5'b00010:    ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0; // fcvt.l.d   d->l
-                                    5'b00011:    ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0; // fcvt.lu.d  d->lu
+                                    5'b00000:    ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.d   d->w
+                                    5'b00001:    ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.d  d->wu
+                                    5'b00010:    ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.d   d->l
+                                    5'b00011:    ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.d  d->lu
                                     5'b01000: if (P.ZFA_SUPPORTED & P.D_SUPPORTED & Funct3D == 3'b001) 
-                                                 ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_1; // fcvtmod.w.d (Zfa)
+                                                 ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_1_0; // fcvtmod.w.d (Zfa)
                                   endcase
                       7'b1101010: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fcvt.h.w   w->h
-                                    5'b00001:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0; // fcvt.h.wu wu->h
-                                    5'b00010:    ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0; // fcvt.h.l   l->h
-                                    5'b00011:    ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0; // fcvt.h.lu lu->h
+                                    5'b00000:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.h.w   w->h
+                                    5'b00001:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.h.wu wu->h
+                                    5'b00010:    ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.h.l   l->h
+                                    5'b00011:    ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.h.lu lu->h
                                   endcase
                       7'b1100010: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0; // fcvt.w.h   h->w
-                                    5'b00001:    ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0; // fcvt.wu.h  h->wu
-                                    5'b00010:    ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0; // fcvt.l.h   h->l
-                                    5'b00011:    ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0; // fcvt.lu.h  h->lu
+                                    5'b00000:    ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.h   h->w
+                                    5'b00001:    ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.h  h->wu
+                                    5'b00010:    ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.h   h->l
+                                    5'b00011:    ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.h  h->lu
                                   endcase
                       // Not covered in testing because rv64gc does not support quad precision
                       // coverage off
                       7'b1101011: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fcvt.q.w   w->q
-                                    5'b00001:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0; // fcvt.q.wu wu->q
-                                    5'b00010:    ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0; // fcvt.q.l   l->q
-                                    5'b00011:    ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0; // fcvt.q.lu lu->q
+                                    5'b00000:    ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fcvt.q.w   w->q
+                                    5'b00001:    ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0_0_0; // fcvt.q.wu wu->q
+                                    5'b00010:    ControlsD = `FCTRLW'b1_0_01_00_111_0_0_0_0_0; // fcvt.q.l   l->q
+                                    5'b00011:    ControlsD = `FCTRLW'b1_0_01_00_110_0_0_0_0_0; // fcvt.q.lu lu->q
                                   endcase
                       7'b1100011: case(Rs2D)
-                                    5'b00000:    ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0; // fcvt.w.q   q->w
-                                    5'b00001:    ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0; // fcvt.wu.q  q->wu
-                                    5'b00010:    ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0; // fcvt.l.q   q->l
-                                    5'b00011:    ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0; // fcvt.lu.q  q->lu
+                                    5'b00000:    ControlsD = `FCTRLW'b0_1_01_00_001_0_0_1_0_0; // fcvt.w.q   q->w
+                                    5'b00001:    ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1_0_0; // fcvt.wu.q  q->wu
+                                    5'b00010:    ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0_0; // fcvt.l.q   q->l
+                                    5'b00011:    ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0_0; // fcvt.lu.q  q->lu
                                   endcase
                       // coverage off
                       // Not covered in testing because rv64gc is not RV64Q or RV32D
                       7'b1011001: if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct3D == 3'b000) 
-                                                  ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.d.x  (Zfa) *** untested, controls could be wrong
+                                                  ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fmvp.d.x  (Zfa) 
                       7'b1011011: if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct3D == 3'b000) 
-                                                  ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.q.x  (Zfa)
+                                                  ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0_0; // fmvp.q.x  (Zfa)
                       // coverage on
                    endcase
       endcase
@@ -250,7 +252,7 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
     /* verilator lint_on CASEINCOMPLETE */
 
   // unswizzle control bits
-  assign {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD, FCvtIntD, ZfaD} = ControlsD;
+  assign {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD, FCvtIntD, ZfaD, ZfaFRoundNXD} = ControlsD;
   
   // rounding modes:
   //    000 - round to nearest, ties to even
@@ -259,7 +261,7 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
   //    011 - round up - round twords positive infinity
   //    100 - round to nearest, ties to max magnitude - round to nearest, ties away from zero
   //    111 - dynamic - choose FRM_REGW as rounding mode
-  assign FrmD = &Funct3D ? FRM_REGW : Funct3D;
+  assign FrmD = (Funct3D == 3'b111) ? FRM_REGW : Funct3D;
 
   // Precision
   //    00 - single
@@ -268,13 +270,13 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
   //    11 - quad
   
     if (P.FPSIZES == 1)
-      assign FmtD = 0;
-    else if (P.FPSIZES == 2)begin
+      assign FmtD = 1'b0;
+    else if (P.FPSIZES == 2) begin
       logic [1:0] FmtTmp;
-      assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0];
+      assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]&~Rs2D[2]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0];
       assign FmtD = (P.FMT == FmtTmp);
     end else if (P.FPSIZES == 3|P.FPSIZES == 4)
-      assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0];
+      assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]&~Rs2D[2]) ? Rs2D[1:0] : Funct7D[1:0];
 
   // Enables indicate that a source register is used and may need stalls. Also indicate special cases for infinity or NaN.
   // When disabled infinity and NaN on source registers are ignored by the unpacker and thus special case logic.
@@ -313,6 +315,7 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
   //        011 - mv to fp        01
   //        110 - min             10
   //        101 - max             10
+  //        100 - fround          11
   //        111 - fli             11
 
   //  OpCtrl:
@@ -350,22 +353,22 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
   assign Adr3D = InstrD[31:27];
  
   // D/E pipleine register
-  flopenrc #(15+P.FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE, 
-              {FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, FCvtIntD, ZfaD, ~IllegalFPUInstrD},
-              {FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE, ZfaE, FPUActiveE});
+  flopenrc #(`FCTRLW+2+P.FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE, 
+              {FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, FCvtIntD, ZfaD, ZfaFRoundNXD, ~IllegalFPUInstrD},
+              {FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE, ZfaE, ZfaFRoundNXE, FPUActiveE});
   flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {Adr1D, Adr2D, Adr3D}, {Adr1E, Adr2E, Adr3E});
   flopenrc #(1) DEFDivStartReg(clk, reset, FlushE, ~StallE|FDivBusyE, FDivStartD, FDivStartE);
   flopenrc #(3) DEEnReg(clk, reset, FlushE, ~StallE, {XEnD, YEnD, ZEnD}, {XEnE, YEnE, ZEnE});
 
   // Integer division on FPU divider
   if (P.M_SUPPORTED & P.IDIV_ON_FPU) assign IDivStartE = IntDivE;
-  else                               assign IDivStartE = 0; 
+  else                               assign IDivStartE = 1'b0; 
 
   // E/M pipleine register
   flopenrc #(14+int'(P.FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,
               {FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, FCvtIntE, ZfaE},
               {FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM, FCvtIntM, ZfaM});
-  
+
   // renameing for readability
   assign FpLoadStoreM = FResSelM[1];
 
@@ -373,5 +376,5 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
   flopenrc #(4)  MWCtrlReg(clk, reset, FlushW, ~StallW,
           {FRegWriteM, FResSelM, FCvtIntM},
           {FRegWriteW, FResSelW, FCvtIntW});
- 
+
 endmodule
diff --git a/src/fpu/fcvt.sv b/src/fpu/fcvt.sv
index ad3a2f602..90e8d7a23 100644
--- a/src/fpu/fcvt.sv
+++ b/src/fpu/fcvt.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Floating point conversions of configurable size
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // Int component of the Wally configurable RISC-V project.
 // 
@@ -190,7 +190,7 @@ module fcvt import cvw::*;  #(parameter cvw_t P) (
   // shifter
   ///////////////////////////////////////////////////////////////////////////
 
-  // kill the shift if it's negative
+  // kill the shift if it is negative
   // select the amount to shift by
   //      fp -> int: 
   //          - shift left by CalcExp - essentially shifting until the unbiased exponent = 0
@@ -201,10 +201,10 @@ module fcvt import cvw::*;  #(parameter cvw_t P) (
   //          - shift left by LeadingZeros - to shift till the result is normalized
   //              - only shift fp -> fp if the intital value is subnormal
   //                  - this is a problem because the input to the lzc was the fraction rather than the mantissa
-  //                  - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true?
+  //                  - rather have a few and-gates than an extra bit in the priority encoder???
   always_comb
       if(ToInt)                       ShiftAmt = Ce[P.LOGCVTLEN-1:0]&{P.LOGCVTLEN{~Ce[P.NE]}};
-      else if (ResSubnormUf)  ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0];
+      else if (ResSubnormUf)          ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0];
       else                            ShiftAmt = LeadingZeros;
       
   ///////////////////////////////////////////////////////////////////////////
diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv
index 1d44cef5d..2a43b2d91 100644
--- a/src/fpu/fdivsqrt/fdivsqrt.sv
+++ b/src/fpu/fdivsqrt/fdivsqrt.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -37,6 +37,8 @@ module fdivsqrt import cvw::*;  #(parameter cvw_t P) (
   input  logic                 XInfE, YInfE, 
   input  logic                 XZeroE, YZeroE, 
   input  logic                 XNaNE, YNaNE, 
+  input  logic [P.NE-2:0]      BiasE,                               // Bias of exponent
+  input  logic [P.LOGFLEN-1:0] NfE,                          // Number of fractional bits in selected format
   input  logic                 FDivStartE, IDivStartE,
   input  logic                 StallM,
   input  logic                 FlushE,
@@ -59,15 +61,12 @@ module fdivsqrt import cvw::*;  #(parameter cvw_t P) (
   logic [P.DIVb+3:0]           D;                            // Iterator Divisor
   logic [P.DIVb:0]             FirstU, FirstUM;              // Intermediate result values
   logic [P.DIVb+1:0]           FirstC;                       // Step tracker
-  logic                        Firstun;                      // Quotient selection
   logic                        WZeroE;                       // Early termination flag
   logic [P.DURLEN-1:0]         CyclesE;                      // FSM cycles
   logic                        SpecialCaseM;                 // Divide by zero, square root of negative, etc.
-  logic                        DivStartE;                    // Enable signal for flops during stall
                                                             
   // Integer div/rem signals                                
   logic                        BZeroM;                       // Denominator is zero
-  logic                        IntDivM;                      // Integer operation
   logic [P.DIVBLEN-1:0]        IntNormShiftM;                // Integer normalizatoin shift amount
   logic                        ALTBM, AsM, BsM, W64M;        // Special handling for postprocessor
   logic [P.XLEN-1:0]           AM;                           // Original Numerator for postprocessor
@@ -75,11 +74,10 @@ module fdivsqrt import cvw::*;  #(parameter cvw_t P) (
 
   fdivsqrtpreproc #(P) fdivsqrtpreproc(                          // Preprocessor
     .clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE),
-    .FmtE, .SqrtE, .XZeroE, .Funct3E, .UeM, .X, .D, .CyclesE,
+    .FmtE, .Bias(BiasE), .Nf(NfE), .SqrtE, .XZeroE, .Funct3E, .UeM, .X, .D, .CyclesE,
     // Int-specific 
     .ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE,
-    .BZeroM, .IntNormShiftM, .AM, 
-    .IntDivM, .W64M, .ALTBM, .AsM, .BsM);
+    .BZeroM, .IntNormShiftM, .AM, .W64M, .ALTBM, .AsM, .BsM);
 
   fdivsqrtfsm #(P) fdivsqrtfsm(                                  // FSM
     .clk, .reset, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, 
@@ -90,11 +88,11 @@ module fdivsqrt import cvw::*;  #(parameter cvw_t P) (
 
   fdivsqrtiter #(P) fdivsqrtiter(                                // CSA Iterator
     .clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .D, 
-    .FirstU, .FirstUM, .FirstC, .Firstun, .FirstWS(WS), .FirstWC(WC));
+    .FirstU, .FirstUM, .FirstC, .FirstWS(WS), .FirstWC(WC));
 
   fdivsqrtpostproc #(P) fdivsqrtpostproc(                        // Postprocessor
     .clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, 
-    .SqrtE, .Firstun, .SqrtM, .SpecialCaseM, 
+    .SqrtE, .SqrtM, .SpecialCaseM, 
     .UmM, .WZeroE, .DivStickyM, 
     // Int-specific 
     .IntNormShiftM, .ALTBM, .AsM, .BsM, .BZeroM, .W64M, .RemOpM(Funct3M[1]), .AM, 
diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv
index 72fe04249..2347c9d21 100644
--- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Determine number of cycles for divsqrt
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -28,40 +28,13 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module fdivsqrtcycles import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.FMTBITS-1:0] FmtE,
-  input  logic                 SqrtE,
+  input  logic [P.LOGFLEN-1:0] Nf,          // Number of fractional bits in selected format
   input  logic                 IntDivE,
   input  logic [P.DIVBLEN-1:0] IntResultBitsE,    
   output logic [P.DURLEN-1:0]  CyclesE
 );
 
-  logic [P.DIVBLEN-1:0] Nf, FPResultBitsE, ResultBitsE; // number of fractional (result) bits
-
-  /* verilator lint_off WIDTH */
-  if (P.FPSIZES == 1)
-    assign Nf = P.NF;
-  else if (P.FPSIZES == 2)
-    always_comb
-      case (FmtE)
-        1'b0: Nf = P.NF1;
-        1'b1: Nf = P.NF;
-      endcase
-  else if (P.FPSIZES == 3)
-    always_comb
-      case (FmtE)
-        P.FMT:   Nf = P.NF;
-        P.FMT1:  Nf = P.NF1;
-        P.FMT2:  Nf = P.NF2; 
-        default: Nf = 'x; // shouldn't happen
-      endcase
-  else if (P.FPSIZES == 4)  
-    always_comb
-      case(FmtE)
-        P.S_FMT: Nf = P.S_NF;
-        P.D_FMT: Nf = P.D_NF;
-        P.H_FMT: Nf = P.H_NF;
-        P.Q_FMT: Nf = P.Q_NF;
-      endcase 
+  logic [P.DIVBLEN-1:0] FPResultBitsE, ResultBitsE; // number of fractional (result) bits
 
   // Cycle logic
   // P.DIVCOPIES = k. P.LOGR = log(R) = r.  P.RK = rk.  
@@ -70,6 +43,7 @@ module fdivsqrtcycles import cvw::*;  #(parameter cvw_t P) (
   // FP Sqrt needs at least Nf fractional bits and 2 guard/round bits.  The integer bit is always initialized to 1 and does not need a cycle.
   // The datapath produces rk bits per cycle, so Cycles = ceil (ResultBitsE / rk)
 
+  /* verilator lint_off WIDTH */
   always_comb begin 
     FPResultBitsE = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard; integer bit implicit because starting at n=1
 
diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
index d24b490ab..058a3d17b 100644
--- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Exponent caclulation for divide and square root
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -28,49 +28,21 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module fdivsqrtexpcalc import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.FMTBITS-1:0] Fmt,
+  input  logic [P.NE-2:0]      Bias,      // Bias of exponent
   input  logic [P.NE-1:0]      Xe, Ye,    // input exponents
   input  logic                 Sqrt,
- input  logic [P.DIVBLEN-1:0] ell, m,    // number of leading 0s in Xe and Ye
+  input  logic [P.DIVBLEN-1:0] ell, m,    // number of leading 0s in Xe and Ye
   output logic [P.NE+1:0]      Ue         // result exponent
   );
-  
-  logic [P.NE-2:0] Bias;
+
   logic [P.NE+1:0] SXExp;
   logic [P.NE+1:0] SExp;
   logic [P.NE+1:0] DExp;
 
-  // Determine exponent bias according to the format
-  
-  if (P.FPSIZES == 1) begin
-    assign Bias = (P.NE-1)'(P.BIAS); 
-
-  end else if (P.FPSIZES == 2) begin
-    assign Bias = Fmt ? (P.NE-1)'(P.BIAS) : (P.NE-1)'(P.BIAS1); 
-
-  end else if (P.FPSIZES == 3) begin
-    always_comb
-      case (Fmt)
-        P.FMT: Bias  =  (P.NE-1)'(P.BIAS);
-        P.FMT1: Bias = (P.NE-1)'(P.BIAS1);
-        P.FMT2: Bias = (P.NE-1)'(P.BIAS2);
-        default: Bias = 'x;
-      endcase
-
-  end else if (P.FPSIZES == 4) begin        
-  always_comb
-    case (Fmt)
-      2'h3: Bias =  (P.NE-1)'(P.Q_BIAS);
-      2'h1: Bias =  (P.NE-1)'(P.D_BIAS);
-      2'h0: Bias =  (P.NE-1)'(P.S_BIAS);
-      2'h2: Bias =  (P.NE-1)'(P.H_BIAS);
-    endcase
-  end
-
   // Square root exponent = (Xe - l - bias) / 2 + bias; l accounts for subnorms
   assign SXExp = {2'b0, Xe} - {{(P.NE+1-P.DIVBLEN){1'b0}}, ell} - (P.NE+2)'(P.BIAS);
   assign SExp  = {SXExp[P.NE+1], SXExp[P.NE+1:1]} + {2'b0, Bias};
-  
+
   // division exponent = (Xe-l) - (Ye-m) + bias; l and m account for subnorms
   assign DExp  = ({2'b0, Xe} - {{(P.NE+1-P.DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(P.NE+1-P.DIVBLEN){1'b0}}, m} + {3'b0, Bias}); 
 
diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
index 732bd6f51..799ded999 100644
--- a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 2 F Addend Generator
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -37,7 +37,7 @@ module fdivsqrtfgen2 import cvw::*;  #(parameter cvw_t P) (
   // Generate for both positive and negative quotient digits
   assign FP = ~(U << 1) & C;
   assign FN = (UM << 1) | (C & ~(C << 2));
-  assign FZ = 0;
+  assign FZ = '0;
 
   always_comb     // Choose which adder input will be used
     if (up)       F = FP;
diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
index f1c2e3281..90af95643 100644
--- a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 4 F Addend Generator
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -37,7 +37,7 @@ module fdivsqrtfgen4 import cvw::*;  #(parameter cvw_t P) (
   // Generate for both positive and negative digits
   assign F2  = (~U << 2) & (C << 2);              // 
   assign F1  = ~(U << 1) & C;
-  assign F0  = 0;
+  assign F0  = '0;
   assign FN1 = (UM << 1) | (C & ~(C << 3));
   assign FN2 = (UM << 2) | ((C << 2) & ~(C << 4));
 
diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv
index 8975edeb6..4e05b5e58 100644
--- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: divsqrt state machine for multi-cycle operations
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv
index c942db450..39de58855 100644
--- a/src/fpu/fdivsqrt/fdivsqrtiter.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: k stages of divsqrt logic, plus registers
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -35,7 +35,6 @@ module fdivsqrtiter import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.DIVb+3:0] X, D,                  // Q4.DIVb
   output logic [P.DIVb:0]   FirstU, FirstUM,       // U1.DIVb
   output logic [P.DIVb+1:0] FirstC,                // Q2.DIVb
-  output logic              Firstun,
   output logic [P.DIVb+3:0] FirstWS, FirstWC       // Q4.DIVb
 );
 
@@ -44,7 +43,7 @@ module fdivsqrtiter import cvw::*;  #(parameter cvw_t P) (
   logic [P.DIVb+3:0]      WCNext[P.DIVCOPIES-1:0]; // Q4.DIVb
   logic [P.DIVb+3:0]      WS[P.DIVCOPIES:0];       // Q4.DIVb
   logic [P.DIVb+3:0]      WC[P.DIVCOPIES:0];       // Q4.DIVb
-  logic [P.DIVb:0]        U[P.DIVCOPIES:0];        // U1.DIVb // *** probably Q not U.  See Table 16.26 notes
+  logic [P.DIVb:0]        U[P.DIVCOPIES:0];        // U1.DIVb
   logic [P.DIVb:0]        UM[P.DIVCOPIES:0];       // U1.DIVb
   logic [P.DIVb:0]        UNext[P.DIVCOPIES-1:0];  // U1.DIVb
   logic [P.DIVb:0]        UMNext[P.DIVCOPIES-1:0]; // U1.DIVb
@@ -81,7 +80,7 @@ module fdivsqrtiter import cvw::*;  #(parameter cvw_t P) (
 
   // C register/initialization mux: C = -R:
   // C = -4 = 00.000000... (in Q2.DIVb) for radix 4, C = -2 = 10.000000... for radix2
-  if(P.RADIX == 4) assign initC = 0;
+  if(P.RADIX == 4) assign initC = '0;
   else             assign initC = {2'b10, {{P.DIVb{1'b0}}}};
   mux2   #(P.DIVb+2) cmux(C[P.DIVCOPIES], initC, IFDivStartE, NextC); 
   flopen #(P.DIVb+2) creg(clk, FDivBusyE, NextC, C[0]);
@@ -119,6 +118,5 @@ module fdivsqrtiter import cvw::*;  #(parameter cvw_t P) (
   assign FirstU  = U[0];
   assign FirstUM = UM[0];
   assign FirstC  = C[0];
-  assign Firstun = un[0];
 endmodule
 
diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index 78a50d0c3..83eee245a 100644
--- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Divide/Square root postprocessing
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -35,7 +35,7 @@ module fdivsqrtpostproc import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.DIVb:0]      FirstU, FirstUM,   // U1.DIVb
   input  logic [P.DIVb+1:0]    FirstC,            // Q2.DIVb
   input  logic                 SqrtE,
-  input  logic                 Firstun, SqrtM, SpecialCaseM, 
+  input  logic                 SqrtM, SpecialCaseM, 
   input  logic [P.XLEN-1:0]    AM,                // U/Q(XLEN.0)
   input  logic                 RemOpM, ALTBM, BZeroM, AsM, BsM, W64M,
   input  logic [P.DIVBLEN-1:0] IntNormShiftM,     
@@ -71,7 +71,7 @@ module fdivsqrtpostproc import cvw::*;  #(parameter cvw_t P) (
     mux2 #(P.DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
     csa #(P.DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
     aplusbeq0 #(P.DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
-    assign WZeroE = weq0E|(wfeq0E & Firstun);
+    assign WZeroE = weq0E | wfeq0E;
   end else begin
     assign WZeroE = weq0E;
   end 
@@ -121,7 +121,7 @@ module fdivsqrtpostproc import cvw::*;  #(parameter cvw_t P) (
         else        IntDivResultM = {(P.XLEN){1'b1}};
      end else if (ALTBM) begin // Numerator is small
         if (RemOpM) IntDivResultM = AM;
-        else        IntDivResultM = 0;
+        else        IntDivResultM = '0;
      end else       IntDivResultM = PreIntResultM[P.XLEN-1:0];
 
     // sign extend result for W64
@@ -131,5 +131,6 @@ module fdivsqrtpostproc import cvw::*;  #(parameter cvw_t P) (
         W64M, FIntDivResultM);
     end else 
       assign FIntDivResultM = IntDivResultM[P.XLEN-1:0];
-  end
+  end else
+    assign FIntDivResultM = '0;
 endmodule
diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index 0f0273c25..9156005fd 100644
--- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Divide/Square root preprocessing: integer absolute value and W64, normalization shift
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -33,6 +33,8 @@ module fdivsqrtpreproc import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.NF:0]        Xm, Ym,      // Floating-point significands
   input  logic [P.NE-1:0]      Xe, Ye,      // Floating-point exponents
   input  logic [P.FMTBITS-1:0] FmtE,
+  input  logic [P.NE-2:0]      Bias,                               // Bias of exponent
+  input  logic [P.LOGFLEN-1:0] Nf,          // Number of fractional bits in selected format
   input  logic                 SqrtE,
   input  logic                 XZeroE,
   input  logic [2:0]           Funct3E,
@@ -45,7 +47,7 @@ module fdivsqrtpreproc import cvw::*;  #(parameter cvw_t P) (
   output logic                 ISpecialCaseE,
   output logic [P.DURLEN-1:0]  CyclesE,
   output logic [P.DIVBLEN-1:0] IntNormShiftM,
-  output logic                 ALTBM, IntDivM, W64M,
+  output logic                 ALTBM, W64M,
   output logic                 AsM, BsM, BZeroM,
   output logic [P.XLEN-1:0]    AM
 );
@@ -56,7 +58,6 @@ module fdivsqrtpreproc import cvw::*;  #(parameter cvw_t P) (
   logic [P.DIVb:0]             IFX, IFD;                            // Correctly-sized inputs for iterator, selected from int or fp input
   logic [P.DIVBLEN-1:0]        mE, ell;                             // Leading zeros of inputs
   logic [P.DIVBLEN-1:0]        IntResultBitsE;                      // bits in integer result
-  logic                        NumerZeroE;                          // Numerator is zero (X or A)
   logic                        AZeroE, BZeroE;                      // A or B is Zero for integer division
   logic                        SignedDivE;                          // signed division
   logic                        AsE, BsE;                            // Signs of integer inputs
@@ -94,11 +95,9 @@ module fdivsqrtpreproc import cvw::*;  #(parameter cvw_t P) (
     // Select integer or floating point inputs
     mux2 #(P.DIVb+1) ifxmux({Xm, {(P.DIVb-P.NF){1'b0}}}, {PosA, {(P.DIVb-P.XLEN+1){1'b0}}}, IntDivE, IFX);
     mux2 #(P.DIVb+1) ifdmux({Ym, {(P.DIVb-P.NF){1'b0}}}, {PosB, {(P.DIVb-P.XLEN+1){1'b0}}}, IntDivE, IFD);
-    mux2 #(1)    numzmux(XZeroE, AZeroE, IntDivE, NumerZeroE);
   end else begin // Int not supported
     assign IFX = {Xm, {(P.DIVb-P.NF){1'b0}}};
     assign IFD = {Ym, {(P.DIVb-P.NF){1'b0}}};
-    assign NumerZeroE = XZeroE;
   end
 
   //////////////////////////////////////////////////////
@@ -145,7 +144,7 @@ module fdivsqrtpreproc import cvw::*;  #(parameter cvw_t P) (
       assign DivXShifted = DivX;
     end
   end else begin
-    assign ISpecialCaseE = 0;
+    assign {ISpecialCaseE, IntResultBitsE} = '0;
   end
 
   //////////////////////////////////////////////////////
@@ -172,7 +171,6 @@ module fdivsqrtpreproc import cvw::*;  #(parameter cvw_t P) (
   // 4          2(x)-4 = 4(x/2 - 1))  2(x/2)-4 = 4(x/4 - 1)
   // Summary: PreSqrtX = r(x/2or4 - 1)
 
-  logic [P.DIVb:0] PreSqrtX;
   assign EvenExp = Xe[0] ^ ell[0]; // effective unbiased exponent after normalization is even
   mux2 #(P.DIVb+4) sqrtxmux({4'b0,Xnorm[P.DIVb:1]}, {5'b00, Xnorm[P.DIVb:2]}, EvenExp, SqrtX); // X/2 if exponent odd, X/4 if exponent even
 
@@ -209,25 +207,24 @@ module fdivsqrtpreproc import cvw::*;  #(parameter cvw_t P) (
   flopen #(P.DIVb+4) dreg(clk, IFDivStartE, {3'b000, Dnorm}, D);
  
   // Floating-point exponent
-  fdivsqrtexpcalc #(P) expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .ell, .m(mE), .Ue(UeE));
+  fdivsqrtexpcalc #(P) expcalc(.Bias, .Xe, .Ye, .Sqrt(SqrtE), .ell, .m(mE), .Ue(UeE));
   flopen #(P.NE+2) expreg(clk, IFDivStartE, UeE, UeM);
 
   // Number of FSM cycles (to FSM)
-  fdivsqrtcycles #(P) cyclecalc(.FmtE, .SqrtE, .IntDivE, .IntResultBitsE, .CyclesE);
+  fdivsqrtcycles #(P) cyclecalc(.Nf, .IntDivE, .IntResultBitsE, .CyclesE);
 
   if (P.IDIV_ON_FPU) begin:intpipelineregs
     logic [P.DIVBLEN-1:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE;
     logic               RemOpE;
 
     /* verilator lint_off WIDTH */
-    assign IntDivNormShiftE = P.DIVb - (CyclesE * P.RK - P.LOGR); // b - rn, used for integer normalization right shift.  rn = Cycles * r * k - r ***explain
+    assign IntDivNormShiftE = P.DIVb - (CyclesE * P.RK - P.LOGR); // b - rn, used for integer normalization right shift.  n = (Cycles * k - 1)
     assign IntRemNormShiftE = mE + (P.DIVb-(P.XLEN-1));           // m + b - (N-1) for remainder normalization shift
     /* verilator lint_on WIDTH */
     assign RemOpE = Funct3E[1];
     mux2 #(P.DIVBLEN) normshiftmux(IntDivNormShiftE, IntRemNormShiftE, RemOpE, IntNormShiftE);
 
     // pipeline registers
-    flopen #(1)          mdureg(clk, IFDivStartE, IntDivE,  IntDivM);
     flopen #(1)         altbreg(clk, IFDivStartE, ALTBE,    ALTBM);
     flopen #(1)        bzeroreg(clk, IFDivStartE, BZeroE,   BZeroM);
     flopen #(1)        asignreg(clk, IFDivStartE, AsE,      AsM);
@@ -236,7 +233,9 @@ module fdivsqrtpreproc import cvw::*;  #(parameter cvw_t P) (
     flopen #(P.XLEN)    srcareg(clk, IFDivStartE, AE,       AM);
     if (P.XLEN==64) 
       flopen #(1)        w64reg(clk, IFDivStartE, W64E,     W64M);
-  end
+    else assign W64M = 0;
+  end else
+    assign {ALTBM, W64M, AsM, BsM, BZeroM, AM, IntNormShiftM} = '0;
 
 endmodule
 
diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv
index a0a552ac8..fa13cadeb 100644
--- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: radix-2 divsqrt recurrence stage
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -58,7 +58,7 @@ module fdivsqrtstage2 import cvw::*;  #(parameter cvw_t P) (
   // Divisor multiple
   always_comb
     if      (up) Dsel = DBar;
-    else if (uz) Dsel = 0;
+    else if (uz) Dsel = '0;
     else         Dsel = D; // un
 
   // Residual Update
diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv
index d879e0f90..551a358c4 100644
--- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: radix-4 divsqrt recurrence stage
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -52,7 +52,7 @@ module fdivsqrtstage4 import cvw::*;  #(parameter cvw_t P) (
 
   // Digit Selection logic
   assign j0     = ~C[P.DIVb+1];             // first step of R digit selection: C = 00...0
-  assign j1     = C[P.DIVb] & ~C[P.DIVb-1]; // second step of R digit selection: C = 1100...0; *** could simplify to ~C[P.DIVb-1] because j=0 case takes priority
+  assign j1     = ~C[P.DIVb-1]; // second step of R digit selection: C = 1100...0; simplified from  C[P.DIVb] & ~C[P.DIVb-1] because j=0 case takes priority
   assign Smsbs  = U[P.DIVb:P.DIVb-4];       // U1.4 most significant bits of square root
   assign Dmsbs  = D[P.DIVb-1:P.DIVb-3];     // U0.3 most significant fractional bits of divisor after leading 1
   assign WCmsbs = WC[P.DIVb+3:P.DIVb-4];    // Q4.4 most significant bits of residual
@@ -68,7 +68,7 @@ module fdivsqrtstage4 import cvw::*;  #(parameter cvw_t P) (
     case (udigit)
       4'b1000: Dsel = DBar2;
       4'b0100: Dsel = DBar;
-      4'b0000: Dsel = 0;
+      4'b0000: Dsel = '0;
       4'b0010: Dsel = D;
       4'b0001: Dsel = D2;
       default: Dsel = 'x;
diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
index 55810665b..db858cb0b 100644
--- a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 2 unified on-the-fly converter
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
index 5a802934e..3d842f9a8 100644
--- a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 4 unified on-the-fly converter
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv
index 2d4cd5e48..193231eea 100644
--- a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 2 Unified Quotient/Square Root Digit Selection
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv
index 610b79395..840215c28 100644
--- a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Table-based Radix 4 Unified Quotient/Square Root Digit Selection
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv
index fd1092497..e6eb45f75 100644
--- a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Comparator-based Radix 4 Unified Quotient/Square Root Digit Selection 
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -47,7 +47,7 @@ module fdivsqrtuslc4cmp (
   // Wmsbs = |        |
 
   logic [6:0] mk2, mk1, mk0, mkm1;
-  logic [6:0] mkj2, mkj1, mkj0, mkjm1;
+  logic [6:0] mkj2, mkj1;
   logic [6:0] mks2[7:0], mks1[7:0], mks0[7:0], mksm1[7:0];
   logic sqrtspecial;
 
@@ -95,7 +95,7 @@ module fdivsqrtuslc4cmp (
   // Choose A for current operation 
  always_comb
     if (SqrtE) begin 
-      if (Smsbs[4]) A = 3'b111; // for S = 1.0000  *** can we optimize away this case?
+      if (Smsbs[4]) A = 3'b111; // for S = 1.0000
       else A = Smsbs[2:0];
     end else A = Dmsbs;
     
@@ -108,7 +108,7 @@ module fdivsqrtuslc4cmp (
 
 /* Nannarelli12 design to exploit symmetry is slower because of negation and mux for special case of A = 000
   assign mk0 = -mk1;
-  assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table *** can we hide from critical path
+  assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table
   */
  
   // Compare residual W to selection constants to choose digit
@@ -117,5 +117,5 @@ module fdivsqrtuslc4cmp (
     else if ($signed(Wmsbs) >= $signed(mk1))  udigit = 4'b0100; // choose 1
     else if ($signed(Wmsbs) >= $signed(mk0))  udigit = 4'b0000; // choose 0
     else if ($signed(Wmsbs) >= $signed(mkm1)) udigit = 4'b0010; // choose -1
-    else                                      udigit = 4'b0001; // choose -2  
+    else                                      udigit = 4'b0001; // choose -2
 endmodule
diff --git a/src/fpu/fhazard.sv b/src/fpu/fhazard.sv
index e68934294..c31324ad1 100644
--- a/src/fpu/fhazard.sv
+++ b/src/fpu/fhazard.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Determine forwarding, stalls and flushes for the FPU
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/fli.sv b/src/fpu/fli.sv
index c352d7a5c..349189f33 100644
--- a/src/fpu/fli.sv
+++ b/src/fpu/fli.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Floating-point float immediate
 // 
-// Documentation: RISC-V System on Chip Design Chapter 16
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -80,7 +80,7 @@ module fli import cvw::*;  #(parameter cvw_t P) (
         endcase
     end
     assign HImmBox = {{(P.FLEN-16){1'b1}}, HImm}; // NaN-box HImm
-  end else assign HImmBox = 0;
+  end else assign HImmBox = '0;
 
   ////////////////////////////
   // single
@@ -168,7 +168,7 @@ module fli import cvw::*;  #(parameter cvw_t P) (
         endcase
     end
     assign DImmBox = {{(P.FLEN-64){1'b1}}, DImm}; // NaN-box DImm
-  end else assign DImmBox = 0;
+  end else assign DImmBox = '0;
   
     ////////////////////////////
   // double
@@ -213,7 +213,7 @@ module fli import cvw::*;  #(parameter cvw_t P) (
         endcase
     end
     assign QImmBox = QImm; // NaN-box QImm trivial because Q is longest format
-  end else assign QImmBox = 0;
+  end else assign QImmBox = '0;
 
   mux4 #(P.FLEN) flimux(SImmBox, DImmBox, HImmBox, QImmBox, Fmt, Imm); // select immediate based on format
 
diff --git a/src/fpu/fma/fma.sv b/src/fpu/fma/fma.sv
index bdf2898f7..36d4a0ad5 100644
--- a/src/fpu/fma/fma.sv
+++ b/src/fpu/fma/fma.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Floating point multiply-accumulate of configurable size
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.7, 9)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -34,13 +34,13 @@ module fma import cvw::*;  #(parameter cvw_t P) (
   input  logic                         XZero, YZero, ZZero,    // is the input zero
   input  logic [2:0]                   OpCtrl,                 // operation control
   output logic                         ASticky,                // sticky bit that is calculated during alignment
-  output logic [3*P.NF+3:0]            Sm,                     // the positive sum's significand
+  output logic [P.FMALEN-1:0]          Sm,                     // the positive sum's significand
   output logic                         InvA,                   // Was A inverted for effective subtraction (P-A or -P+A)
   output logic                         As,                     // the aligned addend's sign (modified Z sign for other operations)
   output logic                         Ps,                     // the product's sign
   output logic                         Ss,                     // the sum's sign
   output logic [P.NE+1:0]              Se,                     // the sum's exponent
-  output logic [$clog2(3*P.NF+5)-1:0]  SCnt                    // normalization shift count
+  output logic [$clog2(P.FMALEN+1)-1:0] SCnt                    // normalization shift count
 );
 
   //  OpCtrl:
@@ -54,8 +54,8 @@ module fma import cvw::*;  #(parameter cvw_t P) (
   //        111 - sub
 
   logic [2*P.NF+1:0]   Pm;         // the product's significand in U(2.2Nf) format
-  logic [3*P.NF+3:0]   Am;         // addend aligned's mantissa for addition in U(NF+4.2NF)
-  logic [3*P.NF+3:0]   AmInv;      // aligned addend's mantissa possibly inverted
+  logic [P.FMALEN-1:0] Am;         // addend aligned's mantissa for addition in U(NF+4.2NF)
+  logic [P.FMALEN-1:0] AmInv;      // aligned addend's mantissa possibly inverted
   logic [2*P.NF+1:0]   PmKilled;   // the product's mantissa possibly killed U(2.2Nf)
   logic                KillProd;   // set the product to zero before addition if the product is too small to matter
   logic [P.NE+1:0]     Pe;         // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign
@@ -89,6 +89,6 @@ module fma import cvw::*;  #(parameter cvw_t P) (
       
   fmaadd #(P) add(.Am, .Pm, .Ze, .Pe, .Ps, .KillProd, .ASticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss);
 
-  fmalza #(3*P.NF+4, P.NF) lza(.A(AmInv), .Pm(PmKilled), .Cin(InvA & (~ASticky | KillProd)), .sub(InvA), .SCnt);
+  fmalza #(P.FMALEN, P.NF) lza(.A(AmInv), .Pm(PmKilled), .Cin(InvA & (~ASticky | KillProd)), .sub(InvA), .SCnt);
   
 endmodule
diff --git a/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv
index 00951ee10..4942f9d9f 100644
--- a/src/fpu/fma/fmaadd.sv
+++ b/src/fpu/fma/fmaadd.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: FMA significand adder
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -28,7 +28,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module fmaadd import cvw::*;  #(parameter cvw_t P) (
-  input  logic [3*P.NF+3:0]    Am,         // aligned addend's mantissa for addition in U(NF+5.2NF+1)
+  input  logic [3*P.NF+5:0]    Am,         // aligned addend's mantissa for addition in U(NF+5.2NF+1)
   input  logic [P.NE-1:0]      Ze,         // exponent of Z
   input  logic                 Ps,         // the product sign and the alligend addeded's sign (Modified Z sign for other operations)
   input  logic [P.NE+1:0]      Pe,         // product's exponet
@@ -36,14 +36,14 @@ module fmaadd import cvw::*;  #(parameter cvw_t P) (
   input  logic                 InvA,       // invert the aligned addend
   input  logic                 KillProd,   // should the product be set to 0
   input  logic                 ASticky,    // Alighed addend's sticky bit
-  output logic [3*P.NF+3:0]    AmInv,      // aligned addend possibly inverted
+  output logic [3*P.NF+5:0]    AmInv,      // aligned addend possibly inverted
   output logic [2*P.NF+1:0]    PmKilled,   // the product's mantissa possibly killed
   output logic                 Ss,         // sum's sign    
   output logic [P.NE+1:0]      Se,         // sum's exponent
-  output logic [3*P.NF+3:0]    Sm          // the positive sum
+  output logic [3*P.NF+5:0]    Sm          // the positive sum
 );
 
-  logic [3*P.NF+3:0]    PreSum, NegPreSum; // possibly negative sum
+  logic [3*P.NF+5:0]    PreSum, NegPreSum; // possibly negative sum
   logic                 NegSum;            // was the sum negative
 
   ///////////////////////////////////////////////////////////////////////////////
@@ -62,8 +62,8 @@ module fmaadd import cvw::*;  #(parameter cvw_t P) (
   //      addend - prod where product is killed (and not exactly zero) then don't add +1 from negation 
   //          ie ~(InvA&ASticky&KillProd)&InvA = (~ASticky|~KillProd)&InvA
   //          in this case this result is only ever selected when InvA=1 so we can remove &InvA
-  assign {NegSum, PreSum} = {{P.NF+2{1'b0}}, PmKilled, 1'b0} + {InvA, AmInv} + {{3*P.NF+4{1'b0}}, (~ASticky|KillProd)&InvA};
-  assign NegPreSum = Am + {{P.NF+1{1'b1}}, ~PmKilled, 1'b0} + {(3*P.NF+2)'(0), ~ASticky|~KillProd, 1'b0};
+  assign {NegSum, PreSum} = {{P.NF+3{1'b0}}, PmKilled, 2'b0} + {InvA, AmInv} + {{3*P.NF+5{1'b0}}, (~ASticky|KillProd)&InvA};
+  assign NegPreSum = Am + {{P.NF+2{1'b1}}, ~PmKilled, 2'b0} + {(3*P.NF+3)'(0), ~ASticky|~KillProd, 2'b0};
     
   // Choose the positive sum and accompanying LZA result.
   assign Sm = NegSum ? NegPreSum : PreSum;
diff --git a/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv
index 9001742e4..292472f7f 100644
--- a/src/fpu/fma/fmaalign.sv
+++ b/src/fpu/fma/fmaalign.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: FMA alginment shift
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -31,14 +31,14 @@ module fmaalign import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.NE-1:0]      Xe, Ye, Ze,          // biased exponents in B(NE.0) format
   input  logic [P.NF:0]        Zm,                  // significand in U(0.NF) format]
   input  logic                 XZero, YZero, ZZero, // is the input zero
-  output logic [3*P.NF+3:0]    Am,                  // addend aligned for addition in U(NF+5.2NF+1)
+  output logic [P.FMALEN-1:0]  Am,                  // addend aligned for addition in U(NF+5.2NF+1)
   output logic                 ASticky,             // Sticky bit calculated from the aliged addend
   output logic                 KillProd             // should the product be set to zero
 );
 
   logic [P.NE+1:0]             ACnt;                // how far to shift the addend to align with the product in Q(NE+2.0) format
-  logic [4*P.NF+3:0]           ZmShifted;           // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
-  logic [4*P.NF+3:0]           ZmPreshifted;        // input to the alignment shifter U(NF+5.3NF+1)
+  logic [P.FMALEN+P.NF-1:0]    ZmShifted;           // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
+  logic [P.FMALEN+P.NF-1:0]    ZmPreshifted;        // input to the alignment shifter U(NF+5.3NF+1)
   logic                        KillZ;               // should the addend be killed
 
   ///////////////////////////////////////////////////////////////////////////////
@@ -49,36 +49,37 @@ module fmaalign import cvw::*;  #(parameter cvw_t P) (
   //      - negative means Z is larger, so shift Z left
   //      - positive means the product is larger, so shift Z right
   // This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed
-  assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)} + (P.NE+2)'(P.NF+2) - {2'b0, Ze};
+  assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)} + (P.NE+2)'(P.NF+3) - {2'b0, Ze};
 
   // Default Addition with only inital left shift
-  //  |   53'b0    |  106'b(product)  | 1'b0 |
+  // extra bit at end and beginning so the correct guard bit is calculated when subtracting
+  //  |   54'b0    |  106'b(product)  | 2'b0 |
   //  | addnend    |
 
-  assign ZmPreshifted = {Zm,(3*P.NF+3)'(0)};
+  assign ZmPreshifted = {Zm,(P.FMALEN-1)'(0)};
   assign KillProd     = (ACnt[P.NE+1]&~ZZero)|XZero|YZero;
-  assign KillZ        = $signed(ACnt)>$signed((P.NE+2)'(3)*(P.NE+2)'(P.NF)+(P.NE+2)'(3));
+  assign KillZ        = $signed(ACnt)>$signed((P.NE+2)'(3)*(P.NE+2)'(P.NF)+(P.NE+2)'(5));
 
   always_comb begin
     // If the product is too small to effect the sum, kill the product
-    //  |   53'b0    |  106'b(product)  | 1'b0 |
+    //  |   54'b0    |  106'b(product)  | 2'b0 |
     //  | addnend    |
     if (KillProd) begin
-        ZmShifted = {(P.NF+2)'(0), Zm, (2*P.NF+1)'(0)};
+        ZmShifted = {(P.NF+3)'(0), Zm, (2*P.NF+2)'(0)};
         ASticky   = ~(XZero|YZero);
 
     // If the addend is too small to effect the addition        
     //      - The addend has to shift two past the end of the product to be considered too small
     //      - The 2 extra bits are needed for rounding
       
-    //  |   53'b0    |  106'b(product)  | 1'b0 |
+    //  |   54'b0    |  106'b(product)  | 2'b0 |
     //  | addnend    |
     end else if (KillZ)  begin
-        ZmShifted = 0;
+        ZmShifted = '0;
         ASticky   = ~ZZero;
 
     // If the Addend is shifted right
-    //  |   53'b0    |  106'b(product)  | 1'b0 |
+    //  |   54'b0    |  106'b(product)  | 2'b0 |
     //  | addnend    |
     end else begin
         ZmShifted = ZmPreshifted >> ACnt;
@@ -86,6 +87,6 @@ module fmaalign import cvw::*;  #(parameter cvw_t P) (
     end
   end
 
-  assign Am = ZmShifted[4*P.NF+3:P.NF];
+  assign Am = ZmShifted[P.FMALEN+P.NF-1:P.NF];
 
 endmodule
diff --git a/src/fpu/fma/fmaexpadd.sv b/src/fpu/fma/fmaexpadd.sv
index 50b85ded0..4ad254f79 100644
--- a/src/fpu/fma/fmaexpadd.sv
+++ b/src/fpu/fma/fmaexpadd.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: FMA exponent addition
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.9)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -37,6 +37,6 @@ module fmaexpadd import cvw::*;  #(parameter cvw_t P) (
   
   // kill the exponent if the product is zero - either X or Y is 0
   assign PZero = XZero | YZero;
-  assign Pe    = PZero ? 0 : ({2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)});
+  assign Pe    = PZero ? '0 : ({2'b0, Xe} + {2'b0, Ye} - {2'b0, (P.NE)'(P.BIAS)});
 
 endmodule
diff --git a/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv
index 822f857c2..417b9de28 100644
--- a/src/fpu/fma/fmalza.sv
+++ b/src/fpu/fma/fmalza.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Leading Zero Anticipator
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.14)
+// Documentation: RISC-V System on Chip Design
 //    See also [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
@@ -41,7 +41,7 @@ module fmalza #(WIDTH, NF) (
   logic [WIDTH-1:0]                   P, G, K;        // propagate, generate, kill for each column
   logic [WIDTH-1:0]                   Pp1, Gm1, Km1;  // propagate shifted right by 1, generate/kill shifted left 1
 
-  assign B = {{(NF+1){1'b0}}, Pm, 1'b0};              // Zero extend product
+  assign B = {{(NF+2){1'b0}}, Pm, 2'b0};              // Zero extend product
 
   assign P = A^B;
   assign G = A&B;
diff --git a/src/fpu/fma/fmamult.sv b/src/fpu/fma/fmamult.sv
index 8ce492f03..ea0ea2238 100644
--- a/src/fpu/fma/fmamult.sv
+++ b/src/fpu/fma/fmamult.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: FMA Significand Multiplier
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/fma/fmasign.sv b/src/fpu/fma/fmasign.sv
index 891c28746..8220f0aad 100644
--- a/src/fpu/fma/fmasign.sv
+++ b/src/fpu/fma/fmasign.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: FMA Sign Logic
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.8)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/fmtparams.sv b/src/fpu/fmtparams.sv
new file mode 100644
index 000000000..ad2dcfa4d
--- /dev/null
+++ b/src/fpu/fmtparams.sv
@@ -0,0 +1,86 @@
+
+///////////////////////////////////////////
+// fmtparams.sv
+//
+// Written: David_Harris@hmc.edu
+// Modified: 5/11/24
+//
+// Purpose: Look up bias of exponent and number of fractional bits for the selected format
+// 
+// Documentation: RISC-V System on Chip Design
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module fmtparams import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.FMTBITS-1:0] Fmt,
+  output logic [P.NE-2:0]      Bias,
+  output logic [P.LOGFLEN-1:0] Nf
+);
+
+  if (P.FPSIZES == 1) begin
+    assign Bias = (P.NE-1)'(P.BIAS); 
+  end else if (P.FPSIZES == 2) begin
+    assign Bias = Fmt ? (P.NE-1)'(P.BIAS) : (P.NE-1)'(P.BIAS1); 
+  end else if (P.FPSIZES == 3) begin
+    always_comb
+      case (Fmt)
+        P.FMT:  Bias =  (P.NE-1)'(P.BIAS);
+        P.FMT1: Bias = (P.NE-1)'(P.BIAS1);
+        P.FMT2: Bias = (P.NE-1)'(P.BIAS2);
+        default: Bias = 'x;
+      endcase
+  end else if (P.FPSIZES == 4) begin        
+    always_comb
+      case (Fmt)
+        2'h3: Bias =  (P.NE-1)'(P.Q_BIAS);
+        2'h1: Bias =  (P.NE-1)'(P.D_BIAS);
+        2'h0: Bias =  (P.NE-1)'(P.S_BIAS);
+        2'h2: Bias =  (P.NE-1)'(P.H_BIAS);
+      endcase
+  end
+
+  /* verilator lint_off WIDTH */
+  if (P.FPSIZES == 1)
+    assign Nf = P.NF;
+  else if (P.FPSIZES == 2)
+    always_comb
+      case (Fmt)
+        1'b0: Nf = P.NF1;
+        1'b1: Nf = P.NF;
+      endcase
+  else if (P.FPSIZES == 3)
+    always_comb
+      case (Fmt)
+        P.FMT:   Nf = P.NF;
+        P.FMT1:  Nf = P.NF1;
+        P.FMT2:  Nf = P.NF2; 
+        default: Nf = 'x; // shouldn't happen
+      endcase
+  else if (P.FPSIZES == 4)  
+    always_comb
+      case(Fmt)
+        P.S_FMT: Nf = P.S_NF;
+        P.D_FMT: Nf = P.D_NF;
+        P.H_FMT: Nf = P.H_NF;
+        P.Q_FMT: Nf = P.Q_NF;
+      endcase 
+  /* verilator lint_on WIDTH */
+
+endmodule
diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv
index c97a12d32..698b79e19 100755
--- a/src/fpu/fpu.sv
+++ b/src/fpu/fpu.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Floating Point Unit Top-Level Interface
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -61,7 +61,15 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.FLEN-1:0]    ReadDataW,                          // Read data (from LSU)
   output logic [P.XLEN-1:0]    FCvtIntResW,                        // convert result to to be written to integer register (to IEU)
   output logic                 FCvtIntW,                           // select FCvtIntRes (to IEU)
-  output logic [P.XLEN-1:0]    FIntDivResultW                      // Result from integer division (to IEU)
+  output logic [P.XLEN-1:0]    FIntDivResultW,                     // Result from integer division (to IEU)
+  // Debug scan chain
+  input  logic                 DebugSel,
+  input  logic [4:0]           DebugRegAddr,
+  input  logic                 DebugCapture,
+  input  logic                 DebugRegUpdate,
+  input  logic                 DebugScanEn,
+  input  logic                 DebugScanIn,
+  output logic                 DebugScanOut
 );
 
   // RISC-V FPU specifics:
@@ -70,7 +78,7 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
 
   // control signals
   logic                        FRegWriteW;                         // FP register write enable
-  logic [2:0]                  FrmM;                               // FP rounding mode
+  logic [2:0]                  FrmE, FrmM;                         // FP rounding mode
   logic [P.FMTBITS-1:0]        FmtE, FmtM;                         // FP precision 0-single 1-double
   logic                        FDivStartE, IDivStartE;             // Start division or squareroot
   logic                        FWriteIntM;                         // Write to integer register
@@ -85,6 +93,7 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
   logic                        FRegWriteE;                         // Write floating-point register
   logic                        FPUActiveE;                         // FP instruction being executed
   logic                        ZfaE, ZfaM;                         // Zfa variants of instructions (fli, fminm, fmaxm, fround, froundnx, fleq, fltq, fmvh, fmvp, fcvtmod.w.d)
+  logic                        ZfaFRoundNXE;                       // Zfa froundnx variant
 
   // regfile signals
   logic [P.FLEN-1:0]           FRD1D, FRD2D, FRD3D;                // Read Data from FP register - decode stage
@@ -112,18 +121,20 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
   logic                        XInfM, YInfM, ZInfM;                // is the input infinity - memory stage
   logic                        XExpMaxE;                           // is the exponent all ones (max value)
   logic [P.FLEN-1:0]           XPostBoxE;                          // X after fixing bad NaN box.  Needed for 1-input operations
+  logic [P.NE-2:0]             BiasE;                              // Bias of exponent
+  logic [P.LOGFLEN-1:0]        NfE;                                // Number of fractional bits
 
   // Fma Signals
   logic                        FmaAddSubE;                         // Multiply by 1.0 when adding or subtracting
   logic [1:0]                  FmaZSelE;                           // Select Z = Y when adding or subtracting, 0 when multiplying
-  logic [3*P.NF+3:0]           SmE, SmM;                           // Sum significand
+  logic [P.FMALEN-1:0]         SmE, SmM;                           // Sum significand
   logic                        FmaAStickyE, FmaAStickyM;           // FMA addend sticky bit output
   logic [P.NE+1:0]             SeE,SeM;                            // Sum exponent
   logic                        InvAE, InvAM;                       // Invert addend
   logic                        AsE, AsM;                           // Addend sign
   logic                        PsE, PsM;                           // Product sign
   logic                        SsE, SsM;                           // Sum sign
-  logic [$clog2(3*P.NF+5)-1:0] SCntE, SCntM;                       // LZA sum leading zero count
+  logic [$clog2(P.FMALEN+1)-1:0] SCntE, SCntM;                       // LZA sum leading zero count
   
   // Cvt Signals
   logic [P.NE:0]               CeE, CeM;                           // convert intermediate expoent
@@ -150,7 +161,8 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
   logic [P.XLEN-1:0]           FIntResE;                           // FPU to IEU E-stage result (classify, compare, move)
   logic [P.FLEN-1:0]           PostProcResM;                       // Postprocessor output
   logic [4:0]                  PostProcFlgM;                       // Postprocessor flags
-  logic                        PreNVE, PreNVM;                     // selected flag that is ready in the memory stage     
+  logic                        PreNVE, PreNVM;                     // selected invalid flag that is ready in the memory stage     
+  logic                        PreNXE, PreNXM;                     // selected inexact flag that is ready in the memory stage     
   logic [P.FLEN-1:0]           FpResM, FpResW;                     // FPU preliminary result
   logic [P.FLEN-1:0]           PreFpResE, PreFpResM;               // selected result that is ready in the memory stage
   logic [P.FLEN-1:0]           FResultW;                           // final FP result being written to the FP register   
@@ -162,8 +174,16 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
   logic                        StallUnpackedM;                     // Stall unpacker outputs during multicycle fdivsqrt
   logic [P.FLEN-1:0]           SgnExtXE;                           // Sign-extended X input for move to integer
   logic                        mvsgn;                              // sign bit for extending move
-  logic [P.FLEN-1:0]           FliResE;                            // Floating-point load immediate value
-
+  logic [P.FLEN-1:0]           ZfaResE;                            // Result of Zfa fli or fround instruction
+  logic                        FRoundNVE, FRoundNXE;               // Zfa fround invalid and inexact flags
+
+  // Debug signals
+  logic                        FRegWriteWM;
+  logic [4:0]                  RA1;
+  logic [4:0]                  WA1;
+  logic [P.FLEN-1:0]           FResultWM;
+  logic [P.FLEN-1:0]           DebugFPRWriteD;
+   
   //////////////////////////////////////////////////////////////////////////////////////////
   // Decode Stage: fctrl decoder, read register file
   //////////////////////////////////////////////////////////////////////////////////////////
@@ -172,18 +192,31 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
   fctrl #(P) fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), 
               .IntDivE, .InstrD,
               .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
-              .reset, .clk, .FRegWriteE, .FRegWriteM, .FRegWriteW, .ZfaE, .ZfaM, .FrmM, .FmtE, .FmtM,
+              .reset, .clk, .FRegWriteE, .FRegWriteM, .FRegWriteW, .ZfaE, .ZfaM, .ZfaFRoundNXE, .FrmE, .FrmM, .FmtE, .FmtM,
               .FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .FpLoadStoreM,
               .IllegalFPUInstrD, .XEnD, .YEnD, .ZEnD, .XEnE, .YEnE, .ZEnE,
               .FResSelE, .FResSelM, .FResSelW, .FPUActiveE, .PostProcSelE, .PostProcSelM, .FCvtIntW, 
               .Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E);
-
+   
   // FP register file
-  fregfile #(P.FLEN) fregfile (.clk, .reset, .we4(FRegWriteW),
-    .a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), 
-    .a4(RdW), .wd4(FResultW),
-    .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D));  
-
+  // Access FPRs from Debug Module
+  if (P.DEBUG_SUPPORTED) begin
+    fregfile #(P.FLEN) fregfile (.clk, .reset, .we4(FRegWriteWM),
+      .a1(RA1), .a2(InstrD[24:20]), .a3(InstrD[31:27]), 
+      .a4(WA1), .wd4(FResultWM),
+      .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D));       
+    assign FRegWriteWM = DebugSel ? DebugRegUpdate : FRegWriteW;
+    assign RA1 = DebugSel ? DebugRegAddr : InstrD[19:15];
+    assign WA1 = DebugSel ? DebugRegAddr : RdW;
+    assign FResultWM = DebugSel ? DebugFPRWriteD : FResultW;
+    flopenrs #(P.FLEN) FPScanReg(.clk, .reset, .en(DebugCapture), .d(FRD1D), .q(DebugFPRWriteD), .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DebugScanOut));
+  end else begin
+    fregfile #(P.FLEN) fregfile (.clk, .reset, .we4(FRegWriteW),
+      .a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), 
+      .a4(RdW), .wd4(FResultW),
+      .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D));       
+  end
+   
   // D/E pipeline registers  
   flopenrc #(P.FLEN) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
   flopenrc #(P.FLEN) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
@@ -213,12 +246,11 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
                               {{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)}, 
                               {2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
   assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(PostProcSelE==2'b10);
-  // ***simplified from appearently redundant assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10);
   mux2  #(P.FLEN)  fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract
   
   // Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z
   // For add and subtract, Z comes from second source operand
-  if(P.FPSIZES == 1) assign BoxedZeroE = 0;
+  if(P.FPSIZES == 1) assign BoxedZeroE = '0;
   else if(P.FPSIZES == 2) 
     mux2 #(P.FLEN) fmulzeromux ({{P.FLEN-P.LEN1{1'b1}}, {P.LEN1{1'b0}}}, (P.FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
   else if(P.FPSIZES == 3 | P.FPSIZES == 4)
@@ -235,7 +267,7 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
     .XNaN(XNaNE), .YNaN(YNaNE), .ZNaN(ZNaNE), .XSNaN(XSNaNE), .XEn(XEnE), 
     .YSNaN(YSNaNE), .ZSNaN(ZSNaNE), .XSubnorm(XSubnormE), 
     .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .XInf(XInfE), .YInf(YInfE), 
-    .ZEn(ZEnE), .ZInf(ZInfE), .XExpMax(XExpMaxE), .XPostBox(XPostBoxE));
+    .ZEn(ZEnE), .ZInf(ZInfE), .XExpMax(XExpMaxE), .XPostBox(XPostBoxE), .Bias(BiasE), .Nf(NfE));
   
   // fused multiply add: fadd/sub, fmul, fmadd/fnmadd/fmsub/fnmsub
   fma #(P) fma (.Xs(XsE), .Ys(YsE), .Zs(ZsE), .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), 
@@ -244,7 +276,7 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
 
   // divide and square root: fdiv, fsqrt, optionally integer division
   fdivsqrt #(P) fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
-    .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE,
+    .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .BiasE, .NfE, .FDivStartE, .IDivStartE, .XsE,
     .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .IntDivE, .W64E,
     .StallM, .FlushE, .DivStickyM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .UeM, 
     .UmM, .FIntDivResultM);
@@ -267,15 +299,28 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
     .ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE), 
     .ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
 
-  // floating-point load immediate: fli
-  if (P.ZFA_SUPPORTED) begin
+  // ZFA: fround and floating-point load immediate fli
+  if (P.ZFA_SUPPORTED) begin:Zfa
     logic [4:0] Rs1E;
     logic [1:0] Fmt2E; // Two-bit format field from instruction
-    
+    logic [P.FLEN-1:0]           FRoundE;                            // Zfa fround output
+    logic [P.FLEN-1:0]           FliResE;                            // Zfa Floating-point load immediate value
+
+    // fround
+    fround #(P) fround(.Xs(XsE), .Xe(XeE), .Xm(XmE), 
+                       .XNaN(XNaNE), .XSNaN(XSNaNE), .Fmt(FmtE), .Frm(FrmE), .Nf(NfE), 
+                       .ZfaFRoundNX(ZfaFRoundNXE),
+                       .FRound(FRoundE), .FRoundNV(FRoundNVE), .FRoundNX(FRoundNXE));
+
+    // fli
     flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, InstrD[19:15], Rs1E);
     flopenrc #(2) Fmt2EReg(clk, reset, FlushE, ~StallE, InstrD[26:25], Fmt2E);
     fli #(P) fli(.Rs1(Rs1E), .Fmt(Fmt2E), .Imm(FliResE)); 
-  end else assign FliResE = 0;
+    mux2  #(P.FLEN) ZfaResMux(FRoundE, FliResE, OpCtrlE[0], ZfaResE);
+  end else begin
+    assign {FRoundNXE, FRoundNVE} = '0;
+    assign ZfaResE = 'x;
+  end
 
   // fmv.*.x: NaN Box SrcA to extend integer to requested FP size 
   if(P.FPSIZES == 1) 
@@ -299,8 +344,9 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
   else assign IntSrcE = PreIntSrcE;
 
   // select a result that may be written to the FP register
-  mux4  #(P.FLEN) FResMux(SgnResE, IntSrcE, CmpFpResE, FliResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE);
-  assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE);
+  mux4  #(P.FLEN) FResMux(SgnResE, IntSrcE, CmpFpResE, ZfaResE, {OpCtrlE[2], &OpCtrlE[1:0] | (OpCtrlE == 3'b100) & ZfaE}, PreFpResE);
+  assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE) | FRoundNVE & (OpCtrlE == 3'b100) & ZfaE;
+  assign PreNXE = FRoundNXE & (OpCtrlE == 3'b100);
 
   // fmv.x.*: select the result that may be written to the integer register
   if(P.FPSIZES == 1) begin
@@ -319,7 +365,7 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
 
   // sign extend to XLEN if necessary
   if (P.FLEN >= 2*P.XLEN)
-    if (P.ZFA_SUPPORTED & P.FLEN == 2*P.XLEN) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.*
+    if (P.ZFA_SUPPORTED) assign IntSrcXE = ZfaE ? XE[2*P.XLEN-1:P.XLEN] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.*
     else                                      assign IntSrcXE = SgnExtXE[P.XLEN-1:0];
   else 
     assign IntSrcXE = {{(P.XLEN-P.FLEN){mvsgn}}, SgnExtXE};
@@ -338,9 +384,9 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
   flopenr #(13) EMFpReg5 (clk, reset, ~StallUnpackedM, 
     {XsE, YsE, XZeroE, YZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
     {XsM, YsM, XZeroM, YZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});     
-  flopenrc #(1)  EMRegCmpFlg (clk, reset, FlushM, ~StallM, PreNVE, PreNVM);      
-  flopenrc #(3*P.NF+4) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);
-  flopenrc #($clog2(3*P.NF+5)+7+P.NE) EMRegFma4(clk, reset, FlushM, ~StallM,
+  flopenrc #(2)  EMRegCmpFlg (clk, reset, FlushM, ~StallM, {PreNVE, PreNXE}, {PreNVM, PreNXM});      
+  flopenrc #(P.FMALEN) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);
+  flopenrc #($clog2(P.FMALEN+1)+7+P.NE) EMRegFma4(clk, reset, FlushM, ~StallM,
     {FmaAStickyE, InvAE, SCntE, AsE, PsE, SsE, SeE},
     {FmaAStickyM, InvAM, SCntM, AsM, PsM, SsM, SeM});
   flopenrc #(P.NE+P.LOGCVTLEN+P.CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM, 
@@ -361,8 +407,7 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
     .PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM));
 
   // FPU flag selection - to privileged
-  //mux2  #(5)       FPUFlgMux({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM);
-  mux2  #(5)       FPUFlgMux({PreNVM, 4'b0}, PostProcFlgM, (FResSelM == 2'b01), SetFflagsM);
+  mux2  #(5)       FPUFlgMux({PreNVM, 3'b0, PreNXM}, PostProcFlgM, (FResSelM == 2'b01), SetFflagsM);
   mux2  #(P.FLEN)  FPUResMux(PreFpResM, PostProcResM, FResSelM[0], FpResM);
 
   // M/W pipe registers
diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv
index 38a9da25e..b2077829c 100644
--- a/src/fpu/fregfile.sv
+++ b/src/fpu/fregfile.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: 3R1W 4-port register file for FPU
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -34,21 +34,21 @@ module fregfile #(parameter FLEN) (
   input logic [FLEN-1:0]   wd4,             // write data
   output logic [FLEN-1:0]  rd1, rd2, rd3    // read data
 );
-   
-   logic [FLEN-1:0] rf[31:0];
-   integer i;
-   
-   // three ported register file
-   // read three ports combinationally (A1/RD1, A2/RD2, A3/RD3)
-   // write fourth port on rising edge of clock (A4/WD4/WE4)
-   // write occurs on falling edge of clock   
-   
-   always_ff @(negedge clk) // or posedge reset)
-     if (reset) for(i=0; i<32; i++) rf[i] <= 0;
-     else if (we4) rf[a4] <= wd4;  
-   
-   assign rd1 = rf[a1];
-   assign rd2 = rf[a2];
-   assign rd3 = rf[a3];
-   
+
+  logic [FLEN-1:0] rf[31:0];
+  integer i;
+
+  // three ported register file
+  // read three ports combinationally (A1/RD1, A2/RD2, A3/RD3)
+  // write fourth port on rising edge of clock (A4/WD4/WE4)
+  // write occurs on falling edge of clock
+
+  always_ff @(negedge clk) // or posedge reset)
+    if (reset) for(i=0; i<32; i++) rf[i] <= '0;
+    else if (we4) rf[a4] <= wd4;
+
+  assign rd1 = rf[a1];
+  assign rd2 = rf[a2];
+  assign rd3 = rf[a3];
+
 endmodule // regfile
diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv
new file mode 100644
index 000000000..3265ec626
--- /dev/null
+++ b/src/fpu/fround.sv
@@ -0,0 +1,152 @@
+///////////////////////////////////////////
+// fround.sv
+//
+// Written: David_Harris@hmc.edu
+// Modified: 4/21/2024
+//
+// Purpose: Floating-point round to integer for Zfa
+// 
+// Documentation: RISC-V System on Chip Design
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module fround import cvw::*;  #(parameter cvw_t P) (
+  input  logic                    Xs,           // input's sign
+  input  logic [P.NE-1:0]         Xe,           // input's exponent
+  input  logic [P.NF:0]           Xm,           // input's fraction with leading integer bit (U1.NF)
+  input  logic                    XNaN,         // X is NaN
+  input  logic                    XSNaN,        // X is Signalling NaN
+  input  logic [P.FMTBITS-1:0]    Fmt,          // the input's precision (11=quad 01=double 00=single 10=half)
+  input  logic [2:0]              Frm,          // rounding mode
+  input  logic [P.LOGFLEN-1:0]    Nf,           // Number of fractional bits in selected format
+  input  logic                    ZfaFRoundNX,  // froundnx instruction can set inexact flag
+  output logic [P.FLEN-1:0]       FRound,       // Rounded result
+  output logic                    FRoundNV,     // fround invalid
+  output logic                    FRoundNX      // fround inexact
+);
+
+  logic [P.NE-1:0] E, Xep1;
+  logic [P.NF:0] IMask, Tmasknonneg, Tmaskneg, Tmask, HotE, HotEP1, Trunc, Rnd;
+  logic [P.FLEN-1:0] W;
+  logic Elt0, Eeqm1, Lnonneg, Lp, Rnonneg, Rp, Tp, RoundUp, Two, EgeNf;
+
+  // Unbiased exponent
+  assign E = Xe - P.BIAS[P.NE-1:0];
+  assign Xep1 = Xe + 1'b1;
+
+  //////////////////////////////////////////
+  // Compute LSB L', rounding bit R' and Sticky bit T'
+  //      if (E < 0)					// negative exponents round to 0 or 1.
+  //              L' = 0      // LSB = 0
+  //              if (E = -1) R' = 1, TMask = 0.1111...111	// if (E = -1) 0.5  X < 1.  Round bit is 1
+  //              else R' = 0; TMask = 1.1111...111  	// if (E < -1), X < 0.5.  Round bit is 0
+  //      else					// positive exponents truncate fraction and may add 1
+  //              IMask = 1.0000…000 >>> E  		// (in U1.Nf form); implies thermometer code generator
+  //              TMask = ~(IMask >>> 1) 			// 0.01111…111 >> E
+  //              HotE = IMask & ~(IMask << 1) 		// a 1 in column E, where 0 is the integer bit, 
+ 	//				// 1 is the most significant fractional bit, etc.
+  //              HotEP1 = HotE >> 1			// a 1 in column E+1
+  //              L' = OR(Xm & HotE) 			// Xm[E], where Xm[0] is the integer bit, 
+ 	//				// Xm[1] is the most significant fractional bit, etc.
+  //              R' = OR(Xm & HotEP1)			// Xm[E+1] 
+  //              TRUNC = Xm & IMask			// Truncated fraction, corresponds to truncated integer value
+  //              RND =  TRUNC + HotE 			// TRUNC + (1 >> E), corresponds to next integer
+  //      T' = OR(Xm & TMask)				// T’ = OR(Xm[E+2:Nf]) if E >= 0, OR(Xf) if E = -1, 1 if E < -1
+  //////////////////////////////////////////
+
+  // Check if exponent is negative and -1
+  assign Elt0 = E[P.NE-1]; // (E < 0);
+  assign Eeqm1 = ($signed(E) == -1);
+
+  // Logic for nonnegative mask and rounding bits
+  assign IMask = {1'b1, {P.NF{1'b0}}} >>> E; /// if E > Nf, this produces all 0s instead of all 1s.  Hence exact handling is needed below.
+  assign Tmasknonneg = ~IMask >>> 1'b1;
+  assign HotE = IMask & ~(IMask << 1'b1);
+  assign HotEP1 = HotE >> 1'b1;
+  assign Lnonneg = |(Xm & HotE);
+  assign Rnonneg = |(Xm & HotEP1);
+  assign Trunc = Xm & IMask;
+  assign {Two, Rnd} = Trunc + HotE; // Two means result overflowed to 10.000000 = 2.0
+
+  // mux and AND-OR logic to select final rounding bits
+  mux2 #(1) Lmux(Lnonneg, 1'b0, Elt0, Lp);
+  mux2 #(1) Rmux(Rnonneg, Eeqm1, Elt0, Rp);
+  assign Tmaskneg = {~Eeqm1, {P.NF{1'b1}}}; // 1.11111 or 0.11111
+  mux2 #(P.NF+1) Tmaskmux(Tmasknonneg, Tmaskneg, Elt0, Tmask);
+  assign Tp = |(Xm & Tmask);
+
+  ///////////////////////////
+  // Rounding, flags, special Cases 
+  //      Flags = 0						// unless overridden later
+  //      if (X is NaN)
+  //              W = Canonical NaN
+  //              Invalid = (X is signaling NaN)
+  //      else if (E >= Nf) 
+  //              W = X						// is exact; this also handles infinity
+  //      else 
+  //              RoundUp = RoundingLogic(Xs, L', R', T', rm)	// Table 16.4
+  //              if (E < 0) 					// 0 <= X < 1 rounds to 0 or 1
+  //                      if (RoundUp)     {Ws, We, Wf} = {Xs, bias, 0}	// +/- 1.0
+  //                     else                    {Ws, We, Wf} = {Xs, 0, 0}	// +/- 0
+  //              else //						// X >= 1 rounds to an integer or overflows to infinity
+  //                     if (RoundUp) Rm = RND else Rm = TRUNC	// Round up to RND or down to TRUNC
+  //                     if (Rm = 2.0)					// rounding requires incrementing exponent
+  //                             if (Xe = emax) {Ws, We, Wf} = {Xs, 111..11, 0} 	// overflow to W = Infinity with sign of Xs
+  //                             else	        {Ws, We, Wf} = {Xs, Xe+1, 0}	// 1.0 x 2E+1
+  //                     else                      {Ws, We, Wf} = {Xs, Xe, Rf}	// Rounded fraction, retain sign and exponent
+  //              If (FroundNX instruction) Inexact = R' | T'
+  ///////////////////////////
+
+  // Exact logic
+  // verilator lint_off WIDTHEXPAND
+  assign EgeNf = (E >= Nf) & Xe[P.NE-1]; // Check if E >= Nf.  Also check that Xe is positive to avoid wraparound problems
+  // verilator lint_on WIDTHEXPAND
+
+  // Rounding logic: determine whether to round up in magnitude
+  always_comb begin
+    case (Frm) // Frm is either specified in the instruction or is the dynamic rounding mode
+      3'b000:  RoundUp = Rp & (Lp | Tp);  // RNE
+      3'b001:  RoundUp = 0;               // RZ
+      3'b010:  RoundUp = Xs & (Rp | Tp);  // RN
+      3'b011:  RoundUp = ~Xs & (Rp | Tp); // RP
+      3'b101:  RoundUp = Rp;              // RNTA
+      default: RoundUp = 0;               // should never happen
+    endcase
+
+    // If result is not exact, select output in unpacked FLEN format initially
+    if (XNaN)            W = {1'b0, {P.NE{1'b1}}, 1'b1, {(P.NF-1){1'b0}}};  // Canonical NaN
+    else if (EgeNf)      W = {Xs, Xe, Xm[P.NF-1:0]};                        // Exact, no rounding needed
+    else if (Elt0)                                                          // 0 <= |X| < 1 rounds to 0 or 1
+      if (RoundUp)       W = {Xs, P.BIAS[P.NE-1:0], {P.NF{1'b0}}};          //   round to +/- 1
+      else               W = {Xs, {(P.FLEN-1){1'b0}}};                      //   round to +/- 0
+    else begin                                                              // |X| >= 1 rounds to an integer
+      if (RoundUp & Two) W = {Xs, Xep1, {(P.NF){1'b0}}};                    //   Round up to 2.0
+      else if (RoundUp)  W = {Xs, Xe, Rnd[P.NF-1:0]};                       //   Round up to Rnd
+      else               W = {Xs, Xe, Trunc[P.NF-1:0]};                     //   Round down to Trunc
+    end
+  end
+
+  packoutput #(P) packoutput(W, Fmt, FRound); // pack and NaN-box based on selected format.
+
+  // Flags
+  assign FRoundNV = XSNaN;                               // invalid if input is signaling NaN
+  assign FRoundNX = ZfaFRoundNX & ~EgeNf & (Rp | Tp);    // Inexact if Round or Sticky bit set for FRoundNX instruction
+
+endmodule
diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv
index 4fe03522b..68e2eb493 100755
--- a/src/fpu/fsgninj.sv
+++ b/src/fpu/fsgninj.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: FPU Sign Injection instructions
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/packoutput.sv b/src/fpu/packoutput.sv
new file mode 100644
index 000000000..e83f403c5
--- /dev/null
+++ b/src/fpu/packoutput.sv
@@ -0,0 +1,103 @@
+
+///////////////////////////////////////////
+// packoutput.sv
+//
+// Written: David_Harris@hmc.edu
+// Modified: 5/11/24
+//
+// Purpose: Pack the output of the FPU
+// 
+// Documentation: RISC-V System on Chip Design
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module packoutput import cvw::*;  #(parameter cvw_t P) (
+  input  logic [P.FLEN-1:0]       Unpacked,
+  input  logic [P.FMTBITS-1:0]    Fmt,
+  output logic [P.FLEN-1:0]       Packed
+);
+
+  logic             Sign; 
+  logic [P.NE1-1:0] Exp1;
+  logic [P.NF1-1:0] Fract1;
+  logic [P.NE2-1:0] Exp2;
+  logic [P.NF2-1:0] Fract2;
+  logic [P.H_NE-1:0] Exp3;
+  logic [P.H_NF-1:0] Fract3;
+
+  // Pack exponent and fraction, with NaN-boxing to full FLEN
+
+  assign Sign = Unpacked[P.FLEN-1];
+  if (P.FPSIZES == 1) begin
+    assign Packed = Unpacked;
+  end else if (P.FPSIZES == 2) begin
+    always_comb begin
+      {Exp1, Fract1} = '0; // default if not used, to prevent latch
+      case (Fmt)
+        1'b1: Packed = Unpacked;
+        1'b0: begin
+                Exp1 = {Unpacked[P.FLEN-2], Unpacked[P.NF+P.NE1-2:P.NF]};
+                Fract1 = Unpacked[P.NF-1:P.NF-P.NF1];
+                Packed = {{(P.FLEN-P.LEN1){1'b1}}, Sign, Exp1, Fract1}; 
+              end
+      endcase
+    end
+  end else if (P.FPSIZES == 3) begin
+    always_comb begin
+      {Exp1, Fract1, Exp2, Fract2} = '0; // default if not used, to prevent latch
+      case (Fmt)
+        P.FMT: Packed = Unpacked;
+        P.FMT1: begin
+                Exp1 = {Unpacked[P.FLEN-2], Unpacked[P.NF+P.NE1-2:P.NF]};
+                Fract1 = Unpacked[P.NF-1:P.NF-P.NF1];
+                Packed = {{(P.FLEN-P.LEN1){1'b1}}, Sign, Exp1, Fract1}; 
+              end
+        P.FMT2: begin
+                Exp2 = {Unpacked[P.FLEN-2], Unpacked[P.NF+P.NE2-2:P.NF]};
+                Fract2 = Unpacked[P.NF-1:P.NF-P.NF2];
+                Packed = {{(P.FLEN-P.LEN2){1'b1}}, Sign, Exp2, Fract2}; 
+              end
+        default: Packed = 'x;
+      endcase
+    end
+  end else if (P.FPSIZES == 4) begin        
+    always_comb begin
+      {Exp1, Fract1, Exp2, Fract2, Exp3, Fract3} = '0; // default if not used, to prevent latch
+      case (Fmt)
+        2'h3: Packed = Unpacked;  // Quad
+        2'h1: begin // double
+                Exp1 = {Unpacked[P.FLEN-2], Unpacked[P.NF+P.NE1-2:P.NF]};
+                Fract1 = Unpacked[P.NF-1:P.NF-P.NF1];
+                Packed = {{(P.FLEN-P.LEN1){1'b1}}, Sign, Exp1, Fract1}; 
+              end
+        2'h0: begin // float
+                Exp2 = {Unpacked[P.FLEN-2], Unpacked[P.NF+P.NE2-2:P.NF]};
+                Fract2 = Unpacked[P.NF-1:P.NF-P.NF2];
+                Packed = {{(P.FLEN-P.LEN2){1'b1}}, Sign, Exp2, Fract2}; 
+              end
+        2'h2: begin // half
+                Exp3 = {Unpacked[P.FLEN-2], Unpacked[P.NF+P.H_NE-2:P.NF]};
+                Fract3 = Unpacked[P.NF-1:P.NF-P.H_NF];
+                Packed = {{(P.FLEN-P.H_LEN){1'b1}}, Sign, Exp3, Fract3}; 
+              end
+      endcase
+    end
+  end
+endmodule
diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv
index 8b7587e49..84f5120a0 100644
--- a/src/fpu/postproc/cvtshiftcalc.sv
+++ b/src/fpu/postproc/cvtshiftcalc.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Conversion shift calculation
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -83,7 +83,7 @@ module cvtshiftcalc import cvw::*;  #(parameter cvw_t P) (
               P.FMT:  ResNegNF  = -($clog2(P.NF)+1)'(P.NF);
               P.FMT1: ResNegNF  = -($clog2(P.NF)+1)'(P.NF1);
               P.FMT2: ResNegNF  = -($clog2(P.NF)+1)'(P.NF2);
-              default: ResNegNF = 0; // Not used for floating-point so don't care, but convert to unsigned long has OutFmt = 11.
+              default: ResNegNF = '0; // Not used for floating-point so don't care, but convert to unsigned long has OutFmt = 11.
           endcase
 
   end else if (P.FPSIZES == 4) begin        
diff --git a/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv
index b0335c780..d46b58f35 100644
--- a/src/fpu/postproc/divshiftcalc.sv
+++ b/src/fpu/postproc/divshiftcalc.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Division shift calculation
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -28,10 +28,8 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module divshiftcalc import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.DIVb:0]              DivUm,              // divsqrt significand
   input  logic [P.NE+1:0]              DivUe,              // divsqrt exponent
   output logic [P.LOGNORMSHIFTSZ-1:0]  DivShiftAmt,        // divsqrt shift amount
-  output logic [P.NORMSHIFTSZ-1:0]     DivShiftIn,         // divsqrt shift input
   output logic                         DivResSubnorm,      // is the divsqrt result subnormal
   output logic                         DivSubnormShiftPos  // is the subnormal shift amount positive
 );
@@ -65,9 +63,7 @@ module divshiftcalc import cvw::*;  #(parameter cvw_t P) (
 
   // if the shift amount is negative then don't shift (keep sticky bit)
   // need to multiply the early termination shift by LOGR*DIVCOPIES =  left shift of log2(LOGR*DIVCOPIES)
-  assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : 0;
+  assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : '0;
   assign DivShiftAmt        = DivResSubnorm ? DivSubnormShiftAmt : NormShift;
 
-  // pre-shift the divider result for normalization
-  assign DivShiftIn = {{P.NF{1'b0}}, DivUm, {P.NORMSHIFTSZ-P.DIVb-1-P.NF{1'b0}}};
 endmodule
diff --git a/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv
index cb16cc2a1..be28a490c 100644
--- a/src/fpu/postproc/flags.sv
+++ b/src/fpu/postproc/flags.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Post-Processing flag calculation
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv
index d6d9cec15..22c354e30 100644
--- a/src/fpu/postproc/fmashiftcalc.sv
+++ b/src/fpu/postproc/fmashiftcalc.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: FMA shift calculation
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -28,18 +28,17 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module fmashiftcalc import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.FMTBITS-1:0]         Fmt,                 // precision 1 = double 0 = single
-  input  logic [P.NE+1:0]              FmaSe,               // sum's exponent
-  input  logic [3*P.NF+3:0]            FmaSm,               // the positive sum
-  input  logic [$clog2(3*P.NF+5)-1:0]  FmaSCnt,             // normalization shift count
-  output logic [P.NE+1:0]              NormSumExp,          // exponent of the normalized sum not taking into account Subnormal or zero results
-  output logic                         FmaSZero,            // is the result subnormal - calculated before LZA corection
-  output logic                         FmaPreResultSubnorm, // is the result subnormal - calculated before LZA corection
-  output logic [$clog2(3*P.NF+5)-1:0]  FmaShiftAmt,         // normalization shift count
-  output logic [3*P.NF+5:0]            FmaShiftIn           // is the sum zero
+  input  logic [P.FMTBITS-1:0]          Fmt,                 // precision 1 = double 0 = single
+  input  logic [P.NE+1:0]               FmaSe,               // sum's exponent
+  input  logic [P.FMALEN-1:0]           FmaSm,               // the positive sum
+  input  logic [$clog2(P.FMALEN+1)-1:0] FmaSCnt,             // normalization shift count
+  output logic [P.NE+1:0]               NormSumExp,          // exponent of the normalized sum not taking into account Subnormal or zero results
+  output logic                          FmaSZero,            // is the sum zero
+  output logic                          FmaPreResultSubnorm, // is the result subnormal - calculated before LZA corection
+  output logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt          // normalization shift count
 );
-  logic [P.NE+1:0]                     PreNormSumExp;       // the exponent of the normalized sum with the P.FLEN bias
-  logic [P.NE+1:0]                     BiasCorr;            // correction for bias
+  logic [P.NE+1:0]                      PreNormSumExp;       // the exponent of the normalized sum with the P.FLEN bias
+  logic [P.NE+1:0]                      BiasCorr;            // correction for bias
 
   ///////////////////////////////////////////////////////////////////////////////
   // Normalization
@@ -48,19 +47,20 @@ module fmashiftcalc import cvw::*;  #(parameter cvw_t P) (
   // Determine if the sum is zero
   assign FmaSZero = ~(|FmaSm);
 
-  // calculate the sum's exponent
-  assign PreNormSumExp = FmaSe + {{P.NE+2-$unsigned($clog2(3*P.NF+5)){1'b1}}, ~FmaSCnt} + (P.NE+2)'(P.NF+3);
+  // calculate the sum's exponent FmaSe-FmaSCnt+NF+2
+  assign PreNormSumExp = FmaSe + {{P.NE+2-$unsigned($clog2(P.FMALEN+1)){1'b1}}, ~FmaSCnt} + (P.NE+2)'(P.NF+4);
 
   //convert the sum's exponent into the proper precision
   if (P.FPSIZES == 1) begin
     assign NormSumExp = PreNormSumExp;
+    assign BiasCorr = '0;
   end else if (P.FPSIZES == 2) begin
     assign BiasCorr = Fmt ? (P.NE+2)'(0) : (P.NE+2)'(P.BIAS1-P.BIAS);
     assign NormSumExp = PreNormSumExp+BiasCorr;
   end else if (P.FPSIZES == 3) begin
     always_comb begin
         case (Fmt)
-            P.FMT:   BiasCorr =  0;
+            P.FMT:   BiasCorr =  '0;
             P.FMT1:  BiasCorr = (P.NE+2)'(P.BIAS1-P.BIAS);
             P.FMT2:  BiasCorr = (P.NE+2)'(P.BIAS2-P.BIAS);
             default: BiasCorr = 'x;
@@ -70,7 +70,7 @@ module fmashiftcalc import cvw::*;  #(parameter cvw_t P) (
   end else if (P.FPSIZES == 4) begin
     always_comb begin
         case (Fmt)
-            2'h3: BiasCorr = 0;
+            2'h3: BiasCorr = '0;
             2'h1: BiasCorr = (P.NE+2)'(P.D_BIAS-P.Q_BIAS);
             2'h0: BiasCorr = (P.NE+2)'(P.S_BIAS-P.Q_BIAS);
             2'h2: BiasCorr = (P.NE+2)'(P.H_BIAS-P.Q_BIAS);
@@ -79,19 +79,19 @@ module fmashiftcalc import cvw::*;  #(parameter cvw_t P) (
     assign NormSumExp = PreNormSumExp+BiasCorr;
   end
   
-  // determine if the result is subnormal: (NormSumExp <= 0) & (NormSumExp >= -FracLen) & ~FmaSZero
+  // determine if the result is subnormal: (NormSumExp <= 0) & (NormSumExp >= -FracLen)
   if (P.FPSIZES == 1) begin
     logic Sum0LEZ, Sum0GEFL;
     assign Sum0LEZ  = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
     assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655
-    assign FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
+    assign FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL;
   end else if (P.FPSIZES == 2) begin
     logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL;
     assign Sum0LEZ  = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
     assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655
     assign Sum1LEZ  = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1));
     assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-1+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
-    assign FmaPreResultSubnorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL) & ~FmaSZero;
+    assign FmaPreResultSubnorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL);
   end else if (P.FPSIZES == 3) begin
     logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL;
     assign Sum0LEZ  = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
@@ -102,9 +102,9 @@ module fmashiftcalc import cvw::*;  #(parameter cvw_t P) (
     assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-1+P.BIAS-P.BIAS2)) | ~|PreNormSumExp;
     always_comb begin
       case (Fmt)
-        P.FMT: FmaPreResultSubnorm   = Sum0LEZ & Sum0GEFL; // & ~FmaSZero; // checking sum is not zero is harmless but turns out to be unnecessary
-        P.FMT1: FmaPreResultSubnorm  = Sum1LEZ & Sum1GEFL; // & ~FmaSZero;
-        P.FMT2: FmaPreResultSubnorm  = Sum2LEZ & Sum2GEFL; // & ~FmaSZero; 
+        P.FMT: FmaPreResultSubnorm   = Sum0LEZ & Sum0GEFL;
+        P.FMT1: FmaPreResultSubnorm  = Sum1LEZ & Sum1GEFL;
+        P.FMT2: FmaPreResultSubnorm  = Sum2LEZ & Sum2GEFL;
         default: FmaPreResultSubnorm = 1'bx;
       endcase
     end
@@ -120,17 +120,15 @@ module fmashiftcalc import cvw::*;  #(parameter cvw_t P) (
     assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.H_NF-1+P.BIAS-P.H_BIAS)) | ~|PreNormSumExp;
     always_comb begin
       case (Fmt)
-        2'h3: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
-        2'h1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL & ~FmaSZero;
-        2'h0: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL & ~FmaSZero;
-        2'h2: FmaPreResultSubnorm = Sum3LEZ & Sum3GEFL & ~FmaSZero;
+        2'h3: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL;
+        2'h1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL;
+        2'h0: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL;
+        2'h2: FmaPreResultSubnorm = Sum3LEZ & Sum3GEFL;
       endcase
     end
   end
 
   // set and calculate the shift input and amount
   //  - shift once if killing a product and the result is subnormal
-  assign FmaShiftIn = {2'b0, FmaSm};
-  if (P.FPSIZES == 1) assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(3*P.NF+5)-1:0]+($clog2(3*P.NF+5))'(P.NF+2): FmaSCnt+1;
-  else                assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(3*P.NF+5)-1:0]+($clog2(3*P.NF+5))'(P.NF+2)+BiasCorr[$clog2(3*P.NF+5)-1:0]: FmaSCnt+1;
+  assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(P.FMALEN-1)-1:0]+($clog2(P.FMALEN-1))'(P.NF+3)+BiasCorr[$clog2(P.FMALEN-1)-1:0]: FmaSCnt+1;
 endmodule
diff --git a/src/fpu/postproc/negateintres.sv b/src/fpu/postproc/negateintres.sv
index 5ca848b0b..b9cb038a4 100644
--- a/src/fpu/postproc/negateintres.sv
+++ b/src/fpu/postproc/negateintres.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Negate integer result
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/postproc/normshift.sv b/src/fpu/postproc/normshift.sv
index f235d4d5b..d0a14cbfd 100644
--- a/src/fpu/postproc/normshift.sv
+++ b/src/fpu/postproc/normshift.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: normalization shifter
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv
index 17dda38a0..f4f7c2b5b 100644
--- a/src/fpu/postproc/postprocess.sv
+++ b/src/fpu/postproc/postprocess.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Post-Processing: normalization, rounding, sign, flags, special cases
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -44,9 +44,9 @@ module postprocess import cvw::*;  #(parameter cvw_t P) (
   input logic                              FmaPs,               // the product's sign
   input logic                              FmaSs,               // Sum sign
   input logic  [P.NE+1:0]                  FmaSe,               // the sum's exponent
-  input logic  [3*P.NF+3:0]                FmaSm,               // the positive sum
+  input logic  [P.FMALEN-1:0]              FmaSm,               // the positive sum
   input logic                              FmaASticky,          // sticky bit that is calculated during alignment
-  input logic  [$clog2(3*P.NF+5)-1:0]      FmaSCnt,             // the normalization shift count
+  input logic  [$clog2(P.FMALEN+1)-1:0]      FmaSCnt,             // the normalization shift count
   //divide signals
   input logic                              DivSticky,           // divider sticky bit
   input logic  [P.NE+1:0]                  DivUe,               // divsqrt exponent
@@ -70,8 +70,8 @@ module postprocess import cvw::*;  #(parameter cvw_t P) (
   logic                        Rs;                   // result sign
   logic [P.NF-1:0]             Rf;                   // Result fraction
   logic [P.NE-1:0]             Re;                   // Result exponent
-  logic                        Ms;                   // norMalized sign
-  logic [P.CORRSHIFTSZ-1:0]    Mf;                   // norMalized fraction
+  logic                        Ms;                   // normalized sign
+  logic [P.NORMSHIFTSZ-1:0]    Mf;                   // normalized fraction
   logic [P.NE+1:0]             Me;                   // normalized exponent
   logic [P.NE+1:0]             FullRe;               // Re with bits to determine sign and overflow
   logic                        UfPlus1;              // do you add one (for determining underflow flag)
@@ -86,13 +86,11 @@ module postprocess import cvw::*;  #(parameter cvw_t P) (
   // fma signals
   logic [P.NE+1:0]             FmaMe;                // exponent of the normalized sum
   logic                        FmaSZero;             // is the sum zero
-  logic [3*P.NF+5:0]           FmaShiftIn;           // fma shift input
   logic [P.NE+1:0]             NormSumExp;           // exponent of the normalized sum not taking into account Subnormal or zero results
   logic                        FmaPreResultSubnorm;  // is the result subnormal - calculated before LZA corection
-  logic [$clog2(3*P.NF+5)-1:0] FmaShiftAmt;          // normalization shift amount for fma
+  logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt;          // normalization shift amount for fma
   // division signals
   logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt;          // divsqrt shif amount
-  logic [P.NORMSHIFTSZ-1:0]    DivShiftIn;           // divsqrt shift input
   logic [P.NE+1:0]             Ue;                   // divsqrt corrected exponent after corretion shift
   logic                        DivByZero;            // divide by zero flag
   logic                        DivResSubnorm;        // is the divsqrt result subnormal
@@ -136,6 +134,7 @@ module postprocess import cvw::*;  #(parameter cvw_t P) (
       assign OutFmt = IntToFp|~CvtOp ? Fmt : (OpCtrl[1:0] == P.FMT); 
   else if (P.FPSIZES == 3 | P.FPSIZES == 4) 
       assign OutFmt = IntToFp|~CvtOp ? Fmt : OpCtrl[1:0]; 
+  else assign OutFmt = 0; // FPSIZES = 1
 
   ///////////////////////////////////////////////////////////////////////////////
   // Normalization
@@ -145,25 +144,25 @@ module postprocess import cvw::*;  #(parameter cvw_t P) (
   cvtshiftcalc #(P) cvtshiftcalc(.ToInt, .CvtCe, .CvtResSubnormUf, .Xm, .CvtLzcIn,  
       .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
 
-  fmashiftcalc #(P) fmashiftcalc(.FmaSm, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe,
-      .FmaSZero, .FmaPreResultSubnorm, .FmaShiftAmt, .FmaShiftIn);
+  fmashiftcalc #(P) fmashiftcalc(.FmaSCnt, .Fmt, .NormSumExp, .FmaSe, .FmaSm,
+      .FmaSZero, .FmaPreResultSubnorm, .FmaShiftAmt);
 
-  divshiftcalc #(P) divshiftcalc(.DivUe, .DivUm, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt, .DivShiftIn);
+  divshiftcalc #(P) divshiftcalc(.DivUe, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt);
 
   // select which unit's output to shift
   always_comb
     case(PostProcSel)
       2'b10: begin // fma
-        ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(3*P.NF+5){1'b0}}, FmaShiftAmt};
-        ShiftIn  =  {FmaShiftIn, {P.NORMSHIFTSZ-(3*P.NF+6){1'b0}}};
+        ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.FMALEN-1){1'b0}}, FmaShiftAmt};
+        ShiftIn  =  {{2'b00, FmaSm}, {P.NORMSHIFTSZ-(P.FMALEN+2){1'b0}}};
       end
       2'b00: begin // cvt
         ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.CVTLEN+1){1'b0}}, CvtShiftAmt};
-        ShiftIn  =  {CvtShiftIn, {P.NORMSHIFTSZ-P.CVTLEN-P.NF-1{1'b0}}};
+        ShiftIn  =  {CvtShiftIn, {P.NORMSHIFTSZ-(P.CVTLEN+P.NF+1){1'b0}}};
       end
       2'b01: begin //divsqrt
         ShiftAmt = DivShiftAmt;
-        ShiftIn  =  DivShiftIn;
+        ShiftIn  = {{P.NF{1'b0}}, DivUm, {P.NORMSHIFTSZ-(P.DIVb+1+P.NF){1'b0}}};
       end
       default: begin 
         ShiftAmt = {P.LOGNORMSHIFTSZ{1'bx}}; 
diff --git a/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv
index 69f25a2b0..9425ec7ee 100644
--- a/src/fpu/postproc/resultsign.sv
+++ b/src/fpu/postproc/resultsign.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: calculating the result's sign
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv
index 9e2de2320..4c6d251fb 100644
--- a/src/fpu/postproc/round.sv
+++ b/src/fpu/postproc/round.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Rounder
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -32,7 +32,7 @@ module round import cvw::*;  #(parameter cvw_t P) (
   input  logic [2:0]               Frm,                // rounding mode
   input  logic [1:0]               PostProcSel,        // select the postprocessor output
   input  logic                     Ms,                 // normalized sign
-  input  logic [P.CORRSHIFTSZ-1:0] Mf,                 // normalized fraction
+  input  logic [P.NORMSHIFTSZ-1:0] Mf,                 // normalized fraction
   // fma
   input  logic                     FmaOp,              // is an fma operation being done?
   input  logic [P.NE+1:0]          FmaMe,              // exponent of the normalized sum for fma
@@ -123,61 +123,61 @@ module round import cvw::*;  #(parameter cvw_t P) (
       //      |    NF     |1|1|
       //                     ^    ^ if floating point result
       //                     ^ if not an FMA result
-      if (XLENPOS == 1)assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes)  |
-                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:0]);
+      if (XLENPOS == 1)assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes)  |
+                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:0]);
       //     2: NF > XLEN
-      if (XLENPOS == 2)assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF-1]&IntRes) |
-                                                (|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
+      if (XLENPOS == 2)assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.NF-1]&IntRes) |
+                                                (|Mf[P.NORMSHIFTSZ-P.NF-2:0]);
 
   end else if (P.FPSIZES == 2) begin
       // XLEN is either 64 or 32
       // so half and single are always smaller then XLEN
 
       // 1: XLEN > NF   > NF1
-      if (XLENPOS == 1) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&FpRes&~OutFmt) |
-                                                (|Mf[P.CORRSHIFTSZ-P.NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes) |
-                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:0]);
+      if (XLENPOS == 1) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.NF-1]&FpRes&~OutFmt) |
+                                                (|Mf[P.NORMSHIFTSZ-P.NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes) |
+                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:0]);
       // 2: NF   > XLEN > NF1
-      if (XLENPOS == 2) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&~OutFmt) | 
-                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF-1]&(IntRes|~OutFmt)) |
-                                                (|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
+      if (XLENPOS == 2) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&~OutFmt) | 
+                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.NF-1]&(IntRes|~OutFmt)) |
+                                                (|Mf[P.NORMSHIFTSZ-P.NF-2:0]);
       // 3: NF   > NF1  > XLEN
-      if (XLENPOS == 3) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF1-1]&IntRes) |
-                                                (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&(~OutFmt|IntRes)) |
-                                                (|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
+      if (XLENPOS == 3) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.NF1-1]&IntRes) |
+                                                (|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.NF-1]&(~OutFmt|IntRes)) |
+                                                (|Mf[P.NORMSHIFTSZ-P.NF-2:0]);
 
   end else if (P.FPSIZES == 3) begin
       // 1: XLEN > NF   > NF1
-      if (XLENPOS == 1) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) |
-                                                (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&FpRes&~(OutFmt==P.FMT)) |
-                                                (|Mf[P.CORRSHIFTSZ-P.NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes) |
-                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:0]);
+      if (XLENPOS == 1) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF2-2:P.NORMSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) |
+                                                (|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.NF-1]&FpRes&~(OutFmt==P.FMT)) |
+                                                (|Mf[P.NORMSHIFTSZ-P.NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes) |
+                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:0]);
       // 2: NF   > XLEN > NF1
-      if (XLENPOS == 2) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) |
-                                                (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&~(OutFmt==P.FMT)) | 
-                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF-1]&(IntRes|~(OutFmt==P.FMT))) |
-                                                (|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
+      if (XLENPOS == 2) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF2-2:P.NORMSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) |
+                                                (|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&~(OutFmt==P.FMT)) | 
+                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.NF-1]&(IntRes|~(OutFmt==P.FMT))) |
+                                                (|Mf[P.NORMSHIFTSZ-P.NF-2:0]);
       // 3: NF   > NF1  > XLEN
-      if (XLENPOS == 3) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&(OutFmt==P.FMT2)) |
-                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF1-1]&((OutFmt==P.FMT2)|IntRes)) |
-                                                (|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&(~(OutFmt==P.FMT)|IntRes)) |
-                                                (|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
+      if (XLENPOS == 3) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.NF2-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&(OutFmt==P.FMT2)) |
+                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.NF1-1]&((OutFmt==P.FMT2)|IntRes)) |
+                                                (|Mf[P.NORMSHIFTSZ-P.NF1-2:P.NORMSHIFTSZ-P.NF-1]&(~(OutFmt==P.FMT)|IntRes)) |
+                                                (|Mf[P.NORMSHIFTSZ-P.NF-2:0]);
 
   end else if (P.FPSIZES == 4) begin
       // Quad precision will always be greater than XLEN
       // 2: NF   > XLEN > NF1
-      if (XLENPOS == 2) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.H_NF-2:P.CORRSHIFTSZ-P.S_NF-1]&FpRes&(OutFmt==P.H_FMT)) |
-                                                (|Mf[P.CORRSHIFTSZ-P.S_NF-2:P.CORRSHIFTSZ-P.D_NF-1]&FpRes&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT))) | 
-                                                (|Mf[P.CORRSHIFTSZ-P.D_NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&~(OutFmt==P.Q_FMT)) | 
-                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.Q_NF-1]&(~(OutFmt==P.Q_FMT)|IntRes)) |
-                                                (|Mf[P.CORRSHIFTSZ-P.Q_NF-2:0]);
+      if (XLENPOS == 2) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.H_NF-2:P.NORMSHIFTSZ-P.S_NF-1]&FpRes&(OutFmt==P.H_FMT)) |
+                                                (|Mf[P.NORMSHIFTSZ-P.S_NF-2:P.NORMSHIFTSZ-P.D_NF-1]&FpRes&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT))) | 
+                                                (|Mf[P.NORMSHIFTSZ-P.D_NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&~(OutFmt==P.Q_FMT)) | 
+                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.Q_NF-1]&(~(OutFmt==P.Q_FMT)|IntRes)) |
+                                                (|Mf[P.NORMSHIFTSZ-P.Q_NF-2:0]);
       // 3: NF   > NF1  > XLEN
       // The extra XLEN bit will be ored later when caculating the final sticky bit - the ufplus1 not needed for integer
-      if (XLENPOS == 3) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.H_NF-2:P.CORRSHIFTSZ-P.S_NF-1]&FpRes&(OutFmt==P.H_FMT)) |
-                                                (|Mf[P.CORRSHIFTSZ-P.S_NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT))) |
-                                                (|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.D_NF-1]&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT)|IntRes)) |
-                                                (|Mf[P.CORRSHIFTSZ-P.D_NF-2:P.CORRSHIFTSZ-P.Q_NF-1]&(~(OutFmt==P.Q_FMT)|IntRes)) |
-                                                (|Mf[P.CORRSHIFTSZ-P.Q_NF-2:0]);
+      if (XLENPOS == 3) assign NormSticky = (|Mf[P.NORMSHIFTSZ-P.H_NF-2:P.NORMSHIFTSZ-P.S_NF-1]&FpRes&(OutFmt==P.H_FMT)) |
+                                                (|Mf[P.NORMSHIFTSZ-P.S_NF-2:P.NORMSHIFTSZ-P.XLEN-1]&FpRes&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT))) |
+                                                (|Mf[P.NORMSHIFTSZ-P.XLEN-2:P.NORMSHIFTSZ-P.D_NF-1]&((OutFmt==P.S_FMT)|(OutFmt==P.H_FMT)|IntRes)) |
+                                                (|Mf[P.NORMSHIFTSZ-P.D_NF-2:P.NORMSHIFTSZ-P.Q_NF-1]&(~(OutFmt==P.Q_FMT)|IntRes)) |
+                                                (|Mf[P.NORMSHIFTSZ-P.Q_NF-2:0]);
 
   end
 
@@ -188,32 +188,32 @@ module round import cvw::*;  #(parameter cvw_t P) (
   // determine round and LSB of the rounded value
   //      - underflow round bit is used to determint the underflow flag
   if (P.FPSIZES == 1) begin
-      assign FpGuard  = Mf[P.CORRSHIFTSZ-P.NF-1];
-      assign FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF];
-      assign FpRound  = Mf[P.CORRSHIFTSZ-P.NF-2];
+      assign FpGuard  = Mf[P.NORMSHIFTSZ-P.NF-1];
+      assign FpLsbRes = Mf[P.NORMSHIFTSZ-P.NF];
+      assign FpRound  = Mf[P.NORMSHIFTSZ-P.NF-2];
 
   end else if (P.FPSIZES == 2) begin
-      assign FpGuard  = OutFmt ? Mf[P.CORRSHIFTSZ-P.NF-1] : Mf[P.CORRSHIFTSZ-P.NF1-1];
-      assign FpLsbRes = OutFmt ? Mf[P.CORRSHIFTSZ-P.NF] : Mf[P.CORRSHIFTSZ-P.NF1];
-      assign FpRound  = OutFmt ? Mf[P.CORRSHIFTSZ-P.NF-2] : Mf[P.CORRSHIFTSZ-P.NF1-2];
+      assign FpGuard  = OutFmt ? Mf[P.NORMSHIFTSZ-P.NF-1] : Mf[P.NORMSHIFTSZ-P.NF1-1];
+      assign FpLsbRes = OutFmt ? Mf[P.NORMSHIFTSZ-P.NF] : Mf[P.NORMSHIFTSZ-P.NF1];
+      assign FpRound  = OutFmt ? Mf[P.NORMSHIFTSZ-P.NF-2] : Mf[P.NORMSHIFTSZ-P.NF1-2];
 
   end else if (P.FPSIZES == 3) begin
       always_comb
           case (OutFmt)
               P.FMT: begin
-                  FpGuard  = Mf[P.CORRSHIFTSZ-P.NF-1];
-                  FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF];
-                  FpRound  = Mf[P.CORRSHIFTSZ-P.NF-2];
+                  FpGuard  = Mf[P.NORMSHIFTSZ-P.NF-1];
+                  FpLsbRes = Mf[P.NORMSHIFTSZ-P.NF];
+                  FpRound  = Mf[P.NORMSHIFTSZ-P.NF-2];
               end
               P.FMT1: begin
-                  FpGuard  = Mf[P.CORRSHIFTSZ-P.NF1-1];
-                  FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF1];
-                  FpRound  = Mf[P.CORRSHIFTSZ-P.NF1-2];
+                  FpGuard  = Mf[P.NORMSHIFTSZ-P.NF1-1];
+                  FpLsbRes = Mf[P.NORMSHIFTSZ-P.NF1];
+                  FpRound  = Mf[P.NORMSHIFTSZ-P.NF1-2];
               end
               P.FMT2: begin
-                  FpGuard  = Mf[P.CORRSHIFTSZ-P.NF2-1];
-                  FpLsbRes = Mf[P.CORRSHIFTSZ-P.NF2];
-                  FpRound  = Mf[P.CORRSHIFTSZ-P.NF2-2];
+                  FpGuard  = Mf[P.NORMSHIFTSZ-P.NF2-1];
+                  FpLsbRes = Mf[P.NORMSHIFTSZ-P.NF2];
+                  FpRound  = Mf[P.NORMSHIFTSZ-P.NF2-2];
               end
               default: begin
                   FpGuard  = 1'bx;
@@ -225,37 +225,37 @@ module round import cvw::*;  #(parameter cvw_t P) (
       always_comb
           case (OutFmt)
               2'h3: begin
-                  FpGuard  = Mf[P.CORRSHIFTSZ-P.Q_NF-1];
-                  FpLsbRes = Mf[P.CORRSHIFTSZ-P.Q_NF];
-                  FpRound  = Mf[P.CORRSHIFTSZ-P.Q_NF-2];
+                  FpGuard  = Mf[P.NORMSHIFTSZ-P.Q_NF-1];
+                  FpLsbRes = Mf[P.NORMSHIFTSZ-P.Q_NF];
+                  FpRound  = Mf[P.NORMSHIFTSZ-P.Q_NF-2];
               end
               2'h1: begin
-                  FpGuard  = Mf[P.CORRSHIFTSZ-P.D_NF-1];
-                  FpLsbRes = Mf[P.CORRSHIFTSZ-P.D_NF];
-                  FpRound  = Mf[P.CORRSHIFTSZ-P.D_NF-2];
+                  FpGuard  = Mf[P.NORMSHIFTSZ-P.D_NF-1];
+                  FpLsbRes = Mf[P.NORMSHIFTSZ-P.D_NF];
+                  FpRound  = Mf[P.NORMSHIFTSZ-P.D_NF-2];
               end
               2'h0: begin
-                  FpGuard  = Mf[P.CORRSHIFTSZ-P.S_NF-1];
-                  FpLsbRes = Mf[P.CORRSHIFTSZ-P.S_NF];
-                  FpRound  = Mf[P.CORRSHIFTSZ-P.S_NF-2];
+                  FpGuard  = Mf[P.NORMSHIFTSZ-P.S_NF-1];
+                  FpLsbRes = Mf[P.NORMSHIFTSZ-P.S_NF];
+                  FpRound  = Mf[P.NORMSHIFTSZ-P.S_NF-2];
               end
               2'h2: begin
-                  FpGuard  = Mf[P.CORRSHIFTSZ-P.H_NF-1];
-                  FpLsbRes = Mf[P.CORRSHIFTSZ-P.H_NF];
-                  FpRound  = Mf[P.CORRSHIFTSZ-P.H_NF-2];
+                  FpGuard  = Mf[P.NORMSHIFTSZ-P.H_NF-1];
+                  FpLsbRes = Mf[P.NORMSHIFTSZ-P.H_NF];
+                  FpRound  = Mf[P.NORMSHIFTSZ-P.H_NF-2];
               end
           endcase
   end
 
-  assign Guard  = CvtToInt ? Mf[P.CORRSHIFTSZ-P.XLEN-1] : FpGuard;
-  assign LsbRes = CvtToInt ? Mf[P.CORRSHIFTSZ-P.XLEN] : FpLsbRes;
-  assign Round  = CvtToInt ? Mf[P.CORRSHIFTSZ-P.XLEN-2] : FpRound;
+  assign Guard  = CvtToInt ? Mf[P.NORMSHIFTSZ-P.XLEN-1] : FpGuard;
+  assign LsbRes = CvtToInt ? Mf[P.NORMSHIFTSZ-P.XLEN] : FpLsbRes;
+  assign Round  = CvtToInt ? Mf[P.NORMSHIFTSZ-P.XLEN-2] : FpRound;
 
   always_comb begin
       // Determine if you add 1
       case (Frm)
           3'b000: CalcPlus1  = Guard & (Round|Sticky|LsbRes);//round to nearest even
-          3'b001: CalcPlus1  = 0;//round to zero
+          3'b001: CalcPlus1  = 1'b0;//round to zero
           3'b010: CalcPlus1  = Ms;//round down
           3'b011: CalcPlus1  = ~Ms;//round up
           3'b100: CalcPlus1  = Guard;//round to nearest max magnitude
@@ -264,7 +264,7 @@ module round import cvw::*;  #(parameter cvw_t P) (
       // Determine if you add 1 (for underflow flag)
       case (Frm)
           3'b000: UfCalcPlus1  = Round & (Sticky|Guard);//round to nearest even
-          3'b001: UfCalcPlus1  = 0;//round to zero
+          3'b001: UfCalcPlus1  = 1'b0;//round to zero
           3'b010: UfCalcPlus1  = Ms;//round down
           3'b011: UfCalcPlus1  = ~Ms;//round up
           3'b100: UfCalcPlus1  = Round;//round to nearest max magnitude
@@ -296,7 +296,7 @@ module round import cvw::*;  #(parameter cvw_t P) (
       assign RoundAdd = {(P.Q_NE+1+P.H_NF)'(0), FpPlus1&(OutFmt==P.H_FMT), (P.S_NF-P.H_NF-1)'(0), FpPlus1&(OutFmt==P.S_FMT), (P.D_NF-P.S_NF-1)'(0), FpPlus1&(OutFmt==P.D_FMT), (P.Q_NF-P.D_NF-1)'(0), FpPlus1&(OutFmt==P.Q_FMT)};
 
   // trim unneeded bits from fraction
-  assign RoundFrac = Mf[P.CORRSHIFTSZ-1:P.CORRSHIFTSZ-P.NF];
+  assign RoundFrac = Mf[P.NORMSHIFTSZ-1:P.NORMSHIFTSZ-P.NF];
   
   // select the exponent
   always_comb
@@ -305,7 +305,7 @@ module round import cvw::*;  #(parameter cvw_t P) (
           2'b00:    Me = {CvtCe[P.NE], CvtCe}&{P.NE+2{~CvtResSubnormUf|CvtResUf}}; // cvt
           // 2'b01: Me = DivDone ? Ue : 0; // divide
           2'b01:    Me = Ue; // divide
-          default:  Me = 0; 
+          default:  Me = '0; 
       endcase
 
 
diff --git a/src/fpu/postproc/roundsign.sv b/src/fpu/postproc/roundsign.sv
index 7eedc5eba..fe422b98c 100644
--- a/src/fpu/postproc/roundsign.sv
+++ b/src/fpu/postproc/roundsign.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Sign calculation for rounding
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv
index b06d8db0d..0524ca364 100644
--- a/src/fpu/postproc/shiftcorrection.sv
+++ b/src/fpu/postproc/shiftcorrection.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: shift correction
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -28,7 +28,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module shiftcorrection import cvw::*;  #(parameter cvw_t P) (
-  input logic  [P.NORMSHIFTSZ-1:0] Shifted,                // the shifted sum before LZA correction
+  input logic  [P.NORMSHIFTSZ-1:0] Shifted,                // normalization shifter output
   // divsqrt
   input logic                      DivOp,                  // is it a divsqrt operation
   input logic                      DivResSubnorm,          // is the divsqrt result subnormal
@@ -41,37 +41,39 @@ module shiftcorrection import cvw::*;  #(parameter cvw_t P) (
   input logic                      FmaSZero,
   // output
   output logic [P.NE+1:0]          FmaMe,                  // exponent of the normalized sum
-  output logic [P.CORRSHIFTSZ-1:0] Mf,                     // the shifted sum before LZA correction
+  output logic [P.NORMSHIFTSZ-1:0] Mf,                     // the shifted sum after correction
   output logic [P.NE+1:0]          Ue                      // corrected exponent for divider
 );
 
-  logic [P.CORRSHIFTSZ-1:0]        CorrSumShifted;         // the shifted sum after LZA correction
-  logic [P.CORRSHIFTSZ-1:0]        CorrQm0, CorrQm1;       // portions of Shifted to select for CorrQmShifted
-  logic [P.CORRSHIFTSZ-1:0]        CorrQmShifted;          // the shifted divsqrt result after one bit shift
   logic                            ResSubnorm;             // is the result Subnormal
   logic                            LZAPlus1;               // add one or two to the sum's exponent due to LZA correction
   logic                            LeftShiftQm;            // should the divsqrt result be shifted one to the left
+  logic                            RightShift;             // shift right by 1
 
-  // LZA correction
-  assign LZAPlus1 = Shifted[P.NORMSHIFTSZ-1];
-
+  // dh 4/16/24 this code is a mess and needs cleaning and explaining
+  // define bit widths
+  // seems to shift by 0, 1, or 2.  right and left shift is confusing
+  
+  // FMA LZA correction
   // correct the shifting error caused by the LZA
   //  - the only possible mantissa for a plus two is all zeroes 
-  //  - a one has to propigate all the way through a sum. so we can leave the bottom statement alone
-  mux2 #(P.NORMSHIFTSZ-2) lzacorrmux(Shifted[P.NORMSHIFTSZ-3:0], Shifted[P.NORMSHIFTSZ-2:1], LZAPlus1, CorrSumShifted);
+  //  - a one has to propagate all the way through a sum. so we can leave the bottom statement alone
+  assign LZAPlus1 = Shifted[P.NORMSHIFTSZ-1];
 
-  // correct the shifting of the divsqrt caused by producing a result in (2, .5] range
+  // correct the shifting of the divsqrt caused by producing a result in (0.5, 2) range
   // condition: if the msb is 1 or the exponent was one, but the shifted quotent was < 1 (Subnorm)
-  assign LeftShiftQm = (LZAPlus1|(DivUe==1&~LZAPlus1));
-  assign CorrQm0     = Shifted[P.NORMSHIFTSZ-3:P.NORMSHIFTSZ-P.CORRSHIFTSZ-2];
-  assign CorrQm1     = Shifted[P.NORMSHIFTSZ-2:P.NORMSHIFTSZ-P.CORRSHIFTSZ-1];
-  mux2 #(P.CORRSHIFTSZ) divcorrmux(CorrQm0, CorrQm1, LeftShiftQm, CorrQmShifted);
-  
+  assign LeftShiftQm = (LZAPlus1|(DivUe==1&~LZAPlus1)); 
+
+  // Determine the shif for either FMA or divsqrt
+  assign RightShift = FmaOp ? LZAPlus1 : LeftShiftQm;
+ 
+  // possible one bit right shift for FMA or division
   // if the result of the divider was calculated to be subnormal, then the result was correctly normalized, so select the top shifted bits
   always_comb
-    if(FmaOp)                       Mf = {CorrSumShifted};
-    else if (DivOp&~DivResSubnorm)  Mf = CorrQmShifted;
-    else                            Mf = Shifted[P.NORMSHIFTSZ-1:P.NORMSHIFTSZ-P.CORRSHIFTSZ];
+    if (FmaOp | (DivOp & ~DivResSubnorm))  // one bit shift for FMA or divsqrt
+      if (RightShift)                      Mf = {Shifted[P.NORMSHIFTSZ-2:1], 2'b00};
+      else                                 Mf = {Shifted[P.NORMSHIFTSZ-3:0], 2'b00};
+    else                                   Mf =  Shifted[P.NORMSHIFTSZ-1:0];  // convert and subnormal division result
     
   // Determine sum's exponent
   //  main exponent issues: 
@@ -86,7 +88,8 @@ module shiftcorrection import cvw::*;  #(parameter cvw_t P) (
   // recalculate if the result is subnormal after LZA correction
   assign ResSubnorm = FmaPreResultSubnorm&~Shifted[P.NORMSHIFTSZ-2]&~Shifted[P.NORMSHIFTSZ-1];
 
-  // the quotent is in the range [.5,2) if there is no early termination
+  // the quotent is in the range (.5,2) if there is no early termination
   // if the quotent < 1 and not Subnormal then subtract 1 to account for the normalization shift
   assign Ue = (DivResSubnorm & DivSubnormShiftPos) ? 0 : DivUe - {(P.NE+1)'(0), ~LZAPlus1};
 endmodule
+
diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv
index e9ba573e1..bb655942d 100644
--- a/src/fpu/postproc/specialcase.sv
+++ b/src/fpu/postproc/specialcase.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: special case selection
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -339,7 +339,7 @@ module specialcase import cvw::*;  #(parameter cvw_t P) (
 
   if (P.ZFA_SUPPORTED & P.D_SUPPORTED) // fcvtmod.w.d support
     always_comb begin
-        if (Zfa) OfIntRes2 = 0;                // fcvtmod.w.d produces 0 on overflow
+        if (Zfa) OfIntRes2 = '0;                // fcvtmod.w.d produces 0 on overflow
         else     OfIntRes2 = OfIntRes;
         if (Zfa) Int64Res = {{(P.XLEN-32){CvtNegRes[P.XLEN-1]}}, CvtNegRes[31:0]};
         else     Int64Res = CvtNegRes[P.XLEN-1:0];
diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv
index eab224dd9..e0e35312f 100644
--- a/src/fpu/unpack.sv
+++ b/src/fpu/unpack.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: unpack X, Y, Z floating-point inputs
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -41,26 +41,29 @@ module unpack import cvw::*;  #(parameter cvw_t P) (
   output logic                    XZero, YZero, ZZero,  // is XYZ zero
   output logic                    XInf, YInf, ZInf,     // is XYZ infinity
   output logic                    XExpMax,              // does X have the maximum exponent (NaN or Inf)
-  output logic [P.FLEN-1:0]       XPostBox              // X after being properly NaN-boxed
+  output logic [P.FLEN-1:0]       XPostBox,             // X after being properly NaN-boxed
+  output logic [P.NE-2:0]         Bias,                 // Exponent bias
+  output logic [P.LOGFLEN-1:0]    Nf                    // Number of fractional bits
 );
 
-  logic XExpNonZero, YExpNonZero, ZExpNonZero;          // is the exponent of XYZ non-zero
-  logic XFracZero, YFracZero, ZFracZero;                // is the fraction zero
   logic YExpMax, ZExpMax;                               // is the exponent all 1s
-  
+
   unpackinput #(P) unpackinputX (.A(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn), .FPUActive,
-                          .NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero),
-                          .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero), 
+                          .NaN(XNaN), .SNaN(XSNaN),
+                          .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax),
                           .Subnorm(XSubnorm), .PostBox(XPostBox));
 
   unpackinput #(P) unpackinputY (.A(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn), .FPUActive,
-                          .NaN(YNaN), .SNaN(YSNaN), .ExpNonZero(YExpNonZero),
-                          .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero), 
+                          .NaN(YNaN), .SNaN(YSNaN),
+                          .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax),
                           .Subnorm(), .PostBox());
 
   unpackinput #(P) unpackinputZ (.A(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn), .FPUActive,
-                          .NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero),
-                          .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero), 
+                          .NaN(ZNaN), .SNaN(ZSNaN),
+                          .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax),
                           .Subnorm(), .PostBox());
  
+  // look up bias and fractional bits for the given format
+  fmtparams #(P) fmtparams(Fmt, Bias, Nf);
+
  endmodule
diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv
index e5c5f3deb..c90ede41d 100644
--- a/src/fpu/unpackinput.sv
+++ b/src/fpu/unpackinput.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: unpack input: extract sign, exponent, significand, characteristics
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -39,8 +39,6 @@ module unpackinput import cvw::*;  #(parameter cvw_t P) (
   output logic                     SNaN,       // is the number a signaling NaN
   output logic                     Zero,       // is the number zero
   output logic                     Inf,        // is the number infinity
-  output logic                     ExpNonZero, // is the exponent not zero
-  output logic                     FracZero,   // is the fraction zero
   output logic                     ExpMax,     // does In have the maximum exponent (NaN or Inf)
   output logic                     Subnorm,    // is the number subnormal
   output logic [P.FLEN-1:0]        PostBox     // Number reboxed correctly as a NaN
@@ -48,13 +46,15 @@ module unpackinput import cvw::*;  #(parameter cvw_t P) (
 
   logic [P.NF-1:0] Frac;        // Fraction of XYZ
   logic            BadNaNBox;   // incorrectly NaN Boxed
+  logic            FracZero;    // is the fraction zero
+  logic            ExpNonZero;  // is the exponent non-zero
   logic [P.FLEN-1:0] In;
 
   // Gate input when FPU is not active to save power and simulation
   assign In = A & {P.FLEN{FPUActive}};
 
   if (P.FPSIZES == 1) begin        // if there is only one floating point format supported
-      assign BadNaNBox = 0;
+      assign BadNaNBox = 1'b0;
       assign Sgn = In[P.FLEN-1];  // sign bit
       assign Frac = In[P.NF-1:0];  // fraction (no assumed 1)
       assign ExpNonZero = |In[P.FLEN-2:P.NF];  // is the exponent non-zero
@@ -133,7 +133,7 @@ module unpackinput import cvw::*;  #(parameter cvw_t P) (
       // Check NaN boxing
       always_comb
           case (Fmt)
-              P.FMT:  BadNaNBox = 0;
+              P.FMT:  BadNaNBox = 1'b0;
               P.FMT1: BadNaNBox = ~&In[P.FLEN-1:P.LEN1];
               P.FMT2: BadNaNBox = ~&In[P.FLEN-1:P.LEN2];
               default: BadNaNBox = 1'bx;
@@ -149,30 +149,30 @@ module unpackinput import cvw::*;  #(parameter cvw_t P) (
 
       // extract the sign bit
       always_comb
-        if (BadNaNBox) Sgn = 0; // improperly boxed NaNs are treated as positive
+        if (BadNaNBox) Sgn = 1'b0; // improperly boxed NaNs are treated as positive
         else
           case (Fmt)
-              P.FMT:  Sgn = In[P.FLEN-1];
-              P.FMT1: Sgn = In[P.LEN1-1];
-              P.FMT2: Sgn = In[P.LEN2-1];
+              P.FMT:   Sgn = In[P.FLEN-1];
+              P.FMT1:  Sgn = In[P.LEN1-1];
+              P.FMT2:  Sgn = In[P.LEN2-1];
               default: Sgn = 1'bx;
           endcase
 
        // extract the fraction
       always_comb
           case (Fmt)
-              P.FMT: Frac = In[P.NF-1:0];
-              P.FMT1: Frac = {In[P.NF1-1:0], (P.NF-P.NF1)'(0)};
-              P.FMT2: Frac = {In[P.NF2-1:0], (P.NF-P.NF2)'(0)};
+              P.FMT:   Frac = In[P.NF-1:0];
+              P.FMT1:  Frac = {In[P.NF1-1:0], (P.NF-P.NF1)'(0)};
+              P.FMT2:  Frac = {In[P.NF2-1:0], (P.NF-P.NF2)'(0)};
               default: Frac = {P.NF{1'bx}};
           endcase
 
       // is the exponent non-zero
       always_comb
           case (Fmt)
-              P.FMT:  ExpNonZero = |In[P.FLEN-2:P.NF];     // if input is largest precision (P.FLEN - ie quad or double)
-              P.FMT1: ExpNonZero = |In[P.LEN1-2:P.NF1];  // if input is larger precsion (P.LEN1 - double or single)
-              P.FMT2: ExpNonZero = |In[P.LEN2-2:P.NF2]; // if input is smallest precsion (P.LEN2 - single or half)
+              P.FMT:   ExpNonZero = |In[P.FLEN-2:P.NF];   // if input is largest precision (P.FLEN - ie quad or double)
+              P.FMT1:  ExpNonZero = |In[P.LEN1-2:P.NF1];  // if input is larger precsion (P.LEN1 - double or single)
+              P.FMT2:  ExpNonZero = |In[P.LEN2-2:P.NF2];  // if input is smallest precsion (P.LEN2 - single or half)
               default: ExpNonZero = 1'bx; 
           endcase
           
@@ -209,13 +209,13 @@ module unpackinput import cvw::*;  #(parameter cvw_t P) (
       //   P.Q_LEN  |  P.D_LEN  |  P.S_LEN  |  P.H_LEN     length of floating point number
       //   P.Q_NE   |  P.D_NE   |  P.S_NE   |  P.H_NE      length of exponent
       //   P.Q_NF   |  P.D_NF   |  P.S_NF   |  P.H_NF      length of fraction
-      //   P.Q_BIAS |  P.D_BIAS |  P.S_BIAS |  P.H_BIAS    exponent's bias value
+      //   P.Q_BIAS |  P.D_= 1'b1; |  P.S_BIAS |  P.H_BIAS    exponent's bias value
       //   P.Q_FMT  |  P.D_FMT  |  P.S_FMT  |  P.H_FMT     precision's format value - Q=11 D=01 Sticky=00 H=10
 
       // Check NaN boxing
       always_comb
           case (Fmt)
-              2'b11: BadNaNBox = 0;
+              2'b11: BadNaNBox = 1'b0;
               2'b01: BadNaNBox = ~&In[P.Q_LEN-1:P.D_LEN];
               2'b00: BadNaNBox = ~&In[P.Q_LEN-1:P.S_LEN];
               2'b10: BadNaNBox = ~&In[P.Q_LEN-1:P.H_LEN];
@@ -234,7 +234,7 @@ module unpackinput import cvw::*;  #(parameter cvw_t P) (
 
       // extract sign bit
       always_comb
-        if (BadNaNBox) Sgn = 0; // improperly boxed NaNs are treated as positive
+        if (BadNaNBox) Sgn = 1'b0; // improperly boxed NaNs are treated as positive
         else
           case (Fmt)
               2'b11: Sgn = In[P.Q_LEN-1];
diff --git a/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv
index dc5f6450c..91e01c7ab 100644
--- a/src/generic/aplusbeq0.sv
+++ b/src/generic/aplusbeq0.sv
@@ -34,7 +34,7 @@ module aplusbeq0 #(parameter WIDTH = 8) (
   logic [WIDTH-1:0] orshift;
 
   // The sum is zero if the bitwise XOR is equal to the bitwise OR shifted left by 1, for all columns
-  // *** explain, cite book
+  // See J. A. Prabhu and G. Zyner, "167 MHz radix-8 divide and square root using overlapped radix-2 stages," IEEE Symp. Computer Arithmetic, 1995, pp. 155-162.
 
   assign x = a ^ b;
   assign orshift = {a[WIDTH-2:0] | b[WIDTH-2:0], 1'b0};
diff --git a/src/generic/binencoder.sv b/src/generic/binencoder.sv
index a9349879a..83b245485 100644
--- a/src/generic/binencoder.sv
+++ b/src/generic/binencoder.sv
@@ -34,7 +34,7 @@ module binencoder #(parameter N = 8) (
   // this is coded as a priority encoder
   // consider redesigning to take advanteage of one-hot nature of input
   always_comb  begin
-    Y = 0;
+    Y = '0;
     for(index = 0; index < N; index++) 
       if(A[index] == 1'b1) Y = index[$clog2(N)-1:0];
   end
diff --git a/src/generic/decoder.sv b/src/generic/decoder.sv
index 78b816c3c..8af273fc5 100644
--- a/src/generic/decoder.sv
+++ b/src/generic/decoder.sv
@@ -29,8 +29,5 @@ module decoder #(parameter BINARY_BITS = 3) (
   output logic [(2**BINARY_BITS)-1:0] onehot
 );
 
-  // *** Double check whether this synthesizes as expected
-  //     -- Ben @ May 4: only warning is that "signed to unsigned assignment occurs"; that said, I haven't checked the netlists
   assign onehot = 1 << binary;
-
 endmodule
diff --git a/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv
index 1973b444b..1e92ac513 100644
--- a/src/generic/flop/flopenr.sv
+++ b/src/generic/flop/flopenr.sv
@@ -31,7 +31,7 @@ module flopenr #(parameter WIDTH = 8) (
   output logic [WIDTH-1:0] q);
 
   always_ff @(posedge clk)
-    if (reset)   q <= 0;
+    if (reset)   q <= '0;
     else if (en) q <= d;
 endmodule
 
diff --git a/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv
index 64d5761a6..45811db6e 100644
--- a/src/generic/flop/flopenrc.sv
+++ b/src/generic/flop/flopenrc.sv
@@ -31,9 +31,9 @@ module flopenrc #(parameter WIDTH = 8) (
   output logic [WIDTH-1:0] q);
 
   always_ff @(posedge clk) 
-    if (reset)   q <= 0;
+    if (reset)   q <= '0;
     else if (en) 
-      if (clear) q <= 0;
+      if (clear) q <= '0;
       else       q <= d;
 endmodule
 
diff --git a/src/generic/flop/flopenrcs.sv b/src/generic/flop/flopenrcs.sv
new file mode 100644
index 000000000..d6b55a5d0
--- /dev/null
+++ b/src/generic/flop/flopenrcs.sv
@@ -0,0 +1,48 @@
+///////////////////////////////////////////
+// flopenrcs.sv
+//
+// Written: matthew.n.otto@okstate.edu 15 April 2024
+// Modified: 
+//
+// Purpose: Scannable D flip-flop with enable, synchronous reset, enabled clear
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License Version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module flopenrcs #(parameter WIDTH = 8) (
+  input  logic clk, reset, clear, en,
+  input  logic [WIDTH-1:0] d,
+  output logic [WIDTH-1:0] q,
+  input  logic scan, // scan enable
+  input  logic scanin,
+  output logic scanout
+);
+  logic [WIDTH-1:0] dmux;
+
+  mux2 #(1) mux (.y(dmux[WIDTH-1]), .s(scan), .d1(scanin), .d0(d[WIDTH-1]));
+  assign scanout = q[0];
+
+  genvar i;
+  for (i=0; i<WIDTH-1; i=i+1) begin
+    mux2 #(1) mux (.y(dmux[i]), .s(scan), .d1(q[i+1]), .d0(d[i]));
+  end
+
+  flopenrc #(WIDTH) flop (.clk, .reset, .clear, .en(en | scan), .d(dmux), .q(q));
+
+endmodule
diff --git a/src/generic/flop/flopenrs.sv b/src/generic/flop/flopenrs.sv
new file mode 100644
index 000000000..e26d4e65a
--- /dev/null
+++ b/src/generic/flop/flopenrs.sv
@@ -0,0 +1,48 @@
+///////////////////////////////////////////
+// flopenrs.sv
+//
+// Written: matthew.n.otto@okstate.edu 15 April 2024
+// Modified: 
+//
+// Purpose: Scannable D flip-flop with enable, synchronous reset
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License Version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module flopenrs #(parameter WIDTH = 8) (
+  input  logic clk, reset, en,
+  input  logic [WIDTH-1:0] d,
+  output logic [WIDTH-1:0] q,
+  input  logic scan, // scan enable
+  input  logic scanin,
+  output logic scanout
+);
+  logic [WIDTH-1:0] dmux;
+
+  mux2 #(1) mux (.y(dmux[WIDTH-1]), .s(scan), .d1(scanin), .d0(d[WIDTH-1]));
+  assign scanout = q[0];
+
+  genvar i;
+  for (i=0; i<WIDTH-1; i=i+1) begin
+    mux2 #(1) mux (.y(dmux[i]), .s(scan), .d1(q[i+1]), .d0(d[i]));
+  end
+
+  flopenr #(WIDTH) flop (.clk, .reset, .en(en | scan), .d(dmux), .q(q));
+
+endmodule
diff --git a/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv
index 538d29f3c..15deb5d54 100644
--- a/src/generic/flop/flopr.sv
+++ b/src/generic/flop/flopr.sv
@@ -31,7 +31,7 @@ module flopr #(parameter WIDTH = 8) (
   output logic [WIDTH-1:0] q);
 
   always_ff @(posedge clk)
-    if (reset) q <= 0;
+    if (reset) q <= '0;
     else       q <= d;
 endmodule
 
diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv
index 4da48d760..d333048b7 100644
--- a/src/generic/mem/ram1p1rwbe.sv
+++ b/src/generic/mem/ram1p1rwbe.sv
@@ -1,5 +1,6 @@
 ///////////////////////////////////////////
-// 1 port sram.
+// ram1p1r2be.sv
+// 1 port sram with byte enables
 //
 // Written: ross1728@gmail.com
 // Created: 3 May 2021
@@ -43,11 +44,9 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
   output logic [WIDTH-1:0]        dout
 );
 
-  bit [WIDTH-1:0]               RAM[DEPTH-1:0];
-
-  // ***************************************************************************
+  ///////////////////////////////////////////////////////////////////////////////
   // TRUE SRAM macro
-  // ***************************************************************************
+  ///////////////////////////////////////////////////////////////////////////////
   if ((USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
     genvar index;
     // 64 x 128-bit SRAM
@@ -78,11 +77,11 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
       .A(addr), .D(din), 
       .BWEB(~BitWriteMask), .Q(dout));     
     
-    // ***************************************************************************
+    ///////////////////////////////////////////////////////////////////////////////
     // READ first SRAM model
-    // ***************************************************************************
+    ///////////////////////////////////////////////////////////////////////////////
   end else begin: ram
-    integer i;
+    bit [WIDTH-1:0] RAM[DEPTH-1:0];
 
     if (PRELOAD_ENABLED) begin
       initial begin
@@ -102,11 +101,13 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
     // Write divided into part for bytes and part for extra msbs
     // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.
     // Therefore these always blocks use the older always @(posedge clk) 
-    if(WIDTH >= 8) 
+    if(WIDTH >= 8) begin
+      integer i;
       always @(posedge clk) 
         if (ce & we) 
           for(i = 0; i < WIDTH/8; i++) 
             if(bwe[i]) RAM[addr][i*8 +: 8] <= din[i*8 +: 8];
+    end
   
     if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
       always @(posedge clk) 
diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv
index ff844ff22..cdca14e38 100644
--- a/src/generic/mem/ram1p1rwe.sv
+++ b/src/generic/mem/ram1p1rwe.sv
@@ -1,4 +1,5 @@
 ///////////////////////////////////////////
+// ram1p1rwe.sv
 // 1 port sram.
 //
 // Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by ross1728@gmail.com)
@@ -40,36 +41,35 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) (
   output logic [WIDTH-1:0]        dout
 );
 
-  bit [WIDTH-1:0]               RAM[DEPTH-1:0];
-
-  // ***************************************************************************
+  //////////////////////////////////////////////////////////////////////////////
   // TRUE SRAM macro
-  // ***************************************************************************
+  //////////////////////////////////////////////////////////////////////////////
   if ((USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
     // 64 x 128-bit SRAM
     ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
       .A(addr), .D(din), 
-      .BWEB(0), .Q(dout));
+      .BWEB('0), .Q(dout));
     
   end else if ((USE_SRAM == 1) & (WIDTH == 44)  & (DEPTH == 64)) begin // RV64 cache tag
     // 64 x 44-bit SRAM
     ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
       .A(addr), .D(din), 
-      .BWEB(0), .Q(dout));
+      .BWEB('0), .Q(dout));
 
   end else if ((USE_SRAM == 1) & (WIDTH == 22)  & (DEPTH == 64)) begin // RV32 cache tag
     // 64 x 22-bit SRAM
     ram1p1rwbe_64x22 sram1 (.CLK(clk), .CEB(~ce), .WEB(~we),
       .A(addr), .D(din), 
-      .BWEB(0), .Q(dout));     
+      .BWEB('0), .Q(dout));     
     
-    // ***************************************************************************
+    //////////////////////////////////////////////////////////////////////////////
     // READ first SRAM model
-    // ***************************************************************************
+    //////////////////////////////////////////////////////////////////////////////
   end else begin: ram
-    // *** Vivado is not implementing this as block ram for some reason.
+    // Vivado is not implementing this as block ram for some reason.
     // The version with byte write enables it correctly infers block ram.
-    integer i;
+
+    bit [WIDTH-1:0]               RAM[DEPTH-1:0];
 
     // Combinational read: register address and read after clock edge
     logic [$clog2(DEPTH)-1:0] addrd;
diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv
index 831ad97c8..196aa0875 100644
--- a/src/generic/mem/ram2p1r1wbe.sv
+++ b/src/generic/mem/ram2p1r1wbe.sv
@@ -1,4 +1,5 @@
 ///////////////////////////////////////////
+// ram2p1r1wbe.sv
 // 2 port sram.
 //
 // Written: ross1728@gmail.com May 3, 2021
@@ -43,23 +44,22 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
   output logic [WIDTH-1:0]         rd1
 );
 
-  bit [WIDTH-1:0]                 mem[DEPTH-1:0];
   localparam                      SRAMWIDTH = 32;
   localparam                      SRAMNUMSETS = SRAMWIDTH/WIDTH;      
 
-  // ***************************************************************************
-  // TRUE Smem macro
-  // ***************************************************************************
+  ///////////////////////////////////////////////////////////////////////////////
+  // TRUE SRAM macro
+  ///////////////////////////////////////////////////////////////////////////////
 
   if ((USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin
     
     ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), 
       .CEBA(~ce1), .CEBB(~ce2),
-      .WEBA(0), .WEBB(~we2),            
+      .WEBA(1'b0), .WEBB(~we2),            
       .AA(ra1), .AB(wa2),
-      .DA(0),
+      .DA('0),
       .DB(wd2),
-      .BWEBA(0), .BWEBB('1),
+      .BWEBA('0), .BWEBB('1),
       .QA(rd1),
       .QB());
 
@@ -67,11 +67,11 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
     
     ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), 
       .CEBA(~ce1), .CEBB(~ce2),
-      .WEBA(0), .WEBB(~we2),            
+      .WEBA(1'b0), .WEBB(~we2),            
       .AA(ra1), .AB(wa2),
-      .DA(0),
+      .DA('0),
       .DB(wd2),
-      .BWEBA(0), .BWEBB('1),
+      .BWEBA('0), .BWEBB('1),
       .QA(rd1),
       .QB());      
 
@@ -95,48 +95,44 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
     assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]];      
     ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk), 
       .CEBA(~ce1), .CEBB(~ce2),
-      .WEBA(0), .WEBB(~we2),            
+      .WEBA(1'b0), .WEBB(~we2),            
       .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), 
       .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]),
-      .DA(0),
+      .DA('0),
       .DB(SRAMWriteData),
-      .BWEBA(0), .BWEBB(SRAMBitMask),
+      .BWEBA('0), .BWEBB(SRAMBitMask),
       .QA(SRAMReadData),
       .QB());
 
-  end else begin
+  end else begin:ram
     
-    // ***************************************************************************
+    ///////////////////////////////////////////////////////////////////////////////
     // READ first SRAM model
-    // ***************************************************************************
-    integer i;
-/*    
-    initial begin // initialize memory for simulation only; not needed because done in the testbench now
-      integer j;
-      for (j=0; j < DEPTH; j++) 
-        mem[j] = 0;
-    end 
-*/
+    ///////////////////////////////////////////////////////////////////////////////
+
+    bit [WIDTH-1:0] RAM[DEPTH-1:0];
 
     // Read
     logic [$clog2(DEPTH)-1:0] ra1d;
     flopen #($clog2(DEPTH)) adrreg(clk, ce1, ra1, ra1d);
-    assign rd1 = mem[ra1d];
+    assign rd1 = RAM[ra1d];
     
     // Write divided into part for bytes and part for extra msbs
     // coverage off     
     //   when byte write enables are tied high, the last IF is always taken
-    if(WIDTH >= 8) 
+    if(WIDTH >= 8) begin
+      integer i;
       always @(posedge clk) 
         if (ce2 & we2) 
           for(i = 0; i < WIDTH/8; i++) 
-            if(bwe2[i]) mem[wa2][i*8 +: 8] <= wd2[i*8 +: 8];
+            if(bwe2[i]) RAM[wa2][i*8 +: 8] <= wd2[i*8 +: 8];
+    end
     // coverage on
   
     if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
       always @(posedge clk) 
         if (ce2 & we2 & bwe2[WIDTH/8])
-          mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= wd2[WIDTH-1:WIDTH-WIDTH%8];
+          RAM[wa2][WIDTH-1:WIDTH-WIDTH%8] <= wd2[WIDTH-1:WIDTH-WIDTH%8];
   end
   
 endmodule
diff --git a/src/generic/mem/ram2p1r1wbe_512x64.sv b/src/generic/mem/ram2p1r1wbe_2048x64.sv
similarity index 100%
rename from src/generic/mem/ram2p1r1wbe_512x64.sv
rename to src/generic/mem/ram2p1r1wbe_2048x64.sv
diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv
index 7350eac9c..e17b8af60 100644
--- a/src/generic/mem/rom1p1r.sv
+++ b/src/generic/mem/rom1p1r.sv
@@ -33,6 +33,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
    output logic [DATA_WIDTH-1:0] dout
 );
 
+
    // Core Memory
    bit [DATA_WIDTH-1:0]    ROM [(2**ADDR_WIDTH)-1:0];
    
@@ -46,16 +47,27 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
 
   end else begin */
 
-  initial begin
+  `ifdef VERILATOR
+    import "DPI-C" function string getenvval(input string env_name);
+  `endif
+  
+  initial 
     if (PRELOAD_ENABLED) begin
-      $readmemh("$WALLY/fpga/src/boot.mem", ROM, 0);
+      if (DATA_WIDTH == 64) begin
+        `ifdef VERILATOR
+            // because Verilator doesn't automatically accept $WALLY from shell
+            string       WALLY_DIR = getenvval("WALLY"); 
+            $readmemh({WALLY_DIR,"/fpga/src/boot.mem"}, ROM, 0);  // load boot ROM for FPGA
+        `else
+            $readmemh({"$WALLY/fpga/src/boot.mem"}, ROM, 0);  // load boot ROM for FPGA
+        `endif
+      end else begin // put something in the ROM so it is not optimized away
+        ROM[0] = 'h00002197;
+      end
     end
-  end
-  
-  always_ff @ (posedge clk) begin
+
+  always_ff @ (posedge clk) 
     if(ce) dout <= ROM[addr];
-  end
-   
    
    // for FPGA, initialize with zero-stage bootloader
    /*if(PRELOAD_ENABLED) begin
diff --git a/src/generic/mux.sv b/src/generic/mux.sv
index f07efeb5c..92178971d 100644
--- a/src/generic/mux.sv
+++ b/src/generic/mux.sv
@@ -76,4 +76,33 @@ module mux7 #(parameter WIDTH = 8) (
 
 endmodule
 
+module clockmux2 #(parameter NUM_STAGES = 3) (
+  input  logic clk0, clk1,
+  input  logic s,
+  output logic clkout);
+
+  // Based loosely on https://www.intel.com/content/www/us/en/docs/programmable/683082/23-1/clock-multiplexing.html
+  // Require select to stay high for NUM_STAGES clock cycles (of its respective clock) before switching
+
+  genvar i;
+
+  logic [NUM_STAGES:0] q0, q1;
+  logic                clk0out, clk1out;
+
+  assign q0[0] = ~s & ~q1[NUM_STAGES];
+  assign q1[0] =  s & ~q0[NUM_STAGES];
+
+  generate
+    for (i=0; i < NUM_STAGES; i = i+1) begin
+      flop #(1) s0stage (clk0, q0[i], q0[i+1]);
+      flop #(1) s1stage (clk1, q1[i], q1[i+1]);
+    end
+  endgenerate
+
+  assign clk0out = clk0 & q0[NUM_STAGES];
+  assign clk1out = clk1 & q1[NUM_STAGES];
+  assign clkout  = clk0out | clk1out;
+
+endmodule
+
 /* verilator lint_on DECLFILENAME */
diff --git a/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv
index 433e12d37..9b25feb65 100644
--- a/src/generic/onehotdecoder.sv
+++ b/src/generic/onehotdecoder.sv
@@ -31,7 +31,7 @@ module onehotdecoder #(parameter WIDTH = 2) (
 );
 
   always_comb begin
-    decoded = 0;
+    decoded = '0;
     decoded[bin] = 1'b1;
   end
     
diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv
index fa731bac8..f7361246f 100644
--- a/src/hazard/hazard.sv
+++ b/src/hazard/hazard.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Determine stalls and flushes
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4, Figure 13.54
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -28,20 +28,22 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module hazard import cvw::*;  #(parameter cvw_t P) ( 
-  input  logic  BPWrongE, CSRWriteFenceM, RetM, TrapM,   
-  input  logic  StructuralStallD,
-  input  logic  LSUStallM, IFUStallF,
-  input  logic  FPUStallD,
-  input  logic  DivBusyE, FDivBusyE,
-  input  logic  wfiM, IntPendingM,
+  input  logic BPWrongE, CSRWriteFenceM, RetM, TrapM,
+  input  logic DRet,
+  input  logic StructuralStallD,
+  input  logic LSUStallM, IFUStallF,
+  input  logic FPUStallD,
+  input  logic DivBusyE, FDivBusyE,
+  input  logic wfiM, IntPendingM,
+  input  logic DebugStall,
   // Stall & flush outputs
   output logic StallF, StallD, StallE, StallM, StallW,
   output logic FlushD, FlushE, FlushM, FlushW
 );
 
-  logic                                       StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
-  logic                                       LatestUnstalledD, LatestUnstalledE, LatestUnstalledM, LatestUnstalledW;
-  logic                                       FlushDCause, FlushECause, FlushMCause, FlushWCause;
+  logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
+  logic LatestUnstalledD, LatestUnstalledE, LatestUnstalledM, LatestUnstalledW;
+  logic FlushDCause, FlushECause, FlushMCause, FlushWCause;
 
   logic WFIStallM, WFIInterruptedM;
 
@@ -69,9 +71,9 @@ module hazard import cvw::*;  #(parameter cvw_t P) (
   // Branch misprediction is found in the Execute stage and must flush the next two instructions.
   //   However, an active division operation resides in the Execute stage, and when the BP incorrectly mispredicts the divide as a taken branch, the divde must still complete
   // When a WFI is interrupted and causes a trap, it flushes the rest of the pipeline but not the W stage, because the WFI needs to commit
-  assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPWrongE;
-  assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPWrongE & ~(DivBusyE | FDivBusyE));
-  assign FlushMCause = TrapM | RetM | CSRWriteFenceM;
+  assign FlushDCause = TrapM | RetM | DRet | CSRWriteFenceM | BPWrongE;
+  assign FlushECause = TrapM | RetM | DRet | CSRWriteFenceM |(BPWrongE & ~(DivBusyE | FDivBusyE));
+  assign FlushMCause = TrapM | RetM | DRet | CSRWriteFenceM;
   assign FlushWCause = TrapM & ~WFIInterruptedM;
 
   // Stall causes
@@ -82,14 +84,14 @@ module hazard import cvw::*;  #(parameter cvw_t P) (
   //  The IFU and LSU stall the entire pipeline on a cache miss, bus access, or other long operation.  
   //    The IFU stalls the entire pipeline rather than just Fetch to avoid complications with instructions later in the pipeline causing Exceptions
   //    A trap could be asserted at the start of a IFU/LSU stall, and should flush the memory operation
-  assign StallFCause = 0;
+  assign StallFCause = 1'b0;
   assign StallDCause = (StructuralStallD | FPUStallD) & ~FlushDCause;
   assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause; 
   assign StallMCause = WFIStallM & ~FlushMCause;
   // Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1.
   // assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause;
   // Because FlushWCause is a strict subset of FlushDCause, FlushWCause is factored out.
-  assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);
+  assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause) | (DebugStall & ~DRet);
 
   // Stall each stage for cause or if the next stage is stalled
   // coverage off: StallFCause is always 0
@@ -107,8 +109,8 @@ module hazard import cvw::*;  #(parameter cvw_t P) (
   assign LatestUnstalledW = ~StallW & StallM;
   
   // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
-  assign FlushD = LatestUnstalledD | FlushDCause; 
-  assign FlushE = LatestUnstalledE | FlushECause;
-  assign FlushM = LatestUnstalledM | FlushMCause;
-  assign FlushW = LatestUnstalledW | FlushWCause;
+  assign FlushD = (LatestUnstalledD | FlushDCause);
+  assign FlushE = (LatestUnstalledE | FlushECause);
+  assign FlushM = (LatestUnstalledM | FlushMCause);
+  assign FlushW = (LatestUnstalledW | FlushWCause);
 endmodule
diff --git a/src/ieu/aes/aes32d.sv b/src/ieu/aes/aes32d.sv
index e3eb61cec..f761b5060 100644
--- a/src/ieu/aes/aes32d.sv
+++ b/src/ieu/aes/aes32d.sv
@@ -34,8 +34,8 @@ module aes32d(
    logic [7:0] 			  SboxOut;
    logic [31:0] 		     so, mixed;
    
-   aesinvsbox8 inv_sbox(SboxIn, SboxOut);         // Apply inverse sbox to si
-   assign so = {24'h0, SboxOut};                  // Pad output of inverse substitution box
-   aesinvmixcolumns32 mix(so, mixed);             // Run so through the mixword AES function
+   aesinvsbox8 inv_sbox(SboxIn, SboxOut);          // Apply inverse sbox to si
+   aesinvmixcolumns8 mix(SboxOut, mixed);          // Run so through the InvMixColumns AES function
+   assign so = {24'h0, SboxOut};                   // Pad output of inverse substitution box
    mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip mixcolumns
 endmodule
diff --git a/src/ieu/aes/aes32e.sv b/src/ieu/aes/aes32e.sv
index ca00afdd3..ab28db196 100644
--- a/src/ieu/aes/aes32e.sv
+++ b/src/ieu/aes/aes32e.sv
@@ -34,8 +34,8 @@ module aes32e(
    logic [7:0] 			  SboxOut;
    logic [31:0] 		     so, mixed;
    
-   aessbox8 sbox(SboxIn, SboxOut);                // Substitute
-   assign so = {24'h0, SboxOut};                  // Pad sbox output
-   aesmixcolumns32 mwd(so, mixed);                // Mix Word using aesmixword component
-   mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip mixcolumns
+   aessbox8 sbox(SboxIn, SboxOut);                 // Substitute
+   assign so = {24'h0, SboxOut};                   // Pad sbox output
+   aesmixcolumns32 mb(so, mixed);                  // Mix using MixColumns component
+   mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip MixColumns
 endmodule
diff --git a/src/ieu/aes/aes64d.sv b/src/ieu/aes/aes64d.sv
index 96355a566..517dd4bf0 100644
--- a/src/ieu/aes/aes64d.sv
+++ b/src/ieu/aes/aes64d.sv
@@ -32,20 +32,20 @@ module aes64d(
    output logic [63:0] result
 );
    
-   logic [63:0] 		    ShiftRowOut, SboxOut, MixcolIn, MixcolOut;
+   logic [63:0] 		    ShiftRowsOut, SboxOut, MixcolsIn, MixcolsOut;
    
    // Apply inverse shiftrows to rs2 and rs1
-   aesinvshiftrow64 srow({rs2, rs1}, ShiftRowOut);
+   aesinvshiftrows64 srow({rs2, rs1}, ShiftRowsOut);
    
    // Apply full word inverse substitution to lower doubleord of shiftrow out
-   aesinvsbox64 invsbox(ShiftRowOut,  SboxOut);
+   aesinvsbox64 invsbox(ShiftRowsOut,  SboxOut);
    
-   mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolIn);
+   mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolsIn);
    
-   // Apply inverse mixword to sbox outputs
-   aesinvmixcolumns32 invmw0(MixcolIn[31:0], MixcolOut[31:0]);
-   aesinvmixcolumns32 invmw1(MixcolIn[63:32], MixcolOut[63:32]);
+   // Apply inverse MixColumns to sbox outputs
+   aesinvmixcolumns32 invmw0(MixcolsIn[31:0], MixcolsOut[31:0]);
+   aesinvmixcolumns32 invmw1(MixcolsIn[63:32], MixcolsOut[63:32]);
    
    // Final round skips mixcolumns.
-   mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result);
+   mux2 #(64) resultmux(MixcolsOut, SboxOut, finalround, result);
 endmodule
diff --git a/src/ieu/aes/aes64e.sv b/src/ieu/aes/aes64e.sv
index b37d8787c..f4b59178a 100644
--- a/src/ieu/aes/aes64e.sv
+++ b/src/ieu/aes/aes64e.sv
@@ -34,22 +34,22 @@ module aes64e(
     output logic [63:0] result
 );
   
-    logic [63:0]  ShiftRowOut, SboxOut, MixcolOut;
+    logic [63:0]  ShiftRowsOut, SboxOut, MixcolsOut;
                 
     // AES shiftrow unit
-    aesshiftrow64 srow({rs2,rs1}, ShiftRowOut);
+    aesshiftrows64 srow({rs2,rs1}, ShiftRowsOut);
    
     // Apply substitution box to 2 lower words
     // Use the shared sbox in zknde64.sv for the first sbox
-    assign SboxEIn = ShiftRowOut[31:0];
+    assign SboxEIn = ShiftRowsOut[31:0];
     assign SboxOut[31:0] = Sbox0Out;
 
-    aessbox32 sbox1(ShiftRowOut[63:32], SboxOut[63:32]); // instantiate second sbox
+    aessbox32 sbox1(ShiftRowsOut[63:32], SboxOut[63:32]); // instantiate second sbox
 
-    // Apply mix columns operations
-    aesmixcolumns32 mw0(SboxOut[31:0],  MixcolOut[31:0]);
-    aesmixcolumns32 mw1(SboxOut[63:32], MixcolOut[63:32]);    
+    // Apply MixColumns operations
+    aesmixcolumns32 mw0(SboxOut[31:0],  MixcolsOut[31:0]);
+    aesmixcolumns32 mw1(SboxOut[63:32], MixcolsOut[63:32]);
 
     // Skip mixcolumns on last round
-    mux2 #(64) resultmux(MixcolOut, SboxOut, finalround, result);
+    mux2 #(64) resultmux(MixcolsOut, SboxOut, finalround, result);
 endmodule
diff --git a/src/ieu/aes/aes64ks1i.sv b/src/ieu/aes/aes64ks1i.sv
index 3c1d203f9..cb2d71018 100644
--- a/src/ieu/aes/aes64ks1i.sv
+++ b/src/ieu/aes/aes64ks1i.sv
@@ -26,11 +26,11 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module aes64ks1i(
-   input  logic [3:0]  round,
-   input  logic [63:0] rs1,
-   input  logic [31:0] Sbox0Out,
-   output logic [31:0] SboxKIn,
-   output logic [63:0] result
+   input  logic [3:0]   round,
+   input  logic [63:32] rs1,
+   input  logic [31:0]  Sbox0Out,
+   output logic [31:0]  SboxKIn,
+   output logic [63:0]  result
 );                 
                  
    logic 			        finalround;
diff --git a/src/ieu/aes/aes64ks2.sv b/src/ieu/aes/aes64ks2.sv
index dac9ed50d..b5209d799 100644
--- a/src/ieu/aes/aes64ks2.sv
+++ b/src/ieu/aes/aes64ks2.sv
@@ -26,9 +26,9 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module aes64ks2(
-   input  logic [63:0] rs2,
-   input  logic [63:0] rs1,
-   output logic [63:0] result
+   input  logic [63:0]  rs2,
+   input  logic [63:32] rs1,
+   output logic [63:0]  result
 );
    
    logic [31:0] 		    w0, w1;
diff --git a/src/ieu/aes/aesinvmixcolumns8.sv b/src/ieu/aes/aesinvmixcolumns8.sv
new file mode 100644
index 000000000..134ceeb11
--- /dev/null
+++ b/src/ieu/aes/aesinvmixcolumns8.sv
@@ -0,0 +1,47 @@
+///////////////////////////////////////////
+// aesinvmixcolumns8.sv
+//
+// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
+// Created: 05 March 2024
+//
+// Purpose: AES Inverted Mix Column Function for use with AES
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module aesinvmixcolumns8(
+   input  logic [7:0] a, 
+   output logic [31:0] y
+);
+
+   logic [10:0] t, x0, x1, x2, x3;
+
+   // aes32d operates on shifted versions of the input
+   assign t  = {a, 3'b0} ^ {3'b0, a};
+   assign x0 = {a, 3'b0} ^ {1'b0, a, 2'b0} ^ {2'b0, a, 1'b0};
+   assign x1 = t;
+   assign x2 = t ^ {1'b0, a, 2'b0};
+   assign x3 = t ^ {2'b0, a, 1'b0};
+
+   galoismultinverse8 gm0 (x0, y[7:0]);
+   galoismultinverse8 gm1 (x1, y[15:8]);
+   galoismultinverse8 gm2 (x2, y[23:16]);
+   galoismultinverse8 gm3 (x3, y[31:24]);
+
+ endmodule 
diff --git a/src/ieu/aes/aesinvshiftrow64.sv b/src/ieu/aes/aesinvshiftrows64.sv
similarity index 87%
rename from src/ieu/aes/aesinvshiftrow64.sv
rename to src/ieu/aes/aesinvshiftrows64.sv
index c6d355b63..7e24f67c8 100644
--- a/src/ieu/aes/aesinvshiftrow64.sv
+++ b/src/ieu/aes/aesinvshiftrows64.sv
@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// aesinvshiftrow.sv
+// aesinvshiftrows64.sv
 //
 // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
 // Created: 20 February 2024
@@ -25,9 +25,11 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aesinvshiftrow64(
-   input  logic [127:0] a, 
-   output logic [63:0] y
+module aesinvshiftrows64(
+   /* verilator lint_off UNUSEDSIGNAL */
+   input  logic [127:0] a,
+   /* verilator lint_on UNUSEDSIGNAL */
+   output logic [63:0]  y
 );
 
    assign y = {a[95:88],   a[119:112], a[15:8],    a[39:32],
diff --git a/src/generic/flop/flopens.sv b/src/ieu/aes/aesmixcolumns8.sv
similarity index 66%
rename from src/generic/flop/flopens.sv
rename to src/ieu/aes/aesmixcolumns8.sv
index d5969128c..256f728d0 100644
--- a/src/generic/flop/flopens.sv
+++ b/src/ieu/aes/aesmixcolumns8.sv
@@ -1,15 +1,15 @@
 ///////////////////////////////////////////
-// flopens.sv
+// aesmixcolumns8.sv
 //
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
+// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu
+// Created: 20 February 2024
+//
+// Purpose: Galois field operation to byte in an individual 32-bit word
 //
-// Purpose: D flip-flop with enable, synchronous set
-// 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
 // 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
 //
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
@@ -25,14 +25,15 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module flopens #(parameter WIDTH = 8) (
-  input  logic             clk, set, en,
-  input  logic [WIDTH-1:0] d, 
-  output logic [WIDTH-1:0] q);
 
-  always_ff @(posedge clk) 
-    if (set)   q <= 1;
-    else if (en) q <= d;
-endmodule
+module aesmixcolumns8(
+   input  logic [7:0]  a, 
+   output logic [31:0] y
+);
 
+   logic [7:0] xa, xapa;
 
+   galoismultforward8 gm(a, xa); // xa
+   assign xapa = a ^ xa;         // a ^ xa
+   assign y = {xapa, a, a, xa};
+endmodule
diff --git a/src/ieu/aes/aesshiftrow64.sv b/src/ieu/aes/aesshiftrows64.sv
similarity index 91%
rename from src/ieu/aes/aesshiftrow64.sv
rename to src/ieu/aes/aesshiftrows64.sv
index 8691a9946..11577bf3a 100644
--- a/src/ieu/aes/aesshiftrow64.sv
+++ b/src/ieu/aes/aesshiftrows64.sv
@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// aesshiftrow.sv
+// aesshiftrows64.sv
 //
 // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
 // Created: 20 February 2024
@@ -25,8 +25,10 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module aesshiftrow64(
+module aesshiftrows64(
+   /* verilator lint_off UNUSEDSIGNAL */
    input  logic [127:0] a, 
+   /* verilator lint_on UNUSEDSIGNAL */
    output logic [63:0] y
 );
 		    
diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv
index ae573ca70..e142de1e7 100644
--- a/src/ieu/alu.sv
+++ b/src/ieu/alu.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: RISC-V Arithmetic/Logic Unit
 //
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -50,6 +50,7 @@ module alu import cvw::*; #(parameter cvw_t P) (
   logic [P.XLEN-1:0] CondMaskB;                                                   // Result of B mask select mux
   logic [P.XLEN-1:0] CondShiftA;                                                  // Result of A shifted select mux
   logic [P.XLEN-1:0] ZeroCondMaskInvB;                                            // B input to AND gate, accounting for czero.* instructions
+  logic [P.XLEN-1:0] AndResult;                                                   // AND result
   logic              Carry, Neg;                                                  // Flags: carry out, negative
   logic              LT, LTU;                                                     // Less than, Less than unsigned
   logic              Asign, Bsign;                                                // Sign bits of A, B
@@ -59,7 +60,22 @@ module alu import cvw::*; #(parameter cvw_t P) (
   // CondShiftA is A for add/sub or a shifted version of A for shift-and-add BMU instructions
   assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB;
   assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(P.XLEN-1){1'b0}}, SubArith};
-  
+
+  // Zicond block conditionally zeros B
+  if (P.ZICOND_SUPPORTED) begin: zicond
+    logic  BZero;
+    
+    assign BZero = (B == 0); // check if rs2 = 0
+    // Create a signal that is 0 when czero.* instruction should clear result
+    // If B = 0 for czero.eqz or if B != 0 for czero.nez
+    always_comb 
+     case (CZero)
+        2'b01:   ZeroCondMaskInvB = {P.XLEN{~BZero}}; // czero.eqz: kill if B = 0
+        2'b10:   ZeroCondMaskInvB = {P.XLEN{BZero}};  // czero.nez: kill if B != 0
+        default: ZeroCondMaskInvB = CondMaskInvB;     // otherwise normal behavior
+      endcase
+  end else assign ZeroCondMaskInvB = CondMaskInvB; // no masking if Zicond is not supported
+
   // Shifts (configurable for rotation)
   shifter #(P) sh(.A, .Amt(B[P.LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
 
@@ -72,6 +88,7 @@ module alu import cvw::*; #(parameter cvw_t P) (
   assign Bsign = B[P.XLEN-1];
   assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; 
   assign LTU = ~Carry;
+  assign AndResult = A & ZeroCondMaskInvB;
  
   // Select appropriate ALU Result
   always_comb 
@@ -81,17 +98,20 @@ module alu import cvw::*; #(parameter cvw_t P) (
       3'b010: FullResult = {{(P.XLEN-1){1'b0}}, LT};       // slt
       3'b011: FullResult = {{(P.XLEN-1){1'b0}}, LTU};      // sltu
       3'b100: FullResult = A ^ CondMaskInvB;               // xor, xnor, binv
-      3'b101: FullResult = (P.ZBS_SUPPORTED | P.ZBB_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported)
+//      3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(A & CondMaskInvB)}} : Shift; // bext (or IEU shift when BMU not supported)
+      3'b101: FullResult = (P.ZBS_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(AndResult)}} : Shift; // bext (or IEU shift when BMU not supported)
       3'b110: FullResult = A | CondMaskInvB;               // or, orn, bset
-      3'b111: FullResult = A & ZeroCondMaskInvB;           // and, bclr, czero.*
+      3'b111: FullResult = AndResult;                      // and, bclr, czero.*
     endcase
 
   // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
-  if (P.XLEN == 64)  assign PreALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
+  if (P.XLEN == 64) assign PreALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
   else              assign PreALUResult = FullResult;
 
   // Bit manipulation muxing
-  if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED | P.ZKNH_SUPPORTED) begin : bitmanipalu
+  if (P.ZBC_SUPPORTED  | P.ZBS_SUPPORTED  | P.ZBA_SUPPORTED  | P.ZBB_SUPPORTED |
+      P.ZBKB_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | 
+      P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED | P.ZKNH_SUPPORTED) begin : bitmanipalu
     bitmanipalu #(P) balu(
       .A, .B, .W64, .BSelect, .ZBBSelect, .BMUActive,
       .Funct3, .Funct7, .Rs2E, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult,
@@ -102,18 +122,4 @@ module alu import cvw::*; #(parameter cvw_t P) (
     assign CondShiftA = A;
   end
 
-  // Zicond block
-  if (P.ZICOND_SUPPORTED) begin: zicond
-    logic  BZero;
-    
-    assign BZero = (B == 0); // check if rs2 = 0
-    // Create a signal that is 0 when czero.* instruction should clear result
-    // If B = 0 for czero.eqz or if B != 0 for czero.nez
-    always_comb 
-     case (CZero)
-        2'b01:   ZeroCondMaskInvB = {P.XLEN{~BZero}}; // czero.eqz: kill if B = 0
-        2'b10:   ZeroCondMaskInvB = {P.XLEN{BZero}};  // czero.nez: kill if B != 0
-        default: ZeroCondMaskInvB = CondMaskInvB;     // otherwise normal behavior
-      endcase
-  end else assign ZeroCondMaskInvB = CondMaskInvB; // no masking if Zicond is not supported
 endmodule
diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv
index 244a5b446..4caee782a 100644
--- a/src/ieu/bmu/bitmanipalu.sv
+++ b/src/ieu/bmu/bitmanipalu.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: RISC-V Arithmetic/Logic Unit Bit-Manipulation Extension and K extension
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -49,7 +49,6 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
   logic [P.XLEN-1:0]        ZBBResult;               // ZBB Result
   logic [P.XLEN-1:0]        ZBCResult;               // ZBC Result   
   logic [P.XLEN-1:0] 	      ZBKBResult;              // ZBKB Result
-  logic [P.XLEN-1:0]        ZBKCResult;              // ZBKC Result
   logic [P.XLEN-1:0]        ZBKXResult;              // ZBKX Result      
   logic [P.XLEN-1:0]        ZKNHResult;              // ZKNH Result
   logic [P.XLEN-1:0]        ZKNDEResult;             // ZKNE or ZKND Result   
@@ -87,40 +86,46 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
   end
 
   // Bit reverse needed for some ZBB, ZBC instructions
-  if (P.ZBC_SUPPORTED | P.ZBB_SUPPORTED) begin: bitreverse
+  if (P.ZBC_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBB_SUPPORTED) begin: bitreverse
     bitreverse #(P.XLEN) brA(.A(ABMU), .RevA);
   end
 
   // ZBC and ZBKCUnit
   if (P.ZBC_SUPPORTED | P.ZBKC_SUPPORTED) begin: zbc
-    zbc #(P.XLEN) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3, .ZBCResult);
-  end else assign ZBCResult = 0;
+    zbc #(P) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3(Funct3[1:0]), .ZBCResult);
+  end else assign ZBCResult = '0;
 
   // ZBB Unit
   if (P.ZBB_SUPPORTED) begin: zbb
     zbb #(P.XLEN) ZBB(.A(ABMU), .RevA, .B(BBMU), .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect(ZBBSelect[2:0]), .ZBBResult);
-  end else assign ZBBResult = 0;
+  end else if (P.ZBKB_SUPPORTED) begin: zbkbonly // only needs rev8 portion
+    genvar i;
+    for (i=0;i<P.XLEN;i+=8) begin:byteloop
+      assign ZBBResult[P.XLEN-i-1:P.XLEN-i-8] = ABMU[i+7:i]; // Rev8
+    end
+  end else assign ZBBResult = '0;
 
   // ZBKB Unit
   if (P.ZBKB_SUPPORTED) begin: zbkb
-    zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU), .RevA, .W64, .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult);
-  end else assign ZBKBResult = 0;
+    zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU[P.XLEN/2-1:0]), .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult);
+  end else assign ZBKBResult = '0;
 
   // ZBKX Unit
   if (P.ZBKX_SUPPORTED) begin: zbkx
-    zbkx #(P.XLEN) ZBKX(.A(ABMU), .B(BBMU), .ZBKXSelect(ZBBSelect[2:0]), .ZBKXResult);
-  end else assign ZBKXResult = 0;
+    zbkx #(P.XLEN) ZBKX(.A(ABMU), .B(BBMU), .ZBKXSelect(ZBBSelect[0]), .ZBKXResult);
+  end else assign ZBKXResult = '0;
 
   // ZKND and ZKNE AES decryption and encryption
-  if (P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED)
-    if (P.XLEN == 32) zknde32 #(P) ZKN32(.A(ABMU), .B(BBMU), .Funct7, .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNDEResult); 
-    else              zknde64 #(P) ZKN64(.A(ABMU), .B(BBMU), .Funct7, .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNDEResult); 
+  if (P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) begin: zknde
+    if (P.XLEN == 32) zknde32 #(P) ZKN32(.A(ABMU), .B(BBMU), .bs(Funct7[6:5]), .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNDEResult); 
+    else              zknde64 #(P) ZKN64(.A(ABMU), .B(BBMU),                   .round(Rs2E[3:0]), .ZKNSelect(ZBBSelect[3:0]), .ZKNDEResult); 
+  end else assign ZKNDEResult = '0;
  
   // ZKNH Unit
   if (P.ZKNH_SUPPORTED) begin: zknh
     if (P.XLEN == 32) zknh32 ZKNH32(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult));
-    else              zknh64 ZKNH64(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult));
-  end else assign ZKNHResult = 0;
+    else              zknh64 ZKNH64(.A(ABMU),           .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult));
+  end else assign ZKNHResult = '0;
 
   // Result Select Mux
   always_comb
diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv
index 083033d53..5fc4e8b49 100644
--- a/src/ieu/bmu/bitreverse.sv
+++ b/src/ieu/bmu/bitreverse.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Bit reverse submodule
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv
index 887ac0065..fb4e603c0 100644
--- a/src/ieu/bmu/bmuctrl.sv
+++ b/src/ieu/bmu/bmuctrl.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Top level bit manipulation instruction decoder
 // 
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -31,11 +31,8 @@
 module bmuctrl import cvw::*;  #(parameter cvw_t P) (
   input  logic        clk, reset,
   // Decode stage control signals
-  input  logic        StallD, FlushD,          // Stall, flush Decode stage
   input  logic [31:0] InstrD,                  // Instruction in Decode stage
   input  logic        ALUOpD,                  // Regular ALU Operation
-  output logic [3:0]  BSelectD,                // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage
-  output logic [3:0]  ZBBSelectD,              // ZBB mux select signal in Decode stage NOTE: do we need this in decode?
   output logic        BRegWriteD,              // Indicates if it is a R type B instruction in Decode Stage
   output logic        BALUSrcBD,               // Indicates if it is an I/IW (non auipc) type B instruction in Decode Stage
   output logic        BW64D,                   // Indiciates if it is a W type B instruction in Decode Stage
@@ -46,7 +43,6 @@ module bmuctrl import cvw::*;  #(parameter cvw_t P) (
   output logic [2:0]  ALUSelectD,              // ALU select
   output logic [3:0]  BSelectE,                // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
   output logic [3:0]  ZBBSelectE,              // ZBB mux select signal
-  output logic        BRegWriteE,              // Indicates if it is a R type B instruction in Execute
   output logic [2:0]  BALUControlE,            // ALU Control signals for B instructions in Execute Stage
   output logic        BMUActiveE               // Bit manipulation instruction being executed
 );
@@ -61,6 +57,8 @@ module bmuctrl import cvw::*;  #(parameter cvw_t P) (
   logic [2:0] BALUControlD;                    // ALU Control signals for B instructions
   logic [2:0] BALUSelectD;                     // ALU Mux select signal in Decode Stage for BMU operations
   logic       BALUOpD;                         // Indicates if it is an ALU B instruction in Decode Stage
+  logic [3:0] BSelectD;                        // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage
+  logic [3:0] ZBBSelectD;                      // ZBB mux select signal in Decode stage
 
   `define BMUCTRLW 20
 
@@ -98,10 +96,6 @@ module bmuctrl import cvw::*;  #(parameter cvw_t P) (
                                   BMUControlsD = `BMUCTRLW'b000_0010_0001_1_1_0_1_0_0_0_0_0;  // sign extend instruction
                                 else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
                                   BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_0_1_0_0_0_0_0;  // count instruction
-//        // coverage off: This case can't occur in RV64
-//        17'b0110011_0000100_100: if (P.XLEN == 32)
-//                                  BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // zexth (rv32)
-//        // coverage on
         17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111)
                                   BMUControlsD = `BMUCTRLW'b000_0010_0010_1_1_0_1_0_0_0_0_0;  // orc.b
         17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0010_0111_1_0_0_1_1_0_0_0_0;  // max
@@ -124,33 +118,34 @@ module bmuctrl import cvw::*;  #(parameter cvw_t P) (
     if (P.ZBC_SUPPORTED)
       casez({OpD, Funct7D, Funct3D})
         17'b0110011_0000101_010: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0;  // clmulr
-        17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0;  // ZBC instruction
+        17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0;  // clmul/clmulh
       endcase
-    if (P.ZBKC_SUPPORTED | P.ZBC_SUPPORTED) begin   
+    if (P.ZBKC_SUPPORTED) begin   
       casez({OpD, Funct7D, Funct3D})
-        17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0;  // clmul
-        17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0;  // clmulh
+        17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0;  // clmul/clmulh
+        //  17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0;  // clmul
+        // 17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0;  // clmulh
       endcase
     end
 
     if (P.ZBS_SUPPORTED) begin // ZBS
       casez({OpD, Funct7D, Funct3D})
         17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_0_0_1_1_0_1_0_0;  // bclr
-        17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_0_0_1_1_0_1_0_0;  // bext
+        17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_0_0_1_0_0_1_0_0;  // bext
         17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_0_0_1_0_0_1_0_0;  // binv
         17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_0_0_1_0_0_1_0_0;  // bset
       endcase
       if (P.XLEN==32) // ZBS 64-bit
         casez({OpD, Funct7D, Funct3D})
           17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_1_1_0_1_0_0;  // bclri
-          17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_1_0_1_0_0;  // bexti
+          17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_0_0_1_0_0;  // bexti
           17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_1_0_0_1_0_0;  // binvi
           17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_1_0_0_1_0_0;  // bseti
         endcase
       else if (P.XLEN==64) // ZBS 64-bit
         casez({OpD, Funct7D, Funct3D})
           17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_1_1_0_1_0_0;  // bclri (rv64)
-          17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_1_0_1_0_0;  // bexti (rv64)
+          17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_0_0_1_0_0;  // bexti (rv64)
           17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_1_0_0_1_0_0;  // binvi (rv64)
           17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_1_0_0_1_0_0;  // bseti (rv64)
         endcase
@@ -264,7 +259,7 @@ module bmuctrl import cvw::*;  #(parameter cvw_t P) (
           17'b0110011_0101111_000:     BMUControlsD = `BMUCTRLW'b000_1000_1010_1_0_0_1_0_0_0_0_0;  // sha512sig1h
           17'b0110011_0101011_000:     BMUControlsD = `BMUCTRLW'b000_1000_1011_1_0_0_1_0_0_0_0_0;  // sha512sig1l
           17'b0110011_0101000_000:     BMUControlsD = `BMUCTRLW'b000_1000_1100_1_0_0_1_0_0_0_0_0;  // sha512sum0r
-          17'b0110011_0101001_000:     BMUControlsD = `BMUCTRLW'b000_1000_1101_1_0_0_1_0_0_0_0_0;  // sha512sum1r
+          17'b0110011_0101001_000:     BMUControlsD = `BMUCTRLW'b000_1000_1110_1_0_0_1_0_0_0_0_0;  // sha512sum1r
         endcase
 
       else if (P.XLEN==64)
@@ -288,5 +283,5 @@ module bmuctrl import cvw::*;  #(parameter cvw_t P) (
   assign ALUSelectD = BALUOpD ? BALUSelectD : (ALUOpD ? Funct3D : 3'b000);
 
   // BMU Execute stage pipieline control register
-  flopenrc #(13) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE, BMUActiveE});
+  flopenrc #(12) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BALUControlE, BMUActiveE});
 endmodule
diff --git a/src/ieu/bmu/byteop.sv b/src/ieu/bmu/byteop.sv
index 980c6d586..33a0dc332 100644
--- a/src/ieu/bmu/byteop.sv
+++ b/src/ieu/bmu/byteop.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: RISCV bitmanip byte-wise operation unit
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -30,24 +30,16 @@
 
 module byteop #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A,             // Operands
-  input  logic [WIDTH-1:0] RevA,          // Reversed A
-  input  logic [1:0]       ByteSelect,    // LSB of Immediate
+  input  logic             ByteSelect,    // LSB of Immediate
   output logic [WIDTH-1:0] ByteResult);   // rev8, orcb result
 
-  logic [WIDTH-1:0] OrcBResult, Rev8Result, Brev8Result;
+  logic [WIDTH-1:0] OrcBResult, Rev8Result;
   genvar i;
 
-  for (i=0;i<WIDTH;i+=8) begin:loop
+  for (i=0;i<WIDTH;i+=8) begin:byteloop
     assign OrcBResult[i+7:i] = {8{|A[i+7:i]}};
     assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i];
-    assign Brev8Result[i+7:i] = RevA[WIDTH-1-i:WIDTH-i-8];
   end
 
-  // ByteOp Result Mux
-  always_comb begin
-    if (ByteSelect[0] == 1'b0)      ByteResult = Rev8Result;
-    else if (ByteSelect[1] == 1'b0) ByteResult = OrcBResult;
-    else                            ByteResult = Brev8Result;
-  end
-  
+  mux2 #(WIDTH) byteresultmux(Rev8Result, OrcBResult, ByteSelect, ByteResult);
 endmodule
diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv
index f32fcece9..2ea45606f 100644
--- a/src/ieu/bmu/clmul.sv
+++ b/src/ieu/bmu/clmul.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Carry-Less multiplication unit
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv
index 3650f14ca..f0bc5f72d 100644
--- a/src/ieu/bmu/cnt.sv
+++ b/src/ieu/bmu/cnt.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Count Instruction Submodule
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -56,8 +56,8 @@ module cnt #(parameter WIDTH = 32) (
   lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult[$clog2(WIDTH):0]));
   popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult[$clog2(WIDTH):0]));
   // zero extend these results to fit into width
-  assign czResult[WIDTH-1:$clog2(WIDTH)+1] = 0;
-  assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = 0;
+  assign czResult[WIDTH-1:$clog2(WIDTH)+1] = '0;
+  assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = '0;
 
   mux2 #(WIDTH) cntresultmux(czResult, cpopResult, B[1], CntResult);
 endmodule
diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv
index 66d69fb21..c5dcbf531 100644
--- a/src/ieu/bmu/ext.sv
+++ b/src/ieu/bmu/ext.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Sign/Zero Extension Submodule
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -29,7 +29,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module ext #(parameter WIDTH = 32) (
-  input  logic [WIDTH-1:0] A,            // Operands
+  input  logic [15:0]      A,            // Operand to extend
   input  logic [1:0]       ExtSelect,    // B[2], B[0] of immediate
   output logic [WIDTH-1:0] ExtResult);   // Extend Result
 
diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv
index 8f5759873..435c8dff1 100644
--- a/src/ieu/bmu/popcnt.sv
+++ b/src/ieu/bmu/popcnt.sv
@@ -5,7 +5,7 @@
 //
 // Purpose: Population Count
 // 
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -34,7 +34,7 @@ module popcnt #(parameter WIDTH = 32) (
   logic [$clog2(WIDTH):0] sum; 
   
   always_comb begin
-    sum = 0;
+    sum = '0;
     for (int i=0;i<WIDTH;i++) begin:loop
       sum = (num[i]) ? sum + 1 : sum;
     end
diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv
index e96ed7acd..d5ca3bd4b 100644
--- a/src/ieu/bmu/zbb.sv
+++ b/src/ieu/bmu/zbb.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: RISC-V ZBB top level unit
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -45,8 +45,8 @@ module zbb #(parameter WIDTH=32) (
 
   mux2 #(1) ltmux(LT, LTU, BUnsigned , lt);
   cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult);
-  byteop #(WIDTH) bu(.A, .RevA, .ByteSelect({B[10], B[0]}), .ByteResult);
-  ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
+  byteop #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
+  ext #(WIDTH) ext(.A(A[15:0]), .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
 
   // ZBBSelect[2] differentiates between min(u) vs max(u) instruction
   mux2 #(WIDTH) minmaxmux(B, A, ZBBSelect[2]^lt, MinMaxResult);
diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv
index 6e1948c33..a9a027ab6 100644
--- a/src/ieu/bmu/zbc.sv
+++ b/src/ieu/bmu/zbc.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: RISC-V ZBC top-level unit
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -28,23 +28,31 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module zbc #(parameter WIDTH=32) (
-  input  logic [WIDTH-1:0] A, RevA, B,       // Operands
-  input  logic [2:0]       Funct3,           // Indicates operation to perform
-  output logic [WIDTH-1:0] ZBCResult);       // ZBC result
+module zbc import cvw::*; #(parameter cvw_t P) (
+  input  logic [P.XLEN-1:0] A, RevA, B,       // Operands
+  input  logic [1:0]        Funct3,           // Indicates operation to perform
+  output logic [P.XLEN-1:0] ZBCResult);       // ZBC result
 
-  logic [WIDTH-1:0] ClmulResult, RevClmulResult;
-  logic [WIDTH-1:0] RevB;
-  logic [WIDTH-1:0] X, Y;
+  logic [P.XLEN-1:0] ClmulResult, RevClmulResult;
+  logic [P.XLEN-1:0] RevB;
+  logic [P.XLEN-1:0] X, Y;
 
-  bitreverse #(WIDTH) brB(B, RevB);
+  bitreverse #(P.XLEN) brB(B, RevB);
 
-  mux3 #(WIDTH) xmux({RevA[WIDTH-2:0], {1'b0}}, RevA, A, ~Funct3[1:0], X);
-  mux2 #(WIDTH) ymux(RevB, B, ~Funct3[1], Y);
+  // choose X = A for clmul, Rev(A) << 1 for clmulh, Rev(A) for clmulr
+  // unshifted Rev(A) source is only needed for clmulr in ZBC, not in ZBKC
+  if (P.ZBC_SUPPORTED)
+    mux3 #(P.XLEN) xmux({RevA[P.XLEN-2:0], {1'b0}}, RevA, A, ~Funct3[1:0], X);
+  else
+    mux2 #(P.XLEN) xmux(A, {RevA[P.XLEN-2:0], {1'b0}}, Funct3[1], X);
 
-  clmul #(WIDTH) clm(.X, .Y, .ClmulResult);
-  
-  bitreverse  #(WIDTH) brClmulResult(ClmulResult, RevClmulResult);
+  // choose X = B for clmul, Rev(B) for clmulH
+  mux2 #(P.XLEN) ymux(B, RevB, Funct3[1], Y);
 
-  mux2 #(WIDTH) zbcresultmux(ClmulResult, RevClmulResult, Funct3[1], ZBCResult);
+  // carry free multiplier
+  clmul #(P.XLEN) clm(.X, .Y, .ClmulResult);
+
+  // choose result = rev(X @ Y) for clmulh/clmulr
+  bitreverse #(P.XLEN) brClmulResult(ClmulResult, RevClmulResult);
+  mux2 #(P.XLEN) zbcresultmux(ClmulResult, RevClmulResult, Funct3[1], ZBCResult);
 endmodule
diff --git a/src/ieu/comparator.sv b/src/ieu/comparator.sv
index 466167fb3..175e7df08 100644
--- a/src/ieu/comparator.sv
+++ b/src/ieu/comparator.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Branch comparison
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index 9bb40af12..4057ea9cd 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Top level controller module
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -53,16 +53,13 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   output logic        ALUSrcAE, ALUSrcBE,      // ALU operands
   output logic        ALUResultSrcE,           // Selects result to pass on to Memory stage
   output logic [2:0]  ALUSelectE,              // ALU mux select signal
-  output logic        MemReadE, CSRReadE,      // Instruction reads memory, reads a CSR (needed for Hazard unit)
   output logic [2:0]  Funct3E,                 // Instruction's funct3 field
   output logic [6:0]  Funct7E,                 // Instruction's funct7 field
   output logic        IntDivE,                 // Integer divide
-  output logic        MDUE,                    // MDU (multiply/divide) operatio
   output logic        W64E,                    // RV64 W-type operation
   output logic        SubArithE,               // Subtraction or arithmetic shift
   output logic        JumpE,                   // jump instruction
   output logic        BranchE,                 // Branch instruction
-  output logic        SCE,                     // Store Conditional instruction
   output logic        BranchSignedE,           // Branch comparison operands are signed (if it's a branch)
   output logic [3:0]  BSelectE,                // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction
   output logic [3:0]  ZBBSelectE,              // ZBB mux select signal in Execute stage
@@ -81,7 +78,6 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   output logic        CSRReadM, CSRWriteM, PrivilegedM, // CSR read, write, or privileged instruction
   output logic [1:0]  AtomicM,                 // Atomic (AMO) instruction
   output logic [2:0]  Funct3M,                 // Instruction's funct3 field
-  output logic        RegWriteM,               // Instruction writes a register (needed for Hazard unit)
   output logic        InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
   output logic        InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
   output logic        FWriteIntM,              // FPU controller writes integer register file
@@ -93,7 +89,11 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   output logic        CSRWriteFenceM,          // CSR write or fence instruction; needs to flush the following instructions
   output logic [4:0]  RdE, RdM,                // Pipelined destination registers
   // Forwarding controls
-  output logic [4:0]  RdW                      // Register destinations in Execute, Memory, or Writeback stage
+  output logic [4:0]  RdW,                     // Register destinations in Execute, Memory, or Writeback stage
+  // Debug scan chain
+  input  logic        DebugScanEn,
+  input  logic        DebugScanIn,
+  output logic        DebugScanOut
 );
 
   logic [4:0] Rs1E;                      // pipelined register sources
@@ -122,6 +122,9 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   logic        FenceXD;                        // Fence instruction
   logic        CMOD;                           // Cache management instruction
   logic        InvalidateICacheD, FlushDCacheD;// Invalidate I$, flush D$
+  logic        MemReadE, CSRReadE;             // Instruction reads memory, reads a CSR (needed for Hazard unit)
+  logic        MDUE;                           // MDU (multiply/divide) operatio
+  logic        SCE;                            // Store Conditional instruction
   logic        CSRWriteD, CSRWriteE;           // CSR write
   logic        PrivilegedD, PrivilegedE;       // Privileged instruction
   logic        InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$
@@ -133,14 +136,12 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   logic        unused; 
   logic        BranchFlagE;                    // Branch flag to use (chosen between eq or lt)
   logic        IEURegWriteE;                   // Register write 
-  logic        BRegWriteE;                     // Register write from BMU controller in Execute Stage
   logic        IllegalERegAdrD;                // RV32E attempts to write upper 16 registers
   logic [1:0]  AtomicE;                        // Atomic instruction 
   logic        FenceD, FenceE;                 // Fence instruction
   logic        SFenceVmaD;                     // sfence.vma instruction
   logic        IntDivM;                        // Integer divide instruction
-  logic [3:0]  BSelectD;                       // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage
-  logic [3:0]  ZBBSelectD;                     // ZBB Mux Select Signal
+  logic        RegWriteM;                      // Instruction writes a register (needed for Hazard unit)
   logic [1:0]  CZeroD;
   logic        IFunctD, RFunctD, MFunctD;      // Detect I, R, and M-type RV32IM/Rv64IM instructions
   logic        LFunctD, SFunctD, BFunctD;      // Detect load, store, branch instructions
@@ -158,7 +159,6 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   logic [3:0]  CMOpD, CMOpE;                   // which CMO instruction 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
   logic        IFUPrefetchD;                   // instruction prefetch
   logic        LSUPrefetchD, LSUPrefetchE;     // data prefetch
-  logic        CMOStallD;                      // Structural hazards from cache management ops
   logic        MatchDE;                        // Match between a source register in Decode stage and destination register in Execute stage
   logic        FCvtIntStallD, MDUStallD, CSRRdStallD; // Stall due to conversion, load, multiply/divide, CSR read 
   logic        FunctCZeroD;                    // Funct7 and Funct3 indicate czero.* (not including Op check)
@@ -175,7 +175,9 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   // Be rigorous about detecting illegal instructions if CSRs or bit manipulation or conditional ops are supported
   // otherwise be cheap
 
-  if (P.ZICSR_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZICOND_SUPPORTED) begin:legalcheck // Exact integer decoding
+  if (P.ZICSR_SUPPORTED | P.ZBA_SUPPORTED  | P.ZBB_SUPPORTED  | P.ZBC_SUPPORTED  | P.ZBS_SUPPORTED | 
+      P.ZBKB_SUPPORTED  | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKNE_SUPPORTED | 
+      P.ZKND_SUPPORTED  | P.ZKNH_SUPPORTED | P.ZICOND_SUPPORTED) begin:legalcheck // Exact integer decoding
     logic Funct7ZeroD, Funct7b5D, IShiftD, INoShiftD;
     logic Funct7ShiftZeroD, Funct7Shiftb5D;
 
@@ -219,23 +221,23 @@ module controller import cvw::*;  #(parameter cvw_t P) (
     assign CSRFunctD        = Funct3D[1:0] != 2'b00; 
     assign IWValidFunct3D   = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b101;
   end else begin:legalcheck2
-    assign IFunctD = 1; // Don't bother to separate out shift decoding
+    assign IFunctD = 1'b1; // Don't bother to separate out shift decoding
     assign RFunctD = ~Funct7D[0]; // Not a multiply
     assign MFunctD = Funct7D[0] & (P.M_SUPPORTED | (P.ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv
-    assign LFunctD = 1; // don't bother to check Funct3 for loads
-    assign FLSFunctD = 1; // don't bother to check Func3 for floating-point loads/stores
-    assign FenceFunctD = 1; // don't bother to check fields for fences
-    assign CMOFunctD = 1; // don't bother to check fields for CMO instructions
-    assign AFunctD = 1; // don't bother to check fields for atomics
-    assign AMOFunctD = 1; // don't bother to check Funct7 for AMO operations
-    assign RWFunctD = 1; // don't bother to check fields for RW instructions
-    assign MWFunctD = 1; // don't bother to check fields for MW instructions
-    assign SFunctD = 1; // don't bother to check Funct3 for stores
-    assign BFunctD = 1; // don't bother to check Funct3 for branches
-    assign JRFunctD = 1; // don't bother to check Funct3 for jalrs
-    assign PFunctD = 1; // don't bother to check fields for privileged instructions
-    assign CSRFunctD = 1; // don't bother to check Funct3 for CSR operations
-    assign IWValidFunct3D = 1;
+    assign LFunctD = 1'b1; // don't bother to check Funct3 for loads
+    assign FLSFunctD = 1'b1; // don't bother to check Func3 for floating-point loads/stores
+    assign FenceFunctD = 1'b1; // don't bother to check fields for fences
+    assign CMOFunctD = 1'b1; // don't bother to check fields for CMO instructions
+    assign AFunctD = 1'b1; // don't bother to check fields for atomics
+    assign AMOFunctD = 1'b1; // don't bother to check Funct7 for AMO operations
+    assign RWFunctD = 1'b1; // don't bother to check fields for RW instructions
+    assign MWFunctD = 1'b1; // don't bother to check fields for MW instructions
+    assign SFunctD = 1'b1; // don't bother to check Funct3 for stores
+    assign BFunctD = 1'b1; // don't bother to check Funct3 for branches
+    assign JRFunctD = 1'b1; // don't bother to check Funct3 for jalrs
+    assign PFunctD = 1'b1; // don't bother to check fields for privileged instructions
+    assign CSRFunctD = 1'b1; // don't bother to check Funct3 for CSR operations
+    assign IWValidFunct3D = 1'b1;
   end
 
   // Main Instruction Decoder
@@ -265,12 +267,12 @@ module controller import cvw::*;  #(parameter cvw_t P) (
                       ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_0; // stores
       7'b0100111: if (FLSFunctD)
                       ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_1; // fsw - only legal if FP supported
-      7'b0101111: if (P.A_SUPPORTED & AFunctD) begin
-                    if (InstrD[31:27] == 5'b00010 & Rs2D == 5'b0)
+      7'b0101111: if (AFunctD) begin
+                    if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00010 & Rs2D == 5'b0)
                       ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0_0; // lr
-                    else if (InstrD[31:27] == 5'b00011)
+                    else if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00011)
                       ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0_0; // sc
-                    else if (AMOFunctD) 
+                    else if ((P.A_SUPPORTED | P.ZAAMO_SUPPORTED) & AMOFunctD) 
                       ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0_0; // amo
                  end
       7'b0110011: if (RFunctD)
@@ -318,16 +320,18 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   assign BaseSubArithD = ALUOpD & (subD | sraD | sltD | sltuD);
 
   // bit manipulation Configuration Block
-  if (P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
+  if (P.ZBS_SUPPORTED  | P.ZBA_SUPPORTED  | P.ZBB_SUPPORTED  | P.ZBC_SUPPORTED |
+      P.ZBKB_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKNE_SUPPORTED | 
+      P.ZKND_SUPPORTED | P.ZKNH_SUPPORTED) begin: bitmanipi 
     logic IllegalBitmanipInstrD;          // Unrecognized B instruction
     logic BRegWriteD;                     // Indicates if it is a R type BMU instruction in decode stage
     logic BW64D;                          // Indicates if it is a W type BMU instruction in decode stage
     logic BSubArithD;                     // TRUE for BMU ext, clr, andn, orn, xnor
     logic BALUSrcBD;                      // BMU alu src select signal
 
-    bmuctrl #(P) bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUOpD, .BSelectD, .ZBBSelectD, 
+    bmuctrl #(P) bmuctrl(.clk, .reset, .InstrD, .ALUOpD,
       .BRegWriteD, .BALUSrcBD, .BW64D, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, 
-      .ALUSelectD(PreALUSelectD), .BSelectE, .ZBBSelectE, .BRegWriteE, .BALUControlE, .BMUActiveE);
+      .ALUSelectD(PreALUSelectD), .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE);
     if (P.ZBA_SUPPORTED) begin
       // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw
       assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ;
@@ -353,7 +357,6 @@ module controller import cvw::*;  #(parameter cvw_t P) (
 
     // tie off unused bit manipulation signals
     assign BSelectE = 4'b0000;
-    assign BSelectD = 4'b0000;
     assign ZBBSelectE = 4'b0000;
     assign BALUControlE = 3'b0;
     assign BMUActiveE = 1'b0;
@@ -378,8 +381,8 @@ module controller import cvw::*;  #(parameter cvw_t P) (
     assign InvalidateICacheD = FenceID;
     assign FlushDCacheD = FenceID;
   end else begin:fencei
-    assign InvalidateICacheD = 0;
-    assign FlushDCacheD = 0;
+    assign InvalidateICacheD = 1'b0;
+    assign FlushDCacheD = 1'b0;
   end
 
   // Cache Management instructions
@@ -442,9 +445,17 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   assign IntDivE = MDUE & Funct3E[2]; // Integer division operation
   
   // Memory stage pipeline control register
-  flopenrc #(25) controlregM(clk, reset, FlushM, ~StallM,
-                         {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE, CMOpE, LSUPrefetchE},
-                         {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM, CMOpM, LSUPrefetchM});
+  if (P.DEBUG_SUPPORTED) begin
+    flopenrc #(22) controlregM(clk, reset, FlushM, ~StallM,
+                          {RegWriteE, ResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, IntDivE, CMOpE, LSUPrefetchE},
+                          {RegWriteM, ResultSrcM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, IntDivM, CMOpM, LSUPrefetchM});
+    flopenrcs #(3) controlscanreg(clk, reset, FlushM, ~StallM, {MemRWE,InstrValidE}, {MemRWM,InstrValidM}, DebugScanEn, DebugScanIn, DebugScanOut);
+  end else begin
+    flopenrc #(25) controlregM(clk, reset, FlushM, ~StallM,
+                          {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE, CMOpE, LSUPrefetchE},
+                          {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM, CMOpM, LSUPrefetchM});
+    assign DebugScanOut = DebugScanIn;
+  end
   flopenrc #(5)  RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);  
 
   // Writeback stage pipeline control register
diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv
index 49da4e0cb..0a378ba05 100644
--- a/src/ieu/datapath.sv
+++ b/src/ieu/datapath.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Wally Integer Datapath
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -33,7 +33,7 @@ module datapath import cvw::*;  #(parameter cvw_t P) (
   // Decode stage signals
   input  logic [2:0]        ImmSrcD,                 // Selects type of immediate extension
   input  logic [31:0]       InstrD,                  // Instruction in Decode stage
-  input  logic [4:0]        Rs1D, Rs2D, Rs2E,             // Source registers
+  input  logic [4:0]        Rs1D, Rs2D, Rs2E,        // Source registers
   // Execute stage signals
   input  logic [P.XLEN-1:0] PCE,                     // PC in Execute stage  
   input  logic [P.XLEN-1:0] PCLinkE,                 // PC + 4 (of instruction in Execute stage)
@@ -72,15 +72,26 @@ module datapath import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.XLEN-1:0] CSRReadValW,             // CSR read result
   input  logic [P.XLEN-1:0] MDUResultW,              // MDU (Multiply/divide unit) result
   input  logic [P.XLEN-1:0] FIntDivResultW,          // FPU's integer divide result
-  input  logic [4:0]        RdW                      // Destination register
-   // Hazard Unit signals 
+  input  logic [4:0]        RdW,                     // Destination register
+  // Hazard Unit signals
+  // Debug scan chain
+  input  logic              DebugScanEn,
+  input  logic              DebugScanIn,
+  output logic              DebugScanOut,
+  input  logic              MiscSel,
+  input  logic              GPRSel,
+  input  logic              DebugCapture,
+  input  logic              DebugRegUpdate,
+  input  logic [4:0]        DebugRegAddr,
+  input  logic              GPRScanIn,
+  output logic              GPRScanOut
 );
 
   // Fetch stage signals
   // Decode stage signals
+  logic [4:0]        Rs1DM;                          // (Debug) Muxed source register
   logic [P.XLEN-1:0] R1D, R2D;                       // Read data from Rs1 (RD1), Rs2 (RD2)
   logic [P.XLEN-1:0] ImmExtD;                        // Extended immediate in Decode stage
-  logic [4:0]        RdD;                            // Destination register in Decode stage
   // Execute stage signals
   logic [P.XLEN-1:0] R1E, R2E;                       // Source operands read from register file
   logic [P.XLEN-1:0] ImmExtE;                        // Extended immediate in Execute stage 
@@ -90,15 +101,31 @@ module datapath import cvw::*;  #(parameter cvw_t P) (
   logic [P.XLEN-1:0] IEUResultM;                     // Result from execution stage
   logic [P.XLEN-1:0] IFResultM;                      // Result from either IEU or single-cycle FPU op writing an integer register
   // Writeback stage signals
+  logic              RegWriteWM;                     // (Debug) Muxed write enable
   logic [P.XLEN-1:0] SCResultW;                      // Store Conditional result
-  logic [P.XLEN-1:0] ResultW;                        // Result to write to register file
+  logic [P.XLEN-1:0] ResultW;
+  logic [P.XLEN-1:0] ResultWM;              // Result to write to register file
+  logic [4:0]        RdWM;                           // Muxed GPR write address
   logic [P.XLEN-1:0] IFResultW;                      // Result from either IEU or single-cycle FPU op writing an integer register
   logic [P.XLEN-1:0] IFCvtResultW;                   // Result from IEU, signle-cycle FPU op, or 2-cycle FCVT float to int 
   logic [P.XLEN-1:0] MulDivResultW;                  // Multiply always comes from MDU.  Divide could come from MDU or FPU (when using fdivsqrt for integer division)
+  // Debug signals
+  logic [P.XLEN-1:0] DebugGPRWriteD;
 
   // Decode stage
-  regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D);
   extend #(P)        ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ImmExtD);
+  // Access GPRs from Debug Module
+  if (P.DEBUG_SUPPORTED) begin
+    regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteWM, Rs1DM, Rs2D, RdWM, ResultWM, R1D, R2D);
+    assign RegWriteWM = GPRSel ? DebugRegUpdate : RegWriteW;
+    assign Rs1DM = GPRSel ? DebugRegAddr : Rs1D;
+    assign RdWM = GPRSel ? DebugRegAddr : RdW;
+    assign ResultWM = GPRSel ? DebugGPRWriteD : ResultW;
+    flopenrs #(P.XLEN) GPScanReg(.clk, .reset, .en(DebugCapture), .d(R1D), .q(DebugGPRWriteD), .scan(DebugScanEn & GPRSel), .scanin(GPRScanIn), .scanout(GPRScanOut));
+  end else begin
+    regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D);
+    assign GPRScanOut = GPRScanIn;
+  end
  
   // Execute stage pipeline register and logic
   flopenrc #(P.XLEN) RD1EReg(clk, reset, FlushE, ~StallE, R1D, R1E);
@@ -117,7 +144,12 @@ module datapath import cvw::*;  #(parameter cvw_t P) (
   // Memory stage pipeline register
   flopenrc #(P.XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
   flopenrc #(P.XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
-  flopenrc #(P.XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM); 
+  if (P.DEBUG_SUPPORTED)
+    flopenrcs #(P.XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM, (DebugScanEn & MiscSel), DebugScanIn, DebugScanOut);
+  else begin
+    flopenrc #(P.XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM);
+    assign DebugScanOut = DebugScanIn;
+  end
   
   // Writeback stage pipeline register and logic
   flopenrc #(P.XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW);
@@ -139,6 +171,6 @@ module datapath import cvw::*;  #(parameter cvw_t P) (
   mux5  #(P.XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); 
  
   // handle Store Conditional result if atomic extension supported
-  if (P.A_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW};
-  else               assign SCResultW = 0;
+  if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW};
+  else                                    assign SCResultW = '0;
 endmodule
diff --git a/src/ieu/extend.sv b/src/ieu/extend.sv
index b090c3f5e..437797859 100644
--- a/src/ieu/extend.sv
+++ b/src/ieu/extend.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Produce sign-extended immediates from various formats
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.3)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -48,7 +48,7 @@ module extend import cvw::*;  #(parameter cvw_t P) (
       // U-type (lui, auipc)
       3'b100:   ImmExtD = {{(P.XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; 
       // Store Conditional: zero offset
-      3'b101:  if (P.A_SUPPORTED | P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) ImmExtD = 0;
+      3'b101:  if (P.A_SUPPORTED | P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) ImmExtD = '0;
                else             ImmExtD = undefined;
       default: ImmExtD = undefined; // undefined
     endcase  
diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv
index 38d50e3c3..6a3b7124e 100644
--- a/src/ieu/ieu.sv
+++ b/src/ieu/ieu.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Integer Execution Unit: datapath and controller
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -28,57 +28,68 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module ieu import cvw::*;  #(parameter cvw_t P) (
-  input  logic              clk, reset,
+  input  logic                     clk, reset,
   // Decode stage signals
-  input  logic [31:0]       InstrD,                          // Instruction
-  input  logic [1:0]        STATUS_FS,                       // is FPU enabled?
-  input  logic [3:0]        ENVCFG_CBE,                      // Cache block operation enables
-  input  logic              IllegalIEUFPUInstrD,             // Illegal instruction
-  output logic              IllegalBaseInstrD,               // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
+  input  logic [31:0]              InstrD,                                // Instruction
+  input  logic [1:0]               STATUS_FS,                             // is FPU enabled?
+  input  logic [3:0]               ENVCFG_CBE,                            // Cache block operation enables
+  input  logic                     IllegalIEUFPUInstrD,                   // Illegal instruction
+  output logic                     IllegalBaseInstrD,                     // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
   // Execute stage signals
-  input  logic [P.XLEN-1:0] PCE,                             // PC
-  input  logic [P.XLEN-1:0] PCLinkE,                         // PC + 4
-  output logic              PCSrcE,                          // Select next PC (between PC+4 and IEUAdrE)
-  input  logic              FWriteIntE, FCvtIntE,            // FPU writes to integer register file, FPU converts float to int
-  output logic [P.XLEN-1:0] IEUAdrE,                         // Memory address
-  output logic              IntDivE, W64E,                   // Integer divide, RV64 W-type instruction 
-  output logic [2:0]        Funct3E,                         // Funct3 instruction field
-  output logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE,  // ALU src inputs before the mux choosing between them and PCE to put in srcA/B
-  output logic [4:0]        RdE,                             // Destination register
-  output logic              MDUActiveE,                      // Mul/Div instruction being executed
-  output logic [3:0]        CMOpM,                           // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
-  output logic              IFUPrefetchE,                    // instruction prefetch
-  output logic              LSUPrefetchM,                    // datata prefetch
-  // Memory stage signals
-  input  logic              SquashSCW,                       // Squash store conditional, from LSU
-  output logic [1:0]        MemRWE,                          // Read/write control goes to LSU
-  output logic [1:0]        MemRWM,                          // Read/write control goes to LSU
-  output logic [1:0]        AtomicM,                         // Atomic control goes to LSU
-  output logic [P.XLEN-1:0] WriteDataM,                      // Write data to LSU
-  output logic [2:0]        Funct3M,                         // Funct3 (size and signedness) to LSU
-  output logic [P.XLEN-1:0] SrcAM,                           // ALU SrcA to Privileged unit and FPU
-  output logic [4:0]        RdM,                             // Destination register
-  input  logic [P.XLEN-1:0] FIntResM,                        // Integer result from FPU (fmv, fclass, fcmp)
-  output logic              InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
-  output logic              InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
-  output logic              BranchD, BranchE,
-  output logic              JumpD, JumpE,
+  input  logic [P.XLEN-1:0]        PCE,                                   // PC
+  input  logic [P.XLEN-1:0]        PCLinkE,                               // PC + 4
+  output logic                     PCSrcE,                                // Select next PC (between PC+4 and IEUAdrE)
+  input  logic                     FWriteIntE, FCvtIntE,                  // FPU writes to integer register file, FPU converts float to int
+  output logic [P.XLEN-1:0]        IEUAdrE,                               // Memory address
+  output logic                     IntDivE, W64E,                         // Integer divide, RV64 W-type instruction 
+  output logic [2:0]               Funct3E,                               // Funct3 instruction field
+  output logic [P.XLEN-1:0]        ForwardedSrcAE, ForwardedSrcBE,        // ALU src inputs before the mux choosing between them and PCE to put in srcA/B
+  output logic [4:0]               RdE,                                   // Destination register
+  output logic                     MDUActiveE,                            // Mul/Div instruction being executed
+  output logic [3:0]               CMOpM,                                 // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
+  output logic                     IFUPrefetchE,                          // instruction prefetch
+  output logic                     LSUPrefetchM,                          // datata prefetch
+  // Memory stage signals 
+  input  logic                     SquashSCW,                             // Squash store conditional, from LSU
+  output logic [1:0]               MemRWE,                                // Read/write control goes to LSU
+  output logic [1:0]               MemRWM,                                // Read/write control goes to LSU
+  output logic [1:0]               AtomicM,                               // Atomic control goes to LSU
+  output logic [P.XLEN-1:0]        WriteDataM,                            // Write data to LSU
+  output logic [2:0]               Funct3M,                               // Funct3 (size and signedness) to LSU
+  output logic [P.XLEN-1:0]        SrcAM,                                 // ALU SrcA to Privileged unit and FPU
+  output logic [4:0]               RdM,                                   // Destination register
+  input  logic [P.XLEN-1:0]        FIntResM,                              // Integer result from FPU (fmv, fclass, fcmp)
+  output logic                     InvalidateICacheM, FlushDCacheM,       // Invalidate I$, flush D$
+  output logic                     InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
+  output logic                     BranchD, BranchE,
+  output logic                     JumpD, JumpE,
   // Writeback stage signals
-  input  logic [P.XLEN-1:0] FIntDivResultW,                  // Integer divide result from FPU fdivsqrt)
-  input  logic [P.XLEN-1:0] CSRReadValW,                     // CSR read value, 
-  input  logic [P.XLEN-1:0] MDUResultW,                      // multiply/divide unit result
-  input  logic [P.XLEN-1:0] FCvtIntResW,                     // FPU's float to int conversion result
-  input  logic              FCvtIntW,                        // FPU converts float to int
-  output logic [4:0]        RdW,                             // Destination register
-  input  logic [P.XLEN-1:0] ReadDataW,                       // LSU's read data
+  input  logic [P.XLEN-1:0]        FIntDivResultW,                        // Integer divide result from FPU fdivsqrt)
+  input  logic [P.XLEN-1:0]        CSRReadValW,                           // CSR read value, 
+  input  logic [P.XLEN-1:0]        MDUResultW,                            // multiply/divide unit result
+  input  logic [P.XLEN-1:0]        FCvtIntResW,                           // FPU's float to int conversion result
+  input  logic                     FCvtIntW,                              // FPU converts float to int
+  output logic [4:0]               RdW,                                   // Destination register
+  input  logic [P.XLEN-1:0]        ReadDataW,                             // LSU's read data
   // Hazard unit signals
-  input  logic              StallD, StallE, StallM, StallW,  // Stall signals from hazard unit
-  input  logic              FlushD, FlushE, FlushM, FlushW,  // Flush signals
-  output logic              StructuralStallD,                // IEU detects structural hazard in Decode stage
-  output logic              LoadStallD,                      // Structural stalls for load, sent to performance counters
-  output logic              StoreStallD,                     // load after store hazard
-  output logic              CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction
-  output logic              CSRWriteFenceM                   // CSR write or fence instruction needs to flush subsequent instructions
+  input  logic              StallD, StallE, StallM, StallW,               // Stall signals from hazard unit
+  input  logic              FlushD, FlushE, FlushM, FlushW,               // Flush signals
+  output logic              StructuralStallD,                             // IEU detects structural hazard in Decode stage
+  output logic              LoadStallD,                                   // Structural stalls for load, sent to performance counters
+  output logic              StoreStallD,                                  // load after store hazard
+  output logic              CSRReadM, CSRWriteM, PrivilegedM,             // CSR read, CSR write, is privileged instruction
+  output logic              CSRWriteFenceM,                               // CSR write or fence instruction needs to flush subsequent instructions
+  // Debug scan chain
+  input  logic              DebugScanEn,
+  input  logic              MiscSel,
+  input  logic              GPRSel,
+  input  logic              DebugScanIn,
+  input  logic              GPRScanIn,
+  output logic              DebugScanOut,
+  output logic              GPRScanOut,
+  input  logic              DebugCapture,
+  input  logic              DebugRegUpdate,
+  input  logic [4:0]        DebugRegAddr
 );
 
   logic [2:0] ImmSrcD;                                       // Select type of immediate extension 
@@ -87,7 +98,6 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
   logic [2:0] ResultSrcW;                                    // Selects result in Writeback stage
   logic       ALUResultSrcE;                                 // Selects ALU result to pass on to Memory stage
   logic [2:0] ALUSelectE;                                    // ALU select mux signal
-  logic       SCE;                                           // Store Conditional instruction
   logic       FWriteIntM;                                    // FPU writing to integer register file
   logic       IntDivW;                                       // Integer divide instruction
   logic [3:0] BSelectE;                                      // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
@@ -99,28 +109,27 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
 
   // Forwarding signals
   logic [4:0] Rs1D, Rs2D;
-  logic [4:0] Rs2E;                                    // Source registers
+  logic [4:0] Rs2E;                                          // Source registers
   logic [1:0] ForwardAE, ForwardBE;                          // Select signals for forwarding multiplexers
-  logic       RegWriteM, RegWriteW;                          // Register will be written in Memory, Writeback stages
-  logic       MemReadE, CSRReadE;                            // Load, CSRRead instruction
+  logic       RegWriteW;                                     // Register will be written in Writeback stage
   logic       BranchSignedE;                                 // Branch does signed comparison on operands
-  logic       MDUE;                                          // Multiply/divide instruction
   logic       BMUActiveE;                                    // Bit manipulation instruction being executed
   logic [1:0] CZeroE;                                        // {czero.nez, czero.eqz} instructions active
+  logic DSCR;                                                             // Debug Scan Chain Register
            
   controller #(P) c(
     .clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD,
     .IllegalIEUFPUInstrD, .IllegalBaseInstrD, 
     .StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D,  .Rs2E,
     .StallE, .FlushE, .FlagsE, .FWriteIntE,
-    .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, 
-    .Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, 
+    .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE,
+    .Funct3E, .Funct7E, .IntDivE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE,
     .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE, .MDUActiveE, 
     .FCvtIntE, .ForwardAE, .ForwardBE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM,
     .StallM, .FlushM, .MemRWE, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
-    .RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
+    .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
     .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM,
-    .RdW, .RdE, .RdM);
+    .RdW, .RdE, .RdM, .DebugScanEn(DebugScanEn & MiscSel), .DebugScanIn, .DebugScanOut(DSCR));
 
   datapath #(P) dp(
     .clk, .reset, .ImmSrcD, .InstrD, .Rs1D, .Rs2D, .Rs2E, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .SubArithE,
@@ -128,5 +137,6 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
     .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE,
     .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
     .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
-    .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW);             
+    .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .DebugScanEn, .DebugScanIn(DSCR), .DebugScanOut,
+    .MiscSel, .GPRSel, .DebugCapture, .DebugRegUpdate, .DebugRegAddr, .GPRScanIn, .GPRScanOut);
 endmodule
diff --git a/src/ieu/kmu/packer.sv b/src/ieu/kmu/packer.sv
index fcf2f9eef..ac44916d7 100644
--- a/src/ieu/kmu/packer.sv
+++ b/src/ieu/kmu/packer.sv
@@ -26,7 +26,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module packer #(parameter WIDTH=32) (
-  input  logic [WIDTH-1:0] A, B,
+  input  logic [WIDTH/2-1:0] A, B,
   input  logic [2:0] 	  PackSelect, 
   output logic [WIDTH-1:0] PackResult
 );
diff --git a/src/ieu/kmu/zbkb.sv b/src/ieu/kmu/zbkb.sv
index 90b774042..942a3d9a9 100644
--- a/src/ieu/kmu/zbkb.sv
+++ b/src/ieu/kmu/zbkb.sv
@@ -26,21 +26,26 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module zbkb #(parameter WIDTH=32) (
-   input  logic [WIDTH-1:0] A, B, RevA,
-   input  logic 	          W64,
-   input  logic [2:0] 	    Funct3,
-   input  logic [2:0] 	    ZBKBSelect,
-   output logic [WIDTH-1:0] ZBKBResult
+  input  logic [WIDTH-1:0]   A, 
+  input  logic [WIDTH/2-1:0] B,
+  input  logic [2:0] 	     Funct3,
+  input  logic [2:0] 	     ZBKBSelect,
+  output logic [WIDTH-1:0]   ZBKBResult
 );
    
-   logic [WIDTH-1:0] 	     ByteResult;   // rev8, brev8
+   logic [WIDTH-1:0] 	     Brev8Result;  // rev8, brev8
    logic [WIDTH-1:0] 	     PackResult;   // pack, packh, packw (RB64 only)
    logic [WIDTH-1:0] 	     ZipResult;    // zip, unzip
+
+   // brev8 just uses wires
+   genvar i, j;
+   for (i=0;i<WIDTH/8;i=i+1) 
+      for (j=0; j<8; j=j+1) 
+         assign Brev8Result[i*8+j] = A[i*8+7-j];
    
-   byteop #(WIDTH) rev(.A, .RevA, .ByteSelect({B[10], B[0]}), .ByteResult);
-   packer #(WIDTH) pack(.A, .B, .PackSelect({ZBKBSelect[2], Funct3[1:0]}), .PackResult);
-   zipper #(WIDTH) zip(.A, .ZipSelect(Funct3[2]), .ZipResult);
+   packer #(WIDTH) pack(.A(A[WIDTH/2-1:0]), .B(B[WIDTH/2-1:0]), .PackSelect({ZBKBSelect[2], Funct3[1:0]}), .PackResult);
+   zipper #(WIDTH) zipper(.A, .ZipSelect(Funct3[2]), .ZipResult);
    
    // ZBKB Result Select Mux
-   mux3 #(WIDTH) zbkbresultmux(ByteResult, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult);   
+   mux3 #(WIDTH) zbkbresultmux(Brev8Result, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult);   
 endmodule
diff --git a/src/ieu/kmu/zbkx.sv b/src/ieu/kmu/zbkx.sv
index dbbaf3d2d..f7937f267 100644
--- a/src/ieu/kmu/zbkx.sv
+++ b/src/ieu/kmu/zbkx.sv
@@ -27,12 +27,14 @@
 
 module zbkx #(parameter WIDTH=32) (
    input  logic [WIDTH-1:0] A, B,
-   input  logic [2:0] 	    ZBKXSelect,
+   input  logic  	          ZBKXSelect,
    output logic [WIDTH-1:0] ZBKXResult
 );
    
-   logic [WIDTH-1:0] 	     xperm4, xperm4lookup;
-   logic [WIDTH-1:0] 	     xperm8, xperm8lookup;
+   logic [WIDTH-1:0] 	     xperm4, xperm8;
+   /* verilator lint_off UNUSEDSIGNAL */
+   logic [WIDTH-1:0]         xperm4lookup, xperm8lookup; // not all bits are used
+   /* verilator lint_on UNUSEDSIGNAL */
    int 		     i;
    
    always_comb begin
@@ -46,5 +48,5 @@ module zbkx #(parameter WIDTH=32) (
       end   
    end
 
-   assign ZBKXResult = ZBKXSelect[0] ? xperm4 : xperm8;
+   assign ZBKXResult = ZBKXSelect ? xperm4 : xperm8;
 endmodule
diff --git a/src/ieu/kmu/zknde32.sv b/src/ieu/kmu/zknde32.sv
index 4c845599c..7e482d757 100644
--- a/src/ieu/kmu/zknde32.sv
+++ b/src/ieu/kmu/zknde32.sv
@@ -28,7 +28,7 @@
 
 module zknde32 import cvw::*; #(parameter cvw_t P) (
    input  logic [31:0] A, B,
-   input  logic [6:0]  Funct7,
+   input  logic [1:0]  bs,
    input  logic [3:0]  round,
    input  logic [3:0]  ZKNSelect,
    output logic [31:0] ZKNDEResult
@@ -39,7 +39,7 @@ module zknde32 import cvw::*; #(parameter cvw_t P) (
     logic [31:0]    ZKNEResult, ZKNDResult, rotin, rotout;             
 
     // Initial shamt and Sbox input selection steps shared between encrypt and decrypt
-    assign shamt = {Funct7[6:5], 3'b0};          // shamt = bs * 8 (convert bytes to bits)
+    assign shamt = {bs, 3'b0};          // shamt = bs * 8 (convert bytes to bits)
     assign SboxIn = B[shamt +: 8];               // select byte bs of rs2
 
     // Handle logic specific to encrypt or decrypt
@@ -55,6 +55,7 @@ module zknde32 import cvw::*; #(parameter cvw_t P) (
         assign rotin = ZKNEResult;
 
     // final rotate and XOR steps shared between encrypt and decrypt
-    rotate #(32) mrot(rotin, shamt, rotout);       // Rotate the mixcolumns output left by shamt (bs * 8)
+    mux4 #(32) mrotmux(rotin, {rotin[23:0], rotin[31:24]}, 
+                       {rotin[15:0], rotin[31:16]}, {rotin[7:0], rotin[31:8]},  bs, rotout); // Rotate the mixcolumns output left by shamt (bs * 8)
     assign ZKNDEResult = A ^ rotout;               // xor with running value (A = rs1)
 endmodule
diff --git a/src/ieu/kmu/zknde64.sv b/src/ieu/kmu/zknde64.sv
index 2a2b6cc10..dee518074 100644
--- a/src/ieu/kmu/zknde64.sv
+++ b/src/ieu/kmu/zknde64.sv
@@ -28,7 +28,6 @@
 
 module zknde64 import cvw::*; #(parameter cvw_t P) (
    input  logic [63:0] A, B,
-   input  logic [6:0]  Funct7,
    input  logic [3:0]  round,
    input  logic [3:0]  ZKNSelect,
    output logic [63:0] ZKNDEResult
@@ -39,16 +38,21 @@ module zknde64 import cvw::*; #(parameter cvw_t P) (
    
     if (P.ZKND_SUPPORTED) // ZKND supports aes64ds, aes64dsm, aes64im
         aes64d    aes64d(.rs1(A), .rs2(B), .finalround(ZKNSelect[2]), .aes64im(ZKNSelect[3]), .result(aes64dRes)); // decode AES
-    if (P.ZKNE_SUPPORTED) // ZKNE supports aes64es, aes64esm
+    else assign aes64dRes = '0;
+    if (P.ZKNE_SUPPORTED) begin // ZKNE supports aes64es, aes64esm
         aes64e    aes64e(.rs1(A), .rs2(B), .finalround(ZKNSelect[2]), .Sbox0Out, .SboxEIn, .result(aes64eRes));
-
+        mux2 #(32) sboxmux(SboxEIn, SboxKIn, ZKNSelect[1], Sbox0In);
+    end else begin  
+        assign aes64eRes = '0;
+        assign Sbox0In = SboxKIn;
+    end
+    
     // One S Box is always needed for aes64ks1i and is also needed for aes64e if that is supported.  Put it at the top level to allow sharing
-    mux2 #(32) sboxmux(SboxEIn, SboxKIn, ZKNSelect[1], Sbox0In);
     aessbox32 sbox(Sbox0In, Sbox0Out);                       // Substitute bytes of value obtained for tmp2 using Rijndael sbox
 
     // Both ZKND and ZKNE support aes64ks1i and aes64ks2 instructions
-    aes64ks1i aes64ks1i(.round, .rs1(A), .Sbox0Out, .SboxKIn, .result(aes64ks1iRes));
-    aes64ks2  aes64ks2(.rs2(B), .rs1(A), .result(aes64ks2Res));
+    aes64ks1i aes64ks1i(.round, .rs1(A[63:32]), .Sbox0Out, .SboxKIn, .result(aes64ks1iRes));
+    aes64ks2  aes64ks2(.rs2(B), .rs1(A[63:32]), .result(aes64ks2Res));
    
     // Choose among decrypt, encrypt, key schedule 1, key schedule 2 results
     mux4 #(64) zkndmux(aes64dRes, aes64eRes, aes64ks1iRes, aes64ks2Res, ZKNSelect[1:0], ZKNDEResult);
diff --git a/src/ieu/kmu/zknh64.sv b/src/ieu/kmu/zknh64.sv
index 923d5ea48..218837ee8 100644
--- a/src/ieu/kmu/zknh64.sv
+++ b/src/ieu/kmu/zknh64.sv
@@ -26,7 +26,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module zknh64 (
-   input  logic [63:0] A, B, 
+   input  logic [63:0] A,
    input  logic [3:0]  ZKNHSelect,
    output logic [63:0] ZKNHResult
 );
diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv
index 0a3fb3d7f..48359d3ca 100644
--- a/src/ieu/regfile.sv
+++ b/src/ieu/regfile.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: 3-port register file
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -50,7 +50,7 @@ module regfile #(parameter XLEN, E_SUPPORTED) (
   // can logic be adjusted to not need resettable registers?
     
   always_ff @(negedge clk)
-    if (reset) for(i=1; i<NUMREGS; i++) rf[i] <= 0;
+    if (reset) for(i=1; i<NUMREGS; i++) rf[i] <= '0;
     else       if (we3)                 rf[a3] <= wd3;  
 
   assign rd1 = (a1 != 0) ? rf[a1] : 0;
diff --git a/src/ieu/sha/sha256.sv b/src/ieu/sha/sha256.sv
index 118f9e24b..12d08f2ce 100644
--- a/src/ieu/sha/sha256.sv
+++ b/src/ieu/sha/sha256.sv
@@ -37,29 +37,29 @@ module sha256 (
    // sha256{sig0/sig1/sum0/sum1} select shifted operands for 32-bit xor3 and then sign-extend
 
    // sha256sig0
-   assign x[0][0] = {A[6:0], A[31:7]};
-   assign x[0][1] = {A[17:0], A[31:18]};
-   assign x[0][2] = {3'b0, A[31:3]};
+   assign x[0][0] = {A[6:0], A[31:7]};    // ror 7
+   assign x[0][1] = {A[17:0], A[31:18]};  // ror 18
+   assign x[0][2] = {3'b0, A[31:3]};      // >> 3
 
    // sha256sig1
-   assign x[1][0] = {A[16:0], A[31:17]};
-   assign x[1][1] = {A[18:0], A[31:19]};
-   assign x[1][2] = {10'b0, A[31:10]};
+   assign x[1][0] = {A[16:0], A[31:17]};  // ror 17
+   assign x[1][1] = {A[18:0], A[31:19]};  // ror 19
+   assign x[1][2] = {10'b0, A[31:10]};    // >> 10
 
    // sha256sum0
-   assign x[2][0] = {A[1:0],  A[31:2]};
-   assign x[2][1] = {A[12:0], A[31:13]};
-   assign x[2][2] = {A[21:0], A[31:22]};
+   assign x[2][0] = {A[1:0],  A[31:2]};   // ror 2
+   assign x[2][1] = {A[12:0], A[31:13]};  // ror 13
+   assign x[2][2] = {A[21:0], A[31:22]};  // ror 22
 
    // sha256sum1
-   assign x[3][0] = {A[5:0], A[31:6]};
-   assign x[3][1] ={A[10:0], A[31:11]};
-   assign x[3][2] = {A[24:0], A[31:25]};
+   assign x[3][0] = {A[5:0], A[31:6]};    // ror 6
+   assign x[3][1] ={ A[10:0], A[31:11]};  // ror 11
+   assign x[3][2] = {A[24:0], A[31:25]};  // ror 25
 
    // 32-bit muxes to select inputs to xor3 for sha256 
-   assign y[0] = x[ZKNHSelect[1:0]][0]; 
-   assign y[1] = x[ZKNHSelect[1:0]][1]; 
-   assign y[2] = x[ZKNHSelect[1:0]][2]; 
+   assign y[0] = x[ZKNHSelect[1:0]][0];
+   assign y[1] = x[ZKNHSelect[1:0]][1];
+   assign y[2] = x[ZKNHSelect[1:0]][2];
 
    // sha256 32-bit xor3
    assign result = y[0] ^ y[1] ^ y[2];
diff --git a/src/ieu/sha/sha512_32.sv b/src/ieu/sha/sha512_32.sv
index 7b0d34908..ce205172c 100644
--- a/src/ieu/sha/sha512_32.sv
+++ b/src/ieu/sha/sha512_32.sv
@@ -31,67 +31,39 @@ module sha512_32 (
    output logic [31:0] result
 );
 
-   logic [31:0] x[6][6];
-   logic [31:0] y[6];
+   logic [31:0] x[4][3];
+   logic [31:0] y[3];
 
-   // sha512{sig0h/sig0l/sig1h/sig1l/sum0r/sum1r} select shifted operands for 32-bit xor6
+   // rotate/shift a 64-bit value contained in {B, A} and select 32 bits
+   // sha512{sig0h/sig0l/sig1h/sig1l/sum0r/sum1r} select shifted operands for 32-bit xor
 
-   // sha512sig0h
-   assign x[0][0] = A >> 1;
-   assign x[0][1] = A >> 7;
-   assign x[0][2] = A >> 8;
-   assign x[0][3] = B << 31;
-   assign x[0][4] = B << 24;
-   assign x[0][5] = 0;   
+   // The l flavors differ from h by using low bits of B instead of zeros in x[0/1][2]
 
-   // sha512sig0l
-   assign x[1][0] = A >> 1; 
-   assign x[1][1] = A >> 7; 
-   assign x[1][2] = A >> 8; 
-   assign x[1][3] = B << 31;
-   assign x[1][4] = B << 25;
-   assign x[1][5] = B << 24;
+   // sha512sig0h/l
+   assign x[0][0] = {B[0], A[31:1]};                           // ror 1
+   assign x[0][1] = {B[7:0], A[31:8]};                         // ror 8
+   assign x[0][2] = {B[6:0] & {7{ZKNHSelect[0]}}, A[31:7]};    // ror/srl 7
 
-   // sha512sig1h
-   assign x[2][0] = A << 3;
-   assign x[2][1] = A >> 6;
-   assign x[2][2] = A >> 19;
-   assign x[2][3] = B >> 29;
-   assign x[2][4] = B << 13;
-   assign x[2][5] = 0;      
-
-   // sha512sig1l
-   assign x[3][0] = A << 3; 
-   assign x[3][1] = A >> 6; 
-   assign x[3][2] = A >> 19; 
-   assign x[3][3] = B >> 29;
-   assign x[3][4] = B << 26;
-   assign x[3][5] = B << 13;
+   // sha512sig1h/l
+   assign x[1][0] = {A[28:0], B[31:29]};                       // ror 61
+   assign x[1][1] = {B[18:0], A[31:19]};                       // ror 19
+   assign x[1][2] = {B[5:0] & {6{ZKNHSelect[0]}}, A[31:6]};    // ror/srl 6
 
    // sha512sum0r
-   assign x[4][0] = A << 25; 
-   assign x[4][1] = A << 30; 
-   assign x[4][2] = A >> 28; 
-   assign x[4][3] = B >> 7;
-   assign x[4][4] = B >> 2;
-   assign x[4][5] = B << 4;
+   assign x[2][0] = {A[6:0], B[31:7]};                         // ror 39
+   assign x[2][1] = {A[1:0], B[31:2]};                         // ror 34
+   assign x[2][2] = {B[27:0], A[31:28]};                       // ror 28
 
    // sha512sum1r
-   assign x[5][0] = A << 23; 
-   assign x[5][1] = A >> 14; 
-   assign x[5][2] = A >> 18; 
-   assign x[5][3] = B >> 9;
-   assign x[5][4] = B << 18;
-   assign x[5][5] = B << 14;   
+   assign x[3][0] = {A[8:0], B[31:9]};                         // ror 41
+   assign x[3][1] = {B[13:0], A[31:14]};                       // ror 14
+   assign x[3][2] = {B[17:0], A[31:18]};                       // ror 18
 
    // 32-bit muxes to select inputs to xor6 for sha512
-   assign y[0] = x[ZKNHSelect[2:0]][0]; 
-   assign y[1] = x[ZKNHSelect[2:0]][1]; 
-   assign y[2] = x[ZKNHSelect[2:0]][2];
-   assign y[3] = x[ZKNHSelect[2:0]][3]; 
-   assign y[4] = x[ZKNHSelect[2:0]][4]; 
-   assign y[5] = x[ZKNHSelect[2:0]][5];    
-
+   assign y[0] = x[ZKNHSelect[2:1]][0];
+   assign y[1] = x[ZKNHSelect[2:1]][1];
+   assign y[2] = x[ZKNHSelect[2:1]][2];
+ 
    // sha512 32-bit xor6
-   assign result = y[0] ^ y[1] ^ y[2] ^ y[3] ^ y[4] ^ y[5];
+   assign result = y[0] ^ y[1] ^ y[2];
 endmodule
diff --git a/src/ieu/sha/sha512_64.sv b/src/ieu/sha/sha512_64.sv
index 8707311e8..47fefce04 100644
--- a/src/ieu/sha/sha512_64.sv
+++ b/src/ieu/sha/sha512_64.sv
@@ -33,33 +33,33 @@ module sha512_64 (
 
    logic [63:0] x[4][3];
    logic [63:0] y[3];
-   
-   // sha512{sig0/sig1/sum0/sum1} select shifted operands for 64-bit xor3
+
+   // sha512{sig0/sig1/sum0/sum1} select rotated/shifted operands for 64-bit xor3
 
    // sha512sig0
-   assign x[0][0] = {A[0],   A[63:1]};
-   assign x[0][1] = {A[7:0], A[63:8]};
-   assign x[0][2] = A >> 7;
+   assign x[0][0] = {A[0],   A[63:1]};    // ror 1
+   assign x[0][1] = {A[7:0], A[63:8]};    // ror 8
+   assign x[0][2] = {7'b0,   A[63:7]};    // >> 7
 
    // sha512sig1
-   assign x[1][0] = {A[18:0], A[63:19]};
-   assign x[1][1] = {A[60:0], A[63:61]};
-   assign x[1][2] = A >> 6;
+   assign x[1][0] = {A[18:0], A[63:19]};  // ror 19
+   assign x[1][1] = {A[60:0], A[63:61]};  // ror 61
+   assign x[1][2] = {6'b0,    A[63:6]};   // >> 6
 
    // sha512sum0
-   assign x[2][0] = {A[27:0], A[63:28]};
-   assign x[2][1] = {A[33:0], A[63:34]};
-   assign x[2][2] = {A[38:0], A[63:39]};
+   assign x[2][0] = {A[27:0], A[63:28]};  // ror 28
+   assign x[2][1] = {A[33:0], A[63:34]};  // ror 34
+   assign x[2][2] = {A[38:0], A[63:39]};  // ror 39
 
    // sha512sum1
-   assign x[3][0] = {A[13:0], A[63:14]};
-   assign x[3][1] = {A[17:0], A[63:18]};
-   assign x[3][2] = {A[40:0], A[63:41]};
+   assign x[3][0] = {A[13:0], A[63:14]};  // ror 14
+   assign x[3][1] = {A[17:0], A[63:18]};  // ror 18
+   assign x[3][2] = {A[40:0], A[63:41]};  // ror 41
 
    // 64-bit muxes to select inputs to xor3 for sha512
-   assign y[0] = x[ZKNHSelect[1:0]][0]; 
-   assign y[1] = x[ZKNHSelect[1:0]][1]; 
-   assign y[2] = x[ZKNHSelect[1:0]][2]; 
+   assign y[0] = x[ZKNHSelect[1:0]][0];
+   assign y[1] = x[ZKNHSelect[1:0]][1];
+   assign y[2] = x[ZKNHSelect[1:0]][2];
 
    // sha512 64-bit xor3
    assign result = y[0] ^ y[1] ^ y[2];
diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv
index af44b6136..8d4da28d9 100644
--- a/src/ieu/shifter.sv
+++ b/src/ieu/shifter.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: RISC-V 32/64 bit shifter
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -40,7 +40,7 @@ module shifter import cvw::*; #(parameter cvw_t P) (
 
   assign Sign = A[P.XLEN-1] & SubArith;  // sign bit for sign extension
   if (P.XLEN==32) begin // rv32
-    if (P.ZBB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates
+    if (P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates
       always_comb  // funnel mux
         case({Right, Rotate})
           2'b00: Z = {A[31:0], 31'b0};
@@ -57,7 +57,7 @@ module shifter import cvw::*; #(parameter cvw_t P) (
   end else begin // rv64
     logic [P.XLEN-1:0]         A64;                            
     mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, A64); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux
-    if (P.ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates
+    if (P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates
       // shifter rotate source select mux
       logic [P.XLEN-1:0]   RotA;                          // rotate source
       mux2 #(P.XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons
diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv
index 5129e9043..b3f13d010 100644
--- a/src/ifu/bpred/RASPredictor.sv
+++ b/src/ifu/bpred/RASPredictor.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: 2 bit saturating counter predictor with parameterized table depth.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -31,7 +31,7 @@
 module RASPredictor import cvw::*;  #(parameter cvw_t P)(
   input  logic             clk,
   input  logic             reset, 
-  input  logic             StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
+  input  logic             StallD, StallE, StallM, FlushD, FlushE, FlushM,
   input  logic             BPReturnWrongD,                      // Prediction class is wrong
   input  logic             ReturnD,
   input  logic             ReturnE, CallE,                  // Instr class
@@ -52,7 +52,7 @@ module RASPredictor import cvw::*;  #(parameter cvw_t P)(
   logic      RepairD;
   logic      IncrRepairD, DecRepairD;
   
-  logic      DecrementPtr;
+  logic      DecPtr;
   logic      FlushedReturnDE;
   logic      WrongPredReturnD;
   
@@ -71,11 +71,11 @@ module RASPredictor import cvw::*;  #(parameter cvw_t P)(
     
   assign CounterEn = PopF | PushE | RepairD;
 
-  assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD;
+  assign DecPtr = (PopF | DecRepairD) & ~IncrRepairD;
 
   assign P1 = 1;
   assign M1 = '1; // -1
-  mux2 #(Depth) PtrMux(P1, M1, DecrementPtr, IncDecPtr);
+  mux2 #(Depth) PtrMux(P1, M1, DecPtr, IncDecPtr);
   logic [Depth-1:0] Sum;
   assign Sum = Ptr + IncDecPtr;
   if(|P.RAS_SIZE[Depth-1:0])
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 568eeecb5..da8a7a2a2 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -59,90 +59,83 @@ module bpred import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.XLEN-1:0] IEUAdrE,                   // The branch/jump target address
   input  logic [P.XLEN-1:0] IEUAdrM,                   // The branch/jump target address
   input  logic [P.XLEN-1:0] PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
-  output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as call, return, jr (not return), j, br
+  output logic [3:0]       IClassM,               // The valid instruction class. 1-hot encoded as call, return, jr (not return), j, br
 
   // Report branch prediction status
   output logic             BPWrongE,                  // Prediction is wrong
   output logic             BPWrongM,                  // Prediction is wrong
-  output logic             BPDirPredWrongM,           // Prediction direction is wrong
+  output logic             BPDirWrongM,           // Prediction direction is wrong
   output logic             BTAWrongM,                 // Prediction target wrong
   output logic             RASPredPCWrongM,           // RAS prediction is wrong
   output logic             IClassWrongM               // Class prediction is wrong
   );
 
-  logic [1:0]              BPDirPredF;
+  logic [1:0]              BPDirF;
 
-  logic [P.XLEN-1:0]        BPBTAF, RASPCF;
-  logic                    BPPCWrongE;
-  logic                    IClassWrongE;
-  logic                    BPDirPredWrongE;
+  logic                    BPDirWrongE;
+  logic [P.XLEN-1:0]       BPBTAF, RASPCF;
   
   logic                    BPPCSrcF;
-  logic [P.XLEN-1:0]        BPPCF;
-  logic [P.XLEN-1:0]        PC0NextF;
-  logic [P.XLEN-1:0]        PCCorrectE;
-  logic [3:0]              WrongPredInstrClassD;
+  logic [P.XLEN-1:0]       BPPCF;
+  logic [P.XLEN-1:0]       PC0NextF;
+  logic [P.XLEN-1:0]       PCCorrectE;
 
-  logic                    BTBTargetWrongE;
   logic                    RASTargetWrongE;
 
-  logic [P.XLEN-1:0]        BPBTAD;
-
-  logic                     BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF;
-  logic                     BPBranchF, BPJumpF, BPReturnF, BPCallF;
-  logic                     BPBranchD, BPJumpD, BPReturnD, BPCallD;
-  logic                     ReturnD, CallD;
-  logic                     ReturnE, CallE;
-  logic                     BranchM, JumpM, ReturnM, CallM;
-  logic                     BranchW, JumpW, ReturnW, CallW;
-  logic                     BPReturnWrongD;
-  logic [P.XLEN-1:0]        BPBTAE;
-  logic                     BPBTAWrongM;
-  logic                     PCSrcM;
+  logic                    BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF;
+  logic                    BPBranchF, BPJumpF, BPReturnF, BPCallF;
+  logic                    BPBranchD, BPJumpD, BPReturnD, BPCallD;
+  logic                    ReturnD, CallD;
+  logic                    ReturnE, CallE;
+  logic                    BranchM, JumpM, ReturnM, CallM;
+  logic                    BranchW, JumpW, ReturnW, CallW;
+  logic                    BPReturnWrongD;
+  logic                    BPBTAWrongM;
+  logic                    PCSrcM;
   
   // Part 1 branch direction prediction
   if (P.BPRED_TYPE == `BP_TWOBIT) begin:Predictor
     twoBitPredictor #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, 
       .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
+      .PCNextF, .PCM, .BPDirF, .BPDirWrongE,
       .BranchE, .BranchM, .PCSrcE);
 
   end else if (P.BPRED_TYPE == `BP_GSHARE) begin:Predictor
     gshare #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirPredF, .BPDirPredWrongE,
+      .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirF, .BPDirWrongE,
       .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW, 
       .PCSrcE);
 
   end else if (P.BPRED_TYPE == `BP_GLOBAL) begin:Predictor
     gshare #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirPredF, .BPDirPredWrongE,
+      .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirF, .BPDirWrongE,
       .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW,
       .PCSrcE);
 
   end else if (P.BPRED_TYPE == `BP_GSHARE_BASIC) begin:Predictor
     gsharebasic #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
+      .PCNextF, .PCM, .BPDirF, .BPDirWrongE,
       .BranchE, .BranchM, .PCSrcE);
 
   end else if (P.BPRED_TYPE == `BP_GLOBAL_BASIC) begin:Predictor
     gsharebasic #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
+      .PCNextF, .PCM, .BPDirF, .BPDirWrongE,
       .BranchE, .BranchM, .PCSrcE);
   
   end else if (P.BPRED_TYPE == `BP_LOCAL_BASIC) begin:Predictor
     localbpbasic #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, 
       .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
+      .PCNextF, .PCM, .BPDirF, .BPDirWrongE,
       .BranchE, .BranchM, .PCSrcE);
   end else if (P.BPRED_TYPE == `BP_LOCAL_AHEAD) begin:Predictor
     localaheadbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, 
       .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE,
+      .PCNextF, .PCM, .BPDirD(BPDirF), .BPDirWrongE,
       .BranchE, .BranchM, .PCSrcE);
   end else if (P.BPRED_TYPE == `BP_LOCAL_REPAIR) begin:Predictor
     localrepairbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, 
       .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCE, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE,
+      .PCNextF, .PCE, .PCM, .BPDirD(BPDirF), .BPDirWrongE,
       .BranchD, .BranchE, .BranchM, .PCSrcE);
   end 
 
@@ -154,23 +147,23 @@ module bpred import cvw::*;  #(parameter cvw_t P) (
   btb #(P, P.BTB_SIZE) 
     TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM,
-      .BPBTAF, .BPBTAD, .BPBTAE,
+      .BPBTAF, 
       .BTBIClassF({BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF}),
       .BPBTAWrongM,
-      .IClassWrongM, .IClassWrongE,
+      .IClassWrongM,
       .IEUAdrE, .IEUAdrM,
-      .InstrClassD({CallD, ReturnD, JumpD, BranchD}), 
-      .InstrClassE({CallE, ReturnE, JumpE, BranchE}), 
-      .InstrClassM({CallM, ReturnM, JumpM, BranchM}),
-      .InstrClassW({CallW, ReturnW, JumpW, BranchW}));
+      .IClassD({CallD, ReturnD, JumpD, BranchD}), 
+      .IClassE({CallE, ReturnE, JumpE, BranchE}), 
+      .IClassM({CallM, ReturnM, JumpM, BranchM}),
+      .IClassW({CallW, ReturnW, JumpW, BranchW}));
 
-  icpred #(P, `INSTR_CLASS_PRED) icpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+  icpred #(P, `INSTR_CLASS_PRED) icpred(.clk, .reset, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, 
     .PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW,
     .CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW, .BTBCallF, .BTBReturnF, .BTBJumpF,
-    .BTBBranchF, .BPCallF, .BPReturnF, .BPJumpF, .BPBranchF, .IClassWrongM, .IClassWrongE, .BPReturnWrongD);
+    .BTBBranchF, .BPCallF, .BPReturnF, .BPJumpF, .BPBranchF, .IClassWrongM, .BPReturnWrongD);
 
   // Part 3 RAS
-  RASPredictor #(P) RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+  RASPredictor #(P) RASPredictor(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
     .BPReturnF, .ReturnD, .ReturnE, .CallE,
     .BPReturnWrongD, .RASPCF, .PCLinkE);
 
@@ -185,7 +178,7 @@ module bpred import cvw::*;  #(parameter cvw_t P) (
   flopenrc #(1) BPWrongMReg(clk, reset, FlushM, ~StallM, BPWrongE, BPWrongM);
   
   // Output the predicted PC or corrected PC on miss-predict.
-  assign BPPCSrcF = (BPBranchF & BPDirPredF[1]) | BPJumpF;
+  assign BPPCSrcF = (BPBranchF & BPDirF[1]) | BPJumpF;
   mux2 #(P.XLEN) pcmuxbp(BPBTAF, RASPCF, BPReturnF, BPPCF);
   // Selects the BP or PC+2/4.
   mux2 #(P.XLEN) pcmux0(PCPlus2or4F, BPPCF, BPPCSrcF, PC0NextF);
@@ -212,14 +205,13 @@ module bpred import cvw::*;  #(parameter cvw_t P) (
     // could be wrong or the fall through address selected for branch predict not taken.
     // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
     // both without the above inaccuracies.
-    // **** use BPBTAWrongM from BTB.
     assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE;
 
     flopenrc #(P.XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
     flopenrc #(P.XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
     flopenrc #(2) BPPredWrongRegM(clk, reset, FlushM, ~StallM, 
-      {BPDirPredWrongE, RASPredPCWrongE},
-      {BPDirPredWrongM, RASPredPCWrongM});
+      {BPDirWrongE, RASPredPCWrongE},
+      {BPDirWrongM, RASPredPCWrongM});
 
     assign BTAWrongM = BPBTAWrongM & PCSrcM;
     
@@ -227,7 +219,6 @@ module bpred import cvw::*;  #(parameter cvw_t P) (
     assign {BTAWrongM, RASPredPCWrongM} = 0;
   end
 
-  // **** Fix me
-  assign InstrClassM = {CallM, ReturnM, JumpM, BranchM};
+  assign IClassM = {CallM, ReturnM, JumpM, BranchM};
   
 endmodule
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index 448be38d0..acd61df67 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -8,7 +8,7 @@
 // Purpose: Branch Target Buffer (BTB). The BTB predicts the target address of all control flow instructions.
 //          It also guesses the type of instrution; jalr(r), return, jump (jr), or branch.
 //
-// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -36,28 +36,26 @@ module btb import cvw::*;  #(parameter cvw_t P,
   input  logic             StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW,
   input  logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages
   output logic [P.XLEN-1:0] BPBTAF,                      // BTB's guess at PC
-  output logic [P.XLEN-1:0] BPBTAD,
-  output logic [P.XLEN-1:0] BPBTAE,
   output logic [3:0]       BTBIClassF,                  // BTB's guess at instruction class
   output logic BPBTAWrongM,
   // update
   input  logic             IClassWrongM,                // BTB's instruction class guess was wrong
-  input  logic             IClassWrongE,
   input  logic [P.XLEN-1:0] IEUAdrE,                     // Branch/jump target address to insert into btb
   input  logic [P.XLEN-1:0] IEUAdrM,                     // Branch/jump target address to insert into btb
-  input  logic [3:0]       InstrClassD,                 // Instruction class to insert into btb
-  input  logic [3:0]       InstrClassE,                 // Instruction class to insert into btb
-  input  logic [3:0]       InstrClassM,                 // Instruction class to insert into btb
-  input  logic [3:0]       InstrClassW
+  input  logic [3:0]       IClassD,                 // Instruction class to insert into btb
+  input  logic [3:0]       IClassE,                 // Instruction class to insert into btb
+  input  logic [3:0]       IClassM,                 // Instruction class to insert into btb
+  input  logic [3:0]       IClassW
 );
 
   logic [Depth-1:0]        PCNextFIndex, PCFIndex, PCDIndex, PCEIndex, PCMIndex, PCWIndex;
   logic                    MatchD, MatchE, MatchM, MatchW, MatchX;
-  logic [P.XLEN+3:0]        ForwardBTBPrediction, ForwardBTBPredictionF;
-  logic [P.XLEN+3:0]        TableBTBPredF;
-  logic [P.XLEN-1:0]        IEUAdrW;
-  logic [P.XLEN-1:0]        PCW;
-  logic                    BTBWrongE, BPBTAWrongE;
+  logic [P.XLEN+3:0]       ForwardBTBPredF;
+  logic [P.XLEN+3:0]       TableBTBPredF;
+  logic [P.XLEN-1:0]       IEUAdrW;
+  logic [P.XLEN-1:0]       PCW;
+  logic [P.XLEN-1:0]       BPBTAD, BPBTAE;
+  logic                    BPBTAWrongE;
   logic                    BTBWrongM;
   
   
@@ -79,18 +77,18 @@ module btb import cvw::*;  #(parameter cvw_t P,
   assign MatchW = PCFIndex == PCWIndex;
   assign MatchX = MatchD | MatchE | MatchM | MatchW;
 
-  assign ForwardBTBPredictionF = MatchD ? {InstrClassD, BPBTAD} :
-                                 MatchE ? {InstrClassE, IEUAdrE} :
-                                 MatchM ? {InstrClassM, IEUAdrM} :
-                                 {InstrClassW, IEUAdrW} ;
+  assign ForwardBTBPredF = MatchD ? {IClassD, BPBTAD} :
+                                 MatchE ? {IClassE, IEUAdrE} :
+                                 MatchM ? {IClassM, IEUAdrM} :
+                                 {IClassW, IEUAdrW} ;
 
-  assign {BTBIClassF, BPBTAF} = MatchX ? ForwardBTBPredictionF : {TableBTBPredF};
+  assign {BTBIClassF, BPBTAF} = MatchX ? ForwardBTBPredF : {TableBTBPredF};
 
 
   // An optimization may be using a PC relative address.
   ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**Depth), .WIDTH(P.XLEN+4)) memory(
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredF),
-     .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(BTBWrongM), .bwe2('1));
+     .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({IClassM, IEUAdrM}), .we2(BTBWrongM), .bwe2('1));
 
   flopenrc #(P.XLEN) BTBD(clk, reset, FlushD, ~StallD, BPBTAF, BPBTAD);
 
@@ -98,7 +96,7 @@ module btb import cvw::*;  #(parameter cvw_t P,
   // 1. It gates updates to the BTB when the prediction does not change.  This save power.
   // 2. BPBTAWrongE is used by the performance counters to track when the BTB's BPBTA or instruction class is wrong.
   flopenrc #(P.XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, BPBTAD, BPBTAE);
-  assign BPBTAWrongE = (BPBTAE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]);
+  assign BPBTAWrongE = (BPBTAE != IEUAdrE) & (IClassE[0] | IClassE[1] & ~IClassE[2]);
 
   flopenrc #(1) BPBTAWrongMReg(clk, reset, FlushM, ~StallM, BPBTAWrongE, BPBTAWrongM);  
   assign BTBWrongM = BPBTAWrongM | IClassWrongM;
diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv
index 7f5906084..691926484 100644
--- a/src/ifu/bpred/gshare.sv
+++ b/src/ifu/bpred/gshare.sv
@@ -37,18 +37,18 @@ module gshare import cvw::*; #(parameter cvw_t P,
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, StallW,
   input logic             FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0]      BPDirPredF, 
-  output logic            BPDirPredWrongE,
+  output logic [1:0]      BPDirF, 
+  output logic            BPDirWrongE,
   // update
   input logic [XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
   input logic             BPBranchF, BranchD, BranchE, BranchM, BranchW, PCSrcE
 );
 
-  logic                   MatchF, MatchD, MatchE, MatchM, MatchW;
+  logic                   MatchD, MatchE, MatchM, MatchW;
   logic                   MatchX;
 
-  logic [1:0]             TableBPDirPredF, BPDirPredD, BPDirPredE, FwdNewDirPredF;
-  logic [1:0]             NewBPDirPredE, NewBPDirPredM, NewBPDirPredW;
+  logic [1:0]             PHTBPDirF, BPDirD, BPDirE, FwdNewBPDirF;
+  logic [1:0]             NewBPDirE, NewBPDirM, NewBPDirW;
 
   logic [k-1:0]           IndexNextF, IndexF, IndexD, IndexE, IndexM, IndexW;
 
@@ -78,33 +78,33 @@ module gshare import cvw::*; #(parameter cvw_t P,
   assign MatchW = BranchW & ~FlushW & (IndexF == IndexW);
   assign MatchX = MatchD | MatchE | MatchM | MatchW;
 
-  assign FwdNewDirPredF = MatchD ? {2{BPDirPredD[1]}} :
-                                   MatchE ? {NewBPDirPredE} :
-                                   MatchM ? {NewBPDirPredM} :
-                   NewBPDirPredW ;
+  assign FwdNewBPDirF = MatchD ? {2{BPDirD[1]}} :
+                                   MatchE ? {NewBPDirE} :
+                                   MatchM ? {NewBPDirM} :
+                   NewBPDirW ;
   
-  assign BPDirPredF = MatchX ? FwdNewDirPredF : TableBPDirPredF;
+  assign BPDirF = MatchX ? FwdNewBPDirF : PHTBPDirF;
 
   ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(IndexNextF),
-    .rd1(TableBPDirPredF),
+    .rd1(PHTBPDirF),
     .wa2(IndexM),
-    .wd2(NewBPDirPredM),
+    .wd2(NewBPDirM),
     .we2(BranchM),
     .bwe2(1'b1));
 
-  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
-  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
+  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirF, BPDirD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirD, BPDirE);
 
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE));
-  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
-  flopenrc #(2) NewPredictionRegW(clk, reset,  FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW);
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE));
+  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirE, NewBPDirM);
+  flopenrc #(2) NewPredictionRegW(clk, reset,  FlushW, ~StallW, NewBPDirM, NewBPDirW);
 
-  assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE;
+  assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE;
 
-  assign GHRNextF = BPBranchF ? {BPDirPredF[1], GHRF[k-1:1]} : GHRF;
-  assign GHRF = BranchD  ? {BPDirPredD[1], GHRD[k-1:1]} : GHRD;
+  assign GHRNextF = BPBranchF ? {BPDirF[1], GHRF[k-1:1]} : GHRF;
+  assign GHRF = BranchD  ? {BPDirD[1], GHRD[k-1:1]} : GHRD;
   assign GHRD = BranchE ? {PCSrcE, GHRE[k-1:1]} : GHRE;
   assign GHRE = BranchM ? {PCSrcM, GHRM[k-1:1]} : GHRM;
 
diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv
index 1fa6f21f6..61c3f55f0 100644
--- a/src/ifu/bpred/gsharebasic.sv
+++ b/src/ifu/bpred/gsharebasic.sv
@@ -36,16 +36,16 @@ module gsharebasic import cvw::*; #(parameter cvw_t P,
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, StallW,
   input logic             FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0]      BPDirPredF, 
-  output logic            BPDirPredWrongE,
+  output logic [1:0]      BPDirF, 
+  output logic            BPDirWrongE,
   // update
   input logic [XLEN-1:0] PCNextF, PCM,
   input logic             BranchE, BranchM, PCSrcE
 );
 
   logic [k-1:0]           IndexNextF, IndexM;
-  logic [1:0]             BPDirPredD, BPDirPredE;
-  logic [1:0]             NewBPDirPredE, NewBPDirPredM;
+  logic [1:0]             BPDirD, BPDirE;
+  logic [1:0]             NewBPDirE, NewBPDirM;
 
   logic [k-1:0]           GHRF, GHRD, GHRE, GHRM, GHR;
   logic [k-1:0]           GHRNext;
@@ -62,19 +62,19 @@ module gsharebasic import cvw::*; #(parameter cvw_t P,
   ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(IndexNextF),
-    .rd1(BPDirPredF),
+    .rd1(BPDirF),
     .wa2(IndexM),
-    .wd2(NewBPDirPredM),
+    .wd2(NewBPDirM),
     .we2(BranchM),
     .bwe2(1'b1));
 
-  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
-  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
+  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirF, BPDirD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirD, BPDirE);
 
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE));
-  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE));
+  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirE, NewBPDirM);
 
-  assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE;
+  assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE;
 
   assign GHRNext = BranchM ? {PCSrcM, GHR[k-1:1]} : GHR;
   flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchM, GHRNext, GHR);
diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv
index 8d0ecc890..f8eec8742 100644
--- a/src/ifu/bpred/icpred.sv
+++ b/src/ifu/bpred/icpred.sv
@@ -30,8 +30,8 @@
 module icpred import cvw::*;  #(parameter cvw_t P, 
                                 parameter INSTR_CLASS_PRED = 1)(
   input  logic             clk, reset,
-  input  logic             StallF, StallD, StallE, StallM, StallW,
-  input  logic             FlushD, FlushE, FlushM, FlushW,
+  input  logic             StallD, StallE, StallM, StallW,
+  input  logic             FlushD, FlushE, FlushM, 
   input  logic [31:0]      PostSpillInstrRawF, InstrD,        // Instruction
   input  logic             BranchD, BranchE,
   input  logic             JumpD, JumpE,
@@ -41,12 +41,13 @@ module icpred import cvw::*;  #(parameter cvw_t P,
   output logic             ReturnD, ReturnE, ReturnM, ReturnW,
   input  logic             BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF,
   output logic             BPCallF, BPReturnF, BPJumpF, BPBranchF,
-  output logic             IClassWrongM, BPReturnWrongD, IClassWrongE
+  output logic             IClassWrongM, BPReturnWrongD
 );
 
   logic                    IClassWrongD;
   logic                    BPBranchD, BPJumpD, BPReturnD, BPCallD;
-
+  logic                    IClassWrongE;
+  
   if (!INSTR_CLASS_PRED) begin : DirectClassDecode
     // This section is mainly for testing, verification, and PPA comparison.
     // An alternative to using the BTB to store the instruction class is to partially decode
@@ -55,7 +56,7 @@ module icpred import cvw::*;  #(parameter cvw_t P,
     logic     cjal, cj, cjr, cjalr, CJumpF, CBranchF;
     logic     NCJumpF, NCBranchF;
 
-    if(P.COMPRESSED_SUPPORTED) begin
+    if(P.ZCA_SUPPORTED) begin
       logic [4:0] CompressedOpcF;
       assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
       assign cjal = CompressedOpcF == 5'h09 & P.XLEN == 32;
@@ -65,19 +66,19 @@ module icpred import cvw::*;  #(parameter cvw_t P,
       assign CJumpF = cjal | cj | cjr | cjalr;
       assign CBranchF = CompressedOpcF[4:1] == 4'h7;
     end else begin
-      assign {cjal, cj, cjr, cjalr, CJumpF, CBranchF} = 0;
+      assign {cjal, cj, cjr, cjalr, CJumpF, CBranchF} = '0;
     end
 
     assign NCJumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F;
     assign NCBranchF = PostSpillInstrRawF[6:0] == 7'h63;
     
-    assign BPBranchF = NCBranchF | (P.COMPRESSED_SUPPORTED & CBranchF);
-    assign BPJumpF = NCJumpF | (P.COMPRESSED_SUPPORTED & (CJumpF));
+    assign BPBranchF = NCBranchF | (P.ZCA_SUPPORTED & CBranchF);
+    assign BPJumpF = NCJumpF | (P.ZCA_SUPPORTED & (CJumpF));
     assign BPReturnF = (NCJumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 & PostSpillInstrRawF[11:7] == 5'b0) | // return must return to ra or r5
-        (P.COMPRESSED_SUPPORTED & cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
+        (P.ZCA_SUPPORTED & cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
     
     assign BPCallF = (NCJumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // call(r) must link to ra or x5
-        (P.COMPRESSED_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
+        (P.ZCA_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
 
   end else begin
     // This section connects the BTB's instruction class prediction.
diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv
index fd8acbc82..5d290e85e 100644
--- a/src/ifu/bpred/localaheadbp.sv
+++ b/src/ifu/bpred/localaheadbp.sv
@@ -34,18 +34,18 @@ module localaheadbp import cvw::*; #(parameter cvw_t P,
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, StallW,
   input logic             FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0]      BPDirPredD, 
-  output logic            BPDirPredWrongE,
+  output logic [1:0]      BPDirD, 
+  output logic            BPDirWrongE,
   // update
   input logic [XLEN-1:0] PCNextF, PCM,
   input logic             BranchE, BranchM, PCSrcE
 );
 
   logic [k-1:0]           IndexNextF, IndexM;
-  //logic [1:0]             BPDirPredD, BPDirPredE;
-  logic [1:0]             BPDirPredE;
-  logic [1:0]             BPDirPredM;
-  logic [1:0]             NewBPDirPredE, NewBPDirPredM, NewBPDirPredW;
+  //logic [1:0]             BPDirD, BPDirE;
+  logic [1:0]             BPDirE;
+  logic [1:0]             BPDirM;
+  logic [1:0]             NewBPDirE, NewBPDirM, NewBPDirW;
 
   logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF;
   logic [k-1:0]           LHRNextW;
@@ -63,21 +63,21 @@ module localaheadbp import cvw::*; #(parameter cvw_t P,
   ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk),
     .ce1(~StallD), .ce2(~StallW & ~FlushW),
     .ra1(LHRF),
-    .rd1(BPDirPredD),
+    .rd1(BPDirD),
     .wa2(IndexM),
-    .wd2(NewBPDirPredW),
+    .wd2(NewBPDirW),
     .we2(BranchM),
     .bwe2(1'b1));
 
-  //flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
-  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
-  flopenrc #(2) PredictionRegM(clk, reset,  FlushM, ~StallM, BPDirPredE, BPDirPredM);
+  //flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirF, BPDirD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirD, BPDirE);
+  flopenrc #(2) PredictionRegM(clk, reset,  FlushM, ~StallM, BPDirE, BPDirM);
 
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredM), .NewState(NewBPDirPredM));
-  //flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
-  flopenrc #(2) NewPredictionRegW(clk, reset,  FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW);
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirM), .NewState(NewBPDirM));
+  //flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirE, NewBPDirM);
+  flopenrc #(2) NewPredictionRegW(clk, reset,  FlushW, ~StallW, NewBPDirM, NewBPDirW);
 
-  assign BPDirPredWrongE = PCSrcE != BPDirPredM[1] & BranchE;
+  assign BPDirWrongE = PCSrcE != BPDirM[1] & BranchE;
 
   // This is the main difference between global and local history basic implementations. In global, 
   // the ghr wraps back into itself directly without
diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv
index 5c4485f3f..c2f3fdff3 100644
--- a/src/ifu/bpred/localbpbasic.sv
+++ b/src/ifu/bpred/localbpbasic.sv
@@ -35,16 +35,16 @@ module localbpbasic import cvw::*; #(parameter cvw_t P,
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, StallW,
   input logic             FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0]      BPDirPredF, 
-  output logic            BPDirPredWrongE,
+  output logic [1:0]      BPDirF, 
+  output logic            BPDirWrongE,
   // update
   input logic [XLEN-1:0] PCNextF, PCM,
   input logic             BranchE, BranchM, PCSrcE
 );
 
   logic [k-1:0]           IndexNextF, IndexM;
-  logic [1:0]             BPDirPredD, BPDirPredE;
-  logic [1:0]             NewBPDirPredE, NewBPDirPredM;
+  logic [1:0]             BPDirD, BPDirE;
+  logic [1:0]             NewBPDirE, NewBPDirM;
 
   logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHR;
   logic [k-1:0]           LHRNextW;
@@ -60,19 +60,19 @@ module localbpbasic import cvw::*; #(parameter cvw_t P,
   ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(IndexNextF),
-    .rd1(BPDirPredF),
+    .rd1(BPDirF),
     .wa2(IndexM),
-    .wd2(NewBPDirPredM),
+    .wd2(NewBPDirM),
     .we2(BranchM),
     .bwe2(1'b1));
 
-  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
-  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
+  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirF, BPDirD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirD, BPDirE);
 
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE));
-  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE));
+  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirE, NewBPDirM);
 
-  assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE;
+  assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE;
 
   // This is the main difference between global and local history basic implementations. In global, 
   // the ghr wraps back into itself directly without
diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv
index 46819fcb7..7294816a1 100644
--- a/src/ifu/bpred/localrepairbp.sv
+++ b/src/ifu/bpred/localrepairbp.sv
@@ -34,17 +34,17 @@ module localrepairbp import cvw::*; #(parameter cvw_t P,
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, StallW,
   input logic             FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0]      BPDirPredD, 
-  output logic            BPDirPredWrongE,
+  output logic [1:0]      BPDirD, 
+  output logic            BPDirWrongE,
   // update
   input logic [XLEN-1:0] PCNextF, PCE, PCM,
   input logic             BranchD, BranchE, BranchM, PCSrcE
 );
 
-  //logic [1:0]             BPDirPredD, BPDirPredE;
-  logic [1:0]             BPDirPredE;
-  logic [1:0]             BPDirPredM;
-  logic [1:0]             NewBPDirPredE, NewBPDirPredM, NewBPDirPredW;
+  //logic [1:0]             BPDirD, BPDirE;
+  logic [1:0]             BPDirE;
+  logic [1:0]             BPDirM;
+  logic [1:0]             NewBPDirE, NewBPDirM, NewBPDirW;
 
   logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF;
   logic [k-1:0]           LHRNextW;
@@ -62,21 +62,21 @@ module localrepairbp import cvw::*; #(parameter cvw_t P,
   ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk),
     .ce1(~StallD), .ce2(~StallW & ~FlushW),
     .ra1(LHRF),
-    .rd1(BPDirPredD),
+    .rd1(BPDirD),
     .wa2(LHRW),
-    .wd2(NewBPDirPredW),
+    .wd2(NewBPDirW),
     .we2(BranchM),
     .bwe2(1'b1));
 
-  //flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
-  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
-  flopenrc #(2) PredictionRegM(clk, reset,  FlushM, ~StallM, BPDirPredE, BPDirPredM);
+  //flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirF, BPDirD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirD, BPDirE);
+  flopenrc #(2) PredictionRegM(clk, reset,  FlushM, ~StallM, BPDirE, BPDirM);
 
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredM), .NewState(NewBPDirPredM));
-  //flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
-  flopenrc #(2) NewPredictionRegW(clk, reset,  FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW);
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirM), .NewState(NewBPDirM));
+  //flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirE, NewBPDirM);
+  flopenrc #(2) NewPredictionRegW(clk, reset,  FlushW, ~StallW, NewBPDirM, NewBPDirW);
 
-  assign BPDirPredWrongE = PCSrcE != BPDirPredM[1] & BranchE;
+  assign BPDirWrongE = PCSrcE != BPDirM[1] & BranchE;
 
   // This is the main difference between global and local history basic implementations. In global, 
   // the ghr wraps back into itself directly without
@@ -100,8 +100,8 @@ module localrepairbp import cvw::*; #(parameter cvw_t P,
     .bwe2('1));
 
   assign IndexLHRD = {PCE[m+1] ^ PCE[1], PCE[m:2]};
-  assign LHRNextE = BranchD ? {BPDirPredD[1], LHRE[k-1:1]} : LHRE;
-  // *** replace with a small CAM
+  assign LHRNextE = BranchD ? {BPDirD[1], LHRE[k-1:1]} : LHRE;
+  // RT: TODO active research: replace with a small CAM, quantify benefit
   ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**m), .WIDTH(k)) SHB(.clk(clk),
     .ce1(~StallF), .ce2(~StallE & ~FlushE),
     .ra1(IndexLHRNextF),
@@ -110,13 +110,13 @@ module localrepairbp import cvw::*; #(parameter cvw_t P,
     .wd2(LHRNextE),
     .we2(BranchD),
     .bwe2('1));
-  // **** replace with small CAM
+  // RT: TODO active research: replace with small CAM, quantify benefit
   logic [2**m-1:0]        FlushedBits;
   always_ff @(posedge clk) begin // Valid bit array,
     SpeculativeFlushedF <= FlushedBits[IndexLHRNextF];
     if (reset | FlushD) FlushedBits        <= '1;
     if(BranchD & ~StallE & ~FlushE) begin
-      FlushedBits[IndexLHRD] <= 0;
+      FlushedBits[IndexLHRD] <= 1'b0;
     end
   end
 
diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv
index 583b8d805..b65fdde7e 100644
--- a/src/ifu/bpred/twoBitPredictor.sv
+++ b/src/ifu/bpred/twoBitPredictor.sv
@@ -34,8 +34,8 @@ module twoBitPredictor import cvw::*; #(parameter cvw_t P, parameter XLEN,
   input  logic             StallF, StallD, StallE, StallM, StallW,
   input  logic             FlushD, FlushE, FlushM, FlushW,
   input  logic [XLEN-1:0]  PCNextF, PCM,
-  output logic [1:0]       BPDirPredF,
-  output logic             BPDirPredWrongE,
+  output logic [1:0]       BPDirF,
+  output logic             BPDirWrongE,
   input  logic             BranchE, BranchM,
   input  logic             PCSrcE
 );
@@ -43,8 +43,8 @@ module twoBitPredictor import cvw::*; #(parameter cvw_t P, parameter XLEN,
   logic [k-1:0]            IndexNextF, IndexM;
   logic [1:0]              PredictionMemory;
   logic                    DoForwarding, DoForwardingF;
-  logic [1:0]              BPDirPredD, BPDirPredE;
-  logic [1:0]              NewBPDirPredE, NewBPDirPredM;
+  logic [1:0]              BPDirD, BPDirE;
+  logic [1:0]              NewBPDirE, NewBPDirM;
 
   // hashing function for indexing the PC
   // We have k bits to index, but XLEN bits as the input.
@@ -54,22 +54,22 @@ module twoBitPredictor import cvw::*; #(parameter cvw_t P, parameter XLEN,
   assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]};  
 
 
-  ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk),
+  ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) BHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(IndexNextF),
-    .rd1(BPDirPredF),
+    .rd1(BPDirF),
     .wa2(IndexM),
-    .wd2(NewBPDirPredM),
+    .wd2(NewBPDirM),
     .we2(BranchM),
     .bwe2(1'b1));
   
-  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
-  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
+  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirF, BPDirD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirD, BPDirE);
 
-  assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE;
+  assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE;
 
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE));
-  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE));
+  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirE, NewBPDirM);
   
 
 endmodule
diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv
index e6c4fcd9a..512dacfd5 100644
--- a/src/ifu/decompress.sv
+++ b/src/ifu/decompress.sv
@@ -6,10 +6,6 @@
 // Modified: 18 January 2023
 //
 // Purpose: Expand 16-bit compressed instructions to 32 bits
-//
-// Documentation: RISC-V System on Chip Design Chapter 11 (Section 11.3.1)
-//                RISC-V Specification 13 Dec 2019 Chapter 16 pg. 97
-// *** probably need more documentation in this file since the book is very light on decompression.
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -80,63 +76,63 @@ module decompress import cvw::*;  #(parameter cvw_t P) (
   always_comb
     if (op == 2'b11) begin // noncompressed instruction
       InstrD = InstrRawD; 
-      IllegalCompInstrD = 0;
+      IllegalCompInstrD = '0;
     end else begin  // convert compressed instruction into uncompressed
-      IllegalCompInstrD = 0;
+      IllegalCompInstrD = '0;
       case ({op, instr16[15:13]})
         5'b00000: if (immCIW != 0) InstrD = {immCIW, 5'b00010, 3'b000, rdp, 7'b0010011}; // c.addi4spn
                   else begin // illegal instruction
-                    IllegalCompInstrD = 1;
+                    IllegalCompInstrD = 1'b1;
                     InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                   end
-        5'b00001: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
+        5'b00001: if (P.ZCD_SUPPORTED)
                     InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
                   else begin // unsupported instruction
-                    IllegalCompInstrD = 1;
+                    IllegalCompInstrD = 1'b1;
                     InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                   end
         5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
         5'b00011: if (P.XLEN==32)
-                    if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) 
+                    if (P.ZCF_SUPPORTED) 
                       InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
                     else begin
-                      IllegalCompInstrD = 1;
+                      IllegalCompInstrD = 1'b1;
                       InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                     end
                   else
                     InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld;
         5'b00100: if (P.ZCB_SUPPORTED) 
                     if (instr16[12:10] == 3'b000) 
-                      InstrD = {10'b0, instr16[6:5], rs1p, 3'b100, rdp, 7'b0000011}; // c.lbu
+                      InstrD = {10'b0, instr16[5], instr16[6], rs1p, 3'b100, rdp, 7'b0000011}; // c.lbu
                     else if (instr16[12:10] == 3'b001) begin
                       if (instr16[6]) 
                         InstrD = {10'b0, instr16[5], 1'b0, rs1p, 3'b001, rdp, 7'b0000011}; // c.lh
                       else
                         InstrD = {10'b0, instr16[5], 1'b0, rs1p, 3'b101, rdp, 7'b0000011}; // c.lhu
                     end else if (instr16[12:10] == 3'b010)
-                      InstrD = {7'b0, rs2p, rs1p, 3'b000, 3'b000, instr16[6:5], 7'b0000011}; // c.sb 
+                      InstrD = {7'b0, rs2p, rs1p, 3'b000, 3'b000, instr16[5], instr16[6], 7'b0100011}; // c.sb 
                     else if (instr16[12:10] == 3'b011 & instr16[6] == 1'b0)
-                      InstrD = {7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0000011}; // c.sh
+                      InstrD = {7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0100011}; // c.sh
                     else begin
-                      IllegalCompInstrD = 1;
+                      IllegalCompInstrD = 1'b1;
                       InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                     end
                  else begin
-                    IllegalCompInstrD = 1;
+                    IllegalCompInstrD = 1'b1;
                     InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                   end
-        5'b00101: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
+        5'b00101: if (P.ZCD_SUPPORTED)
                     InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
                   else begin // unsupported instruction
-                    IllegalCompInstrD = 1;
+                    IllegalCompInstrD = 1'b1;
                     InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                   end
         5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
         5'b00111: if (P.XLEN==32)
-                    if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) 
+                    if (P.ZCF_SUPPORTED) 
                       InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
                     else begin
-                      IllegalCompInstrD = 1;
+                      IllegalCompInstrD = 1'b1;
                       InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                     end
                   else
@@ -173,42 +169,42 @@ module decompress import cvw::*;  #(parameter cvw_t P) (
                       InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
                     else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED) 
                       InstrD = {12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255
-                    else if (instr16[6:2] == 5'b11001 & P.ZCB_SUPPORTED) 
+                    else if (instr16[6:2] == 5'b11001 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED) 
                       InstrD = {12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b
-                    else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED) 
+                    else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED) 
                       InstrD = {7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011};  // c.zext.h
-                    else if (instr16[6:2] == 5'b11011 & P.ZCB_SUPPORTED) 
+                    else if (instr16[6:2] == 5'b11011 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED) 
                       InstrD = {12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h
                     else if (instr16[6:2] == 5'b11101 & P.ZCB_SUPPORTED) 
                       InstrD = {12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori
-                    else if (instr16[6:2] == 5'b11100 & P.ZCB_SUPPORTED & P.XLEN > 32) 
+                    else if (instr16[6:2] == 5'b11100 & P.ZCB_SUPPORTED & P.ZBA_SUPPORTED & P.XLEN > 32) 
                       InstrD = {7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0
-                    else if (instr16[6:5] == 2'b10 & P.ZCB_SUPPORTED) 
+                    else if (instr16[6:5] == 2'b10 & P.ZCB_SUPPORTED & P.ZMMUL_SUPPORTED) 
                       InstrD = {7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul
                     else begin // reserved  
-                      IllegalCompInstrD = 1;
+                      IllegalCompInstrD = 1'b1;
                       InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                     end
                   /** end else begin // illegal instruction
-                    IllegalCompInstrD = 1;
+                    IllegalCompInstrD = 1'b1;
                     InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap **/
                   end
         5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
         5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
         5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
         5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
-        5'b10001: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
+        5'b10001: if (P.ZCD_SUPPORTED)
                     InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
                   else begin // unsupported instruction
-                    IllegalCompInstrD = 1;
+                    IllegalCompInstrD = 1'b1;
                     InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                   end
         5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
         5'b10011: if (P.XLEN == 32)
-                    if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) 
+                    if (P.ZCF_SUPPORTED) 
                       InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
                     else begin
-                      IllegalCompInstrD = 1;
+                      IllegalCompInstrD = 1'b1;
                       InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                     end                    
                   else 
@@ -226,24 +222,24 @@ module decompress import cvw::*;  #(parameter cvw_t P) (
                         InstrD = {12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr
                     else
                       InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
-        5'b10101: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
+        5'b10101: if (P.ZCD_SUPPORTED)
                     InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
                   else begin // unsupported instruction
-                    IllegalCompInstrD = 1;
+                    IllegalCompInstrD = 1'b1;
                     InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                   end
         5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
         5'b10111: if (P.XLEN==32)
-                    if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) 
+                    if (P.ZCF_SUPPORTED) 
                       InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
                     else begin
-                      IllegalCompInstrD = 1;
+                      IllegalCompInstrD = 1'b1;
                       InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                     end                    
                   else
                     InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp
         default: begin // illegal instruction
-                    IllegalCompInstrD = 1;
+                    IllegalCompInstrD = 1'b1;
                     InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                   end
       endcase
diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index f12e02ec9..e5d64716c 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -65,8 +65,8 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   output logic [31:0]          InstrOrigM,                               // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
   output logic [P.XLEN-1:0]    PCM,                                      // Memory stage instruction address
   // branch predictor
-  output logic [3:0]           InstrClassM,                              // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
-  output logic                 BPDirPredWrongM,                          // Prediction direction is wrong
+  output logic [3:0]           IClassM,                              // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
+  output logic                 BPDirWrongM,                          // Prediction direction is wrong
   output logic                 BTAWrongM,                                // Prediction target wrong
   output logic                 RASPredPCWrongM,                          // RAS prediction is wrong
   output logic                 IClassWrongM,                             // Class prediction is wrong
@@ -90,13 +90,21 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   input  logic                 ENVCFG_PBMTE,                             // Page-based memory types enabled
   input  logic                 ENVCFG_ADUE,                              // HPTW A/D Update enable
   input  logic                 sfencevmaM,                               // Virtual memory address fence, invalidate TLB entries
-  output logic                 ITLBMissF,                                // ITLB miss causes HPTW (hardware pagetable walker) walk
-  output logic                 InstrUpdateDAF,                           // ITLB hit needs to update dirty or access bits
+  output logic                 ITLBMissOrUpdateAF,                       // ITLB miss causes HPTW (hardware pagetable walker) walk or update access bit
   input  var logic [7:0]       PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],     // PMP configuration from privileged unit
   input  var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0],// PMP address from privileged unit
   output logic                 InstrAccessFaultF,                        // Instruction access fault 
   output logic                 ICacheAccess,                             // Report I$ read to performance counters
-  output logic                 ICacheMiss                                // Report I$ miss to performance counters
+  output logic                 ICacheMiss,                               // Report I$ miss to performance counters
+  // Debug Mode logic
+  input  logic                 DRet,
+  input  logic                 ProgBuffScanEn,
+  // Debug scan chain
+  input  logic [P.XLEN-1:0]    ProgBufAddr,
+  input  logic                 ProgBufScanIn,
+  input  logic                 DebugScanEn,
+  input  logic                 DebugScanIn,
+  output logic                 DebugScanOut
 );
 
   localparam [31:0]            nop = 32'h00000013;                       // instruction for NOP
@@ -118,7 +126,9 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
 
   logic [31:0]                 IROMInstrF;                               // Instruction from the IROM
   logic [31:0]                 ICacheInstrF;                             // Instruction from the I$
-  logic [31:0]                 InstrRawF;                                // Instruction from the IROM, I$, or bus
+  logic [31:0]                 InstrRawFMain;                            // Instruction from the IROM, I$, or bus  TODO: pick a better name for this signal
+  logic [31:0]                 InstrRawF;                                // Instruction from ProgBuf pr InstrRawFMain (IROM, I$, bus)
+  logic [31:0]                 ProgBufInstrF;                            // Instruction from the ProgBuf
   logic                        CompressedF, CompressedE;                 // The fetched instruction is compressed
   logic [31:0]                 PostSpillInstrRawF;                       // Fetch instruction after merge two halves of spill
   logic [31:0]                 InstrRawD;                                // Non-decompressed instruction in the Decode stage
@@ -137,24 +147,29 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   logic                        BusCommittedF;                            // Bus memory operation in flight, delay interrupts
   logic                        CacheCommittedF;                          // I$ memory operation started, delay interrupts
   logic                        SelIROM;                                  // PMA indicates instruction address is in the IROM
+  logic                        SelProgBuf;                               // PMA indicates instruction address is in Program Buffer
   logic [15:0]                 InstrRawE, InstrRawM;
   logic [LINELEN-1:0]          FetchBuffer;
   logic [31:0]                 ShiftUncachedInstr;
-  
+  logic 		       ITLBMissF;
+  logic 		       InstrUpdateAF;                            // ITLB hit needs to update dirty or access bits
+    // Debug scan chain
+  logic                        DebugScanChainReg;                        // Debug Scan Chain Register
+ 
   assign PCFExt = {2'b00, PCSpillF};
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Spill Support
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  if(P.COMPRESSED_SUPPORTED) begin : Spill
-    spill #(P) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .InstrUpdateDAF, .CacheableF, 
-      .IFUCacheBusStallF, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
+  if(P.ZCA_SUPPORTED) begin : Spill
+    spill #(P) spill(.clk, .reset, .StallF, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,  .CacheableF, 
+      .IFUCacheBusStallF, .ITLBMissOrUpdateAF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
   end else begin : NoSpill
     assign PCSpillNextF = PCNextF;
     assign PCSpillF = PCF;
     assign PostSpillInstrRawF = InstrRawF;
-    assign {SelSpillNextF, CompressedF} = 0;
+    assign {SelSpillNextF, CompressedF} = '0;
   end
 
   ////////////////////////////////////////////////////////////////////////////////////////////////
@@ -185,19 +200,22 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
          .TLBFlush,
          .PhysicalAddress(PCPF),
          .TLBMiss(ITLBMissF),
-         .Cacheable(CacheableF), .Idempotent(), .SelTIM(SelIROM),
+         .Cacheable(CacheableF), .Idempotent(), .SelTIM(SelIROM), .SelProgBuf,
          .InstrAccessFaultF, .LoadAccessFaultM(), .StoreAmoAccessFaultM(),
          .InstrPageFaultF, .LoadPageFaultM(), .StoreAmoPageFaultM(),
          .LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(),
-         .UpdateDA(InstrUpdateDAF), .CMOpM(4'b0),
+         .UpdateDA(InstrUpdateAF), .CMOpM(4'b0),
          .AtomicAccessM(1'b0),.ExecuteAccessF(1'b1), .WriteAccessM(1'b0), .ReadAccessM(1'b0),
          .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
 
+     assign ITLBMissOrUpdateAF = ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateAF);  
   end else begin
-    assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrUpdateDAF} = 0;
+    assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF, InstrUpdateAF} = '0;
     assign PCPF = PCFExt[P.PA_BITS-1:0];
-    assign CacheableF = 1;
-    assign SelIROM = 0;
+    assign CacheableF = 1'b1;
+    assign SelIROM = '0;
+    assign SelProgBuf = '0;
+    assign ITLBMissOrUpdateAF = '0;
   end
 
   ////////////////////////////////////////////////////////////////////////////////////////////////
@@ -207,26 +225,23 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   // CommittedM tells the CPU's privileged unit the current instruction
   // in the memory stage is a memory operaton and that memory operation is either completed
   // or is partially executed. Partially completed memory operations need to prevent an interrupts.
-  // There is not a clean way to restore back to a partial executed instruction.  CommiteedM will
+  // There is not a clean way to restore back to a partial executed instruction.  CommittedM will
   // delay the interrupt until the LSU is in a clean state.
   assign CommittedF = CacheCommittedF | BusCommittedF;
 
-  logic  IgnoreRequest;
-  assign IgnoreRequest = ITLBMissF | FlushD;
-
   // The IROM uses untranslated addresses, so it is not compatible with virtual memory.
   if (P.IROM_SUPPORTED) begin : irom
-  logic IROMce;
-  assign IROMce = ~GatedStallD | reset;
+    logic IROMce;
+    assign IROMce = ~GatedStallD | reset;
     assign IFURWF = 2'b10;
     irom #(P) irom(.clk, .ce(IROMce), .Adr(PCSpillNextF[P.XLEN-1:0]), .IROMInstrF);
   end else begin
     assign IFURWF = 2'b10;
+    assign IROMInstrF = '0;
   end
   if (P.BUS_SUPPORTED) begin : bus
-    // **** must fix words per line vs beats per line as in lsu.
-    localparam   WORDSPERLINE = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/P.XLEN : 1;
-    localparam   LOGBWPL = P.ICACHE_SUPPORTED ? $clog2(WORDSPERLINE) : 1;
+    localparam   BEATSPERLINE = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/P.AHBW : 1;
+    localparam   AHBWLOGBWPL = P.ICACHE_SUPPORTED ? $clog2(BEATSPERLINE) : 1;
     
     if(P.ICACHE_SUPPORTED) begin : icache
       localparam            LLENPOVERAHBW = P.LLEN / P.AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
@@ -234,12 +249,11 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
       logic                 ICacheBusAck;
       logic [1:0]           CacheBusRW, BusRW, CacheRWF;
       
-      assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : 0;
-      assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : 0;
-      // *** RT: PAdr and NextSet are replaced with mux between PCPF/IEUAdrM and PCSpillNextF/IEUAdrE.
+      assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
+      assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
       cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS),
-              .NUMLINES(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS),
-              .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1))
+              .NUMSETS(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS),
+              .NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(AHBWLOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1))
       icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD),
              .FetchBuffer, .CacheBusAck(ICacheBusAck),
              .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), 
@@ -248,14 +262,14 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
              .SelHPTW('0),
              .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
              .ByteMask('0), .BeatCount('0), .SelBusBeat('0),
-             .CacheWriteData('0),
+             .WriteData('0),
              .CacheRW(CacheRWF),
              .FlushCache('0),
              .NextSet(PCSpillNextF[11:0]),
              .PAdr(PCPF),
              .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM), .CMOpM('0)); 
 
-      ahbcacheinterface #(P, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) 
+      ahbcacheinterface #(P, BEATSPERLINE, AHBWLOGBWPL, LINELEN, LLENPOVERAHBW, 1) 
       ahbcacheinterface(.HCLK(clk), .HRESETn(~reset),
             .HRDATA,
             .Flush(FlushD), .CacheBusRW, .BusCMOZero(1'b0), .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(),
@@ -267,7 +281,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
             .BusStall, .BusCommitted(BusCommittedF));
 
       mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(ShiftUncachedInstr), .d2(IROMInstrF),
-                                 .s({SelIROM, ~CacheableF}), .y(InstrRawF[31:0]));
+                                 .s({SelIROM, ~CacheableF}), .y(InstrRawFMain[31:0]));
     end else begin : passthrough
       assign IFUHADDR = PCPF;
       logic [1:0] BusRW;
@@ -279,29 +293,40 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
         .HWSTRB(), .BusRW, .BusAtomic('0), .ByteMask(), .WriteData('0),
         .Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
 
-      assign CacheCommittedF = 0;
-      if(P.IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(ShiftUncachedInstr, IROMInstrF, SelIROM, InstrRawF);
-      else assign InstrRawF = ShiftUncachedInstr;
+      assign CacheCommittedF = '0;
+      if(P.IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(ShiftUncachedInstr, IROMInstrF, SelIROM, InstrRawFMain);
+      else assign InstrRawFMain = ShiftUncachedInstr;
       assign IFUHBURST = 3'b0;
-      assign {ICacheMiss, ICacheAccess, ICacheStallF} = 0;
+      assign {ICacheMiss, ICacheAccess, ICacheStallF} = '0;
     end
+
+    // mux between the alignments of uncached reads.
+    if(P.XLEN == 64) mux4 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], FetchBuffer[48-1:16], 
+                                                      FetchBuffer[64-1:32], {16'b0, FetchBuffer[64-1:48]},
+                                                      PCSpillF[2:1], ShiftUncachedInstr);
+    else mux2 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], {16'b0, FetchBuffer[32-1:16]}, PCSpillF[1], ShiftUncachedInstr);
   end else begin : nobus // block: bus
-    assign {BusStall, CacheCommittedF} = 0;   
-    assign {ICacheStallF, ICacheMiss, ICacheAccess} = 0;
-    assign InstrRawF = IROMInstrF;
+    assign {IFUHADDR, IFUHWRITE, IFUHSIZE, IFUHBURST, IFUHTRANS, 
+            BusStall, CacheCommittedF, BusCommittedF, FetchBuffer} = '0;   
+    assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
+    assign InstrRawFMain = IROMInstrF;
+  end
+
+  // Mux between InstrRawFMain and Progbuf
+  if (P.DEBUG_SUPPORTED) begin
+    progbuf #(P) progbuf(.clk, .reset, .Addr(PCF[5:0]), .ProgBufInstrF, .ScanAddr(ProgBufAddr), .Scan(ProgBuffScanEn), .ScanIn(ProgBufScanIn));
+    assign InstrRawF = SelProgBuf ? ProgBufInstrF : InstrRawFMain;
+  end else begin
+    assign InstrRawF = InstrRawFMain;
   end
 
-  // mux between the alignments of uncached reads.
-  if(P.XLEN == 64) mux4 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], FetchBuffer[48-1:16], FetchBuffer[64-1:32], {16'b0, FetchBuffer[64-1:48]},
-                                                    PCSpillF[2:1], ShiftUncachedInstr);
-  else mux2 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], {16'b0, FetchBuffer[32-1:16]}, PCSpillF[1], ShiftUncachedInstr);
-  
   assign IFUCacheBusStallF = ICacheStallF | BusStall;
   assign IFUStallF = IFUCacheBusStallF | SelSpillNextF;
   assign GatedStallD = StallD & ~SelSpillNextF;
-  
+
   flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
 
+
   ////////////////////////////////////////////////////////////////////////////////////////////////
   // PCNextF logic
   ////////////////////////////////////////////////////////////////////////////////////////////////
@@ -310,7 +335,8 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
     mux2 #(P.XLEN) pcmux2(.d0(PC1NextF), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PC2NextF));
   else assign PC2NextF = PC1NextF;
 
-  mux3 #(P.XLEN) pcmux3(PC2NextF, EPCM, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF);
+
+  mux3 #(P.XLEN) pcmux3(PC2NextF, EPCM, TrapVectorM, {TrapM, (RetM | DRet)}, UnalignedPCNextF);
   mux2 #(P.XLEN) pcresetmux({UnalignedPCNextF[P.XLEN-1:1], 1'b0}, P.RESET_VECTOR[P.XLEN-1:0], reset, PCNextF);
   flopen #(P.XLEN) pcreg(clk, ~StallF | reset, PCNextF, PCF);
 
@@ -318,7 +344,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
   assign PCPlus4F = PCF[P.XLEN-1:2] + 1; // add 4 to PC
 
-  if (P.COMPRESSED_SUPPORTED) begin: pcadd
+  if (P.ZCA_SUPPORTED) begin: pcadd
     // choose PC+2 or PC+4 based on CompressedF, which arrives later. 
     // Speeds up critical path as compared to selecting adder input based on CompressedF
     always_comb
@@ -339,8 +365,8 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
                 .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE, 
                 .BranchD, .BranchE, .JumpD, .JumpE,
                 .InstrD, .PCNextF, .PCPlus2or4F, .PC1NextF, .PCE, .PCM, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCF, .NextValidPCE,
-                .PCD, .PCLinkE, .InstrClassM, .BPWrongE, .PostSpillInstrRawF, .BPWrongM,
-                .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM);
+                .PCD, .PCLinkE, .IClassM, .BPWrongE, .PostSpillInstrRawF, .BPWrongM,
+                .BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM);
 
   end else begin : bpred
     mux2 #(P.XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PC1NextF));    
@@ -348,17 +374,17 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
     logic CallD, CallE, CallM, CallW;
     logic ReturnD, ReturnE, ReturnM, ReturnW;
     assign BPWrongE = PCSrcE;
-    icpred #(P, 0) icpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+    icpred #(P, 0) icpred(.clk, .reset, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, 
       .PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW,
       .CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW, 
       .BTBCallF(1'b0), .BTBReturnF(1'b0), .BTBJumpF(1'b0),
       .BTBBranchF(1'b0), .BPCallF(), .BPReturnF(), .BPJumpF(), .BPBranchF(), .IClassWrongM,
-      .IClassWrongE(), .BPReturnWrongD());
+      .BPReturnWrongD());
     flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, BPWrongM);
-    assign RASPredPCWrongM = 0;
-    assign BPDirPredWrongM = BPWrongM;
+    assign RASPredPCWrongM = 1'b0;
+    assign BPDirWrongM = BPWrongM;
     assign BTAWrongM = BPWrongM;
-    assign InstrClassM = {CallM, ReturnM, JumpM, BranchM};
+    assign IClassM = {CallM, ReturnM, JumpM, BranchM};
     assign NextValidPCE = PCE;
   end      
 
@@ -370,7 +396,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
    
   // expand 16-bit compressed instructions to 32 bits
-  if (P.COMPRESSED_SUPPORTED) begin: decomp
+  if (P.ZCA_SUPPORTED) begin: decomp
     logic IllegalCompInstrD;
     decompress #(P) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); 
     assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
@@ -390,7 +416,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   // only IALIGN=32, the two low bits (mepc[1:0]) are always zero.
   // Spec 3.1.14
   // Traps: Can’t happen.  The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4.  See 3.1.7 of the privileged spec.
-  assign BranchMisalignedFaultE = (IEUAdrE[1] & ~P.COMPRESSED_SUPPORTED) & PCSrcE;
+  assign BranchMisalignedFaultE = (IEUAdrE[1] & ~P.ZCA_SUPPORTED) & PCSrcE;
   flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
 
   // Instruction and PC pipeline registers flush to NOP, not zero
@@ -401,26 +427,42 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   // InstrM is only needed with CSRs or atomic operations
   if (P.ZICSR_SUPPORTED | P.A_SUPPORTED) begin
     mux2    #(32)     FlushInstrMMux(InstrE, nop, FlushM, NextInstrE);
-    flopenr #(32)     InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
-  end else assign InstrM = 0;
+    if (P.DEBUG_SUPPORTED)
+      flopenrs #(32)     InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM, DebugScanEn, DebugScanChainReg, DebugScanOut);
+    else begin
+      flopenr #(32)     InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
+      assign DebugScanOut = DebugScanChainReg;
+    end
+  end else begin
+    assign InstrM = '0;
+    assign DebugScanOut = DebugScanChainReg;
+  end
   // PCM is only needed with CSRs or branch prediction
-  if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED) 
-    flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
-  else assign PCM = 0; 
+  if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED)
+    if (P.DEBUG_SUPPORTED)
+      flopenrs #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM, DebugScanEn, DebugScanIn, DebugScanChainReg);
+    else begin
+      flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
+      assign DebugScanChainReg = DebugScanIn;
+    end
+  else begin
+    assign PCM = '0;
+    assign DebugScanChainReg = DebugScanIn;
+  end
   
   // If compressed instructions are supported, increment PCLink by 2 or 4 for a jal.  Otherwise, just by 4
-  if (P.COMPRESSED_SUPPORTED) begin
+  if (P.ZCA_SUPPORTED) begin
     logic CompressedD;  // instruction is compressed
     flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD);
     flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE);
     assign PCLinkE = PCE + (CompressedE ? 'd2 : 'd4); // 'd4 means 4 but stops Design Compiler complaining about signed to unsigned conversion
   end else begin
-    assign CompressedE = 0;
+    assign CompressedE = 1'b0;
     assign PCLinkE = PCE + 'd4;
   end
  
   // pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception
-  if (P.ZICSR_SUPPORTED & P.COMPRESSED_SUPPORTED | 1) begin
+  if (P.ZICSR_SUPPORTED & P.ZCA_SUPPORTED | 1) begin
     logic CompressedM; // instruction is compressed
     flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);
     flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
diff --git a/src/ifu/irom.sv b/src/ifu/irom.sv
index e5e7a7f96..027c26235 100644
--- a/src/ifu/irom.sv
+++ b/src/ifu/irom.sv
@@ -52,7 +52,7 @@ module irom import cvw::*;  #(parameter cvw_t P) (
   end
   // If the memory addres is aligned to 2 bytes return the upper 2 bytes in the lower 2 bytes.
   // The spill logic will handle merging the two together.
-  if (P.COMPRESSED_SUPPORTED) begin
+  if (P.ZCA_SUPPORTED) begin
     flopen #(1) AdrReg1(clk, ce, Adr[1], AdrD[1]);
     assign IROMInstrF = AdrD[1] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
   end else
diff --git a/src/ifu/progbuf.sv b/src/ifu/progbuf.sv
new file mode 100644
index 000000000..9b8afe38c
--- /dev/null
+++ b/src/ifu/progbuf.sv
@@ -0,0 +1,72 @@
+///////////////////////////////////////////
+// progbuf.sv
+//
+// Written: matthew.n.otto@okstate.edu
+// Created: 18 June 2024
+//
+// Purpose: Holds small programs to be executed in debug mode
+//          This module acts like a small ROM except it can be written by serial Scanning via the Debug Module
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License Version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module progbuf import cvw::*;  #(parameter cvw_t P) (
+    input  logic        clk, reset,
+    input  logic [5:0]  Addr,
+    output logic [31:0] ProgBufInstrF,
+
+    input  logic [P.XLEN-1:0] ScanAddr,
+    input  logic        Scan,
+    input  logic        ScanIn
+);
+
+  localparam PROGBUF_SIZE = (P.PROGBUF_RANGE+1)/4;
+  localparam ADDR_WIDTH = $clog2(PROGBUF_SIZE);
+  
+  bit [31:0] RAM [PROGBUF_SIZE-1:0];
+
+  logic EnPrevClk;
+  logic WriteProgBuf;
+  logic [32:0] WriteData;
+  logic [31:0] ReadRaw;
+  logic [ADDR_WIDTH-1:0] AddrM;
+
+  flopr #(1) Scanenhist (.clk, .reset, .d(Scan), .q(EnPrevClk));
+  assign WriteProgBuf = ~Scan & EnPrevClk;
+
+  assign WriteData[32] = ScanIn;
+  genvar i;
+  for (i=0; i<32; i=i+1) begin
+    flopenr #(1) Scanreg (.clk, .reset, .en(Scan), .d(WriteData[i+1]), .q(WriteData[i]));
+  end
+
+  assign AddrM = WriteProgBuf ? ScanAddr[ADDR_WIDTH-1:0] : Addr[ADDR_WIDTH-1+2:2];
+
+  always_ff @(posedge clk) begin
+    if (WriteProgBuf)
+      RAM[AddrM] <= WriteData[31:0];
+    if (reset)
+      ReadRaw <= 0;
+    else
+      ReadRaw <= RAM[AddrM];
+  end
+
+  assign ProgBufInstrF = Addr[1] ? {16'b0,ReadRaw[31:16]}: ReadRaw; // 
+
+endmodule
diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv
index 122efff1c..b2ee6e9e2 100644
--- a/src/ifu/spill.sv
+++ b/src/ifu/spill.sv
@@ -9,7 +9,7 @@
 //          cache line boundaries or if instruction address without a cache crosses
 //          XLEN/8 boundary.
 //
-// Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -33,14 +33,13 @@
 module spill import cvw::*;  #(parameter cvw_t P) (
   input logic               clk,               
   input logic               reset,
-  input logic               StallD, FlushD,
+  input logic               StallF, FlushD,
   input logic [P.XLEN-1:0]  PCF,               // 2 byte aligned PC in Fetch stage
   input logic [P.XLEN-1:2]  PCPlus4F,          // PCF + 4
   input logic [P.XLEN-1:0]  PCNextF,           // The next PCF
   input logic [31:0]        InstrRawF,         // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
   input logic               IFUCacheBusStallF, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
-  input logic               ITLBMissF,         // ITLB miss, ignore memory request
-  input logic               InstrUpdateDAF,    // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active)
+  input logic               ITLBMissOrUpdateAF, // ITLB miss causes HPTW (hardware pagetable walker) walk or update access bit
   input logic               CacheableF,        // Is the instruction from the cache?
   output logic [P.XLEN-1:0] PCSpillNextF,      // The next PCF for one of the two memory addresses of the spill
   output logic [P.XLEN-1:0] PCSpillF,          // PCF for one of the two memory addresses of the spill
@@ -86,7 +85,7 @@ module spill import cvw::*;  #(parameter cvw_t P) (
   end else
     assign SpillF = PCF[1];
   // Don't take the spill if there is a stall, TLB miss, or hardware update to the D/A bits
-  assign TakeSpillF = SpillF & ~EarlyCompressedF & ~IFUCacheBusStallF & ~(ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF));
+  assign TakeSpillF = SpillF & ~EarlyCompressedF & ~IFUCacheBusStallF & ~ITLBMissOrUpdateAF;
   
   always_ff @(posedge clk)
     if (reset | FlushD)    CurrState <= STATE_READY;
@@ -96,7 +95,7 @@ module spill import cvw::*;  #(parameter cvw_t P) (
     case (CurrState)
       STATE_READY: if (TakeSpillF)                NextState = STATE_SPILL;
                    else                           NextState = STATE_READY;
-      STATE_SPILL: if(StallD)                     NextState = STATE_SPILL;
+      STATE_SPILL: if(StallF)                     NextState = STATE_SPILL;
                    else                           NextState = STATE_READY;
       default:                                    NextState = STATE_READY;
     endcase
diff --git a/src/lsu/align.sv b/src/lsu/align.sv
index 476e77c28..db37f4a66 100644
--- a/src/lsu/align.sv
+++ b/src/lsu/align.sv
@@ -9,7 +9,7 @@
 //          It is simlar to the IFU's spill module and probably could be merged together with 
 //          some effort.
 //
-// Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -76,6 +76,8 @@ module align import cvw::*;  #(parameter cvw_t P) (
   logic [$clog2(LLENINBYTES)-1:0]              AccessByteOffsetM;
   logic [$clog2(LLENINBYTES)+2:0]              ShiftAmount;
   logic                                        PotentialSpillM;
+  logic [P.LLEN*3-1:0]                         LSUWriteDataShiftedExtM; 
+
 
   /* verilator lint_off WIDTHEXPAND */
   assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES;
@@ -95,21 +97,21 @@ module align import cvw::*;  #(parameter cvw_t P) (
   // compute misalignement
   always_comb begin
     case (Funct3M & {FpLoadStoreM, 2'b11}) 
-      3'b000: AccessByteOffsetM = 0; // byte access
+      3'b000: AccessByteOffsetM = '0; // byte access
       3'b001: AccessByteOffsetM = {{OFFSET_LEN-1{1'b0}}, IEUAdrM[0]}; // half access
       3'b010: AccessByteOffsetM = {{OFFSET_LEN-2{1'b0}}, IEUAdrM[1:0]}; // word access
       3'b011: if(P.LLEN >= 64) AccessByteOffsetM = {{OFFSET_LEN-3{1'b0}}, IEUAdrM[2:0]}; // double access
-              else             AccessByteOffsetM = 0;                                    // shouldn't happen
+              else             AccessByteOffsetM = '0;                                    // shouldn't happen
       3'b100: if(P.LLEN == 128) AccessByteOffsetM = IEUAdrM[OFFSET_LEN-1:0]; // quad access
               else              AccessByteOffsetM = IEUAdrM[OFFSET_LEN-1:0];
-      default: AccessByteOffsetM = 0;                                        // shouldn't happen
+      default: AccessByteOffsetM = '0;                                        // shouldn't happen
     endcase
     case (Funct3M[1:0]) 
-      2'b00: PotentialSpillM = 0; // byte access
+      2'b00: PotentialSpillM = 1'b0; // byte access
       2'b01: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:1] == '1; // half access
       2'b10: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:2] == '1; // word access
       2'b11: PotentialSpillM = IEUAdrM[OFFSET_BIT_POS-1:3] == '1; // double access
-      default: PotentialSpillM = 0;
+      default: PotentialSpillM = 1'b0;
     endcase
   end
   assign MisalignedM = (|MemRWM) & (AccessByteOffsetM != 0);
@@ -148,14 +150,13 @@ module align import cvw::*;  #(parameter cvw_t P) (
 
   // shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit)
   // 8 * is for shifting by bytes not bits
-  assign ShiftAmount = SelHPTW ? 0 : {AccessByteOffsetM, 3'b0}; // AND gate
+  assign ShiftAmount = SelHPTW ? '0 : {AccessByteOffsetM, 3'b0}; // AND gate
   assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> ShiftAmount;
   assign DCacheReadDataWordSpillM = ReadDataWordSpillShiftedM[P.LLEN-1:0];
 
-  // write path. Also has the 8:1 shifter muxing for the byteoffset
-  // then it also has the mux to select when a spill occurs
-  logic [P.LLEN*3-1:0] LSUWriteDataShiftedExtM;  // *** RT: Find a better way.  I've extending in both directions so we don't shift in zeros.  The cache expects the writedata to not have any zero data, but instead replicated data.
-
+  // write path. 
+  // 3*LLEN to 2*LLEN funnel shifter to perform left rotation.
+  // Vivado correctly optimizes as 2*LLEN log2(LLEN):1 muxes
   assign LSUWriteDataShiftedExtM = {LSUWriteDataM, LSUWriteDataM, LSUWriteDataM} << ShiftAmount;
   assign LSUWriteDataSpillM = LSUWriteDataShiftedExtM[P.LLEN*3-1:P.LLEN];
 
diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv
index a6ee53e73..bc8a29471 100644
--- a/src/lsu/amoalu.sv
+++ b/src/lsu/amoalu.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Performs AMO operations
 // 
-// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -73,7 +73,7 @@ module amoalu import cvw::*;  #(parameter cvw_t P) (
       5'b10100: y = cmp ? a : b; // amomax
       5'b11000: y = cmp ? a : b; // amominu
       5'b11100: y = cmp ? a : b; // amomaxu
-      default:  y = 'x;          // undefined; *** could change to b for efficiency
+      default:  y = 'x;          // undefined
     endcase
 
   // sign extend output if necessary for w64
diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv
index 7dbd0c8a2..e318260ab 100644
--- a/src/lsu/atomic.sv
+++ b/src/lsu/atomic.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Wrapper for amoalu and lrsc
 //
-// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -48,11 +48,20 @@ module atomic import cvw::*;  #(parameter cvw_t P) (
   logic [P.XLEN-1:0]          AMOResultM;
   logic                       MemReadM;
 
-  amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
-
-  mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
-  assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
-
-  lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
+  // AMO ALU
+  if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED) begin
+    amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);
+    mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
+  end else 
+    assign IMAWriteDataM = IHWriteDataM;
+  
+  // LRSC unit
+  if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) begin
+    assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
+    lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
+  end else begin
+    assign SquashSCW = 0;
+    assign LSURWM = PreLSURWM;
+  end
 
 endmodule  
diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv
index 1386db96f..f46bcbd20 100644
--- a/src/lsu/dtim.sv
+++ b/src/lsu/dtim.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: tightly integrated memory into the LSU.
 //
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -33,7 +33,6 @@ module dtim import cvw::*;  #(parameter cvw_t P) (
   input  logic                 FlushW,        
   input  logic                 ce,            // Chip Enable.  0: Holds ReadDataWordM
   input  logic [1:0]           MemRWM,        // Read/Write control
-  input  logic [1:0]           MemRWE,        // Read/Write control
   input  logic [P.PA_BITS-1:0] DTIMAdr,       // No stall: Execution stage memory address. Stall: Memory stage memory address
   input  logic [P.LLEN-1:0]    WriteDataM,    // Write data from IEU
   input  logic [P.LLEN/8-1:0]  ByteMaskM,     // Selects which bytes within a word to write
diff --git a/src/lsu/endianswap.sv b/src/lsu/endianswap.sv
index 7c042886a..3634e2322 100644
--- a/src/lsu/endianswap.sv
+++ b/src/lsu/endianswap.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Swap byte order for Big-Endian accesses
 // 
-// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv
index f7d1d4799..20d3cb8f6 100644
--- a/src/lsu/lrsc.sv
+++ b/src/lsu/lrsc.sv
@@ -8,7 +8,7 @@
 // Purpose: Load Reserved / Store Conditional unit
 //          Track the reservation and squash the store if it fails
 //
-// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -45,7 +45,6 @@ module lrsc import cvw::*;  #(parameter cvw_t P) (
   localparam RESERVATION_SET_SIZE_IN_BYTES = P.XLEN/8;
   localparam RESERVATION_SET_ADDRESS_BITS = $clog2(RESERVATION_SET_SIZE_IN_BYTES); // 2 for rv32, 3 for rv64
 
-  // possible bug: *** double check if PreLSURWM needs to be flushed by ignorerequest.
   // Handle atomic load reserved / store conditional
   logic [P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS]        ReservationPAdrW;
   logic                        ReservationValidM, ReservationValidW; 
@@ -58,9 +57,9 @@ module lrsc import cvw::*;  #(parameter cvw_t P) (
   assign SquashSCM = scM & ~WriteAdrMatchM;
   assign LSURWM = SquashSCM ? 2'b00 : PreLSURWM;
   always_comb begin // ReservationValidM (next value of valid reservation)
-    if (lrM) ReservationValidM = 1;  // set valid on load reserve
+    if (lrM) ReservationValidM = 1'b1;  // set valid on load reserve
   // if we implement multiple harts invalidate reservation if another hart stores to this reservation.
-    else if (scM) ReservationValidM = 0; // clear valid on store to same address or any sc
+    else if (scM) ReservationValidM = 1'b0; // clear valid on store to same address or any sc
     else ReservationValidM = ReservationValidW; // otherwise don't change valid
   end
   
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 9618e2cae..2209714ee 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -9,7 +9,7 @@
 //          HPTW, DMMU, data cache, interface to external bus
 //          Atomic, Endian swap, and subword read/write logic
 //  
-// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.2)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -33,52 +33,52 @@
 module lsu import cvw::*;  #(parameter cvw_t P) (
   input  logic                    clk, reset,
   input  logic                    StallM, FlushM, StallW, FlushW,
-  output logic                    LSUStallM,                            // LSU stalls pipeline during a multicycle operation
+  output logic                    LSUStallM,                             // LSU stalls pipeline during a multicycle operation
   // connected to cpu (controls)
-  input  logic [1:0]              MemRWE,                               // Read/Write control
-  input  logic [1:0]              MemRWM,                               // Read/Write control
-  input  logic [2:0]              Funct3M,                              // Size of memory operation
-  input  logic [6:0]              Funct7M,                              // Atomic memory operation function
-  input  logic [1:0]              AtomicM,                              // Atomic memory operation
-  input  logic                    FlushDCacheM,                         // Flush D cache to next level of memory
-  input  logic [3:0]              CMOpM,                                // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
-  input  logic                    LSUPrefetchM,                         // Prefetch; presently unused
-  output logic                    CommittedM,                           // Delay interrupts while memory operation in flight
-  output logic                    SquashSCW,                            // Store conditional failed disable write to GPR
-  output logic                    DCacheMiss,                           // D cache miss for performance counters
-  output logic                    DCacheAccess,                         // D cache memory access for performance counters
+  input  logic [1:0]              MemRWE,                                // Read/Write control
+  input  logic [1:0]              MemRWM,                                // Read/Write control
+  input  logic [2:0]              Funct3M,                               // Size of memory operation
+  input  logic [6:0]              Funct7M,                               // Atomic memory operation function
+  input  logic [1:0]              AtomicM,                               // Atomic memory operation
+  input  logic                    FlushDCacheM,                          // Flush D cache to next level of memory
+  input  logic [3:0]              CMOpM,                                 // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
+  input  logic                    LSUPrefetchM,                          // Prefetch; presently unused
+  output logic                    CommittedM,                            // Delay interrupts while memory operation in flight
+  output logic                    SquashSCW,                             // Store conditional failed disable write to GPR
+  output logic                    DCacheMiss,                            // D cache miss for performance counters
+  output logic                    DCacheAccess,                          // D cache memory access for performance counters
   // address and write data
-  input  logic [P.XLEN-1:0]       IEUAdrE,                              // Execution stage memory address
-  output logic [P.XLEN-1:0]       IEUAdrM,                              // Memory stage memory address
-  input  logic [P.XLEN-1:0]       WriteDataM,                           // Write data from IEU
-  output logic [P.LLEN-1:0]       ReadDataW,                            // Read data to IEU or FPU
+  input  logic [P.XLEN-1:0]       IEUAdrE,                               // Execution stage memory address
+  output logic [P.XLEN-1:0]       IEUAdrM,                               // Memory stage memory address
+  input  logic [P.XLEN-1:0]       WriteDataM,                            // Write data from IEU
+  output logic [P.LLEN-1:0]       ReadDataW,                             // Read data to IEU or FPU
   // cpu privilege
-  input  logic [1:0]              PrivilegeModeW,                       // Current privilege mode
-  input  logic                    BigEndianM,                           // Swap byte order to big endian
-  input  logic                    sfencevmaM,                           // Virtual memory address fence, invalidate TLB entries
-  output logic                    DCacheStallM,                         // D$ busy with multicycle operation
+  input  logic [1:0]              PrivilegeModeW,                        // Current privilege mode
+  input  logic                    BigEndianM,                            // Swap byte order to big endian
+  input  logic                    sfencevmaM,                            // Virtual memory address fence, invalidate TLB entries
+  output logic                    DCacheStallM,                          // D$ busy with multicycle operation
   // fpu
-  input  logic [P.FLEN-1:0]       FWriteDataM,                          // Write data from FPU
-  input  logic                    FpLoadStoreM,                         // Selects FPU as store for write data
+  input  logic [P.FLEN-1:0]       FWriteDataM,                           // Write data from FPU
+  input  logic                    FpLoadStoreM,                          // Selects FPU as store for write data
   // faults
-  output logic                    LoadPageFaultM, StoreAmoPageFaultM,   // Page fault exceptions
-  output logic                    LoadMisalignedFaultM,                 // Load address misaligned fault
-  output logic                    LoadAccessFaultM,                     // Load access fault (PMA)
-  output logic                    HPTWInstrAccessFaultF,                // HPTW generated access fault during instruction fetch
-  output logic                    HPTWInstrPageFaultF,                  // HPTW generated access fault during instruction fetch
+  output logic                    LoadPageFaultM, StoreAmoPageFaultM,    // Page fault exceptions
+  output logic                    LoadMisalignedFaultM,                  // Load address misaligned fault
+  output logic                    LoadAccessFaultM,                      // Load access fault (PMA)
+  output logic                    HPTWInstrAccessFaultF,                 // HPTW generated access fault during instruction fetch
+  output logic                    HPTWInstrPageFaultF,                   // HPTW generated access fault during instruction fetch
   // cpu hazard unit (trap)
-  output logic                    StoreAmoMisalignedFaultM,             // Store or AMO address misaligned fault
-  output logic                    StoreAmoAccessFaultM,                 // Store or AMO access fault
+  output logic                    StoreAmoMisalignedFaultM,              // Store or AMO address misaligned fault
+  output logic                    StoreAmoAccessFaultM,                  // Store or AMO access fault
   // connect to ahb
-  output logic [P.PA_BITS-1:0]    LSUHADDR,                             // Bus address from LSU to EBU
-  input  logic [P.XLEN-1:0]       HRDATA,                               // Bus read data from LSU to EBU
-  output logic [P.XLEN-1:0]       LSUHWDATA,                            // Bus write data from LSU to EBU
-  input  logic                    LSUHREADY,                            // Bus ready from LSU to EBU
-  output logic                    LSUHWRITE,                            // Bus write operation from LSU to EBU
-  output logic [2:0]              LSUHSIZE,                             // Bus operation size from LSU to EBU
-  output logic [2:0]              LSUHBURST,                            // Bus burst from LSU to EBU
-  output logic [1:0]              LSUHTRANS,                            // Bus transaction type from LSU to EBU
-  output logic [P.XLEN/8-1:0]     LSUHWSTRB,                            // Bus byte write enables from LSU to EBU
+  output logic [P.PA_BITS-1:0]    LSUHADDR,                              // Bus address from LSU to EBU
+  input  logic [P.XLEN-1:0]       HRDATA,                                // Bus read data from LSU to EBU
+  output logic [P.XLEN-1:0]       LSUHWDATA,                             // Bus write data from LSU to EBU
+  input  logic                    LSUHREADY,                             // Bus ready from LSU to EBU
+  output logic                    LSUHWRITE,                             // Bus write operation from LSU to EBU
+  output logic [2:0]              LSUHSIZE,                              // Bus operation size from LSU to EBU
+  output logic [2:0]              LSUHBURST,                             // Bus burst from LSU to EBU
+  output logic [1:0]              LSUHTRANS,                             // Bus transaction type from LSU to EBU
+  output logic [P.XLEN/8-1:0]     LSUHWSTRB,                             // Bus byte write enables from LSU to EBU
   // page table walker
   input  logic [P.XLEN-1:0]       SATP_REGW,                            // SATP (supervisor address translation and protection) CSR
   input  logic                    STATUS_MXR, STATUS_SUM, STATUS_MPRV,  // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
@@ -86,17 +86,21 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   input  logic                    ENVCFG_PBMTE,                         // Page-based memory types enabled
   input  logic                    ENVCFG_ADUE,                          // HPTW A/D Update enable
   input  logic [P.XLEN-1:0]       PCSpillF,                             // Fetch PC 
-  input  logic                    ITLBMissF,                            // ITLB miss causes HPTW (hardware pagetable walker) walk
-  input  logic                    InstrUpdateDAF,                       // ITLB hit needs to update dirty or access bits
+  input  logic                    ITLBMissOrUpdateAF,                   // ITLB miss causes HPTW (hardware pagetable walker) walk or update access bit
   output logic [P.XLEN-1:0]       PTE,                                  // Page table entry write to ITLB
   output logic [1:0]              PageType,                             // Type of page table entry to write to ITLB
   output logic                    ITLBWriteF,                           // Write PTE to ITLB
   output logic                    SelHPTW,                              // During a HPTW walk the effective privilege mode becomes S_MODE
   input var logic [7:0]           PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit
-  input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0] // PMP address from privileged unit
+  input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0],// PMP address from privileged unit
+  // Debug scan chain
+  input  logic                    DebugCapture,
+  input  logic                    DebugScanEn,
+  input  logic                    DebugScanIn,
+  output logic                    DebugScanOut
 );
   localparam logic MISALIGN_SUPPORT = P.ZICCLSM_SUPPORTED & P.DCACHE_SUPPORTED;
-  localparam MLEN = MISALIGN_SUPPORT ? 2*P.LLEN : P.LLEN; // widen buffer for misaligned accessess
+  localparam MLEN = MISALIGN_SUPPORT ? 2*P.LLEN : P.LLEN;        // widen buffer for misaligned accessess
 
   logic [P.XLEN+1:0]     IEUAdrExtM;                             // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
   logic [P.XLEN+1:0]     IEUAdrExtE;                             // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
@@ -131,7 +135,6 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   logic [P.LLEN-1:0]     DCacheReadDataWordSpillM;               // D$ read data
   logic [P.LLEN-1:0]     ReadDataWordMuxM;                       // DTIM or D$ read data
   logic [P.LLEN-1:0]     LittleEndianReadDataWordM;              // Endian-swapped read data
-  logic [P.LLEN-1:0]     ReadDataWordM;                          // Read data before subword selection
   logic [P.LLEN-1:0]     ReadDataM;                              // Final read data
 
   logic [P.XLEN-1:0]     IHWriteDataM;                           // IEU or HPTW write data
@@ -146,7 +149,6 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   
   logic                  DTLBMissM;                              // DTLB miss causes HPTW walk
   logic                  DTLBWriteM;                             // Writes PTE and PageType to DTLB
-  logic                  DataUpdateDAM;                          // DTLB hit needs to update dirty or access bits
   logic                  LSULoadAccessFaultM;                    // Load acces fault
   logic                  LSUStoreAmoAccessFaultM;                // Store access fault
   logic                  IgnoreRequestTLB;                       // On either ITLB or DTLB miss, ignore miss so HPTW can handle
@@ -154,13 +156,23 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   logic                  SelDTIM;                                // Select DTIM rather than bus or D$
   logic [P.XLEN-1:0]     WriteDataZM;
   logic                  LSULoadPageFaultM, LSUStoreAmoPageFaultM;
+  logic 		             DTLBMissOrUpdateDAM;
+
+  logic                  DSCR;                                   // Debug Scan Chain Register (DSCR)
   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Pipeline for IEUAdr E to M
   // Zero-extend address to 34 bits for XLEN=32
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
+  if (P.DEBUG_SUPPORTED) begin
+    flopenrcs #(P.XLEN) AddressMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(IEUAdrE), .q(IEUAdrM),
+      .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DSCR));
+  end else begin
+    flopenrc #(P.XLEN) AddressMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(IEUAdrE), .q(IEUAdrM));
+    assign DSCR = DebugScanIn;
+  end
+
   if(MISALIGN_SUPPORT) begin : ziccslm_align
     logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
     align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, .FpLoadStoreM, 
@@ -173,12 +185,12 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   end else begin : no_ziccslm_align
     assign IEUAdrExtM = {2'b00, IEUAdrM}; 
     assign IEUAdrExtE = {2'b00, IEUAdrE};
-    assign SelSpillE = 0;
+    assign SelSpillE = 1'b0;
     assign DCacheReadDataWordSpillM = DCacheReadDataWordM;
     assign ByteMaskSpillM = ByteMaskM;
     assign LSUWriteDataSpillM = LSUWriteDataM;
     assign MemRWSpillM = MemRWM;
-    assign {SpillStallM} = 0;
+    assign {SpillStallM} = 1'b0;
   end
 
     if(P.ZICBOZ_SUPPORTED) begin : cboz
@@ -193,14 +205,14 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   /////////////////////////////////////////////////////////////////////////////////////////////
 
   if(P.VIRTMEM_SUPPORTED) begin : hptw
-    hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
-      .DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM,
+    hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrUpdateAF, .ITLBWriteF,
+      .DTLBMissOrUpdateDAM, .DTLBWriteM,
       .FlushW, .DCacheBusStallM, .SATP_REGW, .PCSpillF,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_ADUE, .PrivilegeModeW,
       .ReadDataM(ReadDataM[P.XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
       .WriteDataM(WriteDataZM), .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
       .IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
-      .IHAdrM, .HPTWStall, .SelHPTW,
+      .IHAdrM, .HPTWStall, .SelHPTW, 
       .IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM, 
       .LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultF,
       .LoadPageFaultM, .StoreAmoPageFaultM, .LSULoadPageFaultM, .LSUStoreAmoPageFaultM, .HPTWInstrPageFaultF
@@ -216,8 +228,8 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM;
     assign LoadPageFaultM = LSULoadPageFaultM;
     assign StoreAmoPageFaultM = LSUStoreAmoPageFaultM;
-    assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = 0;
-    assign {HPTWInstrAccessFaultF, HPTWInstrPageFaultF} = 0;
+    assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;
+    assign {HPTWInstrAccessFaultF, HPTWInstrPageFaultF} = '0;
    end
 
   // CommittedM indicates the cache, bus, or HPTW are busy with a multiple cycle operation.
@@ -236,25 +248,29 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   if(P.ZICSR_SUPPORTED == 1) begin : dmmu
     logic DisableTranslation;                             // During HPTW walk or D$ flush disable virtual memory address translation
     logic WriteAccessM;
+    logic DataUpdateDAM;                                  // DTLB hit needs to update dirty or access bits
+
     assign DisableTranslation = SelHPTW | FlushDCacheM;
     assign WriteAccessM = PreLSURWM[0];
     mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0))
     dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
       .PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]),
       .PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(sfencevmaM),
-      .PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM), 
+      .PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM), .SelProgBuf(),
       .InstrAccessFaultF(), .LoadAccessFaultM(LSULoadAccessFaultM), 
       .StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM), .InstrPageFaultF(), .LoadPageFaultM(LSULoadPageFaultM), 
-    .StoreAmoPageFaultM(LSUStoreAmoPageFaultM),
-      .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,   // *** these faults need to be supressed during hptw.
+      .StoreAmoPageFaultM(LSUStoreAmoPageFaultM),
+      .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
       .UpdateDA(DataUpdateDAM), .CMOpM(CMOpM),
       .AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0), 
       .WriteAccessM, .ReadAccessM(PreLSURWM[1]),
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
 
+    assign DTLBMissOrUpdateDAM = DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM);  
   end else begin  // No MMU, so no PMA/page faults and no address translation
-    assign {DTLBMissM, LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = 0;
-    assign {LSULoadPageFaultM, LSUStoreAmoPageFaultM} = 0;
+    assign DTLBMissOrUpdateDAM = '0;
+    assign {DTLBMissM, LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0;
+    assign {LSULoadPageFaultM, LSUStoreAmoPageFaultM} = '0;
     assign PAdrM = IHAdrM[P.PA_BITS-1:0];
     assign CacheableM = 1'b1;
     assign SelDTIM = P.DTIM_SUPPORTED & ~P.BUS_SUPPORTED; // if no PMA then select dtim if there is a DTIM.  If there is 
@@ -280,14 +296,12 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     // The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
     mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], MemRWM[0], DTIMAdr);
     assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : 0;
-    // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
-    // **** create config to support DTIM with floating point.
-    // Add support for cboz
-    dtim #(P) dtim(.clk, .reset, .ce(~GatedStallW), .MemRWE(MemRWE), // *** update when you update the cache RWE
+    dtim #(P) dtim(.clk, .reset, .ce(~GatedStallW),
               .MemRWM(DTIMMemRWM),
               .DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM), 
               .ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM));
-  end
+  end else
+    assign DTIMReadDataWordM = '0;
   if (P.BUS_SUPPORTED) begin : bus              
     if(P.DCACHE_SUPPORTED) begin : dcache
       localparam   LLENWORDSPERLINE = P.DCACHE_LINELENINBITS/P.LLEN;             // Number of LLEN words in cacheline
@@ -316,25 +330,25 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
 
       if(P.ZICBOZ_SUPPORTED) begin 
         assign BusCMOZero = CMOpM[3] & ~CacheableM;
-        assign CacheCMOpM = (CacheableM & ~SelHPTW) ? CMOpM : 0;
+        assign CacheCMOpM = (CacheableM & ~SelHPTW) ? CMOpM : '0;
         assign BusAtomic = AtomicM[1] & ~CacheableM;
       end else begin
-        assign BusCMOZero = 0;
-        assign CacheCMOpM = 0;
-        assign BusAtomic = 0;
+        assign BusCMOZero = 1'b0;
+        assign CacheCMOpM = '0;
+        assign BusAtomic = 1'b0;
       end
-      assign BusRW = (~CacheableM & ~SelDTIM )? LSURWM : 0;
+      assign BusRW = (~CacheableM & ~SelDTIM )? LSURWM : '0;
       assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
-      assign CacheRWM = (CacheableM & ~SelDTIM) ? LSURWM : 0;
+      assign CacheRWM = (CacheableM & ~SelDTIM) ? LSURWM : '0;
       assign FlushDCache = FlushDCacheM & ~(SelHPTW);
       
-      cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
+      cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
               .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
         .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(FlushW | IgnoreRequestTLB),
         .CacheRW(CacheRWM), 
         .FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM), 
         .ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
-        .CacheWriteData(LSUWriteDataSpillM), .SelHPTW,
+        .WriteData(LSUWriteDataSpillM), .SelHPTW,
         .CacheStall, .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
         .CacheCommitted(DCacheCommittedM), 
         .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), 
@@ -354,11 +368,6 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
         .Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW),
         .BusStall, .BusCommitted(BusCommittedM));
 
-
-    // Mux between the 3 sources of read data, 0: cache, 1: Bus, 2: DTIM
-    // Uncache bus access may be smaller width than LLEN.  Duplicate LLENPOVERAHBW times.
-      // *** DTIMReadDataWordM should be increased to LLEN.
-      // pma should generate exception for LLEN read to periph.
       mux3 #(P.LLEN) UnCachedDataMux(.d0(DCacheReadDataWordSpillM), .d1({LLENPOVERAHBW{FetchBuffer[P.XLEN-1:0]}}),
                                     .d2({{P.LLEN-P.XLEN{1'b0}}, DTIMReadDataWordM[P.XLEN-1:0]}),
                                     .s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM));
@@ -377,16 +386,17 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
 
     // Mux between the 2 sources of read data, 0: Bus, 1: DTIM
       if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]);
-      else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0]; // *** bus only does not support double wide floats.
+      else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0];
       assign LSUHBURST = 3'b0;
-      assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = 0;
- end
+      assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess, DCacheReadDataWordM} = '0;
+    end
   end else begin: nobus // block: bus, only DTIM
-    assign LSUHWDATA = 0; 
+    assign {LSUHWDATA, LSUHADDR, LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHWSTRB} = '0; 
+    assign DCacheReadDataWordM = '0;
     assign ReadDataWordMuxM = DTIMReadDataWordM;
-    assign {BusStall, BusCommittedM} = 0;   
-    assign {DCacheMiss, DCacheAccess} = 0;
-    assign {DCacheStallM, DCacheCommittedM} = 0;
+    assign {BusStall, BusCommittedM} = '0;   
+    assign {DCacheMiss, DCacheAccess} = '0;
+    assign {DCacheStallM, DCacheCommittedM} = '0;
   end
 
   assign LSUBusStallM = BusStall & ~IgnoreRequestTLB;
@@ -395,12 +405,14 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   // Atomic operations
   /////////////////////////////////////////////////////////////////////////////////////////////
  
-  if (P.A_SUPPORTED) begin:atomic
+  if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic
     atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM, 
       .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, 
       .IMAWriteDataM, .SquashSCW, .LSURWM);
   end else begin:lrsc
-    assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign IMAWriteDataM = IHWriteDataM;
+    assign SquashSCW = 1'b0; 
+    assign LSURWM = PreLSURWM; 
+    assign IMAWriteDataM = IHWriteDataM;
   end
 
   if (P.F_SUPPORTED) 
@@ -419,6 +431,14 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
   subwordwrite #(P.LLEN) subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
 
+  // Capture ReadDataM
+  if (P.DEBUG_SUPPORTED) begin
+    flopenrs #(P.LLEN) ReadDataMScan (.clk, .reset, .en(DebugCapture), .d(ReadDataM), .q(),
+      .scan(DebugScanEn), .scanin(DSCR), .scanout(DebugScanOut));
+  end else begin
+    assign DebugScanOut = DSCR;
+  end
+
   // Compute byte masks
   swbytemask #(P.LLEN, P.ZICCLSM_SUPPORTED) swbytemask(.Size(LSUFunct3M), .Adr(PAdrM[$clog2(P.LLEN/8)-1:0]), .ByteMask(ByteMaskM), .ByteMaskExtended(ByteMaskExtendedM));
 
diff --git a/src/lsu/subwordread.sv b/src/lsu/subwordread.sv
index a5ccd12bf..40e3c11c6 100644
--- a/src/lsu/subwordread.sv
+++ b/src/lsu/subwordread.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Extract subwords and sign extend for reads
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -52,6 +52,7 @@ module subwordread import cvw::*;  #(parameter cvw_t P) (
   // Use indexed part select to imply muxes to select each size of subword
   if (P.LLEN == 128) mux2 #(64) dblmux(ReadDataWordMuxM[63:0], ReadDataWordMuxM[127:64], PAdrSwapM[3], DblWordM);
   else if (P.LLEN == 64) assign DblWordM = ReadDataWordMuxM;
+  else assign DblWordM = '0; // unused for RV32F
   if (P.LLEN >= 64) mux2 #(32) wordmux(DblWordM[31:0], DblWordM[63:32], PAdrSwapM[2], WordM);
   else assign WordM = ReadDataWordMuxM;
   mux2 #(16) halfwordmux(WordM[15:0], WordM[31:16], PAdrSwapM[1], HalfwordM);
diff --git a/src/lsu/subwordwrite.sv b/src/lsu/subwordwrite.sv
index 659d6d9c7..4ae097cc3 100644
--- a/src/lsu/subwordwrite.sv
+++ b/src/lsu/subwordwrite.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Masking and muxing for subword writes
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -35,6 +35,7 @@ module subwordwrite #(parameter LLEN) (
 );
 
   // Replicate data for subword writes
+
   if (LLEN == 128) begin:sww
     always_comb 
       case(LSUFunct3M[2:0])
diff --git a/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv
index d8db91cbc..cbe4070cc 100644
--- a/src/lsu/swbytemask.sv
+++ b/src/lsu/swbytemask.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: On-chip RAM, external to core
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -34,6 +34,7 @@ module swbytemask #(parameter WORDLEN, EXTEND = 0)(
   output logic [WORDLEN/8-1:0]         ByteMask,
   output logic [WORDLEN/8-1:0]         ByteMaskExtended
 );
+
   if(EXTEND) begin
     logic [WORDLEN*2/8-1:0]              ExtendedByteMask;
     // 'd2 means 2, but stops Design Compiler from complaining about signed to unsigned conversion    
@@ -42,7 +43,7 @@ module swbytemask #(parameter WORDLEN, EXTEND = 0)(
     assign ByteMaskExtended = ExtendedByteMask[WORDLEN*2/8-1:WORDLEN/8];
   end else begin    
     assign ByteMask = (('d2**('d2**Size))-'d1) << Adr;
-    assign ByteMaskExtended = 0;
+    assign ByteMaskExtended = '0;
   end
 
 /* Equivalent to the following
@@ -50,7 +51,7 @@ module swbytemask #(parameter WORDLEN, EXTEND = 0)(
   if(WORDLEN == 64) begin
     always_comb begin
       case(Size[1:0])
-        2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1; end // sb
+        2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1'b1; end // sb
         2'b01: case (Adr[2:1])
                   2'b00: ByteMask = 8'b0000_0011;
                   2'b01: ByteMask = 8'b0000_1100;
@@ -65,7 +66,7 @@ module swbytemask #(parameter WORDLEN, EXTEND = 0)(
   end else begin
     always_comb begin
       case(Size[1:0])
-        2'b00: begin ByteMask = 4'b0000; ByteMask[Adr[1:0]] = 1; end // sb
+        2'b00: begin ByteMask = 4'b0000; ByteMask[Adr[1:0]] = 1'b1; end // sb
         2'b01: if (Adr[1]) ByteMask = 4'b1100;
                else        ByteMask = 4'b0011;
         2'b10: ByteMask = 4'b1111;
diff --git a/src/mdu/div.sv b/src/mdu/div.sv
index 2ae35d8f4..66fe5d9d4 100644
--- a/src/mdu/div.sv
+++ b/src/mdu/div.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Restoring integer division using a shift register and subtractor
 // 
-// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/mdu/divstep.sv b/src/mdu/divstep.sv
index f478ad86f..d47742fa9 100644
--- a/src/mdu/divstep.sv
+++ b/src/mdu/divstep.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Radix-2 restoring integer division step.  k steps are used in div
 // 
-// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv
index 886eaf2b3..b2f0f7514 100644
--- a/src/mdu/mdu.sv
+++ b/src/mdu/mdu.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: M extension multiply and divide
 // 
-// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.21)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -45,12 +45,6 @@ module mdu import cvw::*;  #(parameter cvw_t P) (
   logic [P.XLEN-1:0]        MDUResultM;                     // result after W truncation
   logic                     W64M;                           // W-type instruction
 
-  logic [P.XLEN-1:0]        AMDU, BMDU;                     // Gated inputs to MDU
-
-  // gate data inputs to MDU to only operate when MDU is active.
-  assign AMDU = ForwardedSrcAE & {P.XLEN{MDUActiveE}};
-  assign BMDU = ForwardedSrcBE & {P.XLEN{MDUActiveE}};
-
   // Multiplier
   mul #(P.XLEN) mul(.clk, .reset, .StallM, .FlushM, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .ProdM);
 
@@ -58,10 +52,10 @@ module mdu import cvw::*;  #(parameter cvw_t P) (
   // Start a divide when a new division instruction is received and the divider isn't already busy or finishing
   // When IDIV_ON_FPU is set, use the FPU divider instead
   // In ZMMUL, with M_SUPPORTED = 0, omit the divider
-  if ((P.IDIV_ON_FPU & P.F_SUPPORTED) || (!P.M_SUPPORTED)) begin:nodiv  
-    assign QuotM = 0;
-    assign RemM = 0;
-    assign DivBusyE = 0;
+  if ((P.IDIV_ON_FPU & P.F_SUPPORTED) | (!P.M_SUPPORTED)) begin:nodiv  
+    assign QuotM = '0;
+    assign RemM = '0;
+    assign DivBusyE = 1'b0;
   end else begin:div
     div #(P) div(.clk, .reset, .StallM, .FlushE, .DivSignedE(~Funct3E[0]), .W64E, .IntDivE, 
         .ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM);
diff --git a/src/mdu/mul.sv b/src/mdu/mul.sv
index 65eaefd82..7c3f13a85 100644
--- a/src/mdu/mul.sv
+++ b/src/mdu/mul.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Integer multiplication
 // 
-// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.18)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/mmu/adrdec.sv b/src/mmu/adrdec.sv
index bf092dbc6..f4de5a7b7 100644
--- a/src/mmu/adrdec.sv
+++ b/src/mmu/adrdec.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Address decoder
 // 
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv
index d71fef82a..953071cce 100644
--- a/src/mmu/adrdecs.sv
+++ b/src/mmu/adrdecs.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: All the address decoders for peripherals
 // 
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -33,7 +33,7 @@ module adrdecs import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.PA_BITS-1:0] PhysicalAddress,
   input  logic                 AccessRW, AccessRX, AccessRWXC,
   input  logic [1:0]           Size,
-  output logic [11:0]          SelRegions
+  output logic [14:0]          SelRegions
 );
 
   localparam logic [3:0]       SUPPORTED_SIZE = (P.LLEN == 32 ? 4'b0111 : 4'b1111);
@@ -49,8 +49,11 @@ module adrdecs import cvw::*;  #(parameter cvw_t P) (
   adrdec #(P.PA_BITS) plicdec(PhysicalAddress, P.PLIC_BASE[P.PA_BITS-1:0], P.PLIC_RANGE[P.PA_BITS-1:0], P.PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[9]);
   adrdec #(P.PA_BITS) sdcdec(PhysicalAddress, P.SDC_BASE[P.PA_BITS-1:0], P.SDC_RANGE[P.PA_BITS-1:0], P.SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[10]); 
   adrdec #(P.PA_BITS) spidec(PhysicalAddress, P.SPI_BASE[P.PA_BITS-1:0], P.SPI_RANGE[P.PA_BITS-1:0], P.SPI_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[11]);
+  adrdec #(P.PA_BITS) bsgdmcconfdec(PhysicalAddress, P.BSG_DMC_CONF_BASE[P.PA_BITS-1:0], P.BSG_DMC_CONF_RANGE[P.PA_BITS-1:0], P.BSG_DMC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[12]);
+  adrdec #(P.PA_BITS) pllconfdec(PhysicalAddress, P.PLL_CONF_BASE[P.PA_BITS-1:0], P.PLL_CONF_RANGE[P.PA_BITS-1:0], P.PLL_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[13]);
+  adrdec #(P.PA_BITS) progbufdec(PhysicalAddress, P.PROGBUF_BASE[P.PA_BITS-1:0], P.PROGBUF_RANGE[P.PA_BITS-1:0], P.DEBUG_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[14]);
 
-  assign SelRegions[0] = ~|(SelRegions[11:1]); // none of the regions are selected
+  assign SelRegions[0] = ~|(SelRegions[14:1]); // none of the regions are selected
 endmodule
 
   // verilator lint_on UNOPTFLAT 
diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv
index 77e73e696..da56a21a0 100644
--- a/src/mmu/hptw.sv
+++ b/src/mmu/hptw.sv
@@ -10,7 +10,7 @@
 //
 // Purpose: Hardware Page Table Walker
 //
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -46,11 +46,9 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
   input  logic              DCacheBusStallM,           // stall from LSU
   input  logic [2:0]        Funct3M,
   input  logic [6:0]        Funct7M,
-  input  logic              ITLBMissF,
-  input  logic              DTLBMissM,
+  input  logic              ITLBMissOrUpdateAF,
+  input  logic              DTLBMissOrUpdateDAM,
   input  logic              FlushW,
-  input  logic              InstrUpdateDAF,
-  input  logic              DataUpdateDAM,
   output logic [P.XLEN-1:0] PTE,                    // page table entry to TLBs
   output logic [1:0]        PageType,               // page type to TLBs
   output logic              ITLBWriteF, DTLBWriteM, // write TLB with new entry
@@ -83,7 +81,7 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
   logic                     Misaligned, MegapageMisaligned;
   logic                     ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE;
   logic                     StartWalk;
-  logic                     TLBMiss;
+  logic                     TLBMissOrUpdateDA;
   logic                     PRegEn;
   logic [1:0]               NextPageType;
   logic [P.SVMODE_BITS-1:0] SvMode;
@@ -94,7 +92,6 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
   logic [P.PA_BITS-1:0]     HPTWReadAdr;
   logic                     SelHPTWAdr;
   logic [P.XLEN+1:0]        HPTWAdrExt;
-  logic                     DTLBMissOrUpdateDAM;
   logic                     LSUAccessFaultM;
   logic [P.PA_BITS-1:0]     HPTWAdr;
   logic [1:0]               HPTWRW;
@@ -105,8 +102,7 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
   logic                     HPTWLoadPageFault, HPTWStoreAmoPageFault, HPTWInstrPageFault;
   logic                     HPTWLoadPageFaultDelay, HPTWStoreAmoPageFaultDelay, HPTWInstrPageFaultDelay;
   logic                     HPTWAccessFaultDelay;
-  logic                     TakeHPTWFault, TakeHPTWFaultDelay;
-  logic [P.XLEN-1:0]        ReadDataNoXM;
+  logic                     TakeHPTWFault;
   logic                     PBMTFaultM;
   logic                     HPTWFaultM;
   
@@ -120,9 +116,9 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
   assign HPTWStoreAmoPageFault   = PBMTFaultM & DTLBWalk & MemRWM[0];   
   assign HPTWInstrPageFault      = PBMTFaultM & ~DTLBWalk;
 
-  flopr #(7) HPTWAccesFaultReg(clk, reset, {TakeHPTWFault, HPTWLoadAccessFault, HPTWStoreAmoAccessFault, HPTWInstrAccessFault, 
+  flopr #(6) HPTWAccesFaultReg(clk, reset, {HPTWLoadAccessFault, HPTWStoreAmoAccessFault, HPTWInstrAccessFault, 
                                             HPTWLoadPageFault, HPTWStoreAmoPageFault, HPTWInstrPageFault},
-                               {TakeHPTWFaultDelay, HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay,
+                               {HPTWLoadAccessFaultDelay, HPTWStoreAmoAccessFaultDelay, HPTWInstrAccessFaultDelay,
                                 HPTWLoadPageFaultDelay, HPTWStoreAmoPageFaultDelay, HPTWInstrPageFaultDelay});
 
   assign TakeHPTWFault = WalkerState != IDLE;
@@ -138,7 +134,7 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
   // Extract bits from CSRs and inputs
   assign SvMode = SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS];
   assign BasePageTablePPN = SATP_REGW[P.PPN_BITS-1:0];
-  assign TLBMiss = (DTLBMissOrUpdateDAM | ITLBMissF);
+  assign TLBMissOrUpdateDA = DTLBMissOrUpdateDAM | ITLBMissOrUpdateAF;
 
   // Determine which address to translate
   mux2 #(P.XLEN) vadrmux(PCSpillF, IEUAdrExtM[P.XLEN-1:0], DTLBWalk, TranslationVAdr);
@@ -173,9 +169,7 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
     logic [P.XLEN-1:0]    AccessedPTE;
 
     assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit
-    //assign ReadDataNoXM = (ReadDataM[0] === 'x) ? 0 : ReadDataM; // If the PTE.V bit is x because it was read from uninitialized memory set to 0 to avoid x propagation and hanging the simulation.
-    assign ReadDataNoXM = ReadDataM; // *** temporary fix for synthesis; === and x in line above are not synthesizable.
-    mux2 #(P.XLEN) NextPTEMux(ReadDataNoXM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataNoXM when ADUE = 0 because UpdatePTE = 0
+    mux2 #(P.XLEN) NextPTEMux(ReadDataM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataM when ADUE = 0 because UpdatePTE = 0
     flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);
     
     assign SaveHPTWAdr = WalkerState == L0_ADR;
@@ -211,15 +205,15 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
     assign UpdatePTE = (WalkerState == LEAF) & HPTWUpdateDA;  // UpdatePTE will always be 0 if ADUE = 0 because HPTWUpdateDA will be 0
 
   end else begin // block: hptwwrites
-    assign NextPTE = ReadDataNoXM;
+    assign NextPTE = ReadDataM;
     assign HPTWAdr = HPTWReadAdr;
-    assign HPTWUpdateDA = 0;
-    assign UpdatePTE = 0;
-    assign HPTWRW[0] = 0;
+    assign HPTWUpdateDA = 1'b0;
+    assign UpdatePTE = 1'b0;
+    assign HPTWRW[0] = 1'b0;
   end
 
   // Enable and select signals based on states
-  assign StartWalk  = (WalkerState == IDLE) & TLBMiss; 
+  assign StartWalk  = (WalkerState == IDLE) & TLBMissOrUpdateDA; 
   assign HPTWRW[1]  = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
   assign DTLBWriteM = (WalkerState == LEAF & ~HPTWUpdateDA) & DTLBWalk;
   assign ITLBWriteF = (WalkerState == LEAF & ~HPTWUpdateDA) & ~DTLBWalk;
@@ -267,86 +261,65 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
   end else begin
     logic  GigapageMisaligned, TerapageMisaligned;
     assign InitialWalkerState = (SvMode == P.SV48) ? L3_ADR : L2_ADR;
-    assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0
-    assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0
-    assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0      
+    assign TerapageMisaligned = |(CurrentPPN[26:0]); // Must have zero PPN2, PPN1, PPN0
+    assign GigapageMisaligned = |(CurrentPPN[17:0]); // Must have zero PPN1 and PPN0
+    assign MegapageMisaligned = |(CurrentPPN[8:0]);  // Must have zero PPN0      
     assign Misaligned = ((WalkerState == L2_ADR) & TerapageMisaligned) | ((WalkerState == L1_ADR) & GigapageMisaligned) | ((WalkerState == L0_ADR) & MegapageMisaligned);
   end
 
   // Page Table Walker FSM
-  // *** there is a bug here (RT).  Each memory access needs to be potentially flushed if the PMA/P checkers
-  // generate an access fault.  Specially the store on UDPATE_PTE needs to check for access violation.
-  // I think the solution is to do 1 of the following
-  // 1. Allow the HPTW to generate exceptions and stop walking immediately.
-  // 2. If the store would generate an exception don't store to dcache but still write the TLB.  When we go back
-  // to LEAF then the PMA/P.  Wait this does not work.  The PMA/P won't be looking a the address in the table, but
-  // rather than physical address of the translated instruction/data.  So we must generate the exception.
-  // *** DH 1/1/24 another bug: when the NAPOT bits (PTE[62:61]) are nonzero on a nonleaf PTE, the walker should make a page fault (Issue 546)
   flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); 
   always_comb 
     case (WalkerState)
-      IDLE:       if (TLBMiss)                                        NextWalkerState = InitialWalkerState;                      
+      IDLE:       if (TLBMissOrUpdateDA)                              NextWalkerState = InitialWalkerState;                      
                   else                                                NextWalkerState = IDLE;
-      L3_ADR:                                                         NextWalkerState = L3_RD; // first access in SV48
+      L3_ADR:                                                         NextWalkerState = L3_RD; // First access in SV48
       L3_RD:      if (DCacheBusStallM)                                NextWalkerState = L3_RD;
-                  else if(HPTWFaultM)                                 NextWalkerState = FAULT;
+                  else if (HPTWFaultM)                                NextWalkerState = FAULT;
                   else                                                NextWalkerState = L2_ADR;
-      L2_ADR:     if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // first access in SV39
+      L2_ADR:     if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // First access in SV39
                   else                                                NextWalkerState = LEAF;
       L2_RD:      if (DCacheBusStallM)                                NextWalkerState = L2_RD;
-                  else if(HPTWFaultM)                                 NextWalkerState = FAULT;
+                  else if (HPTWFaultM)                                NextWalkerState = FAULT;
                   else                                                NextWalkerState = L1_ADR;
-      L1_ADR:     if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32                 
+      L1_ADR:     if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // First access in SV32                 
                   else                                                NextWalkerState = LEAF;  
       L1_RD:      if (DCacheBusStallM)                                NextWalkerState = L1_RD;
-                  else if(HPTWFaultM)                                 NextWalkerState = FAULT;
+                  else if (HPTWFaultM)                                NextWalkerState = FAULT;
                   else                                                NextWalkerState = L0_ADR;
       L0_ADR:     if (ValidNonLeafPTE)                                NextWalkerState = L0_RD;
                   else                                                NextWalkerState = LEAF;
       L0_RD:      if (DCacheBusStallM)                                NextWalkerState = L0_RD;
-                  else if(HPTWFaultM)                                 NextWalkerState = FAULT;
+                  else if (HPTWFaultM)                                NextWalkerState = FAULT;
                   else                                                NextWalkerState = LEAF;
       LEAF:       if (P.SVADU_SUPPORTED & HPTWUpdateDA)               NextWalkerState = UPDATE_PTE;
                   else                                                NextWalkerState = IDLE;
-      UPDATE_PTE: if(DCacheBusStallM)                                 NextWalkerState = UPDATE_PTE;
+      UPDATE_PTE: if (DCacheBusStallM)                                NextWalkerState = UPDATE_PTE;
                   else                                                NextWalkerState = LEAF;
       FAULT:                                                          NextWalkerState = IDLE;
-      default:                                                        NextWalkerState = IDLE; // should never be reached
+      default:                                                        NextWalkerState = IDLE; // Should never be reached
     endcase // case (WalkerState)
 
-  assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMiss) | (HPTWFaultM); // RT : 05 April 2023 if hptw request has pmp/a fault suppress bus access.
+  assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | (HPTWFaultM); // If hptw request has pmp/a fault suppress bus access.
   assign SelHPTW = WalkerState != IDLE;
-
-  // RT 30 May 2023: When there is an access fault caused by the hptw itself, the fsm jumps to FAULT, removes
-  // stall and asserts one of HPTWLoadAccessFault, HPTWStoreAmoAccessFault or HPTWInstrAccessFaultDelay.
-  // The FSM directly transistions to IDLE to ready for the next operation when the delayed version will not be high.
-
-  assign HPTWAccessFaultDelay = HPTWLoadAccessFaultDelay | HPTWStoreAmoAccessFaultDelay | HPTWInstrAccessFaultDelay;
-  assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMiss); 
-
-  assign DTLBMissOrUpdateDAM = DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM);  
+  assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMissOrUpdateDA); 
 
   // HTPW address/data/control muxing
 
   // Once the walk is done and it is time to update the TLB we need to switch back 
   // to the orignal data virtual address.
   assign SelHPTWAdr = SelHPTW & ~(DTLBWriteM | ITLBWriteF);
-  // always block interrupts when using the hardware page table walker.
 
   // multiplex the outputs to LSU
-  if(P.XLEN == 64) assign HPTWAdrExt = {{(P.XLEN+2-P.PA_BITS){1'b0}}, HPTWAdr}; // extend to 66 bits
-  else             assign HPTWAdrExt = HPTWAdr;
+  if (P.XLEN == 64) assign HPTWAdrExt = {{(P.XLEN+2-P.PA_BITS){1'b0}}, HPTWAdr}; // Extend to 66 bits
+  else              assign HPTWAdrExt = HPTWAdr;
   mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM);
   mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
   mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);    
   mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM);
   mux2 #(P.XLEN+2) lsupadrmux(IEUAdrExtM, HPTWAdrExt, SelHPTWAdr, IHAdrM);
-  if(P.SVADU_SUPPORTED)
+  if (P.SVADU_SUPPORTED) 
     mux2 #(P.XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, IHWriteDataM);
   else assign IHWriteDataM = WriteDataM;
 
 endmodule
-
-// another idea.  We keep gating the control by ~FlushW, but this adds considerable length to the critical path.
-// should we do this differently?  For example TLBMiss is gated by ~FlushW and then drives HPTWStall, which drives LSUStallM, which drives
-// the hazard unit to issue stall and flush controlls. ~FlushW already suppresses these in the hazard unit.
diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv
index e842016a2..ab6ab3e43 100644
--- a/src/mmu/mmu.sv
+++ b/src/mmu/mmu.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Memory management unit, including TLB, PMA, PMP
 // 
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -50,6 +50,7 @@ module mmu import cvw::*;  #(parameter cvw_t P,
   output logic                 Cacheable,          // PMA indicates memory address is cachable
   output logic                 Idempotent,         // PMA indicates memory address is idempotent
   output logic                 SelTIM,             // Select a tightly integrated memory
+  output logic                 SelProgBuf,         // Select ProgBuf
   // Faults
   output logic                 InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources
   output logic                 InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,       // page fault sources
@@ -71,7 +72,6 @@ module mmu import cvw::*;  #(parameter cvw_t P,
   logic                        PMPStoreAmoAccessFaultM;  // Store or AMO access fault from PMP
   logic                        DataMisalignedM;          // load or store misaligned
   logic                        Translate;                // Translation occurs when virtual memory is active and DisableTranslation is off
-  logic                        TLBHit;                   // Hit in TLB
   logic                        TLBPageFault;             // Page fault from TLB
   logic                        ReadNoAmoAccessM;         // Read that is not part of atomic operation causes Load faults.  Otherwise StoreAmo faults
   logic [1:0]                  PBMemoryType;             // PBMT field of PTE during TLB hit, or 00 otherwise
@@ -90,14 +90,15 @@ module mmu import cvw::*;  #(parameter cvw_t P,
           .VAdr(VAdr[P.XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
           .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM,
           .DisableTranslation, .PTE, .PageTypeWriteVal,
-          .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit, 
+          .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss,
           .Translate, .TLBPageFault, .UpdateDA, .PBMemoryType);
   end else begin:tlb // just pass address through as physical
-    assign Translate    = 0;
-    assign TLBMiss      = 0;
-    assign TLBHit       = 1; // *** is this necessary
-    assign TLBPageFault = 0;
+    assign Translate    = 1'b0;
+    assign TLBMiss      = 1'b0;
+    assign TLBPageFault = 1'b0;
     assign PBMemoryType = 2'b00;
+    assign UpdateDA     = 1'b0;
+    assign TLBPAdr      = '0;
   end
 
   // If translation is occuring, select translated physical address from TLB
@@ -112,7 +113,7 @@ module mmu import cvw::*;  #(parameter cvw_t P,
 
   pmachecker #(P) pmachecker(.PhysicalAddress, .Size, .CMOpM, 
     .AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .PBMemoryType,
-    .Cacheable, .Idempotent, .SelTIM, 
+    .Cacheable, .Idempotent, .SelTIM, .SelProgBuf,
     .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
  
   if (P.PMP_ENTRIES > 0) begin : pmp
@@ -121,9 +122,9 @@ module mmu import cvw::*;  #(parameter cvw_t P,
       .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .CMOpM, 
       .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
   end else begin
-    assign PMPInstrAccessFaultF     = 0;
-    assign PMPStoreAmoAccessFaultM  = 0;
-    assign PMPLoadAccessFaultM      = 0;
+    assign PMPInstrAccessFaultF     = 1'b0;
+    assign PMPStoreAmoAccessFaultM  = 1'b0;
+    assign PMPLoadAccessFaultM      = 1'b0;
   end
 
   assign ReadNoAmoAccessM  = ReadAccessM & ~WriteAccessM;// AMO causes StoreAmo rather than Load fault
@@ -132,7 +133,7 @@ module mmu import cvw::*;  #(parameter cvw_t P,
   // Misaligned faults
   always_comb // exclusion-tag: immu-wordaccess
     case(Size[1:0]) 
-      2'b00:  DataMisalignedM = 0;                 // lb, sb, lbu
+      2'b00:  DataMisalignedM = 1'b0;              // lb, sb, lbu
       2'b01:  DataMisalignedM = VAdr[0];           // lh, sh, lhu
       2'b10:  DataMisalignedM = VAdr[1] | VAdr[0]; // lw, sw, flw, fsw, lwu
       2'b11:  DataMisalignedM = |VAdr[2:0];        // ld, sd, fld, fsd
diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv
index 84e41ba65..4ee7163d5 100644
--- a/src/mmu/pmachecker.sv
+++ b/src/mmu/pmachecker.sv
@@ -8,7 +8,7 @@
 //          the memory region accessed.
 //          Can report illegal accesses to the trap unit and cause a fault.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -38,7 +38,7 @@ module pmachecker import cvw::*;  #(parameter cvw_t P) (
   input  logic                 WriteAccessM,   // Write access 
   input  logic                 ReadAccessM,    // Read access
   input  logic [1:0]           PBMemoryType,     // PBMT field of PTE during TLB hit, or 00 otherwise
-  output logic                 Cacheable, Idempotent, SelTIM,
+  output logic                 Cacheable, Idempotent, SelTIM, SelProgBuf,
   output logic                 PMAInstrAccessFaultF,
   output logic                 PMALoadAccessFaultM,
   output logic                 PMAStoreAmoAccessFaultM
@@ -46,7 +46,7 @@ module pmachecker import cvw::*;  #(parameter cvw_t P) (
 
   logic                        PMAAccessFault;
   logic                        AccessRW, AccessRWXC, AccessRX;
-  logic [11:0]                 SelRegions;
+  logic [14:0]                 SelRegions;
   logic                        AtomicAllowed;
   logic                        CacheableRegion, IdempotentRegion;
 
@@ -60,7 +60,7 @@ module pmachecker import cvw::*;  #(parameter cvw_t P) (
 
   // Only non-core RAM/ROM memory regions are cacheable. PBMT can override cachable; NC and IO are uncachable
   assign CacheableRegion = SelRegions[3] | SelRegions[4] | SelRegions[5];  // exclusion-tag: unused-cachable
-  assign Cacheable = (PBMemoryType == 2'b00) ? CacheableRegion : 0;  
+  assign Cacheable = (PBMemoryType == 2'b00) ? CacheableRegion : 1'b0;  
 
   // Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly
   // I/O is nonidempotent.  PBMT can override PMA; NC is idempotent and IO is non-idempotent
@@ -72,6 +72,9 @@ module pmachecker import cvw::*;  #(parameter cvw_t P) (
   // Check if tightly integrated memories are selected
   assign SelTIM = SelRegions[1] | SelRegions[2]; // exclusion-tag: unused-tim
 
+  // Debug program buffer
+  assign SelProgBuf = SelRegions[14];
+
   // Detect access faults
   assign PMAAccessFault          = SelRegions[0] & AccessRWXC | AtomicAccessM & ~AtomicAllowed;  
   assign PMAInstrAccessFaultF    = ExecuteAccessF & PMAAccessFault;
diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv
index 7226237f6..71a6b890a 100644
--- a/src/mmu/pmpadrdec.sv
+++ b/src/mmu/pmpadrdec.sv
@@ -10,7 +10,7 @@
 //          naturally aligned power-of-two region/NAPOT), then selects the
 //          output based on which mode is input.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -77,7 +77,7 @@ module pmpadrdec import cvw::*;  #(parameter cvw_t P) (
 
   assign Match = (AdrMode == TOR) ? TORMatch : 
                  (AdrMode == NA4 | AdrMode == NAPOT) ? NAMatch :
-                 0;
+                 1'b0;
 
   assign L = PMPCfg[7];
   assign X = PMPCfg[2];
diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv
index 30a525744..a97b7ff2e 100644
--- a/src/mmu/pmpchecker.sv
+++ b/src/mmu/pmpchecker.sv
@@ -9,7 +9,7 @@
 //          Can raise an access fault on illegal reads, writes, and instruction
 //          fetches.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv
index 5fbd10caf..7add2162e 100644
--- a/src/mmu/tlb/tlb.sv
+++ b/src/mmu/tlb/tlb.sv
@@ -9,7 +9,7 @@
 // Purpose: Translation lookaside buffer
 //          Cache of virtural-to-physical address translations
 // 
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -72,7 +72,6 @@ module tlb import cvw::*;  #(parameter cvw_t P,
   input  logic                     TLBFlush,
   output logic [P.PA_BITS-1:0]     TLBPAdr,
   output logic                     TLBMiss,
-  output logic                     TLBHit,
   output logic                     Translate,
   output logic                     TLBPageFault,
   output logic                     UpdateDA,
@@ -87,6 +86,7 @@ module tlb import cvw::*;  #(parameter cvw_t P,
   logic [11:0]                    PTEAccessBits;
   logic [1:0]                     HitPageType;
   logic                           CAMHit;
+  logic                           TLBHit;
   logic                           SV39Mode;
   logic                           Misaligned;
   logic                           MegapageMisaligned;
@@ -110,12 +110,12 @@ module tlb import cvw::*;  #(parameter cvw_t P,
   assign NAPOT4 = (PPN[3:0] == 4'b1000); // 64 KiB contiguous region with pte.napot_bits = 4
 
   tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
-    .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM, .DisableTranslation, .TLBFlush,
+    .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM, .DisableTranslation,
     .PTEAccessBits, .CAMHit, .Misaligned, .NAPOT4, 
     .TLBMiss, .TLBHit, .TLBPageFault, 
     .UpdateDA, .SV39Mode, .Translate, .PTE_N, .PBMemoryType);
 
-  tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .TLBHit, .WriteEnables);
+  tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .Matches, .TLBHit, .WriteEnables);
   tlbcam #(P, TLB_ENTRIES, P.VPN_BITS + P.ASID_BITS, P.VPN_SEGMENT_BITS) 
   tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, .PTE_NAPOTs,
            .SATP_ASID, .Matches, .HitPageType, .CAMHit);
diff --git a/src/mmu/tlb/tlbcam.sv b/src/mmu/tlb/tlbcam.sv
index aa569f2dd..06b66efcc 100644
--- a/src/mmu/tlb/tlbcam.sv
+++ b/src/mmu/tlb/tlbcam.sv
@@ -9,7 +9,7 @@
 // Purpose: Stores virtual page numbers with cached translations.
 //          Determines whether a given virtual page number is in the TLB.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/mmu/tlb/tlbcamline.sv b/src/mmu/tlb/tlbcamline.sv
index f5856ef56..e66c22da2 100644
--- a/src/mmu/tlb/tlbcamline.sv
+++ b/src/mmu/tlb/tlbcamline.sv
@@ -9,7 +9,7 @@
 // Purpose: CAM line for the translation lookaside buffer (TLB)
 //          Determines whether a virtual page number matches the stored key.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -41,7 +41,7 @@ module tlbcamline import cvw::*;  #(parameter cvw_t P,
   input  logic                  PTE_NAPOT,  // entry is in NAPOT mode (N bit set and PPN[3:0] = 1000)
   input  logic [1:0]            PageTypeWriteVal,
   input  logic                  TLBFlush,   // Flush this line (set valid to 0)
-  output logic [1:0]            PageTypeRead,  // *** should this be the stored version or the always updated one?
+  output logic [1:0]            PageTypeRead,  
   output logic                  Match
 );
 
@@ -102,8 +102,6 @@ module tlbcamline import cvw::*;  #(parameter cvw_t P,
 
   // On a write, set the valid bit high and update the stored key.
   // On a flush, zero the valid bit and leave the key unchanged.
-  // *** Might we want to update stored key right away to output match on the
-  // write cycle? (using a mux)
   flopenr #(1) validbitflop(clk, reset, WriteEnable | TLBFlush, ~TLBFlush, Valid);
   flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {SATP_ASID, VPN}, Key);
 endmodule
diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv
index 83074deb3..9bd3b8148 100644
--- a/src/mmu/tlb/tlbcontrol.sv
+++ b/src/mmu/tlb/tlbcontrol.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Control signals for TLB
 // 
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -38,7 +38,6 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
   input  logic                     ReadAccess, WriteAccess,
   input  logic [3:0]               CMOpM,
   input  logic                     DisableTranslation,
-  input  logic                     TLBFlush,           // Invalidate all TLB entries
   input  logic [11:0]              PTEAccessBits,
   input  logic                     CAMHit,
   input  logic                     Misaligned,
diff --git a/src/mmu/tlb/tlblru.sv b/src/mmu/tlb/tlblru.sv
index 4776b5afb..6700ddcd0 100644
--- a/src/mmu/tlb/tlblru.sv
+++ b/src/mmu/tlb/tlblru.sv
@@ -7,7 +7,7 @@
 // Purpose: Implementation of bit pseudo least-recently-used algorithm for
 //          cache evictions. Outputs the index of the next entry to be written.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -31,7 +31,6 @@
 module tlblru #(parameter TLB_ENTRIES = 8) (
   input  logic                    clk, reset,
   input  logic                    TLBWrite,
-  input  logic                    TLBFlush,
   input  logic [TLB_ENTRIES-1:0]  Matches,
   input  logic                    TLBHit,
   output logic [TLB_ENTRIES-1:0]  WriteEnables
diff --git a/src/mmu/tlb/tlbmixer.sv b/src/mmu/tlb/tlbmixer.sv
index d615d1370..502d3ef83 100644
--- a/src/mmu/tlb/tlbmixer.sv
+++ b/src/mmu/tlb/tlbmixer.sv
@@ -9,7 +9,7 @@
 //          number with segments from the second, based on the page type.
 //          NOTE: this DOES NOT include the 12 bit offset, which is the same no matter the translation mode or page type.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/mmu/tlb/tlbram.sv b/src/mmu/tlb/tlbram.sv
index 620f338a1..3b329705d 100644
--- a/src/mmu/tlb/tlbram.sv
+++ b/src/mmu/tlb/tlbram.sv
@@ -8,7 +8,7 @@
 //          Outputs the physical page number and access bits of the current
 //          virtual address on a TLB hit.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/mmu/tlb/tlbramline.sv b/src/mmu/tlb/tlbramline.sv
index 910db3aec..0b3e3994a 100644
--- a/src/mmu/tlb/tlbramline.sv
+++ b/src/mmu/tlb/tlbramline.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR
 // 
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/mmu/tlb/vm64check.sv b/src/mmu/tlb/vm64check.sv
index 4a4e96387..6f2d3c2d4 100644
--- a/src/mmu/tlb/vm64check.sv
+++ b/src/mmu/tlb/vm64check.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Check for good upper address bits in RV64 mode
 // 
-// Documentation: RISC-V System on Chip Design Chapter 8
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -28,10 +28,10 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module vm64check import cvw::*;  #(parameter cvw_t P) (
-  input  logic [P.SVMODE_BITS-1:0] SATP_MODE,
-  input  logic [P.XLEN-1:0]        VAdr,
-  output logic                    SV39Mode, 
-  output logic                    UpperBitsUnequal
+  input  logic [P.SVMODE_BITS-1:0]  SATP_MODE,
+  input  logic [P.XLEN-1:0]         VAdr,
+  output logic                      SV39Mode, 
+  output logic                      UpperBitsUnequal
 );
 
   if (P.XLEN == 64) begin
@@ -43,7 +43,7 @@ module vm64check import cvw::*;  #(parameter cvw_t P) (
     assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); 
     assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47;
   end else begin
-    assign SV39Mode = 0;
-    assign UpperBitsUnequal = 0;
+    assign SV39Mode = 1'b0;
+    assign UpperBitsUnequal = 1'b0;
   end
 endmodule
diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv
index 4be12e383..6b63a0ac1 100644
--- a/src/privileged/csr.sv
+++ b/src/privileged/csr.sv
@@ -8,7 +8,7 @@
 // Purpose: Counter Control and Status Registers
 //          See RISC-V Privileged Mode Specification 20190608 
 // 
-// Documentation: RISC-V System on Chip Design Chapter 5
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -57,12 +57,12 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   input  logic                     LoadStallD, StoreStallD, 
   input  logic                     ICacheStallF,
   input  logic                     DCacheStallM,
-  input  logic                     BPDirPredWrongM,
+  input  logic                     BPDirWrongM,
   input  logic                     BTAWrongM,
   input  logic                     RASPredPCWrongM,
   input  logic                     IClassWrongM,
   input  logic                     BPWrongM,                  // branch predictor is wrong
-  input  logic [3:0]               InstrClassM,
+  input  logic [3:0]               IClassM,
   input  logic                     DCacheMiss,
   input  logic                     DCacheAccess,
   input  logic                     ICacheMiss,
@@ -92,29 +92,47 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   //
   output logic [P.XLEN-1:0]        CSRReadValW,               // value read from CSR
   output logic                     IllegalCSRAccessM,         // Illegal CSR access: CSR doesn't exist or is inaccessible at this privilege level
-  output logic                     BigEndianM                 // memory access is big-endian based on privilege mode and STATUS register endian fields
+  output logic                     BigEndianM,                // memory access is big-endian based on privilege mode and STATUS register endian fields
+  // Debug Mode output
+  input  logic                     DebugMode,
+  input  logic [2:0]               DebugCause,
+  output logic                     ebreakEn,
+  output logic                     Step,
+  output logic [P.XLEN-1:0]        DPC,
+  input  logic                     DCall,
+  input  logic                     DRet,
+  input  logic                     ExecProgBuf,
+  // Debug scan chain
+  input  logic                     DebugSel,
+  input  logic [11:0]              DebugRegAddr,
+  input  logic                     DebugCapture,
+  input  logic                     DebugRegUpdate,
+  input  logic                     DebugScanEn,
+  input  logic                     DebugScanIn,
+  output logic                     DebugScanOut
 );
 
   localparam MIP = 12'h344;
   localparam SIP = 12'h144;
   
-  logic [P.XLEN-1:0]       CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM;
+  logic [P.XLEN-1:0]       CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM, CSRDReadValM;
   logic [P.XLEN-1:0]       CSRReadValM;  
   logic [P.XLEN-1:0]       CSRSrcM;
   logic [P.XLEN-1:0]       CSRRWM, CSRRSM, CSRRCM;  
-  logic [P.XLEN-1:0]       CSRWriteValM;
+  logic [P.XLEN-1:0]       CSRWriteValM, CSRWriteValDM, DebugCSRScanVal;
   logic [P.XLEN-1:0]       MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
   logic [P.XLEN-1:0]       STVEC_REGW, MTVEC_REGW;
   logic [P.XLEN-1:0]       MEPC_REGW, SEPC_REGW;
   logic [31:0]             MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
   logic                    WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
+  logic                    CSRWriteDM;
   logic                    CSRMWriteM, CSRSWriteM, CSRUWriteM;
   logic                    UngatedCSRMWriteM;
   logic                    WriteFRMM, WriteFFLAGSM;
   logic [P.XLEN-1:0]       UnalignedNextEPCM, NextEPCM, NextMtvalM;
   logic [4:0]              NextCauseM;
-  logic [11:0]             CSRAdrM;
-  logic                    IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM;
+  logic [11:0]             CSRAdrM, CSRAdrDM;
+  logic                    IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, IllegalCSRDAccessM;
   logic                    InsufficientCSRPrivilegeM;
   logic                    IllegalCSRMWriteReadonlyM;
   logic [P.XLEN-1:0]       CSRReadVal2M;
@@ -138,12 +156,12 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   ///////////////////////////////////////////
 
   always_comb
-    if (InterruptM)           NextFaultMtvalM = 0;
+    if (InterruptM)           NextFaultMtvalM = '0;
     else case (CauseM)
       12, 1, 3:               NextFaultMtvalM = PCM;  // Instruction page/access faults, breakpoint
       2:                      NextFaultMtvalM = {{(P.XLEN-32){1'b0}}, InstrOrigM}; // Illegal instruction fault 
       0, 4, 6, 13, 15, 5, 7:  NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults
-      default:                NextFaultMtvalM = 0; // Ecall, interrupts
+      default:                NextFaultMtvalM = '0; // Ecall, interrupts
     endcase
 
   ///////////////////////////////////////////
@@ -168,7 +186,16 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   // Trap Returns
   // A trap sets the PC to TrapVector
   // A return sets the PC to MEPC or SEPC
-  mux2 #(P.XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPCM);
+  if (P.DEBUG_SUPPORTED) begin
+    always_comb
+      if      (ExecProgBuf)   EPCM = P.PROGBUF_BASE[P.XLEN-1:0];
+      else if (DRet)          EPCM = DPC;
+      else if (mretM)         EPCM = MEPC_REGW;
+      else                    EPCM = SEPC_REGW;
+  end else begin
+    mux2 #(P.XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPCM);
+  end
+
 
   ///////////////////////////////////////////
   // CSRWriteValM
@@ -179,7 +206,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
     CSRSrcM = InstrM[14] ? {{(P.XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM;
 
     // CSR set and clear for MIP/SIP should only touch internal state, not interrupt inputs
-    if (CSRAdrM == MIP | CSRAdrM == SIP) CSRReadVal2M = {{(P.XLEN-12){1'b0}}, MIP_REGW_writeable};
+    if (CSRAdrDM == MIP | CSRAdrDM == SIP) CSRReadVal2M = {{(P.XLEN-12){1'b0}}, MIP_REGW_writeable};
     else                                 CSRReadVal2M = CSRReadValM;
 
     // Compute AND/OR modification
@@ -200,13 +227,13 @@ module csr import cvw::*;  #(parameter cvw_t P) (
 
   assign CSRAdrM = InstrM[31:20];
   assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM;
-  assign NextEPCM = P.COMPRESSED_SUPPORTED ? {UnalignedNextEPCM[P.XLEN-1:1], 1'b0} : {UnalignedNextEPCM[P.XLEN-1:2], 2'b00}; // 3.1.15 alignment
+  assign NextEPCM = P.ZCA_SUPPORTED ? {UnalignedNextEPCM[P.XLEN-1:1], 1'b0} : {UnalignedNextEPCM[P.XLEN-1:2], 2'b00}; // 3.1.15 alignment
   assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[P.XLEN-1], CSRWriteValM[3:0]};
   assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
-  assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == P.M_MODE);
+  assign UngatedCSRMWriteM = CSRWriteDM & (PrivilegeModeW == P.M_MODE);
   assign CSRMWriteM = UngatedCSRMWriteM & InstrValidNotFlushedM;
-  assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW) & InstrValidNotFlushedM;
-  assign CSRUWriteM = CSRWriteM  & InstrValidNotFlushedM;
+  assign CSRSWriteM = CSRWriteDM & (|PrivilegeModeW) & InstrValidNotFlushedM;
+  assign CSRUWriteM = CSRWriteDM & InstrValidNotFlushedM;
   assign MTrapM = TrapM & (NextPrivilegeModeM == P.M_MODE);
   assign STrapM = TrapM & (NextPrivilegeModeM == P.S_MODE) & P.S_SUPPORTED;
 
@@ -215,76 +242,90 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   ///////////////////////////////////////////
 
   csri #(P) csri(.clk, .reset,  
-    .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, 
+    .CSRMWriteM, .CSRSWriteM, .CSRWriteValM(CSRWriteValDM), .CSRAdrM(CSRAdrDM), 
     .MExtInt, .SExtInt, .MTimerInt, .STimerInt, .MSwInt,
     .MIDELEG_REGW, .ENVCFG_STCE, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
 
   csrsr #(P) csrsr(.clk, .reset, .StallW, 
     .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, 
     .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
-    .mretM, .sretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM, .SelHPTW,
+    .mretM, .sretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM(CSRWriteValDM), .SelHPTW,
     .MSTATUS_REGW, .SSTATUS_REGW, .MSTATUSH_REGW,
     .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
     .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
     .STATUS_FS, .BigEndianM);
 
   csrm #(P) csrm(.clk, .reset, 
-    .UngatedCSRMWriteM, .CSRMWriteM, .MTrapM, .CSRAdrM,
+    .UngatedCSRMWriteM, .CSRMWriteM, .MTrapM, .CSRAdrM(CSRAdrDM),
     .NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
-    .CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
+    .CSRWriteValM(CSRWriteValDM), .CSRMReadValM, .MTVEC_REGW,
     .MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW, 
     .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
     .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
     .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM,
     .MENVCFG_REGW);
 
-
   if (P.S_SUPPORTED) begin:csrs
     logic STCE; 
     assign STCE = P.SSTC_SUPPORTED & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_REGW[1] & ENVCFG_STCE));
     csrs #(P) csrs(.clk, .reset,
-      .CSRSWriteM, .STrapM, .CSRAdrM,
+      .CSRSWriteM, .STrapM, .CSRAdrM(CSRAdrDM),
       .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, 
       .STATUS_TVM, 
-      .CSRWriteValM, .PrivilegeModeW,
+      .CSRWriteValM(CSRWriteValDM), .PrivilegeModeW,
       .CSRSReadValM, .STVEC_REGW, .SEPC_REGW,      
       .SCOUNTEREN_REGW,
       .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT, .STCE,
       .WriteSSTATUSM, .IllegalCSRSAccessM, .STimerInt, .SENVCFG_REGW);
   end else begin
-    assign WriteSSTATUSM = 0;
-    assign CSRSReadValM = 0;
-    assign SEPC_REGW = 0;
-    assign STVEC_REGW = 0;
-    assign SCOUNTEREN_REGW = 0;
-    assign SATP_REGW = 0;
-    assign IllegalCSRSAccessM = 1;
+    assign WriteSSTATUSM = 1'b0;
+    assign CSRSReadValM = '0;
+    assign SEPC_REGW = '0;
+    assign STVEC_REGW = '0;
+    assign SCOUNTEREN_REGW = '0;
+    assign SATP_REGW = '0;
+    assign IllegalCSRSAccessM = 1'b1;
   end
 
   // Floating Point CSRs in User Mode only needed if Floating Point is supported
   if (P.F_SUPPORTED | P.D_SUPPORTED) begin:csru
     csru #(P) csru(.clk, .reset, .InstrValidNotFlushedM, 
-      .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,  
+      .CSRUWriteM, .CSRAdrM(CSRAdrDM), .CSRWriteValM(CSRWriteValDM), .STATUS_FS, .CSRUReadValM,  
       .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
       .IllegalCSRUAccessM);
   end else begin
-    assign FRM_REGW = 0;
-    assign CSRUReadValM = 0;
-    assign IllegalCSRUAccessM = 1;
+    assign FRM_REGW = '0;
+    assign CSRUReadValM = '0;
+    assign IllegalCSRUAccessM = 1'b1;
+    assign WriteFRMM = 1'b0;
+    assign WriteFFLAGSM = 1'b0;
   end
   
   if (P.ZICNTR_SUPPORTED) begin:counters
     csrc #(P) counters(.clk, .reset, .StallE, .StallM, .FlushM,
-      .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
-      .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
-      .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM,
+      .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM(CSRWriteDM), .CSRMWriteM,
+      .BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
+      .IClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM,
       .InterruptM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
-      .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
+      .CSRAdrM(CSRAdrDM), .PrivilegeModeW, .CSRWriteValM(CSRWriteValDM),
       .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
       .MTIME_CLINT,  .CSRCReadValM, .IllegalCSRCAccessM);
   end else begin
-    assign CSRCReadValM = 0;
-    assign IllegalCSRCAccessM = 1; // counters aren't enabled
+    assign CSRCReadValM = '0;
+    assign IllegalCSRCAccessM = 1'b1; // counters aren't enabled
+  end
+
+  if (P.DEBUG_SUPPORTED) begin:csrd
+    csrd #(P) csrd(.clk, .reset, .DebugMode, .PrivilegeModeW,
+    .CSRWriteDM, .CSRAdrM(CSRAdrDM), .CSRWriteValM(CSRWriteValDM), .CSRDReadValM, .IllegalCSRDAccessM,
+    .DebugCause, .ebreakEn, .Step, .DPC, .PCM, .DCall);
+  end else begin
+    assign Step = '0;
+    assign DPC = '0;
+    assign DebugScanOut = '0;
+    assign ebreakEn = 0;
+    assign CSRDReadValM = '0;
+    assign IllegalCSRDAccessM = 1'b1; // Debug isn't supported
   end
 
    // Broadcast appropriate environment configuration based on privilege mode
@@ -300,13 +341,27 @@ module csr import cvw::*;  #(parameter cvw_t P) (
                                                                        (MENVCFG_REGW[0] & SENVCFG_REGW[0]);
 
   // merge CSR Reads
-  assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM; 
+  assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRDReadValM; 
   flopenrc #(P.XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW);
 
   // merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient
-  assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 & PrivilegeModeW != P.M_MODE) |
-                                     (CSRAdrM[9:8] == 2'b01 & PrivilegeModeW == P.U_MODE);
+  // TODO: ignore/modify this check when in debug mode
+  assign InsufficientCSRPrivilegeM = (CSRAdrDM[9:8] == 2'b11 & PrivilegeModeW != P.M_MODE) |
+                                     (CSRAdrDM[9:8] == 2'b01 & PrivilegeModeW == P.U_MODE);
   assign IllegalCSRAccessM = ((IllegalCSRCAccessM & IllegalCSRMAccessM & 
-    IllegalCSRSAccessM & IllegalCSRUAccessM |
+    IllegalCSRSAccessM & IllegalCSRUAccessM & IllegalCSRDAccessM |
     InsufficientCSRPrivilegeM) & CSRReadM) | IllegalCSRMWriteReadonlyM;
+
+  // Debug module CSR access
+  // TODO: should DM be able to access CSRs when hart isn't in M mode?
+  if (P.DEBUG_SUPPORTED) begin
+    assign CSRAdrDM = DebugSel ? DebugRegAddr : CSRAdrM;
+    assign CSRWriteDM = DebugSel ? DebugRegUpdate : CSRWriteM; // TODO: add write support
+    assign CSRWriteValDM = DebugSel ? DebugCSRScanVal : CSRWriteValM;
+    flopenrs #(P.XLEN) GPScanReg(.clk, .reset, .en(DebugCapture), .d(CSRReadValM), .q(DebugCSRScanVal), .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DebugScanOut));
+  end else begin
+    assign CSRAdrDM = CSRAdrM;
+    assign CSRWriteDM = CSRWriteM;
+    assign CSRWriteValDM = CSRWriteValM;
+  end
 endmodule
diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv
index db39f26b9..d8ce0e709 100644
--- a/src/privileged/csrc.sv
+++ b/src/privileged/csrc.sv
@@ -7,7 +7,7 @@
 // Purpose: Counter CSRs
 //          See RISC-V Privileged Mode Specification 20190608 3.1.10-11
 // 
-// Documentation: RISC-V System on Chip Design Chapter 5
+// Documentation: RISC-V System on Chip Design
 //    MHPMEVENT is not supported
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
@@ -35,12 +35,12 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
   input  logic              FlushM, 
   input  logic              InstrValidNotFlushedM, LoadStallD, StoreStallD,
   input  logic              CSRMWriteM, CSRWriteM,
-  input  logic              BPDirPredWrongM,
+  input  logic              BPDirWrongM,
   input  logic              BTAWrongM,
   input  logic              RASPredPCWrongM,
   input  logic              IClassWrongM,
   input  logic              BPWrongM,                                  // branch predictor is wrong
-  input  logic [3:0]        InstrClassM,
+  input  logic [3:0]        IClassM,
   input  logic              DCacheMiss,
   input  logic              DCacheAccess,
   input  logic              ICacheMiss,
@@ -95,34 +95,36 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
   assign CounterEvent[1]    = 1'b0;                                                      // Counter 1 doesn't exist
   assign CounterEvent[2]    = InstrValidNotFlushedM;                                     // MINSTRET instructions retired
   if (P.ZIHPM_SUPPORTED) begin: cevent                                                   // User-defined counters
-    assign CounterEvent[3]  = InstrClassM[0] & InstrValidNotFlushedM;                    // branch instruction
-    assign CounterEvent[4]  = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM;  // jump and not return instructions
-    assign CounterEvent[5]  = InstrClassM[2] & InstrValidNotFlushedM;                    // return instructions
+    // Ideally all events would be counted in the M stage, but the pipelining is costly. The counters may
+    // count an event in a previous pipeline stage.
+    assign CounterEvent[3]  = IClassM[0] & InstrValidNotFlushedM;                        // branch instruction
+    assign CounterEvent[4]  = IClassM[1] & ~IClassM[2] & InstrValidNotFlushedM;          // jump and not return instructions
+    assign CounterEvent[5]  = IClassM[2] & InstrValidNotFlushedM;                        // return instructions
     assign CounterEvent[6]  = BPWrongM & InstrValidNotFlushedM;                          // branch predictor wrong
-    assign CounterEvent[7]  = BPDirPredWrongM & InstrValidNotFlushedM;                   // Branch predictor wrong direction
+    assign CounterEvent[7]  = BPDirWrongM & InstrValidNotFlushedM;                       // Branch predictor wrong direction
     assign CounterEvent[8]  = BTAWrongM & InstrValidNotFlushedM;                         // branch predictor wrong target
     assign CounterEvent[9]  = RASPredPCWrongM & InstrValidNotFlushedM;                   // return address stack wrong address
     assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM;                      // instruction class predictor wrong
     assign CounterEvent[11] = LoadStallM;                                                // Load Stalls. don't want to suppress on flush as this only happens if flushed.
-    assign CounterEvent[12] = StoreStallM;                                               // depricated Store Stall
+    assign CounterEvent[12] = StoreStallM;                                               // Store Stall
     assign CounterEvent[13] = DCacheAccess;                                              // data cache access
     assign CounterEvent[14] = DCacheMiss;                                                // data cache miss. Miss asserted 1 cycle at start of cache miss
-    assign CounterEvent[15] = DCacheStallM;                                              // d cache miss cycles
+    assign CounterEvent[15] = DCacheStallM;                                              // D$ miss cycles
     assign CounterEvent[16] = ICacheAccess;                                              // instruction cache access
     assign CounterEvent[17] = ICacheMiss;                                                // instruction cache miss. Miss asserted 1 cycle at start of cache miss
-    assign CounterEvent[18] = ICacheStallF;                                              // i cache miss cycles
+    assign CounterEvent[18] = ICacheStallF;                                              // I$ miss cycles
     assign CounterEvent[19] = CSRWriteM & InstrValidNotFlushedM;                         // CSR writes
     assign CounterEvent[20] = InvalidateICacheM & InstrValidNotFlushedM;                 // fence.i
     assign CounterEvent[21] = sfencevmaM & InstrValidNotFlushedM;                        // sfence.vma
     assign CounterEvent[22] = InterruptM;                                                // interrupt, InstrValidNotFlushedM will be low
     assign CounterEvent[23] = ExceptionM;                                                // exceptions, InstrValidNotFlushedM will be low
     // coverage off
-    // DivBusyE will never be assert high since this configuration uses the FPU to do integer division
-    assign CounterEvent[24] = DivBusyE | FDivBusyE;                                      // division cycles *** RT: might need to be delay until the next cycle
+    // DivBusyE will never be asserted high because the RV64GC configuration uses the FPU to do integer division
+    assign CounterEvent[24] = DivBusyE | FDivBusyE;                                      // division cycles
     // coverage on
-    assign CounterEvent[P.COUNTERS-1:25] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
+    assign CounterEvent[P.COUNTERS-1:25] = '0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
   end else begin: cevent
-    assign CounterEvent[P.COUNTERS-1:3] = 0;
+    assign CounterEvent[P.COUNTERS-1:3] = '0;
   end
   
   // Counter update and write logic
@@ -130,7 +132,7 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
       assign WriteHPMCOUNTERM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERBASE + i);
       assign NextHPMCOUNTERM[i][P.XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][P.XLEN-1:0];
       always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
-        if (reset) HPMCOUNTER_REGW[i][P.XLEN-1:0] <= 0;
+        if (reset) HPMCOUNTER_REGW[i][P.XLEN-1:0] <= '0;
         else       HPMCOUNTER_REGW[i][P.XLEN-1:0] <= NextHPMCOUNTERM[i];
 
       if (P.XLEN==32) begin // write high and low separately
@@ -140,10 +142,11 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
         assign WriteHPMCOUNTERHM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERHBASE + i);
         assign NextHPMCOUNTERHM[i] = WriteHPMCOUNTERHM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][63:32];
         always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
-            if (reset) HPMCOUNTERH_REGW[i][P.XLEN-1:0] <= 0;
+            if (reset) HPMCOUNTERH_REGW[i][P.XLEN-1:0] <= '0;
             else       HPMCOUNTERH_REGW[i][P.XLEN-1:0] <= NextHPMCOUNTERHM[i];
       end else begin // XLEN=64; write entire register
           assign HPMCOUNTERPlusM[i] = HPMCOUNTER_REGW[i] + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
+          assign HPMCOUNTERH_REGW[i] = '0; // disregard for RV64
       end
   end
 
@@ -152,7 +155,7 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
   always_comb 
     if (PrivilegeModeW == P.M_MODE | 
         MCOUNTEREN_REGW[CounterNumM] & (!P.S_SUPPORTED | PrivilegeModeW == P.S_MODE | SCOUNTEREN_REGW[CounterNumM])) begin
-      IllegalCSRCAccessM = 0;
+      IllegalCSRCAccessM = 1'b0;
       if (P.XLEN==64) begin // 64-bit counter reads
         // Veri lator doesn't realize this only occurs for XLEN=64
         /* verilator lint_off WIDTH */  
@@ -163,8 +166,8 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
         else if (CSRAdrM >= HPMCOUNTERBASE  & CSRAdrM  < HPMCOUNTERBASE+P.COUNTERS)  
                  CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
         else begin
-            CSRCReadValM = 0;
-            IllegalCSRCAccessM = 1;  // requested CSR doesn't exist
+            CSRCReadValM = '0;
+            IllegalCSRCAccessM = 1'b1;  // requested CSR doesn't exist
         end
       end else begin // 32-bit counter reads
         // Veril ator doesn't realize this only occurs for XLEN=32
@@ -181,13 +184,13 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
         else if (CSRAdrM >= HPMCOUNTERHBASE  & CSRAdrM < HPMCOUNTERHBASE+P.COUNTERS)   
                  CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
         else begin
-          CSRCReadValM = 0;
-          IllegalCSRCAccessM = 1; // requested CSR doesn't exist
+          CSRCReadValM = '0;
+          IllegalCSRCAccessM = 1'b1; // requested CSR doesn't exist
         end            
       end
     end else begin 
-      CSRCReadValM = 0;
-      IllegalCSRCAccessM = 1; // no privileges for this csr
+      CSRCReadValM = '0;
+      IllegalCSRCAccessM = 1'b1; // no privileges for this csr
     end
 endmodule
 
diff --git a/src/privileged/csrd.sv b/src/privileged/csrd.sv
new file mode 100644
index 000000000..cded34e03
--- /dev/null
+++ b/src/privileged/csrd.sv
@@ -0,0 +1,111 @@
+///////////////////////////////////////////
+// csrd.sv
+//
+// Written: matthew.n.otto@okstate.edu
+// Created: 13 June 2024
+//
+// Purpose: Debug Control and Status Registers
+//          See RISC-V Debug Specification (4.10)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License Version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module csrd import cvw::*;  #(parameter cvw_t P) (
+  input  logic              clk, reset,
+  input  logic              DebugMode,
+  input  logic [1:0]        PrivilegeModeW,
+  input  logic              CSRWriteDM,
+  input  logic [11:0]       CSRAdrM,
+  input  logic [P.XLEN-1:0] CSRWriteValM,
+  output logic [P.XLEN-1:0] CSRDReadValM,
+  output logic              IllegalCSRDAccessM,
+  input  logic [P.XLEN-1:0] PCM,
+  input  logic              DCall,
+  input  logic [2:0]        DebugCause,
+  output logic              ebreakEn,
+  output logic              Step,
+  output logic [P.XLEN-1:0] DPC
+);
+  `include "debug.vh"
+
+  localparam DCSR_ADDR = 12'h7B0;  // Debug Control and Status Register
+  localparam DPC_ADDR  = 12'h7B1;  // Debug PC
+
+  logic CSRDWriteM;
+  logic [31:0] DCSR;
+  logic [P.XLEN-1:0] DPCWriteVal;
+  logic WriteDCSRM;
+  logic WriteDPCM;
+
+  // DCSR fields
+  const logic [3:0] DebugVer = 4;
+  const logic       ebreakVS = 0;
+  const logic       ebreakVU = 0;
+  logic             ebreakM;
+  const logic       ebreakS = 0;
+  const logic       ebreakU = 0;
+  const logic       StepIE = 0;
+  const logic       StopCount = 0;
+  const logic       StopTime = 0;
+  logic [2:0]       Cause;
+  const logic       V = 0;
+  const logic       MPrvEn = 0;
+  const logic       NMIP = 0;      // pending non-maskable interrupt TODO: update
+  logic [1:0]       Prv;
+
+  
+  //assign ebreakEn = ebreakM; // Only support ebreak from M mode
+  assign ebreakEn = 1'b1; // OpenOCD doesn't set ebreakM????         ebreakM; // Only support ebreak from M mode
+  assign CSRDWriteM = CSRWriteDM & (PrivilegeModeW == P.M_MODE) & DebugMode;
+
+  assign WriteDCSRM = CSRDWriteM & (CSRAdrM == DCSR_ADDR);
+  assign WriteDPCM  = CSRDWriteM & (CSRAdrM == DPC_ADDR);
+
+  always_ff @(posedge clk) begin
+    if (reset) begin
+      Prv <= 2'h3;
+      Cause <= 3'h0;
+    end else if (DCall) begin
+      Prv <= PrivilegeModeW;
+      Cause <= DebugCause;
+    end
+  end
+
+  flopenr #(2) DCSRreg (clk, reset, WriteDCSRM, {CSRWriteValM[`EBREAKM], CSRWriteValM[`STEP]}, {ebreakM, Step});
+
+  assign DCSR = {DebugVer, 10'b0, ebreakVS, ebreakVU, ebreakM, 1'b0, ebreakS, ebreakU, StepIE,
+                      StopCount, StopTime, Cause, V, MPrvEn, NMIP, Step, Prv};
+
+  assign DPCWriteVal = DCall ? PCM : CSRWriteValM;
+  flopenr #(P.XLEN) DPCreg (clk, reset, WriteDPCM | DCall, DPCWriteVal, DPC);
+
+  always_comb begin
+    CSRDReadValM = '0;
+    IllegalCSRDAccessM = 1'b0;
+    if (~((PrivilegeModeW == P.M_MODE) & DebugMode))
+      IllegalCSRDAccessM = 1'b1;
+    else
+      case (CSRAdrM)
+        DCSR_ADDR : CSRDReadValM = {{(P.XLEN-32){1'b0}},DCSR};
+        DPC_ADDR  : CSRDReadValM = DPC;
+        default: IllegalCSRDAccessM = 1'b1;
+      endcase
+  end
+
+endmodule
diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv
index fafc5c845..b3db38e8a 100644
--- a/src/privileged/csri.sv
+++ b/src/privileged/csri.sv
@@ -7,7 +7,7 @@
 // Purpose: Interrupt Control & Status Registers (IP, EI)
 //          See RISC-V Privileged Mode Specification 20190608 & 20210108 draft
 // 
-// Documentation: RISC-V System on Chip Design Chapter 5
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv
index 35c27736c..17b9506f5 100644
--- a/src/privileged/csrm.sv
+++ b/src/privileged/csrm.sv
@@ -11,7 +11,7 @@
 //   - Disabling portions of the instruction set with bits of the MISA register
 //   - Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register
 //
-// Documentation: RISC-V System on Chip Design Chapter 5
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -45,8 +45,10 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   output logic [31:0]              MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, 
   output logic [15:0]              MEDELEG_REGW,
   output logic [11:0]              MIDELEG_REGW,
+  /* verilator lint_off UNDRIVEN */ // PMP registers are only used when PMP_ENTRIES > 0
   output var logic [7:0]           PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],
   output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0],
+  /* verilator lint_on UNDRIVEN */
   output logic                     WriteMSTATUSM, WriteMSTATUSHM,
   output logic                     IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM,
   output logic [63:0]              MENVCFG_REGW
@@ -89,14 +91,10 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   localparam TDATA1        = 12'h7A1;
   localparam TDATA2        = 12'h7A2;
   localparam TDATA3        = 12'h7A3;
-  localparam DCSR          = 12'h7B0;
-  localparam DPC           = 12'h7B1;
-  localparam DSCRATCH0     = 12'h7B2;
-  localparam DSCRATCH1     = 12'h7B3;
   // Constants
   localparam ZERO = {(P.XLEN){1'b0}};
   // when compressed instructions are supported, there can't be misaligned instructions
-  localparam MEDELEG_MASK  = P.COMPRESSED_SUPPORTED ? 16'hB3FE : 16'hB3FF;
+  localparam MEDELEG_MASK  = P.ZCA_SUPPORTED ? 16'hB3FE : 16'hB3FF;
   localparam MIDELEG_MASK  = 12'h222; // we choose to not make machine interrupts delegable
 
  // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
@@ -132,7 +130,7 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   assign MISA_REGW = {(P.XLEN == 32 ? 2'b01 : 2'b10), {(P.XLEN-28){1'b0}}, MISA_26[25:0]};
 
   // MHARTID is hardwired. It only exists as a signal so that the testbench can easily see it.
-  assign MHARTID_REGW = 0;
+  assign MHARTID_REGW = '0;
 
   // Write machine Mode CSRs 
   assign WriteMSTATUSM       = CSRMWriteM & (CSRAdrM == MSTATUS);
@@ -154,7 +152,7 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   if (P.S_SUPPORTED) begin:deleg // DELEG registers should exist
     flopenr #(16) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM[15:0] & MEDELEG_MASK, MEDELEG_REGW);
     flopenr #(12) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & MIDELEG_MASK, MIDELEG_REGW);
-  end else assign {MEDELEG_REGW, MIDELEG_REGW} = 0;
+  end else assign {MEDELEG_REGW, MIDELEG_REGW} = '0;
 
   flopenr #(P.XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW);
   flopenr #(P.XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); 
@@ -163,7 +161,7 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   flopenr #(32)   MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW);
   if (P.U_SUPPORTED) begin: mcounteren // MCOUNTEREN only exists when user mode is supported
     flopenr #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
-  end else assign MCOUNTEREN_REGW = 0;
+  end else assign MCOUNTEREN_REGW = '0;
 
   // MENVCFG register
   if (P.U_SUPPORTED) begin // menvcfg only exists if there is a lower privilege to control
@@ -184,7 +182,7 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
     if (P.XLEN == 64) begin
       assign MENVCFG_PreWriteValM = CSRWriteValM;
       flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM, MENVCFG_REGW);
-      assign MENVCFGH_REGW = 0;
+      assign MENVCFGH_REGW = '0;
     end else begin // RV32 has high and low halves
       logic WriteMENVCFGHM;
       assign MENVCFG_PreWriteValM = {CSRWriteValM, CSRWriteValM};
@@ -199,8 +197,8 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   // verilator lint_off WIDTH
   logic [5:0] entry;
   always_comb begin
-    entry = 0;
-    CSRMReadValM = 0;
+    entry = '0;
+    CSRMReadValM = '0;
     IllegalCSRMAccessM = !(P.S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
     if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + P.PMP_ENTRIES) // reading a PMP entry
       CSRMReadValM = {{(P.XLEN-(P.PA_BITS-2)){1'b0}}, PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0]};
@@ -221,10 +219,10 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
       MARCHID:       CSRMReadValM = {{(P.XLEN-32){1'b0}}, 32'h24}; // 36 for CV-Wally 
       MIMPID:        CSRMReadValM = {{P.XLEN-12{1'b0}}, 12'h100}; // pipelined implementation
       MHARTID:       CSRMReadValM = MHARTID_REGW; // hardwired to 0 
-      MCONFIGPTR:    CSRMReadValM = 0; // hardwired to 0
+      MCONFIGPTR:    CSRMReadValM = '0; // hardwired to 0
       MSTATUS:       CSRMReadValM = MSTATUS_REGW;
       MSTATUSH:      if (P.XLEN==32) CSRMReadValM = MSTATUSH_REGW; 
-                     else IllegalCSRMAccessM = 1;
+                     else IllegalCSRMAccessM = 1'b1;
       MTVEC:         CSRMReadValM = MTVEC_REGW;
       MEDELEG:       CSRMReadValM = {{(P.XLEN-16){1'b0}}, MEDELEG_REGW};
       MIDELEG:       CSRMReadValM = {{(P.XLEN-12){1'b0}}, MIDELEG_REGW};
@@ -236,11 +234,11 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
       MTVAL:         CSRMReadValM = MTVAL_REGW;
       MCOUNTEREN:    CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTEREN_REGW};
       MENVCFG:       if (P.U_SUPPORTED) CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0];
-                     else IllegalCSRMAccessM = 1;
+                     else IllegalCSRMAccessM = 1'b1;
       MENVCFGH:      if (P.U_SUPPORTED & P.XLEN==32) CSRMReadValM = MENVCFGH_REGW;
-                     else IllegalCSRMAccessM = 1;
+                     else IllegalCSRMAccessM = 1'b1;
       MCOUNTINHIBIT: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
-      default:       IllegalCSRMAccessM = 1;
+      default:       IllegalCSRMAccessM = 1'b1;
     endcase
   end
   // verilator lint_on WIDTH
diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv
index 2357fc131..ebd468ad6 100644
--- a/src/privileged/csrs.sv
+++ b/src/privileged/csrs.sv
@@ -8,7 +8,7 @@
 // Purpose: Supervisor-Mode Control and Status Registers
 //          See RISC-V Privileged Mode Specification 20190608 
 //
-// Documentation: RISC-V System on Chip Design Chapter 5
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -108,7 +108,7 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
   if (P.VIRTMEM_SUPPORTED)
     flopenr #(P.XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
   else
-    assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported
+    assign SATP_REGW = '0; // hardwire to zero if virtual memory not supported
   flopenr #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
   if (P.SSTC_SUPPORTED) begin : sstc
     if (P.XLEN == 64) begin : sstc64
@@ -117,14 +117,14 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
       flopenr #(P.XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW[31:0]);
       flopenr #(P.XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, STIMECMP_REGW[63:32]);
     end
-  end else assign STIMECMP_REGW = 0;
+  end else assign STIMECMP_REGW = '0;
 
   // Supervisor timer interrupt logic
   // Spec is a bit peculiar - Machine timer interrupts are produced in CLINT, while Supervisor timer interrupts are in CSRs
   if (P.SSTC_SUPPORTED)
    assign STimerInt  = ({1'b0, MTIME_CLINT} >= {1'b0, STIMECMP_REGW}); // unsigned comparison
   else 
-    assign STimerInt = 0;
+    assign STimerInt = 1'b0;
 
   assign SENVCFG_WriteValM = {
     {(P.XLEN-8){1'b0}},
@@ -138,7 +138,7 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
     
   // CSR Reads
   always_comb begin:csrr
-    IllegalCSRSAccessM = 0;
+    IllegalCSRSAccessM = 1'b0;
     case (CSRAdrM) 
       SSTATUS:   CSRSReadValM = SSTATUS_REGW;
       STVEC:     CSRSReadValM = STVEC_REGW;
@@ -150,26 +150,26 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
       STVAL:     CSRSReadValM = STVAL_REGW;
       SATP:      if (P.VIRTMEM_SUPPORTED & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW;
                  else begin
-                   CSRSReadValM = 0;
-                   IllegalCSRSAccessM = 1;
+                   CSRSReadValM = '0;
+                   IllegalCSRSAccessM = 1'b1;
                  end
       SCOUNTEREN:CSRSReadValM = {{(P.XLEN-32){1'b0}}, SCOUNTEREN_REGW};
       SENVCFG:   CSRSReadValM = SENVCFG_REGW;
       STIMECMP:  if (STCE) 
                    CSRSReadValM = STIMECMP_REGW[P.XLEN-1:0]; 
                  else begin 
-                   CSRSReadValM = 0;
-                   IllegalCSRSAccessM = 1;
+                   CSRSReadValM = '0;
+                   IllegalCSRSAccessM = 1'b1;
                  end
       STIMECMPH: if (STCE & P.XLEN == 32) // not supported for RV64
                    CSRSReadValM = {{(P.XLEN-32){1'b0}}, STIMECMP_REGW[63:32]};
                  else begin 
-                   CSRSReadValM = 0;
-                   IllegalCSRSAccessM = 1;
+                   CSRSReadValM = '0;
+                   IllegalCSRSAccessM = 1'b1;
                  end
       default: begin
-                  CSRSReadValM = 0; 
-                  IllegalCSRSAccessM = 1;  
+                  CSRSReadValM = '0; 
+                  IllegalCSRSAccessM = 1'b1;  
                end       
     endcase
   end
diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv
index 58e4aac61..22f34124c 100644
--- a/src/privileged/csrsr.sv
+++ b/src/privileged/csrsr.sv
@@ -7,7 +7,7 @@
 // Purpose: Status register (and environment configuration register and others shared across modes)
 //          See RISC-V Privileged Mode Specification 20190608 
 // 
-// Documentation: RISC-V System on Chip Design Chapter 5
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -66,7 +66,7 @@ module csrsr import cvw::*;  #(parameter cvw_t P) (
                            STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0,
                            STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE,
                           /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0};
-    assign MSTATUSH_REGW = 0; // *** does not exist when XLEN=64, but don't want it to have an undefined value.  Spec is not clear what it should be.
+    assign MSTATUSH_REGW = '0; // does not exist when XLEN=64, and accessing will throw an illegal instruction
   end else begin: csrsr32 // RV32
     assign MSTATUS_REGW  = {STATUS_SD, 8'b0,
                            STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
@@ -89,14 +89,11 @@ module csrsr import cvw::*;  #(parameter cvw_t P) (
     assign nextSBE = STATUS_SBE;
   end
 
-  // harwired STATUS bits
+  // hardwired STATUS bits
   assign STATUS_TSR  = P.S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported
   assign STATUS_TW   = (P.S_SUPPORTED | P.U_SUPPORTED) & STATUS_TW_INT; // override register with 0 if only machine mode supported
   assign STATUS_TVM  = P.S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported
   assign STATUS_MXR  = P.S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported
-/* assign STATUS_UBE = 0; // little-endian
-  assign STATUS_SBE  = 0; // little-endian
-  assign STATUS_MBE  = 0; // little-endian */
   // SXL and UXL bits only matter for RV64.  Set to 10 for RV64 if mode is supported, or 0 if not
   assign STATUS_SXL  = P.S_SUPPORTED ? 2'b10 : 2'b00; // 10 if supervisor mode supported
   assign STATUS_UXL  = P.U_SUPPORTED ? 2'b10 : 2'b00; // 10 if user mode supported
@@ -133,29 +130,29 @@ module csrsr import cvw::*;  #(parameter cvw_t P) (
       endcase
     end
   end else begin: endianmux
-    assign BigEndianM = 0;
+    assign BigEndianM = 1'b0;
   end
 
   // registers for STATUS bits
   // complex register with reset, write enable, and the ability to update other bits in certain cases
   always_ff @(posedge clk) //, posedge reset)
     if (reset) begin
-      STATUS_TSR_INT  <= 0;
-      STATUS_TW_INT   <= 0;
-      STATUS_TVM_INT  <= 0;
-      STATUS_MXR_INT  <= 0;
-      STATUS_SUM_INT  <= 0;
-      STATUS_MPRV_INT <= 0; // Per Priv 3.3
-      STATUS_FS_INT   <= P.F_SUPPORTED ? 2'b00 : 2'b00; // leave floating-point off until activated, even if F_SUPPORTED
-      STATUS_MPP      <= 0; 
-      STATUS_SPP      <= 0; 
-      STATUS_MPIE     <= 0; 
-      STATUS_SPIE     <= 0; 
-      STATUS_MIE      <= 0; 
-      STATUS_SIE      <= 0; 
-      STATUS_MBE      <= 0;
-      STATUS_SBE      <= 0;
-      STATUS_UBE      <= 0;
+      STATUS_TSR_INT  <= 1'b0;
+      STATUS_TW_INT   <= 1'b0;
+      STATUS_TVM_INT  <= 1'b0;
+      STATUS_MXR_INT  <= 1'b0;
+      STATUS_SUM_INT  <= 1'b0;
+      STATUS_MPRV_INT <= 1'b0; // Per Priv 3.3
+      STATUS_FS_INT   <= 2'b00; // leave floating-point off until activated, even if F_SUPPORTED
+      STATUS_MPP      <= 2'b00; 
+      STATUS_SPP      <= 1'b0; 
+      STATUS_MPIE     <= 1'b0; 
+      STATUS_SPIE     <= 1'b0; 
+      STATUS_MIE      <= 1'b0; 
+      STATUS_SIE      <= 1'b0; 
+      STATUS_MBE      <=1'b 0;
+      STATUS_SBE      <= 1'b0;
+      STATUS_UBE      <= 1'b0;
     end else if (~StallW) begin
       if (TrapM) begin
         // Update interrupt enables per Privileged Spec p. 21
@@ -164,23 +161,23 @@ module csrsr import cvw::*;  #(parameter cvw_t P) (
         // Modes: 11 = Machine, 01 = Supervisor, 00 = User
         if (NextPrivilegeModeM == P.M_MODE) begin
           STATUS_MPIE <= STATUS_MIE;
-          STATUS_MIE  <= 0;
+          STATUS_MIE  <= 1'b0;
           STATUS_MPP  <= PrivilegeModeW;
         end else begin // supervisor mode
           STATUS_SPIE <= STATUS_SIE;
-          STATUS_SIE  <= 0;
+          STATUS_SIE  <= 1'b0;
           STATUS_SPP  <= PrivilegeModeW[0];
        end
       end else if (mretM) begin // Privileged 3.1.6.1
         STATUS_MIE      <= STATUS_MPIE; // restore global interrupt enable
-        STATUS_MPIE     <= 1; // 
+        STATUS_MPIE     <= 1'b1; // 
         STATUS_MPP      <= P.U_SUPPORTED ? P.U_MODE : P.M_MODE; // set MPP to lowest supported privilege level
         STATUS_MPRV_INT <= STATUS_MPRV_INT & (STATUS_MPP == P.M_MODE); // page 21 of privileged spec.
       end else if (sretM) begin
         STATUS_SIE      <= STATUS_SPIE; // restore global interrupt enable
         STATUS_SPIE     <= P.S_SUPPORTED; 
-        STATUS_SPP      <= 0; // set SPP to lowest supported privilege level to catch bugs
-        STATUS_MPRV_INT <= 0; // always clear MPRV
+        STATUS_SPP      <= 1'b0; // set SPP to lowest supported privilege level to catch bugs
+        STATUS_MPRV_INT <= 1'b0; // always clear MPRV
       end else if (WriteMSTATUSM) begin
         STATUS_TSR_INT  <= CSRWriteValM[22];
         STATUS_TW_INT   <= CSRWriteValM[21];
diff --git a/src/privileged/csru.sv b/src/privileged/csru.sv
index 37891d009..eeb364a89 100644
--- a/src/privileged/csru.sv
+++ b/src/privileged/csru.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: User-Mode Control and Status Registers for Floating Point
 // 
-// Documentation: RISC-V System on Chip Design Chapter 5
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -66,17 +66,17 @@ module csru import cvw::*;  #(parameter cvw_t P) (
   // CSR Reads
   always_comb begin
     if (STATUS_FS == 2'b00) begin // fpu disabled, trap
-      IllegalCSRUAccessM = 1;
-      CSRUReadValM = 0;
+      IllegalCSRUAccessM = 1'b1;
+      CSRUReadValM = '0;
     end else begin
-      IllegalCSRUAccessM = 0;
+      IllegalCSRUAccessM = 1'b0;
       case (CSRAdrM) 
         FFLAGS:    CSRUReadValM = {{(P.XLEN-5){1'b0}}, FFLAGS_REGW};
         FRM:       CSRUReadValM = {{(P.XLEN-3){1'b0}}, FRM_REGW};
         FCSR:      CSRUReadValM = {{(P.XLEN-8){1'b0}}, FRM_REGW, FFLAGS_REGW};
         default: begin
-                   CSRUReadValM = 0; 
-                   IllegalCSRUAccessM = 1;
+                   CSRUReadValM = '0; 
+                   IllegalCSRUAccessM = 1'b1;
         end         
       endcase
     end
diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv
index cf32c1f28..236db5d30 100644
--- a/src/privileged/privdec.sv
+++ b/src/privileged/privdec.sv
@@ -7,7 +7,7 @@
 // Purpose: Decode Privileged & related instructions 
 //          See RISC-V Privileged Mode Specification 20190608 3.1.10-11
 // 
-// Documentation: RISC-V System on Chip Design Chapter 5
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -30,7 +30,8 @@
 
 module privdec import cvw::*;  #(parameter cvw_t P) (
   input  logic         clk, reset,
-  input  logic         StallW, FlushW, 
+  input  logic         StallW, FlushW,
+  input  logic         ForceBreakPoint,                             // Debug Module initiated break to debug mode
   input  logic [31:15] InstrM,                              // privileged instruction function field
   input  logic         PrivilegedM,                         // is this a privileged instruction (from IEU controller)
   input  logic         IllegalIEUFPUInstrM,                 // Not a legal IEU instruction
@@ -40,13 +41,14 @@ module privdec import cvw::*;  #(parameter cvw_t P) (
   output logic         IllegalInstrFaultM,                  // Illegal instruction
   output logic         EcallFaultM, BreakpointFaultM,       // Ecall or breakpoint; must retire, so don't flush it when the trap occurs
   output logic         sretM, mretM, RetM,                  // return instructions
-  output logic         wfiM, wfiW, sfencevmaM               // wfi / sfence.vma / sinval.vma instructions
+  output logic         wfiM, wfiW, sfencevmaM,              // wfi / sfence.vma / sinval.vma instructions
+  output logic         ebreakM                              // ebreak instruction
 );
 
   logic                rs1zeroM;                            // rs1 field = 0
   logic                IllegalPrivilegedInstrM;             // privileged instruction isn't a legal one or in legal mode
   logic                WFITimeoutM;                         // WFI reaches timeout threshold
-  logic                ebreakM, ecallM;                     // ebreak / ecall instructions
+  logic                ecallM;                              // ecall instructions
   logic                sinvalvmaM;                          // sinval.vma
   logic                sfencewinvalM, sfenceinvalirM;       // sfence.w.inval, sfence.inval.ir
   logic                invalM;                              // any of the svinval instructions
@@ -86,7 +88,7 @@ module privdec import cvw::*;  #(parameter cvw_t P) (
   // WFI Timout trap will not occur when STATUS_TW is low while in supervisor mode, so the system gets stuck waiting for an interrupt and triggers a watchdog timeout.
     assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != P.M_MODE) | (P.S_SUPPORTED & PrivilegeModeW == P.U_MODE)) & WFICount[P.WFI_TIMEOUT_BIT]; 
   // coverage on
-  end else assign WFITimeoutM = 0;
+  end else assign WFITimeoutM = 1'b0;
 
   flopenrc #(1) wfiWReg(clk, reset, FlushW, ~StallW, wfiM, wfiW);
 
@@ -94,7 +96,10 @@ module privdec import cvw::*;  #(parameter cvw_t P) (
   // Extract exceptions by name and handle them 
   ///////////////////////////////////////////
 
-  assign BreakpointFaultM = ebreakM; // could have other causes from a debugger
+  if (P.DEBUG_SUPPORTED)
+    assign BreakpointFaultM = ebreakM | ForceBreakPoint;
+  else
+    assign BreakpointFaultM = ebreakM;
   assign EcallFaultM = ecallM;
 
   ///////////////////////////////////////////
diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv
index 09a56259f..ed4cbfa1b 100644
--- a/src/privileged/privileged.sv
+++ b/src/privileged/privileged.sv
@@ -7,7 +7,7 @@
 // Purpose: Implements the CSRs, Exceptions, and Privileged operations
 //          See RISC-V Privileged Mode Specification 20190608 
 // 
-// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.8)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -49,12 +49,12 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
   input  logic              StoreStallD,                                    // store instruction is stalling
   input  logic              ICacheStallF,                                   // I cache stalled
   input  logic              DCacheStallM,                                   // D cache stalled
-  input  logic              BPDirPredWrongM,                                // branch predictor guessed wrong direction
+  input  logic              BPDirWrongM,                                // branch predictor guessed wrong direction
   input  logic              BTAWrongM,                                      // branch predictor guessed wrong target
   input  logic              RASPredPCWrongM,                                // return adddress stack guessed wrong target
   input  logic              IClassWrongM,                                   // branch predictor guessed wrong instruction class
   input  logic              BPWrongM,                                       // branch predictor is wrong
-  input  logic [3:0]        InstrClassM,                                    // actual instruction class
+  input  logic [3:0]        IClassM,                                    // actual instruction class
   input  logic              DCacheMiss,                                     // data cache miss
   input  logic              DCacheAccess,                                   // data cache accessed (hit or miss)
   input  logic              ICacheMiss,                                     // instruction cache miss
@@ -96,9 +96,28 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
   input  logic              InvalidateICacheM,                              // fence instruction
   output logic              BigEndianM,                                     // Use big endian in current privilege mode
   // Fault outputs                                                         
-  output logic              wfiM, IntPendingM                               // Stall in Memory stage for WFI until interrupt pending or timeout
-);                                                                         
-                                                                           
+  output logic              wfiM, IntPendingM,                              // Stall in Memory stage for WFI until interrupt pending or timeout
+  output logic              ebreakM,                                        // Notifies DM to enter debug mode
+  // Debuge Mode
+  output logic              ebreakEn,
+  input  logic              ForceBreakPoint,
+  input  logic              DebugMode,
+  input  logic [2:0]        DebugCause,
+  output logic              Step,
+  output logic [P.XLEN-1:0] DPC,
+  input  logic              DCall,
+  input  logic              DRet,
+  input  logic              ExecProgBuf,
+  // Debug scan chain
+  input  logic              DebugSel,
+  input  logic [11:0]       DebugRegAddr,
+  input  logic              DebugCapture,
+  input  logic              DebugRegUpdate,
+  input  logic              DebugScanEn,
+  input  logic              DebugScanIn,
+  output logic              DebugScanOut
+);
+
   logic [3:0]               CauseM;                                         // trap cause
   logic [15:0]              MEDELEG_REGW;                                   // exception delegation CSR
   logic [11:0]              MIDELEG_REGW;                                   // interrupt delegation CSR
@@ -127,9 +146,9 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
 
   // decode privileged instructions
   privdec #(P) pmd(.clk, .reset, .StallW, .FlushW, .InstrM(InstrM[31:15]), 
-    .PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM, 
+    .PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM, .ForceBreakPoint,
     .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM, 
-    .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .RetM, .wfiM, .wfiW, .sfencevmaM);
+    .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .RetM, .wfiM, .wfiW, .sfencevmaM, .ebreakM);
 
   // Control and Status Registers
   csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
@@ -137,9 +156,9 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
     .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM,
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
     .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
-    .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM,
+    .BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM,
     .sfencevmaM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
-    .IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
+    .IClassWrongM, .IClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
     .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
     .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
     .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
@@ -147,7 +166,9 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
     .SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
     .SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE,
     .EPCM, .TrapVectorM,
-    .CSRReadValW, .IllegalCSRAccessM, .BigEndianM);
+    .CSRReadValW, .IllegalCSRAccessM, .BigEndianM,
+    .DebugMode, .DebugCause, .ebreakEn, .Step, .DPC, .DCall, .DRet, .ExecProgBuf,
+    .DebugSel, .DebugRegAddr, .DebugCapture, .DebugRegUpdate, .DebugScanEn, .DebugScanIn, .DebugScanOut);
 
   // pipeline early-arriving trap sources
   privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
@@ -161,6 +182,6 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
     .LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
     .LoadPageFaultM, .StoreAmoPageFaultM, .PrivilegeModeW, 
     .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .STATUS_MIE, .STATUS_SIE,
-    .InstrValidM, .CommittedM, .CommittedF,
+    .InstrValidM, .CommittedM, .CommittedF, .DebugMode,
     .TrapM, .wfiM, .wfiW, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM);
 endmodule
diff --git a/src/privileged/privmode.sv b/src/privileged/privmode.sv
index f1c5bfd76..f9a38d501 100644
--- a/src/privileged/privmode.sv
+++ b/src/privileged/privmode.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Track privilege mode.  Change on traps and returns.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 5
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/privileged/privpiperegs.sv b/src/privileged/privpiperegs.sv
index ed43571bd..4cab65c34 100644
--- a/src/privileged/privpiperegs.sv
+++ b/src/privileged/privpiperegs.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Pipeline registers for early exceptions
 // 
-// Documentation: RISC-V System on Chip Design Chapter 5
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv
index db31afa69..c3e564509 100644
--- a/src/privileged/trap.sv
+++ b/src/privileged/trap.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Handle Traps: Exceptions and Interrupts
 // 
-// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -40,6 +40,7 @@ module trap import cvw::*;  #(parameter cvw_t P) (
   input  logic                 STATUS_MIE, STATUS_SIE,                          // machine/supervisor interrupt enables
   input  logic                 InstrValidM,                                     // current instruction is valid, not flushed
   input  logic                 CommittedM, CommittedF,                          // LSU/IFU has committed to a bus operation that can't be interrupted
+  input  logic                 DebugMode,                                       // Ignore all interrupts in debug mode
   output logic                 TrapM,                                           // Trap is occurring
   output logic                 InterruptM,                                      // Interrupt is occurring
   output logic                 ExceptionM,                                      // exception is occurring
@@ -65,8 +66,8 @@ module trap import cvw::*;  #(parameter cvw_t P) (
   assign PendingIntsM  = MIP_REGW & MIE_REGW;
   assign IntPendingM   = |PendingIntsM;
   assign Committed     = CommittedM | CommittedF;
-  assign EnabledIntsM  = (MIntGlobalEnM ? PendingIntsM & ~MIDELEG_REGW : 0) | (SIntGlobalEnM ? PendingIntsM & MIDELEG_REGW : 0);
-  assign ValidIntsM    = Committed ? 0 : EnabledIntsM;
+  assign EnabledIntsM  = (MIntGlobalEnM ? PendingIntsM & ~MIDELEG_REGW : '0) | (SIntGlobalEnM ? PendingIntsM & MIDELEG_REGW : '0);
+  assign ValidIntsM    = (Committed | DebugMode) ? '0 : EnabledIntsM;
   assign InterruptM    = (|ValidIntsM) & InstrValidM & (~wfiM | wfiW); // suppress interrupt if the memory system has partially processed a request. Delay interrupt until wfi is in the W stage. 
   // wfiW is to support possible but unlikely back to back wfi instructions. wfiM would be high in the M stage, while also in the W stage.
   assign DelegateM     = P.S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) & 
@@ -88,36 +89,38 @@ module trap import cvw::*;  #(parameter cvw_t P) (
                       BreakpointFaultM | EcallFaultM |
                       LoadAccessFaultM | StoreAmoAccessFaultM;
   // coverage on
-  assign TrapM = (ExceptionM & ~CommittedF) | InterruptM; // *** RT: review this additional ~CommittedF with DH and update priv chapter.
+  //assign TrapM = (ExceptionM & ~CommittedF) | InterruptM;
+  // Debug Test
+  assign TrapM = DebugMode ? BreakpointFaultM : (ExceptionM & ~CommittedF) | InterruptM;
 
   ///////////////////////////////////////////
   // Cause priority defined in privileged spec
   ///////////////////////////////////////////
 
   always_comb
-    if      (reset)                    CauseM = 0; // hard reset 3.3
-    else if (ValidIntsM[11])           CauseM = 11; // Machine External Int
-    else if (ValidIntsM[3])            CauseM = 3;  // Machine Sw Int
-    else if (ValidIntsM[7])            CauseM = 7;  // Machine Timer Int
-    else if (ValidIntsM[9])            CauseM = 9;  // Supervisor External Int 
-    else if (ValidIntsM[1])            CauseM = 1;  // Supervisor Sw Int       
-    else if (ValidIntsM[5])            CauseM = 5;  // Supervisor Timer Int    
-    else if (BothInstrPageFaultM)      CauseM = 12;
-    else if (BothInstrAccessFaultM)    CauseM = 1;
-    else if (IllegalInstrFaultM)       CauseM = 2;
+    if      (reset)                    CauseM = 4'd0;  // hard reset 3.3
+    else if (ValidIntsM[11])           CauseM = 4'd11; // Machine External Int
+    else if (ValidIntsM[3])            CauseM = 4'd3;  // Machine Sw Int
+    else if (ValidIntsM[7])            CauseM = 4'd7;  // Machine Timer Int
+    else if (ValidIntsM[9])            CauseM = 4'd9;  // Supervisor External Int 
+    else if (ValidIntsM[1])            CauseM = 4'd1;  // Supervisor Sw Int       
+    else if (ValidIntsM[5])            CauseM = 4'd5;  // Supervisor Timer Int    
+    else if (BothInstrPageFaultM)      CauseM = 4'd12;
+    else if (BothInstrAccessFaultM)    CauseM = 4'd1;
+    else if (IllegalInstrFaultM)       CauseM = 4'd2;
     // coverage off
     // Misaligned instructions cannot occur in rv64gc
-    else if (InstrMisalignedFaultM)    CauseM = 0;
+    else if (InstrMisalignedFaultM)    CauseM = 4'd0;
     // coverage on
-    else if (BreakpointFaultM)         CauseM = 3;
+    else if (BreakpointFaultM)         CauseM = 4'd3;
     else if (EcallFaultM)              CauseM = {2'b10, PrivilegeModeW};
-    else if (StoreAmoMisalignedFaultM & ~P.ZICCLSM_SUPPORTED) CauseM = 6;  // misaligned faults are higher priority if they always are taken
-    else if (LoadMisalignedFaultM & ~P.ZICCLSM_SUPPORTED)     CauseM = 4;
-    else if (StoreAmoPageFaultM)       CauseM = 15;
-    else if (LoadPageFaultM)           CauseM = 13;
-    else if (StoreAmoAccessFaultM)     CauseM = 7;
-    else if (LoadAccessFaultM)         CauseM = 5;
-    else if (StoreAmoMisalignedFaultM & P.ZICCLSM_SUPPORTED) CauseM = 6; // See priority in Privileged Spec 3.1.15
-    else if (LoadMisalignedFaultM & P.ZICCLSM_SUPPORTED)     CauseM = 4;
-    else                               CauseM = 0;
+    else if (StoreAmoMisalignedFaultM & ~P.ZICCLSM_SUPPORTED) CauseM = 4'd6;  // misaligned faults are higher priority if they always are taken
+    else if (LoadMisalignedFaultM & ~P.ZICCLSM_SUPPORTED)     CauseM = 4'd4;
+    else if (StoreAmoPageFaultM)       CauseM = 4'd15;
+    else if (LoadPageFaultM)           CauseM = 4'd13;
+    else if (StoreAmoAccessFaultM)     CauseM = 4'd7;
+    else if (LoadAccessFaultM)         CauseM = 4'd5;
+    else if (StoreAmoMisalignedFaultM & P.ZICCLSM_SUPPORTED) CauseM = 4'd6; // See priority in Privileged Spec 3.1.15
+    else if (LoadMisalignedFaultM & P.ZICCLSM_SUPPORTED)     CauseM = 4'd4;
+    else                               CauseM = 4'd0;
 endmodule
diff --git a/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv
index dc7ceeab3..84979ddee 100644
--- a/src/uncore/ahbapbbridge.sv
+++ b/src/uncore/ahbapbbridge.sv
@@ -5,7 +5,7 @@
 //
 // Purpose: AHB to APB bridge
 // 
-// Documentation: RISC-V System on Chip Design Chapter 6
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -89,7 +89,7 @@ module ahbapbbridge import cvw::*;  #(parameter cvw_t P,
   int i;
   always_comb begin
     // default: no peripheral selected: read 0, indicate ready during access phase so bus doesn't hang
-    HRDATA = 0;
+    HRDATA = '0;
     PREADYOUT = 1'b1; 
     for (i=0; i<PERIPHS; i++)  begin
       if (PSEL[i]) begin // highest numbered peripheral has priority, but multiple PSEL should never be asserted
@@ -101,5 +101,5 @@ module ahbapbbridge import cvw::*;  #(parameter cvw_t P,
 assign HREADYOUT = PREADYOUT & ~initTransSelD; // don't raise HREADYOUT before access phase
 
   // resp logic
-  assign HRESP = 0; // bridge never indicates errors
+  assign HRESP = 1'b0; // bridge never indicates errors
 endmodule
diff --git a/src/uncore/bsg_dmc_config_apb.sv b/src/uncore/bsg_dmc_config_apb.sv
new file mode 100644
index 000000000..82107717a
--- /dev/null
+++ b/src/uncore/bsg_dmc_config_apb.sv
@@ -0,0 +1,162 @@
+///////////////////////////////////////////
+// bsg_dmc_config_apb.sv
+//
+// Written: infinitymdm@gmail.com 3 June 2024
+//
+// Purpose: Synchronized configuration registers for BSG memory controller
+// 
+// Documentation: 
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module bsg_dmc_config_apb #(parameter APB_DATA_SIZE = 64) (
+  input  logic                     PCLK, PRESETn,
+  input  logic                     PSEL,
+  input  logic [7:0]               PADDR,
+  input  logic [APB_DATA_SIZE-1:0] PWDATA,
+  input  logic                     PWRITE,
+  input  logic                     PENABLE,
+  output logic [APB_DATA_SIZE-1:0] PRDATA,
+  output logic                     PREADY,
+  input  logic                     ui_clk,
+  output logic [15:0]              dmc_trefi,
+  output logic [3:0]               dmc_tmrd,
+  output logic [3:0]               dmc_trfc,
+  output logic [3:0]               dmc_trc,
+  output logic [3:0]               dmc_trp,
+  output logic [3:0]               dmc_tras,
+  output logic [3:0]               dmc_trrd,
+  output logic [3:0]               dmc_trcd,
+  output logic [3:0]               dmc_twr,
+  output logic [3:0]               dmc_twtr,
+  output logic [3:0]               dmc_trtp,
+  output logic [3:0]               dmc_tcas,
+  output logic [3:0]               dmc_col_width,
+  output logic [3:0]               dmc_row_width,
+  output logic [1:0]               dmc_bank_width,
+  output logic [5:0]               dmc_bank_pos,
+  output logic [2:0]               dmc_dqs_sel_cal,
+  output logic [15:0]              dmc_init_cycles,
+  output logic                     dmc_config_changed
+);
+
+  logic [7:0]   entry, wentry;
+  logic         wren;
+  logic [15:0]  wdata;
+  logic [15:0]  rdata;
+  logic         fifo_full, fifo_deq;
+
+  assign entry  = {PADDR[7:3], 3'b0};
+  assign PREADY = ~fifo_full;
+
+  // Send writes to ui_clk domain
+  assign wren = PWRITE & PENABLE & PSEL;
+  bsg_async_fifo #(
+    .lg_size_p(3),
+    .width_p(8 + 16) // entry + data
+  ) dmc_config_fifo (
+    .w_clk_i(PCLK),
+    .w_reset_i(~PRESETn),
+    .w_enq_i(wren),
+    .w_data_i({entry, PWDATA[15:0]}),
+    .w_full_o(fifo_full),
+    .r_clk_i(ui_clk),
+    .r_reset_i(~PRESETn),
+    .r_deq_i(fifo_deq & dmc_config_changed),
+    .r_data_o({wentry, wdata}),
+    .r_valid_o(dmc_config_changed)
+  );
+  flopr #(1) deqreg (ui_clk, ~PRESETn, dmc_config_changed, fifo_deq);
+
+  // Write on ui_clk with async reset
+  always_ff @(posedge ui_clk, negedge PRESETn) begin
+    if (~PRESETn) begin
+      // TODO: Should these be reset to Micron defaults instead?
+      dmc_trefi        <= 0;
+      dmc_tmrd         <= 0;
+      dmc_trfc         <= 0;
+      dmc_trc          <= 0;
+      dmc_trp          <= 0;
+      dmc_tras         <= 0;
+      dmc_trrd         <= 0;
+      dmc_trcd         <= 0;
+      dmc_twr          <= 0;
+      dmc_twtr         <= 0;
+      dmc_trtp         <= 0;
+      dmc_tcas         <= 0;
+      dmc_col_width    <= 0;
+      dmc_row_width    <= 0;
+      dmc_bank_width   <= 0;
+      dmc_bank_pos     <= 0;
+      dmc_dqs_sel_cal  <= 0;
+      dmc_init_cycles  <= 0;
+    end else begin
+      if (dmc_config_changed) begin
+        case (wentry)
+          8'h00: dmc_trefi       <= wdata;
+          8'h08: dmc_tmrd        <= wdata[3:0];
+          8'h10: dmc_trfc        <= wdata[3:0];
+          8'h18: dmc_trc         <= wdata[3:0];
+          8'h20: dmc_trp         <= wdata[3:0];
+          8'h28: dmc_tras        <= wdata[3:0];
+          8'h30: dmc_trrd        <= wdata[3:0];
+          8'h38: dmc_trcd        <= wdata[3:0];
+          8'h40: dmc_twr         <= wdata[3:0];
+          8'h48: dmc_twtr        <= wdata[3:0];
+          8'h50: dmc_trtp        <= wdata[3:0];
+          8'h58: dmc_tcas        <= wdata[3:0];
+          8'h60: dmc_col_width   <= wdata[3:0];
+          8'h68: dmc_row_width   <= wdata[3:0];
+          8'h70: dmc_bank_width  <= wdata[1:0];
+          8'h78: dmc_bank_pos    <= wdata[5:0];
+          8'h80: dmc_dqs_sel_cal <= wdata[2:0];
+          8'h88: dmc_init_cycles <= wdata;
+        endcase
+      end
+    end
+  end
+
+  // Read on PCLK
+  assign PRDATA = {{APB_DATA_SIZE-17{1'b0}}, rdata};
+  always_ff @(posedge PCLK) begin
+    case (entry)
+      8'h00:   rdata <=         dmc_trefi;
+      8'h08:   rdata <= {12'b0, dmc_tmrd};
+      8'h10:   rdata <= {12'b0, dmc_trfc};
+      8'h18:   rdata <= {12'b0, dmc_trc};
+      8'h20:   rdata <= {12'b0, dmc_trp};
+      8'h28:   rdata <= {12'b0, dmc_tras};
+      8'h30:   rdata <= {12'b0, dmc_trrd};
+      8'h38:   rdata <= {12'b0, dmc_trcd};
+      8'h40:   rdata <= {12'b0, dmc_twr};
+      8'h48:   rdata <= {12'b0, dmc_twtr};
+      8'h50:   rdata <= {12'b0, dmc_trtp};
+      8'h58:   rdata <= {12'b0, dmc_tcas};
+      8'h60:   rdata <= {12'b0, dmc_col_width};
+      8'h68:   rdata <= {12'b0, dmc_row_width};
+      8'h70:   rdata <= {14'b0, dmc_bank_width};
+      8'h78:   rdata <= {10'b0, dmc_bank_pos};
+      8'h80:   rdata <= {13'b0, dmc_dqs_sel_cal};
+      8'h88:   rdata <=         dmc_init_cycles;
+      default: rdata <= 0;
+    endcase
+  end
+
+endmodule
diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv
index 997c1bd39..76735aaa6 100644
--- a/src/uncore/clint_apb.sv
+++ b/src/uncore/clint_apb.sv
@@ -7,7 +7,7 @@
 // Purpose: Core-Local Interruptor
 //   See FE310-G002-Manual-v19p05 for specifications
 // 
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -42,6 +42,11 @@ module clint_apb import cvw::*;  #(parameter cvw_t P) (
   output logic                MTimerInt, MSwInt
 );
 
+  // register map
+  localparam CLINT_MSIP     = 16'h0000;
+  localparam CLINT_MTIMECMP = 16'h4000;
+  localparam CLINT_MTIME    = 16'hBFF8;
+
   logic                       MSIP;
   logic [15:0]                entry;
   logic                       memwrite;
@@ -65,31 +70,31 @@ module clint_apb import cvw::*;  #(parameter cvw_t P) (
   if (P.XLEN==64) begin:clint // 64-bit
     always_ff @(posedge PCLK) begin
       case(entry)
-        16'h0000: PRDATA <= {63'b0, MSIP};
-        16'h4000: PRDATA <= MTIMECMP;
-        16'hBFF8: PRDATA <= MTIME;
-        default:  PRDATA <= 0;
+        CLINT_MSIP:     PRDATA <= {63'b0, MSIP};
+        CLINT_MTIMECMP: PRDATA <= MTIMECMP;
+        CLINT_MTIME:    PRDATA <= MTIME;
+        default:        PRDATA <= '0;
       endcase
     end 
-    always_ff @(posedge PCLK or negedge PRESETn) 
+    always_ff @(posedge PCLK) 
       if (~PRESETn) begin
-        MSIP <= 0;
+        MSIP <= 1'b0;
         MTIMECMP <= 64'hFFFFFFFFFFFFFFFF; // Spec says MTIMECMP is not reset, but we reset to maximum value to prevent spurious timer interrupts
       end else if (memwrite) begin
-        if (entry == 16'h0000) MSIP <= PWDATA[0];
-        if (entry == 16'h4000) begin
+        if (entry == CLINT_MSIP) MSIP <= PWDATA[0];
+        if (entry == CLINT_MTIMECMP) begin
           for(i=0;i<P.XLEN/8;i++)
             if(PSTRB[i])
-              MTIMECMP[i*8 +: 8] <= PWDATA[i*8 +: 8]; // ***dh: this notation isn't in book yet - maybe from Ross
+              MTIMECMP[i*8 +: 8] <= PWDATA[i*8 +: 8];
         end
       end
 
 // eventually replace MTIME logic below with timereg
 //    timereg tr(PCLK, PRESETn, TIMECLK, memwrite & (entry==16'hBFF8), 1'b0, PWDATA, MTIME, done);
 
-    always_ff @(posedge PCLK or negedge PRESETn) 
+    always_ff @(posedge PCLK) 
       if (~PRESETn) begin
-        MTIME <= 0;
+        MTIME <= '0;
       end else if (memwrite & entry == 16'hBFF8) begin
         // MTIME Counter.  Eventually change this to run off separate clock.  Synchronization then needed
         for(j=0;j<P.XLEN/8;j++)
@@ -104,14 +109,13 @@ module clint_apb import cvw::*;  #(parameter cvw_t P) (
         16'h4004: PRDATA <= MTIMECMP[63:32];
         16'hBFF8: PRDATA <= MTIME[31:0];
         16'hBFFC: PRDATA <= MTIME[63:32];
-        default:  PRDATA <= 0;
+        default:  PRDATA <= '0;
       endcase
     end 
-    always_ff @(posedge PCLK or negedge PRESETn) 
+    always_ff @(posedge PCLK) 
       if (~PRESETn) begin
-        MSIP <= 0;
-        MTIMECMP <= 0;
-        // MTIMECMP is not reset ***?
+        MSIP <= 1'b0;
+        MTIMECMP <= '0;
       end else if (memwrite) begin
         if (entry == 16'h0000) MSIP <= PWDATA[0];
         if (entry == 16'h4000) 
@@ -127,9 +131,9 @@ module clint_apb import cvw::*;  #(parameter cvw_t P) (
 
 // eventually replace MTIME logic below with timereg
 //     timereg tr(PCLK, PRESETn, TIMECLK, memwrite & (entry==16'hBFF8), memwrite & (entry == 16'hBFFC), PWDATA, MTIME, done);
-    always_ff @(posedge PCLK or negedge PRESETn) 
+    always_ff @(posedge PCLK) 
       if (~PRESETn) begin
-        MTIME <= 0;
+        MTIME <= '0;
         // MTIMECMP is not reset
       end else if (memwrite & (entry == 16'hBFF8)) begin
         for(i=0;i<P.XLEN/8;i++)
@@ -159,12 +163,12 @@ module timeregsync  import cvw::*;  #(parameter cvw_t P) (
 
   if (P.XLEN==64) 
     always_ff @(posedge clk or negedge resetn) 
-      if (~resetn)  q <= 0;
+      if (~resetn)  q <= '0;
       else if (we0) q <= wd;
       else          q <= q + 1;
   else
     always_ff @(posedge clk or negedge resetn) 
-      if (~resetn)  q <= 0;
+      if (~resetn)  q <= '0;
       else if (we0) q[31:0] <= wd;
       else if (we1) q[63:32] <= wd;
       else          q <= q + 1;
@@ -190,7 +194,7 @@ module timereg  import cvw::*;  #(parameter cvw_t P) (
     // Synchronizing this for a read is safe because we are guaranteed to get either the old or the new value.
     // Writing to the counter requires a request/acknowledge handshake to ensure the write value is held long enough.
     // The handshake signals are synchronized in each direction across the interface
-    // There is no back pressure on instructions, so if multiple counter writes occur ***
+    // There is no back pressure on instructions, so if multiple counter writes occur too close together, the results are unpredictable.
 
     logic req, req_sync, ack, we0_stored, we1_stored, ack_stored, resetn_sync;
     logic [P.XLEN-1:0] wd_stored;
@@ -198,7 +202,7 @@ module timereg  import cvw::*;  #(parameter cvw_t P) (
 
     // When a write enable is asserted for a cycle, sample the enables and data and raise a request until it is acknowledged
     // When the acknowledge falls, the transaction is done and the system is ready for another write.
-    // ***look at redoing this assuming write enable and data are held rather than pulsed.
+    // When adding asynchronous timebase, look at redoing this assuming write enable and data are held rather than pulsed.
     always_ff @(posedge PCLK or negedge PRESETn) 
       if (~PRESETn) 
         req <= 0; // don't bother resetting wd
@@ -247,4 +251,4 @@ module graytobinary #(parameter N) (
       assign b[i] = g[i] ^ b[i+1];
     end
 endmodule
-*/
\ No newline at end of file
+*/
diff --git a/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv
index 430b44111..7721d9986 100644
--- a/src/uncore/gpio_apb.sv
+++ b/src/uncore/gpio_apb.sv
@@ -8,7 +8,7 @@
 //   See FE310-G002-Manual-v19p05 for specifications
 //   No interrupts, drive strength, or pull-ups supported
 // 
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -45,6 +45,23 @@ module gpio_apb import cvw::*;  #(parameter cvw_t P) (
   output logic                GPIOIntr
 );
 
+  // register map
+  localparam GPIO_INPUT_VAL  = 8'h00;
+  localparam GPIO_INPUT_EN   = 8'h04;
+  localparam GPIO_OUTPUT_EN  = 8'h08;
+  localparam GPIO_OUTPUT_VAL = 8'h0C;
+  localparam GPIO_RISE_IE    = 8'h18;
+  localparam GPIO_RISE_IP    = 8'h1C;
+  localparam GPIO_FALL_IE    = 8'h20;
+  localparam GPIO_FALL_IP    = 8'h24;
+  localparam GPIO_HIGH_IE    = 8'h28;
+  localparam GPIO_HIGH_IP    = 8'h2C;
+  localparam GPIO_LOW_IE     = 8'h30;
+  localparam GPIO_LOW_IP     = 8'h34;
+  localparam GPIO_IOF_EN     = 8'h38;
+  localparam GPIO_IOF_SEL    = 8'h3C;
+  localparam GPIO_OUT_XOR    = 8'h40;
+
   logic [31:0]                input0d, input1d, input2d, input3d;
   logic [31:0]                input_val, input_en, output_en, output_val;
   logic [31:0]                rise_ie, rise_ip, fall_ie, fall_ip, high_ie, high_ip, low_ie, low_ip; 
@@ -65,68 +82,67 @@ module gpio_apb import cvw::*;  #(parameter cvw_t P) (
   else              assign PRDATA = Dout;    
 
   // register access
-  always_ff @(posedge PCLK, negedge PRESETn)
-    if (~PRESETn) begin // asynch reset
-      input_en  <= 0;
-      output_en <= 0;
-      // *** synch reset not yet implemented [DH: can we delete this comment?  Check if a sync reset is required]
-      output_val <= 0;
-      rise_ie    <= 0;
-      rise_ip    <= 0;
-      fall_ie    <= 0;
-      fall_ip    <= 0;
-      high_ie    <= 0;
-      high_ip    <= 0;
-      low_ie     <= 0;
-      low_ip     <= 0;
-      iof_en     <= 0;
-      iof_sel    <= 0;
-      out_xor    <= 0;
+  always_ff @(posedge PCLK)
+    if (~PRESETn) begin
+      input_en  <= '0;
+      output_en <= '0;
+      output_val <= '0;
+      rise_ie    <= '0;
+      rise_ip    <= '0;
+      fall_ie    <= '0;
+      fall_ip    <= '0;
+      high_ie    <= '0;
+      high_ip    <= '0;
+      low_ie     <= '0;
+      low_ip     <= '0;
+      iof_en     <= '0;
+      iof_sel    <= '0;
+      out_xor    <= '0;
     end else begin     // writes
         // According to FE310 spec: Once the interrupt is pending, it will remain set until a 1 is written to the *_ip register at that bit.
         /* verilator lint_off CASEINCOMPLETE */
       if (memwrite) 
         case(entry)
-          8'h04: input_en   <= Din;
-          8'h08: output_en  <= Din;
-          8'h0C: output_val <= Din;
-          8'h18: rise_ie    <= Din;
-          8'h20: fall_ie    <= Din;
-          8'h28: high_ie    <= Din;
-          8'h30: low_ie     <= Din;
-          8'h38: iof_en     <= Din;
-          8'h3C: iof_sel    <= Din;
-          8'h40: out_xor    <= Din;
+          GPIO_INPUT_EN:   input_en   <= Din;
+          GPIO_OUTPUT_EN:  output_en  <= Din;
+          GPIO_OUTPUT_VAL: output_val <= Din;
+          GPIO_RISE_IE:    rise_ie    <= Din;
+          GPIO_FALL_IE:    fall_ie    <= Din;
+          GPIO_HIGH_IE:    high_ie    <= Din;
+          GPIO_LOW_IE:     low_ie     <= Din;
+          GPIO_IOF_EN:     iof_en     <= Din;
+          GPIO_IOF_SEL:    iof_sel    <= Din;
+          GPIO_OUT_XOR:    out_xor    <= Din;
         endcase
         /* verilator lint_on CASEINCOMPLETE */
 
       // interrupts can be cleared by writing corresponding bits to a register
-      if (memwrite & entry == 8'h1C)   rise_ip <= rise_ip & ~Din;
-      else                             rise_ip <= rise_ip | (input2d & ~input3d);
-      if (memwrite & (entry == 8'h24)) fall_ip <= fall_ip & ~Din;
-      else                             fall_ip <= fall_ip | (~input2d & input3d);
-      if (memwrite & (entry == 8'h2C)) high_ip <= high_ip & ~Din;
-      else                             high_ip <= high_ip | input3d;
-      if (memwrite & (entry == 8'h34)) low_ip  <= low_ip  & ~Din;
-      else                             low_ip  <= low_ip  | ~input3d;
+      if (memwrite & entry == GPIO_RISE_IP)   rise_ip <= rise_ip & ~Din;
+      else                                    rise_ip <= rise_ip | (input2d & ~input3d);
+      if (memwrite & (entry == GPIO_FALL_IP)) fall_ip <= fall_ip & ~Din;
+      else                                    fall_ip <= fall_ip | (~input2d & input3d);
+      if (memwrite & (entry == GPIO_HIGH_IP)) high_ip <= high_ip & ~Din;
+      else                                    high_ip <= high_ip | input3d;
+      if (memwrite & (entry == GPIO_LOW_IP))  low_ip  <= low_ip  & ~Din;
+      else                                    low_ip  <= low_ip  | ~input3d;
 
       case(entry) // flop to sample inputs
-        8'h00: Dout   <= input_val;
-        8'h04: Dout   <= input_en;
-        8'h08: Dout   <= output_en;
-        8'h0C: Dout   <= output_val;
-        8'h18: Dout   <= rise_ie;
-        8'h1C: Dout   <= rise_ip;
-        8'h20: Dout   <= fall_ie;
-        8'h24: Dout   <= fall_ip;
-        8'h28: Dout   <= high_ie;
-        8'h2C: Dout   <= high_ip;
-        8'h30: Dout   <= low_ie;
-        8'h34: Dout   <= low_ip;
-        8'h38: Dout   <= iof_en;
-        8'h3C: Dout   <= iof_sel;
-        8'h40: Dout   <= out_xor; 
-        default: Dout <= 0;
+        GPIO_INPUT_VAL:   Dout <= input_val;
+        GPIO_INPUT_EN:    Dout <= input_en;
+        GPIO_OUTPUT_EN:   Dout <= output_en;
+        GPIO_OUTPUT_VAL:  Dout <= output_val;
+        GPIO_RISE_IE:     Dout <= rise_ie;
+        GPIO_RISE_IP:     Dout <= rise_ip;
+        GPIO_FALL_IE:     Dout <= fall_ie;
+        GPIO_FALL_IP:     Dout <= fall_ip;
+        GPIO_HIGH_IE:     Dout <= high_ie;
+        GPIO_HIGH_IP:     Dout <= high_ip;
+        GPIO_LOW_IE:      Dout <= low_ie;
+        GPIO_LOW_IP:      Dout <= low_ip;
+        GPIO_IOF_EN:      Dout <= iof_en;
+        GPIO_IOF_SEL:     Dout <= iof_sel;
+        GPIO_OUT_XOR:     Dout <= out_xor; 
+        default:          Dout <= '0;
       endcase
     end
 
diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv
index 2fdbb947b..607994906 100644
--- a/src/uncore/plic_apb.sv
+++ b/src/uncore/plic_apb.sv
@@ -11,7 +11,7 @@
 //   This PLIC implementation serves as both the PLIC Gateways and PLIC Core.
 //   It assumes interrupt sources are level-triggered wires.
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -54,6 +54,19 @@ module plic_apb import cvw::*;  #(parameter cvw_t P) (
   output logic                MExtInt, SExtInt
 );
 
+  // register map
+  localparam PLIC_INTPRIORITY0   = 24'h000000;
+  localparam PLIC_INTPENDING0    = 24'h001000;
+  localparam PLIC_INTPENDING1    = 24'h001004;
+  localparam PLIC_INTEN00        = 24'h002000;
+  localparam PLIC_INTEN01        = 24'h002004;
+  localparam PLIC_INTEN10        = 24'h002080;
+  localparam PLIC_INTEN11        = 24'h002084;
+  localparam PLIC_THRESHOLD0     = 24'h200000;
+  localparam PLIC_CLAIMCOMPLETE0 = 24'h200004;
+  localparam PLIC_THRESHOLD1     = 24'h201000;
+  localparam PLIC_CLAIMCOMPLETE1 = 24'h201004;
+
   logic                       memwrite, memread;
   logic [23:0]                entry;
   logic [31:0]                Din, Dout;
@@ -91,7 +104,7 @@ module plic_apb import cvw::*;  #(parameter cvw_t P) (
   assign memread  = ~PWRITE & PSEL;           // read at start of access phase.  PENABLE hasn't set up before this
   assign PREADY   = 1'b1;                     // PLIC never takes >1 cycle to respond
   assign entry    = {PADDR[23:2],2'b0};
-  assign One[P.PLIC_NUM_SRC-1:1] = 0; assign One[0] = 1'b1; // Vivado does not like this as a single assignment.
+  assign One[P.PLIC_NUM_SRC-1:1] = '0; assign One[0] = 1'b1; // Vivado does not like this as a single assignment.
 
   // account for subword read/write circuitry
   // -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
@@ -107,48 +120,49 @@ module plic_apb import cvw::*;  #(parameter cvw_t P) (
   always_ff @(posedge PCLK) begin
     // resetting
     if (~PRESETn) begin
-      intPriority   <= 0;
-      intEn         <= 0;
-      intThreshold  <= 0;
-      intInProgress <= 0;
+      intPriority   <= '0;
+      intEn         <= '0;
+      intThreshold  <= '0;
+      intInProgress <= '0;
     // writing
     end else begin
       if (memwrite)        
         casez(entry)
-          24'h0000??: intPriority[entry[7:2]] <= Din[2:0];
-          24'h002000: intEn[0][PLIC_NUM_SRC_MIN_32:1] <= Din[PLIC_NUM_SRC_MIN_32:1];
-          24'h002080: intEn[1][PLIC_NUM_SRC_MIN_32:1] <= Din[PLIC_NUM_SRC_MIN_32:1];
-          24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT]         <= Din[PLIC_SRC_DINTOP:0];
-          24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT]         <= Din[PLIC_SRC_DINTOP:0];
-          24'h200000: intThreshold[0]         <= Din[2:0];
-          24'h200004: intInProgress           <= intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion 
-          24'h201000: intThreshold[1]         <= Din[2:0];
-          24'h201004: intInProgress           <= intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion 
+          24'h0000??:          intPriority[entry[7:2]] <= Din[2:0];
+          PLIC_INTEN00:        intEn[0][PLIC_NUM_SRC_MIN_32:1] <= Din[PLIC_NUM_SRC_MIN_32:1];
+          PLIC_INTEN10:        intEn[1][PLIC_NUM_SRC_MIN_32:1] <= Din[PLIC_NUM_SRC_MIN_32:1];
+          PLIC_INTEN01:        if (P.PLIC_NUM_SRC >= 32) intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT]         <= Din[PLIC_SRC_DINTOP:0];
+          PLIC_INTEN11:        if (P.PLIC_NUM_SRC >= 32) intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT]         <= Din[PLIC_SRC_DINTOP:0];
+          PLIC_THRESHOLD0:     intThreshold[0]         <= Din[2:0];
+          PLIC_CLAIMCOMPLETE0: intInProgress           <= intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion 
+          PLIC_THRESHOLD1:     intThreshold[1]         <= Din[2:0];
+          PLIC_CLAIMCOMPLETE1: intInProgress           <= intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion 
         endcase
+
       // Read synchronously because a read can have side effect of changing intInProgress
       if (memread) begin
         casez(entry)
-          24'h000000: Dout <= 32'b0;  // there is no intPriority[0]
-          24'h0000??: Dout <= {29'b0,intPriority[entry[7:2]]};      
-          24'h001000: Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intPending[PLIC_NUM_SRC_MIN_32:1],1'b0};
-          24'h002000: Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[0][PLIC_NUM_SRC_MIN_32:1],1'b0};
-          24'h001004: if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intPending[PLIC_SRC_TOP:PLIC_SRC_BOT]};
-          24'h002004: if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT]};
-          24'h002080: Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[1][PLIC_NUM_SRC_MIN_32:1],1'b0};
-          24'h002084: if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT]};
-          24'h200000: Dout <= {29'b0,intThreshold[0]};
-          24'h200004: begin
+          PLIC_INTPRIORITY0: Dout <= 32'b0;  // there is no intPriority[0]
+          24'h0000??:        Dout <= {29'b0,intPriority[entry[7:2]]};      
+          PLIC_INTPENDING0:  Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intPending[PLIC_NUM_SRC_MIN_32:1],1'b0};
+          PLIC_INTEN00:      Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[0][PLIC_NUM_SRC_MIN_32:1],1'b0};
+          PLIC_INTPENDING1:  if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intPending[PLIC_SRC_TOP:PLIC_SRC_BOT]};
+          PLIC_INTEN01:      if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT]};
+          PLIC_INTEN10:      Dout <= {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[1][PLIC_NUM_SRC_MIN_32:1],1'b0};
+          PLIC_INTEN11:      if (P.PLIC_NUM_SRC >= 32) Dout <= {{(PLIC_SRC_EXT){1'b0}},intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT]};
+          PLIC_THRESHOLD0:   Dout <= {29'b0,intThreshold[0]};
+          PLIC_CLAIMCOMPLETE0: begin
             Dout <= {26'b0,intClaim[0]};
             intInProgress <= intInProgress | (One << (intClaim[0]-1)); // claimed requests are currently in progress of being serviced until they are completed
           end
-          24'h201000: Dout <= {29'b0,intThreshold[1]};
-          24'h201004: begin
+          PLIC_THRESHOLD1:   Dout <= {29'b0,intThreshold[1]};
+          PLIC_CLAIMCOMPLETE1: begin
             Dout <= {26'b0,intClaim[1]};
             intInProgress <= intInProgress | (One << (intClaim[1]-1)); // claimed requests are currently in progress of being serviced until they are completed
           end
-          default: Dout <= 32'h0; // invalid access
+          default:           Dout <= 32'h0; // invalid access
         endcase
-      end else Dout <= 32'h0;
+      end else               Dout <= 32'h0;
    end
   end
 
diff --git a/src/uncore/pll_config_apb.sv b/src/uncore/pll_config_apb.sv
new file mode 100644
index 000000000..80694fabd
--- /dev/null
+++ b/src/uncore/pll_config_apb.sv
@@ -0,0 +1,152 @@
+///////////////////////////////////////////
+// pll_config_apb.sv
+//
+// Written: infinitymdm@gmail.com 3 June 2024
+//
+// Purpose: Synchronized configuration registers for PLL
+// 
+// Documentation: 
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+// 
+// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module pll_config_apb #(
+  parameter APB_DATA_SIZE = 64
+) (
+  input  logic                     PCLK, PRESETn,
+  input  logic                     PSEL,
+  input  logic [7:0]               PADDR,
+  input  logic [APB_DATA_SIZE-1:0] PWDATA,
+  input  logic                     PWRITE,
+  input  logic                     PENABLE,
+  output logic [APB_DATA_SIZE-1:0] PRDATA,
+  output logic                     PREADY,
+  input  logic                     PLLrefclk,
+  input  logic                     PLLrfen,
+  input  logic                     PLLfben,
+  output logic [5:0]               PLLclkr,
+  output logic [12:0]              PLLclkf,
+  output logic [3:0]               PLLclkod,
+  output logic [11:0]              PLLbwadj,
+  output logic                     PLLtest,
+  output logic                     PLLfasten,
+  input  logic                     PLLlock,
+  output logic                     PLLconfigdone
+);
+
+  logic [7:0]  entry;
+  logic        wren;
+  logic [12:0] wdata;
+  logic [12:0] rdata;
+  logic [5:0]  wcode;
+  logic        clkr_en,  clkf_en,  clkod_en,  bwadj_en,  test_en,  fasten_en;
+  logic        clkr_rdy, clkf_rdy, clkod_rdy, bwadj_rdy, test_rdy, fasten_rdy;
+
+  assign entry  = {PADDR[7:3], 3'b0};
+  assign wren   = PWRITE & PENABLE & PSEL;
+  assign PREADY = clkr_rdy & clkf_rdy & clkod_rdy & bwadj_rdy;
+
+  // PLL config is not ready until all config values are nonzero and we have a lock
+  assign PLLconfigdone = &{|PLLclkr, |PLLclkf, |PLLclkod, |PLLbwadj} & PLLlock;
+
+  // Read on PCLK
+  assign PRDATA = {{APB_DATA_SIZE-14{1'b0}}, rdata};
+  always_ff @(posedge PCLK) begin
+    case (entry)
+      8'h00:   rdata <= { 7'b0, PLLclkr};
+      8'h08:   rdata <=         PLLclkf;
+      8'h10:   rdata <= { 9'b0, PLLclkod};
+      8'h18:   rdata <= { 1'b0, PLLbwadj};
+      8'h20:   rdata <= {12'b0, PLLtest};
+      8'h28:   rdata <= {12'b0, PLLfasten};
+      8'h30:   rdata <= {12'b0, PLLlock};
+      default: rdata <= 0;
+    endcase
+  end
+
+  // Decode write address into one-hot enable
+  always_comb begin
+    if (wren) begin
+      case (entry)
+        8'h00:   wcode = 6'b100000;
+        8'h08:   wcode = 6'b010000;
+        8'h10:   wcode = 6'b001000;
+        8'h18:   wcode = 6'b000100;
+        8'h20:   wcode = 6'b000010;
+        8'h28:   wcode = 6'b000001;
+        default: wcode = 6'b000000;
+      endcase
+    end else begin
+      wcode = 6'b000000;
+    end
+  end
+  assign {clkr_en, clkf_en, clkod_en, bwadj_en, test_en, fasten_en} = wcode;
+
+  // Writes are synced to different clocks depending on the signal
+  flopen #(13) datareg (PCLK, PREADY, PWDATA[12:0], wdata);
+  pll_sync #(6)  clkrsync   (.clk(PCLK), .trigger(PLLrfen),   .reset(~PRESETn), .data(wdata[5:0]),  .enable(clkr_en),   .sync_data(PLLclkr),   .ready(clkr_rdy));
+  pll_sync #(13) clkfsync   (.clk(PCLK), .trigger(PLLfben),   .reset(~PRESETn), .data(wdata),       .enable(clkf_en),   .sync_data(PLLclkf),   .ready(clkf_rdy));
+  pll_sync #(4)  clkodsync  (.clk(PCLK), .trigger(PLLrefclk), .reset(~PRESETn), .data(wdata[3:0]),  .enable(clkod_en),  .sync_data(PLLclkod),  .ready(clkod_rdy));
+  pll_sync #(12) bwadjsync  (.clk(PCLK), .trigger(PLLrefclk), .reset(~PRESETn), .data(wdata[11:0]), .enable(bwadj_en),  .sync_data(PLLbwadj),  .ready(bwadj_rdy));
+  pll_sync #(1)  testsync   (.clk(PCLK), .trigger(PLLrefclk), .reset(~PRESETn), .data(wdata[0]),    .enable(test_en),   .sync_data(PLLtest),   .ready(test_rdy));
+  pll_sync #(1)  fastensync (.clk(PCLK), .trigger(PLLrefclk), .reset(~PRESETn), .data(wdata[0]),    .enable(fasten_en), .sync_data(PLLfasten), .ready(fasten_rdy));
+
+endmodule
+
+/* verilator lint_off DECLFILENAME */
+module pll_sync #(parameter SIZE = 8) (
+  input  logic            clk,
+  input  logic            trigger,
+  input  logic            reset,
+  input  logic [SIZE-1:0] data,
+  input  logic            enable,
+  output logic [SIZE-1:0] sync_data,
+  output logic            ready
+); /* lint_on */
+
+  logic selected_clk;
+  logic [SIZE-1:0] data1d;
+  logic            enable1d, enable2d;
+  logic            sync_enable, sync_enable1d, sync_enable2d;
+
+  assign ready = ~enable1d; // Ready as long as we don't have a command in progress
+
+  // Use clk during reset. Otherwise sync to rising edge of trigger signal
+  clockmux2 clkmux (trigger, clk, reset, selected_clk);
+
+  // Feedback loop for data enable
+  initial enable1d = 0;
+  always @(posedge clk or posedge sync_enable2d) begin: enablesync1
+    // We use an SR FF to ensure enable is latched until data sync is complete
+    if (sync_enable2d) enable1d <= 0;
+    else begin
+      if (enable)      enable1d <= 1;
+      else             enable1d <= enable1d;
+    end
+  end
+  flop  #(1) enablesync2 (selected_clk, enable1d,      enable2d);
+  flop  #(1) enablesync3 (selected_clk, enable2d,      sync_enable);
+  flop  #(1) enablesync4 (clk,          sync_enable,   sync_enable1d);
+  flop  #(1) enablesync5 (clk,          sync_enable1d, sync_enable2d);
+
+  // Pass data when we have a synchronized enable signal
+  flopen  #(SIZE) datasync1 (clk,                 enable1d,    data,   data1d);
+  flopenr #(SIZE) datasync2 (selected_clk, reset, sync_enable, data1d, sync_data);
+
+endmodule
diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv
index d26161f4f..0b4e777e4 100644
--- a/src/uncore/ram_ahb.sv
+++ b/src/uncore/ram_ahb.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: On-chip RAM, external to core, with AHB interface
 // 
-// Documentation: RISC-V System on Chip Design Chapter 6
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -64,7 +64,7 @@ module ram_ahb import cvw::*;  #(parameter cvw_t P,
   assign nextHREADYRam = (~(memwriteD & memread)) & ~DelayReady;
   flopr #(1) readyreg(HCLK, ~HRESETn, nextHREADYRam, HREADYRam);
 
-  assign HRESPRam = 0; // OK
+  assign HRESPRam = 1'b0; // OK
 
   // On writes or during a wait state, use address delayed by one cycle to sync RamAddr with HWDATA or hold stalled address
   mux2 #(P.PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
@@ -104,7 +104,7 @@ module ram_ahb import cvw::*;  #(parameter cvw_t P,
     assign DelayReady = NextState == DELAY;
     assign CntRst = NextState == READY;
   end else begin
-    assign DelayReady = 0;
+    assign DelayReady = 1'b0;
   end
 
 endmodule
diff --git a/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv
index 9576f33d7..d20ef64da 100644
--- a/src/uncore/rom_ahb.sv
+++ b/src/uncore/rom_ahb.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: On-chip ROM, external to core
 // 
-// Documentation: RISC-V System on Chip Design Chapter 6
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -43,7 +43,7 @@ module rom_ahb import cvw::*;  #(parameter cvw_t P,
  
   // Never stalls
   assign HREADYRom = 1'b1;
-  assign HRESPRom  = 0; // OK
+  assign HRESPRom  = 1'b0; // OK
 
   // single-ported ROM
   rom1p1r #(ADDR_WIDTH, P.XLEN, PRELOAD)
diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv
index 3f34e938e..94f188120 100644
--- a/src/uncore/spi_apb.sv
+++ b/src/uncore/spi_apb.sv
@@ -45,6 +45,26 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     output logic                SPIIntr
 );
 
+    // register map
+    localparam SPI_SCKDIV =  8'h00;
+    localparam SPI_SCKMODE = 8'h04;
+    localparam SPI_CSID =    8'h10;
+    localparam SPI_CSDEF =   8'h14;
+    localparam SPI_CSMODE =  8'h18;
+    localparam SPI_DELAY0 =  8'h28;
+    localparam SPI_DELAY1 =  8'h2C;
+    localparam SPI_FMT =     8'h40;
+    localparam SPI_TXDATA =  8'h48;
+    localparam SPI_RXDATA =  8'h4C;
+    localparam SPI_TXMARK =  8'h50;
+    localparam SPI_RXMARK =  8'h54;
+    localparam SPI_IE =      8'h70;
+    localparam SPI_IP =      8'h74;
+
+    // receive shift register states
+    typedef enum logic [1:0] {ReceiveShiftFullState, ReceiveShiftNotFullState, ReceiveShiftDelayState} rsrstatetype;
+
+
     // SPI control registers. Refer to SiFive FU540-C000 manual 
     logic [11:0] SckDiv;
     logic [1:0]  SckMode;
@@ -61,7 +81,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     // Bus interface signals
     logic [7:0] Entry;
     logic Memwrite;
-    logic [31:0] Din, Dout;
+    logic [31:0] Din,  Dout;
     logic TransmitInactive;                         // High when there is no transmission, used as hardware interlock signal
 
     // FIFO FSM signals
@@ -72,8 +92,11 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     logic ReceiveFIFOReadIncrement;
     logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty;
     logic [7:0] TransmitFIFOReadData;
-    logic [2:0] TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel;
+    /* verilator lint_off UNDRIVEN */
+    logic [2:0] TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel; // unused generic FIFO outputs
+    /* verilator lint_off UNDRIVEN */
     logic [7:0] ReceiveShiftRegEndian;              // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)
+    rsrstatetype ReceiveState;
 
     // Transmission signals
     logic sck;
@@ -130,17 +153,17 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     // -- Note SPI registers are 32 bits no matter what; access them with LW SW.
    
     assign Din = PWDATA[31:0]; 
-    if (P.XLEN == 64) assign PRDATA = {Dout, Dout}; 
-    else              assign PRDATA = Dout;  
+    if (P.XLEN == 64) assign PRDATA = { Dout,  Dout}; 
+    else              assign PRDATA =  Dout;  
 
     // Register access  
-    always_ff@(posedge PCLK, negedge PRESETn)
+    always_ff@(posedge PCLK)
         if (~PRESETn) begin 
             SckDiv <= 12'd3;
             SckMode <= 2'b0;
             ChipSelectID <= 2'b0;
             ChipSelectDef <= 4'b1111;
-            ChipSelectMode <= 0;
+            ChipSelectMode <= 2'b0;
             Delay0 <= {8'b1,8'b1};
             Delay1 <= {8'b0,8'b1};
             Format <= {5'b10000};
@@ -155,18 +178,18 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
             /* verilator lint_off CASEINCOMPLETE */
             if (Memwrite & TransmitInactive)
                 case(Entry) // flop to sample inputs
-                    8'h00: SckDiv <= Din[11:0];
-                    8'h04: SckMode <= Din[1:0];
-                    8'h10: ChipSelectID <= Din[1:0];
-                    8'h14: ChipSelectDef <= Din[3:0];
-                    8'h18: ChipSelectMode <= Din[1:0];
-                    8'h28: Delay0 <= {Din[23:16], Din[7:0]};
-                    8'h2C: Delay1 <= {Din[23:16], Din[7:0]};
-                    8'h40: Format <= {Din[19:16], Din[2]};
-                    8'h48: if (~TransmitFIFOWriteFull) TransmitData[7:0] <= Din[7:0];
-                    8'h50: TransmitWatermark <= Din[2:0];
-                    8'h54: ReceiveWatermark <= Din[2:0];
-                    8'h70: InterruptEnable <= Din[1:0];
+                    SPI_SCKDIV:  SckDiv <= Din[11:0];
+                    SPI_SCKMODE: SckMode <= Din[1:0];
+                    SPI_CSID:    ChipSelectID <= Din[1:0];
+                    SPI_CSDEF:   ChipSelectDef <= Din[3:0];
+                    SPI_CSMODE:  ChipSelectMode <= Din[1:0];
+                    SPI_DELAY0:  Delay0 <= {Din[23:16], Din[7:0]};
+                    SPI_DELAY1:  Delay1 <= {Din[23:16], Din[7:0]};
+                    SPI_FMT:     Format <= {Din[19:16], Din[2]};
+                    SPI_TXDATA:  if (~TransmitFIFOWriteFull) TransmitData[7:0] <= Din[7:0];
+                    SPI_TXMARK:  TransmitWatermark <= Din[2:0];
+                    SPI_RXMARK:  ReceiveWatermark <= Din[2:0];
+                    SPI_IE:      InterruptEnable <= Din[1:0];
                 endcase
             /* verilator lint_off CASEINCOMPLETE */
 
@@ -176,21 +199,21 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
             InterruptPending[1] <= RecieveWriteMark;  
 
             case(Entry) // Flop to sample inputs
-                8'h00: Dout <= {20'b0, SckDiv};
-                8'h04: Dout <= {30'b0, SckMode};
-                8'h10: Dout <= {30'b0, ChipSelectID};
-                8'h14: Dout <= {28'b0, ChipSelectDef};
-                8'h18: Dout <= {30'b0, ChipSelectMode};
-                8'h28: Dout <= {8'b0, Delay0[15:8], 8'b0, Delay0[7:0]};
-                8'h2C: Dout <= {8'b0, Delay1[15:8], 8'b0, Delay1[7:0]};
-                8'h40: Dout <= {12'b0, Format[4:1], 13'b0, Format[0], 2'b0};
-                8'h48: Dout <= {23'b0, TransmitFIFOWriteFull, 8'b0};
-                8'h4C: Dout <= {23'b0, ReceiveFIFOReadEmpty, ReceiveData[7:0]};
-                8'h50: Dout <= {29'b0, TransmitWatermark};
-                8'h54: Dout <= {29'b0, ReceiveWatermark};
-                8'h70: Dout <= {30'b0, InterruptEnable};
-                8'h74: Dout <= {30'b0, InterruptPending};
-                default: Dout <= 32'b0;
+                SPI_SCKDIV:  Dout <= {20'b0, SckDiv};
+                SPI_SCKMODE: Dout <= {30'b0, SckMode};
+                SPI_CSID:    Dout <= {30'b0, ChipSelectID};
+                SPI_CSDEF:   Dout <= {28'b0, ChipSelectDef};
+                SPI_CSMODE:  Dout <= {30'b0, ChipSelectMode};
+                SPI_DELAY0:  Dout <= {8'b0, Delay0[15:8], 8'b0, Delay0[7:0]};
+                SPI_DELAY1:  Dout <= {8'b0, Delay1[15:8], 8'b0, Delay1[7:0]};
+                SPI_FMT:     Dout <= {12'b0, Format[4:1], 13'b0, Format[0], 2'b0};
+                SPI_TXDATA:  Dout <= {23'b0, TransmitFIFOWriteFull, 8'b0};
+                SPI_RXDATA:  Dout <= {23'b0, ReceiveFIFOReadEmpty, ReceiveData[7:0]};
+                SPI_TXMARK:  Dout <= {29'b0, TransmitWatermark};
+                SPI_RXMARK:  Dout <= {29'b0, ReceiveWatermark};
+                SPI_IE:      Dout <= {30'b0, InterruptEnable};
+                SPI_IP:      Dout <= {30'b0, InterruptPending};
+                default:     Dout <= 32'b0;
             endcase
         end
 
@@ -199,9 +222,9 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     // Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase
     assign SCLKenable = (DivCounter == SckDiv);
     assign SCLKenableEarly = ((DivCounter + 12'b1) == SckDiv);
-    always_ff @(posedge PCLK, negedge PRESETn)
-        if (~PRESETn) DivCounter <= 0;
-        else if (SCLKenable) DivCounter <= 0;
+    always_ff @(posedge PCLK)
+        if (~PRESETn) DivCounter <= '0;
+        else if (SCLKenable) DivCounter <= 12'b0;
         else DivCounter <= DivCounter + 12'b1;
 
     // Asserts when transmission is one frame before complete
@@ -213,34 +236,57 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     assign ImplicitDelay2 = SckMode[0] ? 9'b1 : 9'b0;
 
     // Calculate when tx/rx shift registers are full/empty
-    TransmitShiftFSM TransmitShiftFSM(PCLK, PRESETn, TransmitFIFOReadEmpty, ReceivePenultimateFrame, Active0, TransmitShiftEmpty);
-    ReceiveShiftFSM ReceiveShiftFSM(PCLK, PRESETn, SCLKenable, ReceivePenultimateFrame, SampleEdge, SckMode[0], ReceiveShiftFull);
+
+    // Transmit Shift FSM
+    always_ff @(posedge PCLK)
+        if (~PRESETn) TransmitShiftEmpty <= 1'b1;
+        else if (TransmitShiftEmpty) begin        
+            if (TransmitFIFOReadEmpty | (~TransmitFIFOReadEmpty & (ReceivePenultimateFrame & Active0))) TransmitShiftEmpty <= 1'b1;
+            else if (~TransmitFIFOReadEmpty) TransmitShiftEmpty <= 1'b0;
+        end else begin
+            if (ReceivePenultimateFrame & Active0) TransmitShiftEmpty <= 1'b1;
+            else TransmitShiftEmpty <= 1'b0;
+        end
+
+    // Receive Shift FSM
+    always_ff @(posedge PCLK)
+        if (~PRESETn) ReceiveState <= ReceiveShiftNotFullState;
+        else if (SCLKenable) begin
+            case (ReceiveState)
+                ReceiveShiftFullState:    ReceiveState <= ReceiveShiftNotFullState;
+                ReceiveShiftNotFullState: if (ReceivePenultimateFrame & (SampleEdge)) ReceiveState <= ReceiveShiftDelayState;
+                                          else ReceiveState <= ReceiveShiftNotFullState;
+                ReceiveShiftDelayState:   ReceiveState <= ReceiveShiftFullState;
+            endcase
+        end
+
+    assign ReceiveShiftFull = SckMode[0] ? (ReceiveState == ReceiveShiftFullState) : (ReceiveState == ReceiveShiftDelayState);
 
     // Calculate tx/rx fifo write and recieve increment signals 
 
-    always_ff @(posedge PCLK, negedge PRESETn)
-        if (~PRESETn) TransmitFIFOWriteIncrement <= 0;
+    always_ff @(posedge PCLK)
+        if (~PRESETn) TransmitFIFOWriteIncrement <= 1'b0;
         else TransmitFIFOWriteIncrement <= (Memwrite & (Entry == 8'h48) & ~TransmitFIFOWriteFull & TransmitInactive);
 
-    always_ff @(posedge PCLK, negedge PRESETn)
-        if (~PRESETn) ReceiveFIFOReadIncrement <= 0;
+    always_ff @(posedge PCLK)
+        if (~PRESETn) ReceiveFIFOReadIncrement <= 1'b0;
         else ReceiveFIFOReadIncrement <= ((Entry == 8'h4C) & ~ReceiveFIFOReadEmpty & PSEL & ~ReceiveFIFOReadIncrement);
     
     // Tx/Rx FIFOs
-    SynchFIFO #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn, TransmitFIFOWriteIncrement, TransmitShiftEmpty, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0],
+    spi_fifo #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn, TransmitFIFOWriteIncrement, TransmitShiftEmpty, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0],
                             TransmitFIFOReadData[7:0], TransmitFIFOWriteFull, TransmitFIFOReadEmpty, TransmitWriteMark, TransmitReadMark);
-    SynchFIFO #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn, ReceiveShiftFullDelay, ReceiveFIFOReadIncrement, ReceiveShiftRegEndian, ReceiveWatermark[2:0], ReceiveReadWatermarkLevel, 
+    spi_fifo #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn, ReceiveShiftFullDelay, ReceiveFIFOReadIncrement, ReceiveShiftRegEndian, ReceiveWatermark[2:0], ReceiveReadWatermarkLevel, 
                             ReceiveData[7:0], ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty, RecieveWriteMark, RecieveReadMark);
 
-    always_ff @(posedge PCLK, negedge PRESETn)
-        if (~PRESETn) TransmitFIFOReadEmptyDelay <= 1;
+    always_ff @(posedge PCLK)
+        if (~PRESETn) TransmitFIFOReadEmptyDelay <= 1'b1;
         else  if (SCLKenable) TransmitFIFOReadEmptyDelay <= TransmitFIFOReadEmpty;
 
-    always_ff @(posedge PCLK, negedge PRESETn)
-        if (~PRESETn) ReceiveShiftFullDelay <= 0;
+    always_ff @(posedge PCLK)
+        if (~PRESETn) ReceiveShiftFullDelay <= 1'b0;
         else if (SCLKenable) ReceiveShiftFullDelay <= ReceiveShiftFull;
-    always_ff @(posedge PCLK, negedge PRESETn)
-        if (~PRESETn) ReceiveShiftFullDelayPCLK <= 0;
+    always_ff @(posedge PCLK)
+        if (~PRESETn) ReceiveShiftFullDelayPCLK <= 1'b0;
         else if (SCLKenableEarly) ReceiveShiftFullDelayPCLK <= ReceiveShiftFull; 
 
     assign TransmitShiftRegLoad = ~TransmitShiftEmpty & ~Active | (((ChipSelectMode == 2'b10) & ~|(Delay1[15:8])) & ((ReceiveShiftFullDelay | ReceiveShiftFull) & ~SampleEdge & ~TransmitFIFOReadEmpty));
@@ -249,7 +295,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     typedef enum logic [2:0] {CS_INACTIVE, DELAY_0, ACTIVE_0, ACTIVE_1, DELAY_1,INTER_CS, INTER_XFR} statetype;
     statetype state;
 
-    always_ff @(posedge PCLK, negedge PRESETn)
+    always_ff @(posedge PCLK)
         if (~PRESETn) begin 
                         state <= CS_INACTIVE;
                         FrameCount <= 4'b0;                      
@@ -331,7 +377,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
 
     // Transmit shift register
     assign TransmitDataEndian = Format[0] ? {TransmitFIFOReadData[0], TransmitFIFOReadData[1], TransmitFIFOReadData[2], TransmitFIFOReadData[3], TransmitFIFOReadData[4], TransmitFIFOReadData[5], TransmitFIFOReadData[6], TransmitFIFOReadData[7]} : TransmitFIFOReadData[7:0];
-    always_ff @(posedge PCLK, negedge PRESETn)
+    always_ff @(posedge PCLK)
         if(~PRESETn)                        TransmitShiftReg <= 8'b0; 
         else if (TransmitShiftRegLoad)      TransmitShiftReg <= TransmitDataEndian;
         else if (ShiftEdge & Active)        TransmitShiftReg <= {TransmitShiftReg[6:0], 1'b0};
@@ -343,7 +389,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     assign ShiftIn = P.SPI_LOOPBACK_TEST ? SPIOut : SPIIn;
 
     // Receive shift register
-    always_ff @(posedge PCLK, negedge PRESETn)
+    always_ff @(posedge PCLK)
         if(~PRESETn)  ReceiveShiftReg <= 8'b0;
         else if (SampleEdge & SCLKenable) begin
             if (~Active)    ReceiveShiftReg <= 8'b0;
@@ -369,95 +415,3 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
 
     assign SPICS = ChipSelectMode[0] ? ChipSelectDef : ChipSelectAuto;
 endmodule
-
-module SynchFIFO #(parameter M=3, N=8)(                 // 2^M entries of N bits each
-    input  logic         PCLK, wen, ren, PRESETn,
-    input  logic         winc, rinc,
-    input  logic [N-1:0] wdata,
-    input  logic [M-1:0] wwatermarklevel, rwatermarklevel,
-    output logic [N-1:0] rdata,
-    output logic         wfull, rempty,
-    output logic         wwatermark, rwatermark);
-
-    /* Pointer FIFO using design elements from "Simulation and Synthesis Techniques
-       for Asynchronous FIFO Design" by Clifford E. Cummings. Namely, M bit read and write pointers
-       are an extra bit larger than address size to determine full/empty conditions. 
-       Watermark comparisons use 2's complement subtraction between the M-1 bit pointers,
-       which are also used to address memory
-    */
-       
-    logic [N-1:0] mem[2**M];
-    logic [M:0] rptr, wptr;
-    logic [M:0] rptrnext, wptrnext;
-    logic [M-1:0] raddr;
-    logic [M-1:0] waddr;
- 
-    assign rdata = mem[raddr];
-    always_ff @(posedge PCLK)
-        if (winc & ~wfull) mem[waddr] <= wdata;
-
-    // write and read are enabled 
-    always_ff @(posedge PCLK, negedge PRESETn)
-        if (~PRESETn) begin 
-            rptr <= 0;
-            wptr <= 0;
-            wfull <= 1'b0;
-            rempty <= 1'b1;
-        end
-        else begin 
-            if (wen) begin
-                wfull <= ({~wptrnext[M], wptrnext[M-1:0]} == rptr);
-                wptr  <= wptrnext;
-            end
-            if (ren) begin 
-                rptr <= rptrnext;
-                rempty <= (wptr == rptrnext);
-            end
-        end 
-    
-    assign raddr = rptr[M-1:0];
-    assign rptrnext = rptr + {{(M){1'b0}}, (rinc & ~rempty)};      
-    assign rwatermark = ((waddr - raddr) < rwatermarklevel) & ~wfull;
-    assign waddr = wptr[M-1:0];
-    assign wwatermark = ((waddr - raddr) > wwatermarklevel) | wfull;
-    assign wptrnext = wptr + {{(M){1'b0}}, (winc & ~wfull)};
-endmodule
-
-module TransmitShiftFSM(
-    input  logic PCLK, PRESETn,
-    input  logic TransmitFIFOReadEmpty, ReceivePenultimateFrame, Active0,
-    output logic TransmitShiftEmpty);
-
-    always_ff @(posedge PCLK, negedge PRESETn)
-        if (~PRESETn) TransmitShiftEmpty <= 1;
-        else if (TransmitShiftEmpty) begin        
-            if (TransmitFIFOReadEmpty | (~TransmitFIFOReadEmpty & (ReceivePenultimateFrame & Active0))) TransmitShiftEmpty <= 1;
-            else if (~TransmitFIFOReadEmpty) TransmitShiftEmpty <= 0;
-        end else begin
-            if (ReceivePenultimateFrame & Active0) TransmitShiftEmpty <= 1;
-            else TransmitShiftEmpty <= 0;
-        end
-
-endmodule
-
-module ReceiveShiftFSM(
-    input  logic PCLK, PRESETn, SCLKenable,
-    input  logic ReceivePenultimateFrame, SampleEdge, SckMode,
-    output logic ReceiveShiftFull
-);
-    typedef enum logic [1:0] {ReceiveShiftFullState, ReceiveShiftNotFullState, ReceiveShiftDelayState} statetype;
-    statetype ReceiveState, ReceiveNextState;
-    always_ff @(posedge PCLK, negedge PRESETn)
-        if (~PRESETn) ReceiveState <= ReceiveShiftNotFullState;
-        else if (SCLKenable) begin
-            case (ReceiveState)
-                ReceiveShiftFullState: ReceiveState <= ReceiveShiftNotFullState;
-                ReceiveShiftNotFullState: if (ReceivePenultimateFrame & (SampleEdge)) ReceiveState <= ReceiveShiftDelayState;
-                                          else ReceiveState <= ReceiveShiftNotFullState;
-                ReceiveShiftDelayState:   ReceiveState <= ReceiveShiftFullState;
-            endcase
-        end
-
-    assign ReceiveShiftFull = SckMode ? (ReceiveState == ReceiveShiftFullState) : (ReceiveState == ReceiveShiftDelayState);
-endmodule
-
diff --git a/src/uncore/spi_fifo.sv b/src/uncore/spi_fifo.sv
new file mode 100644
index 000000000..40c3ca4ff
--- /dev/null
+++ b/src/uncore/spi_fifo.sv
@@ -0,0 +1,51 @@
+module spi_fifo #(parameter M=3, N=8)(                 // 2^M entries of N bits each
+    input  logic         PCLK, wen, ren, PRESETn,
+    input  logic         winc, rinc,
+    input  logic [N-1:0] wdata,
+    input  logic [M-1:0] wwatermarklevel, rwatermarklevel,
+    output logic [N-1:0] rdata,
+    output logic         wfull, rempty,
+    output logic         wwatermark, rwatermark);
+
+    /* Pointer FIFO using design elements from "Simulation and Synthesis Techniques
+       for Asynchronous FIFO Design" by Clifford E. Cummings. Namely, M bit read and write pointers
+       are an extra bit larger than address size to determine full/empty conditions. 
+       Watermark comparisons use 2's complement subtraction between the M-1 bit pointers,
+       which are also used to address memory
+    */
+       
+    logic [N-1:0] mem[2**M];
+    logic [M:0] rptr, wptr;
+    logic [M:0] rptrnext, wptrnext;
+    logic [M-1:0] raddr;
+    logic [M-1:0] waddr;
+ 
+    assign rdata = mem[raddr];
+    always_ff @(posedge PCLK)
+        if (winc & ~wfull) mem[waddr] <= wdata;
+
+    // write and read are enabled 
+    always_ff @(posedge PCLK)
+        if (~PRESETn) begin 
+            rptr <= '0;
+            wptr <= '0;
+            wfull <= 1'b0;
+            rempty <= 1'b1;
+        end else begin 
+            if (wen) begin
+                wfull <= ({~wptrnext[M], wptrnext[M-1:0]} == rptr);
+                wptr  <= wptrnext;
+            end
+            if (ren) begin 
+                rptr <= rptrnext;
+                rempty <= (wptr == rptrnext);
+            end
+        end 
+    
+    assign raddr = rptr[M-1:0];
+    assign rptrnext = rptr + {{(M){1'b0}}, (rinc & ~rempty)};      
+    assign rwatermark = ((waddr - raddr) < rwatermarklevel) & ~wfull;
+    assign waddr = wptr[M-1:0];
+    assign wwatermark = ((waddr - raddr) > wwatermarklevel) | wfull;
+    assign wptrnext = wptr + {{(M){1'b0}}, (winc & ~wfull)};
+endmodule
diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv
index 94a587d9f..31172462d 100644
--- a/src/uncore/uartPC16550D.sv
+++ b/src/uncore/uartPC16550D.sv
@@ -13,7 +13,7 @@
 //   Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1
 //   Timeout not yet implemented
 // 
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -52,6 +52,16 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   output logic       SOUT, RTSb, DTRb, OUT1b, OUT2b  // UART external serial and flow-control outputs
 );
 
+  // register map
+  localparam UART_DLL_RBR = 3'b000;
+  localparam UART_DLM_IER = 3'b001;
+  localparam UART_IIR = 3'b010;
+  localparam UART_LCR = 3'b011;
+  localparam UART_MCR = 3'b100;
+  localparam UART_LSR = 3'b101;
+  localparam UART_MSR = 3'b110;
+  localparam UART_SCR = 3'b111;
+  
   // transmit and receive states 
   typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
 
@@ -84,7 +94,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   logic [7:0]                   txfifo[15:0];
   logic [4:0]                   rxfifotailunwrapped;
   logic [3:0]                   rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel;
-  logic [3:0]                   rxfifoentries, txfifoentries;
+  logic [3:0]                   rxfifoentries;
   logic [3:0]                   rxbitsexpected, txbitsexpected;
 
   // receive data
@@ -135,50 +145,50 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   // Register interface (Table 1, note some are read only and some write only)
   ///////////////////////////////////////////
   
-  always_ff @(posedge PCLK, negedge PRESETn) 
+  always_ff @(posedge PCLK) 
     if (~PRESETn) begin // Table 3 Reset Configuration
       IER <= 4'b0;
       FCR <= 8'b0;
-      LCR <= 8'b11; // **** fpga used to require reset to 3, double check this is no longer needed.
+      LCR <= 8'b11; // PC16550D datasheet resets to 0, but all modern systems will use 8-bit data.  Wally resets to 3 for 8-bit data.
       MCR <= 5'b0;
-      LSR <= 8'b01100000;
+      LSR <= 8'b0110_0000;
       MSR <= 4'b0;
-      DLL <= 8'd1; // this cannot be zero with DLM also zer0.
+      DLL <= 8'd1; // this cannot be zero with DLM also zero.
       DLM <= 8'b0;
       SCR <= 8'b0; // not strictly necessary to reset
     end else begin
       if (~MEMWb) begin
         /* verilator lint_off CASEINCOMPLETE */
         case (A)
-          3'b000: if (DLAB) DLL <= Din; // else TXHR <= Din; // TX handled in TX register/FIFO section
-          3'b001: if (DLAB) DLM <= Din; else IER <= Din[3:0];
-          3'b010: FCR <= {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing
-          3'b011: LCR <= Din;
-          3'b100: MCR <= Din[4:0];
-          3'b111: SCR <= Din;
+          UART_DLL_RBR: if (DLAB) DLL <= Din; // else TXHR <= Din; // TX handled in TX register/FIFO section
+          UART_DLM_IER: if (DLAB) DLM <= Din; else IER <= Din[3:0];
+          UART_IIR: FCR <= {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing
+          UART_LCR: LCR <= Din;
+          UART_MCR: MCR <= Din[4:0];
+          UART_SCR: SCR <= Din;
         endcase
         /* verilator lint_on CASEINCOMPLETE */
       end
 
       // Line Status Register (8.6.3)
       // Ben 6/9/21 I don't like how this is a register. A lot of the individual bits have clocked components, so this just adds unecessary delay.
-      if (~MEMWb & (A == 3'b101))
+      if (~MEMWb & (A == UART_LSR))
         LSR[6:1] <= Din[6:1]; // recommended only for test, see 8.6.3
       else begin
         LSR[0]   <= rxdataready; // Data ready
-        LSR[1]   <= (LSR[1] | RXBR[10]) & ~squashRXerrIP;; // overrun error
-        LSR[2]   <= (LSR[2] | RXBR[9]) & ~squashRXerrIP; // parity error
-        LSR[3]   <= (LSR[3] | RXBR[8]) & ~squashRXerrIP; // framing error
-        LSR[4]   <= (LSR[4] | rxbreak) & ~squashRXerrIP; // break indicator
+        LSR[1]   <= (LSR[1] | RXBR[10]) & ~squashRXerrIP; // overrun error
+        LSR[2]   <= (LSR[2] | RXBR[9])  & ~squashRXerrIP; // parity error
+        LSR[3]   <= (LSR[3] | RXBR[8])  & ~squashRXerrIP; // framing error
+        LSR[4]   <= (LSR[4] | rxbreak)  & ~squashRXerrIP; // break indicator
         LSR[5]   <= THRE; // THRE
         LSR[6]   <= ~txsrfull & THRE; //  TEMT
-        if (rxfifohaserr) LSR[7] <= 1; // any bits in FIFO have error
+        if (rxfifohaserr) LSR[7] <= 1'b1; // any bits in FIFO have error
       end
 
       // Modem Status Register (8.6.8)
-      if (~MEMWb & (A == 3'b110))
+      if (~MEMWb & (A == UART_MSR))
         MSR <= Din[3:0];
-      else if (~MEMRb & (A == 3'b110)) 
+      else if (~MEMRb & (A == UART_MSR)) 
         MSR <= 4'b0; // Reading MSR clears the flags in MSR bits 3:0
       else begin
         MSR[0] <= MSR[0] | CTSb2 ^ CTSbsync; // Delta Clear to Send
@@ -187,18 +197,18 @@ module uartPC16550D #(parameter UART_PRESCALE) (
         MSR[3] <= MSR[3] | DCDb2 ^ DCDbsync; // Delta Data Carrier Detect
       end
     end
+  
   always_comb
     if (~MEMRb)
       case (A)
-        3'b000: if (DLAB) Dout = DLL; else Dout = RBR[7:0];
-        3'b001: if (DLAB) Dout = DLM; else Dout = {4'b0, IER[3:0]};
-        3'b010: Dout = {{2{fifoenabled}}, 2'b00, intrID[2:0], ~intrpending}; // Read only Interupt Ident Register
-        3'b011: Dout = LCR;
-        3'b100: Dout = {3'b000, MCR};
-        3'b101: Dout = LSR;
-        // 3'b110: Dout = {~CTSbsync, ~DSRbsync, ~RIbsync, ~DCDbsync, MSR[3:0]}; 
-        3'b110: Dout = {~DCDbsync, ~RIbsync, ~DSRbsync, ~CTSbsync, MSR[3:0]};
-        3'b111: Dout = SCR;      
+        UART_DLL_RBR: if (DLAB) Dout = DLL; else Dout = RBR[7:0];
+        UART_DLM_IER: if (DLAB) Dout = DLM; else Dout = {4'b0, IER[3:0]};
+        UART_IIR: Dout = {{2{fifoenabled}}, 2'b00, intrID[2:0], ~intrpending}; // Read only Interupt Ident Register
+        UART_LCR: Dout = LCR;
+        UART_MCR: Dout = {3'b000, MCR};
+        UART_LSR: Dout = LSR;
+        UART_MSR: Dout = {~DCDbsync, ~RIbsync, ~DSRbsync, ~CTSbsync, MSR[3:0]};
+        UART_SCR: Dout = SCR;      
       endcase
     else Dout = 8'b0;
 
@@ -212,10 +222,10 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   // the data, so the baud rate is 320x10^6 / (65 x 2^5 x 16) = 9615 Hz, which is
   // close enough to 9600 baud to stay synchronized over the duration of one character.
   ///////////////////////////////////////////
-  always_ff @(posedge PCLK, negedge PRESETn) 
+  always_ff @(posedge PCLK) 
     if (~PRESETn) begin
       baudcount <= 1;
-      baudpulse <= 0;
+      baudpulse <= 1'b0;
     end else if (~MEMWb & DLAB & (A == 3'b0 | A == 3'b1)) begin
       baudcount <= 1;
     end else begin
@@ -238,20 +248,20 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   // receive timing and control
   ///////////////////////////////////////////
   
-  always_ff @(posedge PCLK, negedge PRESETn)
+  always_ff @(posedge PCLK)
     if (~PRESETn) begin
-      rxoversampledcnt   <= 0;
+      rxoversampledcnt   <= '0;
       rxstate            <= UART_IDLE;
-      rxbitsreceived     <= 0;
-      rxtimeoutcnt       <= 0;
+      rxbitsreceived     <= '0;
+      rxtimeoutcnt       <= '0;
     end else begin
       if (rxstate == UART_IDLE & ~SINsync) begin // got start bit
         rxstate          <= UART_ACTIVE;
-        rxoversampledcnt <= 0;
-        rxbitsreceived   <= 0;
-        if (~rxfifotimeout) rxtimeoutcnt <= 0; // reset timeout when new character is arriving. Jacob Pease: Only if the timeout was not already reached. p.16 PC16550D.pdf
+        rxoversampledcnt <= '0;
+        rxbitsreceived   <= '0;
+        if (~rxfifotimeout) rxtimeoutcnt <= '0; // reset timeout when new character is arriving. Jacob Pease: Only if the timeout was not already reached. p.16 PC16550D.pdf
       end else if (rxbaudpulse & (rxstate == UART_ACTIVE)) begin
-        rxoversampledcnt <= rxoversampledcnt + 1;  // 16x oversampled counter
+        rxoversampledcnt <= rxoversampledcnt + 4'b1;  // 16x oversampled counter
         if (rxcentered) rxbitsreceived <= rxbitsreceived + 1;
         if (rxbitsreceived == rxbitsexpected) rxstate <= UART_DONE; // pulse rxdone for a cycle
       end else if (rxstate == UART_DONE | rxstate == UART_BREAK) begin
@@ -259,7 +269,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
         else rxstate <= UART_IDLE;
       end
       // timeout counting
-      if (~MEMRb & A == 3'b000 & ~DLAB) rxtimeoutcnt <= 0; // reset timeout on read
+      if (~MEMRb & A == 3'b000 & ~DLAB) rxtimeoutcnt <= '0; // reset timeout on read
       else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= rxtimeoutcnt+1; // may not be right
     end
 
@@ -271,7 +281,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   // receive shift register, buffer register, FIFO
   ///////////////////////////////////////////
   
-  always_ff @(posedge PCLK, negedge PRESETn)
+  always_ff @(posedge PCLK)
     if (~PRESETn) rxshiftreg <= 10'b0000000001; // initialize so that there is a valid stop bit
     else if (rxcentered) rxshiftreg <= {rxshiftreg[8:0], SINsync}; // capture bit
   assign rxparitybit = rxshiftreg[1]; // parity, if it exists, in bit 1 when all done
@@ -287,7 +297,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
 
   // ERROR CONDITIONS
   assign rxparity     = ^rxdata;
-  assign rxparityerr  = (rxparity ^ rxparitybit ^ ~evenparitysel) & LCR[3]; // Check even/odd parity (*** check if LCR needs to be inverted)
+  assign rxparityerr  = (rxparity ^ rxparitybit ^ ~evenparitysel) & LCR[3]; // Check even/odd parity
   assign rxoverrunerr = fifoenabled ? (rxfifoentries == 15) : rxdataready; // overrun if FIFO or receive buffer register full 
   assign rxframingerr = ~rxstopbit; // framing error if no stop bit
   assign rxbreak      = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time
@@ -295,32 +305,32 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   // receive FIFO and register
   always_ff @(posedge PCLK)
     if (~PRESETn) begin
-      rxfifohead <= 0; rxfifotail <= 0; rxdataready <= 0; RXBR <= 0;
+      rxfifohead <= '0; rxfifotail <= '0; rxdataready <= 1'b0; RXBR <= '0;
     end else begin
       if (~MEMWb & (A == 3'b010) & Din[1]) begin
-        rxfifohead <= 0; rxfifotail <= 0; rxdataready <= 0;
+        rxfifohead <= '0; rxfifotail <= '0; rxdataready <= 1'b0;
       end else if (rxstate == UART_DONE) begin
         RXBR <= {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register
-        if (rxoverrunerr) $warning("UART RX Overrun Err\n");
-        if (rxparityerr)  $warning("UART RX Parity Err\n");
-        if (rxframingerr) $warning("UART RX Framing Err\n");
+//        if (rxoverrunerr) $warning("UART RX Overrun Err\n");
+//        if (rxparityerr)  $warning("UART RX Parity Err\n");
+//        if (rxframingerr) $warning("UART RX Framing Err\n");
         if (fifoenabled) begin
           rxfifo[rxfifohead] <= {rxoverrunerr, rxparityerr, rxframingerr, rxdata};
-          rxfifohead <= rxfifohead + 1;
+          rxfifohead <= rxfifohead + 1'b1;
         end
-        rxdataready <= 1;
+        rxdataready <= 1'b1;
       end else if (~MEMRb & A == 3'b000 & ~DLAB) begin // reading RBR updates ready / pops fifo 
         if (fifoenabled) begin
           if (~rxfifoempty) rxfifotail <= rxfifotail + 1;
-          // if (rxfifoempty) rxdataready <= 0;
-          if (rxfifoentries == 1) rxdataready <= 0; // When reading the last entry, data ready becomes zero
+          // if (rxfifoempty) rxdataready <= 1'b0;
+          if (rxfifoentries == 1) rxdataready <= 1'b0; // When reading the last entry, data ready becomes zero
         end else begin
-          rxdataready <= 0;
+          rxdataready <= 1'b0;
           RXBR <= {1'b0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode)
         end
       end else if (~MEMWb & A == 3'b010)  // writes to FIFO Control Register
         if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents
-          rxfifohead <= 0; rxfifotail <= 0;
+          rxfifohead <= '0; rxfifotail <= '0;
         end
     end
 
@@ -353,10 +363,10 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   assign rxfifohaserr   = |(RXerrbit & rxfullbit);
 
   // receive buffer register and ready bit
-  always_ff @(posedge PCLK, negedge PRESETn) // track rxrdy for DMA mode (FCR3 = FCR0 = 1)
-    if (~PRESETn) rxfifodmaready <= 0;
-    else if (rxfifotriggered | rxfifotimeout) rxfifodmaready <= 1;
-    else if (rxfifoempty) rxfifodmaready <= 0;
+  always_ff @(posedge PCLK) // track rxrdy for DMA mode (FCR3 = FCR0 = 1)
+    if (~PRESETn) rxfifodmaready <= 1'b0;
+    else if (rxfifotriggered | rxfifotimeout) rxfifodmaready <= 1'b1;
+    else if (rxfifoempty) rxfifodmaready <= 1'b0;
 
   always_comb
     if (fifoenabled) begin
@@ -373,19 +383,19 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   // transmit timing and control
   ///////////////////////////////////////////
   
-  always_ff @(posedge PCLK, negedge PRESETn)
+  always_ff @(posedge PCLK)
     if (~PRESETn) begin
-      txoversampledcnt <= 0;
+      txoversampledcnt <= '0;
       txstate          <= UART_IDLE;
-      txbitssent       <= 0;
+      txbitssent       <= '0;
     end else if ((txstate == UART_IDLE) & txsrfull) begin // start transmitting
       txstate          <= UART_ACTIVE;
-      txoversampledcnt <= 1;
-      txbitssent       <= 0;
+      txoversampledcnt <= 4'b1;
+      txbitssent       <= '0;
     end else if (txbaudpulse & (txstate == UART_ACTIVE)) begin
-      txoversampledcnt <= txoversampledcnt + 1; 
+      txoversampledcnt <= txoversampledcnt + 1'b1; 
       if (txnextbit) begin // transmit at end of phase
-        txbitssent <= txbitssent+1;
+        txbitssent <= txbitssent + 1'b1;
         if (txbitssent == txbitsexpected) txstate <= UART_DONE;
       end
     end else if (txstate == UART_DONE) begin
@@ -421,19 +431,19 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   end
   
   // registers & FIFO
-  always_ff @(posedge PCLK, negedge PRESETn)
+  always_ff @(posedge PCLK)
     if (~PRESETn) begin
-      txfifohead <= 0; txfifotail <= 0; txhrfull <= 0; txsrfull <= 0; TXHR <= 0; txsr <= 12'hfff;
+      txfifohead <= '0; txfifotail <= '0; txhrfull <= 1'b0; txsrfull <= 1'b0; TXHR <= '0; txsr <= 12'hfff;
     end else if (~MEMWb & (A == 3'b010) & Din[2]) begin
-      txfifohead <= 0; txfifotail <= 0;
+      txfifohead <= '0; txfifotail <= '0;
     end else begin
       if (~MEMWb & A == 3'b000 & ~DLAB) begin // writing transmit holding register or fifo
         if (fifoenabled) begin
           txfifo[txfifohead] <= Din;
-          txfifohead         <= txfifohead + 1;          
+          txfifohead         <= txfifohead + 4'b1;          
         end else begin 
           TXHR     <= Din;
-          txhrfull <= 1;
+          txhrfull <= 1'b1;
         end
         $write("%c",Din); // for testbench
       end
@@ -442,22 +452,22 @@ module uartPC16550D #(parameter UART_PRESCALE) (
           if (~txfifoempty & ~txsrfull) begin
             txsr       <= txdata;
             txfifotail <= txfifotail+1;
-            txsrfull   <= 1;
+            txsrfull   <= 1'b1;
           end
         end else if (txhrfull) begin
           txsr     <= txdata;
-          txhrfull <= 0;
-          txsrfull <= 1;
+          txhrfull <= 1'b0;
+          txsrfull <= 1'b1;
         end
-      end else if (txstate == UART_DONE) txsrfull <= 0; // done transmitting shift register
+      end else if (txstate == UART_DONE) txsrfull <= 1'b0; // done transmitting shift register
       else if (txstate == UART_ACTIVE & txnextbit) txsr <= {txsr[10:0], 1'b1}; // shift txhr
       if (!MEMWb & A == 3'b010) // writes to FIFO control register
         if (Din[2] | ~Din[0]) begin // tx FIFO reste or FIFO disable clears FIFO contents
-          txfifohead <= 0; txfifotail <= 0;
+          txfifohead <= '0; txfifotail <= '0;
         end
     end
 
-  always_ff @(posedge PCLK, negedge PRESETn) begin
+  always_ff @(posedge PCLK) begin
   // special condition to check if the fifo is empty or full.  Because the head
   // pointer indicates where the next write goes and not the location of the
   // current head, the head and tail pointer being equal imply two different
@@ -474,18 +484,14 @@ module uartPC16550D #(parameter UART_PRESCALE) (
     HeadPointerLastMove <= 1'b0;
   end
 
-  assign txfifoempty   = (txfifohead == txfifotail) & ~HeadPointerLastMove;
-  // verilator lint_off WIDTH
-  assign txfifoentries = (txfifohead >= txfifotail) ? (txfifohead-txfifotail) : 
-                         (txfifohead + 16 - txfifotail);
-  // verilator lint_on WIDTH
-  assign txfifofull = (txfifohead == txfifotail) & HeadPointerLastMove;
+  assign txfifoempty = (txfifohead == txfifotail) & ~HeadPointerLastMove;
+  assign txfifofull  = (txfifohead == txfifotail) & HeadPointerLastMove;
 
   // transmit buffer ready bit
-  always_ff @(posedge PCLK, negedge PRESETn) // track txrdy for DMA mode (FCR3 = FCR0 = 1)
-    if (~PRESETn) txfifodmaready <= 0;
-    else if (txfifoempty) txfifodmaready <= 1;
-    else if (txfifofull)  txfifodmaready <= 0;
+  always_ff @(posedge PCLK) // track txrdy for DMA mode (FCR3 = FCR0 = 1)
+    if (~PRESETn)         txfifodmaready <= 1'b0;
+    else if (txfifoempty) txfifodmaready <= 1'b1;
+    else if (txfifofull)  txfifodmaready <= 1'b0;
 
   always_comb
     if (fifoenabled & fifodmamodesel) TXRDYb = ~txfifodmaready;
@@ -493,7 +499,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
 
   // Transmitter pin 
   assign SOUTbit = txsr[11]; // transmit most significant bit
-  assign SOUT    = loop ? 1 : (LCR[6] ? 0 : SOUTbit); // tied to 1 during loopback or 0 during break 
+  assign SOUT    = loop ? 1 : (LCR[6] ? '0 : SOUTbit); // tied to 1 during loopback or 0 during break 
 
   ///////////////////////////////////////////
   // interrupts
@@ -509,7 +515,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   // IIR: interrupt priority (Table 5)
   // set intrID based on highest priority pending interrupt source; otherwise, no interrupt is pending
   always_comb begin
-    intrpending = 1;
+    intrpending = 1'b1;
     if      (RXerrIP & IER[2])                     intrID = 3'b011;
     else if (rxdataavailintr & IER[0])             intrID = 3'b010;
     else if (rxfifotimeout & fifoenabled & IER[0]) intrID = 3'b110;
@@ -517,7 +523,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
     else if (modemstatusintr & IER[3])             intrID = 3'b000;
     else begin
       intrID = 3'b000;
-      intrpending = 0;
+      intrpending = 1'b0;
     end
   end
   always_ff @(posedge PCLK) INTR <= intrpending; // prevent glitches on interrupt pin
@@ -549,10 +555,10 @@ module uartPC16550D #(parameter UART_PRESCALE) (
   assign fifodmamodesel = FCR[3];
   always_comb
     case (FCR[7:6]) 
-      2'b00: rxfifotriggerlevel = 1;
-      2'b01: rxfifotriggerlevel = 4;
-      2'b10: rxfifotriggerlevel = 8;
-      2'b11: rxfifotriggerlevel = 14;
+      2'b00: rxfifotriggerlevel = 4'd1;
+      2'b01: rxfifotriggerlevel = 4'd4;
+      2'b10: rxfifotriggerlevel = 4'd8;
+      2'b11: rxfifotriggerlevel = 4'd14;
     endcase
 
 endmodule
diff --git a/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv
index eeecb7ea5..f7dcf2a60 100644
--- a/src/uncore/uart_apb.sv
+++ b/src/uncore/uart_apb.sv
@@ -8,7 +8,7 @@
 //          Emulates interface of Texas Instruments PC165550D
 //          Compatible with UART in Imperas Virtio model
 // 
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -60,7 +60,7 @@ module uart_apb import cvw::*; #(parameter cvw_t P) (
   else              assign PRDATA = {Dout, Dout, Dout, Dout};   
   
   logic BAUDOUTb;  // loop tx clock BAUDOUTb back to rx clock RCLK
-  uartPC16550D #(P.UART_PRESCALE) u(  
+  uartPC16550D #(P.UART_PRESCALE) uartPC(  
     // Processor Interface
     .PCLK, .PRESETn,
     .A(entry), .Din, 
diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv
index 22e0a35fc..495740579 100644
--- a/src/uncore/uncore.sv
+++ b/src/uncore/uncore.sv
@@ -7,7 +7,7 @@
 // Purpose: System-on-Chip components outside the core
 //          Memories, peripherals, external bus control
 // 
-// Documentation: RISC-V System on Chip Design Chapter 15 (and Figure 6.20)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -28,7 +28,11 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module uncore import cvw::*;  #(parameter cvw_t P)(
+module uncore
+  import cvw::*;
+#(
+  parameter cvw_t P
+) (
   // AHB Bus Interface
   input  logic                 HCLK, HRESETn,
   input  logic                 TIMECLK,
@@ -58,28 +62,61 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
   input  logic                 SDCIntr,
   input  logic                 SPIIn,
   output logic                 SPIOut,
-  output logic [3:0]           SPICS                  
+  output logic [3:0]           SPICS,
+  input  logic                 ui_clk,
+  output logic [15:0]          dmc_trefi,
+  output logic [3:0]           dmc_tmrd,
+  output logic [3:0]           dmc_trfc,
+  output logic [3:0]           dmc_trc,
+  output logic [3:0]           dmc_trp,
+  output logic [3:0]           dmc_tras,
+  output logic [3:0]           dmc_trrd,
+  output logic [3:0]           dmc_trcd,
+  output logic [3:0]           dmc_twr,
+  output logic [3:0]           dmc_twtr,
+  output logic [3:0]           dmc_trtp,
+  output logic [3:0]           dmc_tcas,
+  output logic [3:0]           dmc_col_width,
+  output logic [3:0]           dmc_row_width,
+  output logic [1:0]           dmc_bank_width,
+  output logic [5:0]           dmc_bank_pos,
+  output logic [2:0]           dmc_dqs_sel_cal,
+  output logic [15:0]          dmc_init_cycles,
+  output logic                 dmc_config_changed,
+  input  logic                 PLLrefclk,
+  input  logic                 PLLrfen,
+  input  logic                 PLLfben,
+  output logic [5:0]           PLLclkr,
+  output logic [12:0]          PLLclkf,
+  output logic [3:0]           PLLclkod,
+  output logic [11:0]          PLLbwadj,
+  output logic                 PLLtest,
+  output logic                 PLLfasten,
+  input  logic                 PLLlock,
+  output logic                 PLLconfigdone
 );
   
   logic [P.XLEN-1:0]           HREADRam, HREADSDC;
 
-  logic [11:0]                 HSELRegions;
-  logic                        HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSPI;
-  logic                        HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD, HSELSPID;
+  logic [14:0]                 HSELRegions;
+  logic                        HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSPI, HSELBSGDMCCONF, HSELPLLCONF;
+  logic                        HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD, HSELSPID, HSELBSGDMCCONFD, HSELPLLCONFD;
   logic                        HRESPRam,  HRESPSDC;
   logic                        HREADYRam, HRESPSDCD;
-  logic [P.XLEN-1:0]           HREADBootRom; 
+  logic [P.XLEN-1:0]           HREADBootRom;
   logic                        HSELBootRom, HSELBootRomD, HRESPBootRom, HREADYBootRom, HREADYSDC;
   logic                        HSELNoneD;
   logic                        UARTIntr,GPIOIntr, SPIIntr;
   logic                        SDCIntM;
-  
   logic                        PCLK, PRESETn, PWRITE, PENABLE;
-  logic [4:0]                  PSEL, PREADY;
+  logic [6:0]                  PSEL;
   logic [31:0]                 PADDR;
   logic [P.XLEN-1:0]           PWDATA;
   logic [P.XLEN/8-1:0]         PSTRB;
-  logic [4:0][P.XLEN-1:0]      PRDATA;
+  /* verilator lint_off UNDRIVEN */ // undriven in rv32e configuration
+  logic [6:0]                  PREADY;
+  logic [6:0][P.XLEN-1:0]      PRDATA;
+  /* verilator lint_on UNDRIVEN */
   logic [P.XLEN-1:0]           HREADBRIDGE;
   logic                        HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED;
 
@@ -92,43 +129,43 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
   adrdecs #(P) adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
 
   // unswizzle HSEL signals
-  assign {HSELSPI, HSELEXTSDC, HSELPLIC, HSELUART, HSELGPIO, HSELCLINT, HSELRam, HSELBootRom, HSELEXT, HSELIROM, HSELDTIM} = HSELRegions[11:1];
+  assign {HSELPLLCONF, HSELBSGDMCCONF, HSELSPI, HSELEXTSDC, HSELPLIC, HSELUART, HSELGPIO, HSELCLINT, HSELRam, HSELBootRom, HSELEXT, HSELIROM, HSELDTIM} = HSELRegions[13:1];
 
   // AHB -> APB bridge
-  ahbapbbridge #(P, 5) ahbapbbridge (
-    .HCLK, .HRESETn, .HSEL({HSELSPI, HSELUART, HSELPLIC, HSELCLINT, HSELGPIO}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, 
+  ahbapbbridge #(P, 7) ahbapbbridge (
+    .HCLK, .HRESETn, .HSEL({HSELPLLCONF, HSELBSGDMCCONF, HSELSPI, HSELUART, HSELPLIC, HSELCLINT, HSELGPIO}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, 
     .HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE),
     .PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA);
-  assign HSELBRIDGE = HSELGPIO | HSELCLINT | HSELPLIC | HSELUART | HSELSPI; // if any of the bridge signals are selected
+  assign HSELBRIDGE = HSELPLLCONF | HSELBSGDMCCONF | HSELGPIO | HSELCLINT | HSELPLIC | HSELUART | HSELSPI; // if any of the bridge signals are selected
                 
   // on-chip RAM
   if (P.UNCORE_RAM_SUPPORTED) begin : ram
     ram_ahb #(.P(P), .BASE(P.UNCORE_RAM_BASE), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram (
       .HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY, 
       .HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam);
-  end
+  end else assign {HREADRam, HRESPRam, HREADYRam} = '0;
 
  if (P.BOOTROM_SUPPORTED) begin : bootrom
     rom_ahb #(.P(P), .BASE(P.BOOTROM_BASE), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD))
     bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS, 
       .HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom));
-  end
+  end else assign {HREADBootRom, HRESPBootRom, HREADYBootRom} = '0;
 
   // memory-mapped I/O peripherals
   if (P.CLINT_SUPPORTED == 1) begin : clint
     clint_apb #(P) clint(.PCLK, .PRESETn, .PSEL(PSEL[1]), .PADDR(PADDR[15:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
       .PRDATA(PRDATA[1]), .PREADY(PREADY[1]), .MTIME(MTIME_CLINT), .MTimerInt, .MSwInt);
   end else begin : clint
-    assign MTIME_CLINT = 0;
-    assign MTimerInt = 0; assign MSwInt = 0;
+    assign MTIME_CLINT = '0;
+    assign MTimerInt = 1'b0; assign MSwInt = 1'b0;
   end
 
   if (P.PLIC_SUPPORTED == 1) begin : plic
     plic_apb #(P) plic(.PCLK, .PRESETn, .PSEL(PSEL[2]), .PADDR(PADDR[27:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
       .PRDATA(PRDATA[2]), .PREADY(PREADY[2]), .UARTIntr, .GPIOIntr, .SDCIntr, .SPIIntr, .MExtInt, .SExtInt);
   end else begin : plic
-    assign MExtInt = 0;
-    assign SExtInt = 0;
+    assign MExtInt = 1'b0;
+    assign SExtInt = 1'b0;
   end
 
   if (P.GPIO_SUPPORTED == 1) begin : gpio
@@ -137,9 +174,9 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
       .PRDATA(PRDATA[0]), .PREADY(PREADY[0]), 
       .iof0(), .iof1(), .GPIOIN, .GPIOOUT, .GPIOEN, .GPIOIntr);
   end else begin : gpio
-    assign GPIOOUT = 0; assign GPIOEN = 0; assign GPIOIntr = 0;
+    assign GPIOOUT = '0; assign GPIOEN = '0; assign GPIOIntr = 1'b0;
   end
-  if (P.UART_SUPPORTED == 1) begin : uart
+  if (P.UART_SUPPORTED == 1) begin : uartgen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769
     uart_apb #(P) uart(
       .PCLK, .PRESETn, .PSEL(PSEL[3]), .PADDR(PADDR[2:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, 
       .PRDATA(PRDATA[3]), .PREADY(PREADY[3]), 
@@ -147,7 +184,7 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
       .SOUT(UARTSout), .RTSb(), .DTRb(),                                // to E1A driver to RS232 interface
       .OUT1b(), .OUT2b(), .INTR(UARTIntr), .TXRDYb(), .RXRDYb());       // to CPU
   end else begin : uart
-    assign UARTSout = 0; assign UARTIntr = 0; 
+    assign UARTSout = 1'b0; assign UARTIntr = 1'b0; 
   end
   if (P.SPI_SUPPORTED == 1) begin : spi
     spi_apb  #(P) spi (
@@ -155,7 +192,53 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
       .PREADY(PREADY[4]), .PRDATA(PRDATA[4]), 
       .SPIOut, .SPIIn, .SPICS, .SPIIntr);
   end else begin : spi
-    assign SPIOut = 0; assign SPICS = 0; assign SPIIntr = 0;
+    assign SPIOut = 1'b0; assign SPICS = '0; assign SPIIntr = 1'b0;
+  end
+
+  if (P.BSG_DMC_SUPPORTED == 1) begin : bsg_dmc_config
+    bsg_dmc_config_apb #(P.XLEN) bsg_dmc_conf (
+      .PCLK, .PRESETn, .PSEL(PSEL[5]), .PADDR(PADDR[7:0]), .PWDATA, .PWRITE, .PENABLE,
+      .PRDATA(PRDATA[5]), .PREADY(PREADY[5]),
+      .ui_clk, .dmc_trefi, .dmc_tmrd, .dmc_trfc, .dmc_trc, .dmc_trp, .dmc_tras, .dmc_trrd,
+      .dmc_trcd, .dmc_twr, .dmc_twtr, .dmc_trtp, .dmc_tcas, .dmc_col_width, .dmc_row_width,
+      .dmc_bank_width, .dmc_bank_pos, .dmc_dqs_sel_cal, .dmc_init_cycles, .dmc_config_changed);
+  end else begin : bsg_dmc_config
+    assign dmc_trefi        = 0;
+    assign dmc_tmrd         = 0;
+    assign dmc_trfc         = 0;
+    assign dmc_trc          = 0;
+    assign dmc_trp          = 0;
+    assign dmc_tras         = 0;
+    assign dmc_trrd         = 0;
+    assign dmc_trcd         = 0;
+    assign dmc_twr          = 0;
+    assign dmc_twtr         = 0;
+    assign dmc_trtp         = 0;
+    assign dmc_tcas         = 0;
+    assign dmc_col_width    = 0;
+    assign dmc_row_width    = 0;
+    assign dmc_bank_width   = 0;
+    assign dmc_bank_pos     = 0;
+    assign dmc_dqs_sel_cal  = 0;
+    assign dmc_init_cycles  = 0;
+    assign dmc_config_changed      = 0;
+  end
+
+  if (P.PLL_SUPPORTED == 1) begin : pll_config
+    pll_config_apb #(P.XLEN) pll_conf (
+      .PCLK, .PRESETn, .PSEL(PSEL[6]), .PADDR(PADDR[7:0]), .PWDATA, .PWRITE, .PENABLE,
+      .PRDATA(PRDATA[6]), .PREADY(PREADY[6]),
+      .PLLrefclk, .PLLrfen, .PLLfben, 
+      .PLLclkr, .PLLclkf, .PLLclkod, .PLLbwadj, .PLLtest, .PLLfasten, .PLLlock,
+      .PLLconfigdone);
+  end else begin : pll_config
+    assign PLLclkr       = 0;
+    assign PLLclkf       = 0;
+    assign PLLclkod      = 0;
+    assign PLLbwadj      = 0;
+    assign PLLtest       = 0;
+    assign PLLfasten     = 0;
+    assign PLLconfigdone = 1;
   end
 
   // AHB Read Multiplexer
@@ -170,7 +253,7 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
                  HSELBootRomD & HRESPBootRom;
   
   assign HREADY = HSELRamD & HREADYRam |
-		          (HSELEXTD | HSELEXTSDCD) & HREADYEXT |		  
+		              (HSELEXTD | HSELEXTSDCD) & HREADYEXT |		  
                   HSELBRIDGED & HREADYBRIDGE |
                   HSELBootRomD & HREADYBootRom |
                   HSELNoneD; // don't lock up the bus if no region is being accessed
@@ -180,8 +263,9 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
   // takes more than 1 cycle to repsond it needs to hold on to the old select until the
   // device is ready.  Hense this register must be selectively enabled by HREADY.
   // However on reset None must be seleted.
-  flopenl #(12) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 12'b1, 
-    {HSELSPID, HSELEXTSDCD, HSELPLICD, HSELUARTD, HSELGPIOD, HSELCLINTD,
-      HSELRamD, HSELBootRomD, HSELEXTD, HSELIROMD, HSELDTIMD, HSELNoneD});
+  flopenl #(14) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[13:0], 14'b1, 
+    {HSELPLLCONFD, HSELBSGDMCCONFD, HSELSPID, HSELEXTSDCD, HSELPLICD, HSELUARTD,
+     HSELGPIOD, HSELCLINTD, HSELRamD, HSELBootRomD, HSELEXTD, HSELIROMD, HSELDTIMD,
+     HSELNoneD});
   flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);
 endmodule
diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv
index 440307806..8b47378af 100644
--- a/src/wally/wallypipelinedcore.sv
+++ b/src/wally/wallypipelinedcore.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: Pipelined RISC-V Processor
 // 
-// Documentation: RISC-V System on Chip Design (Figure 4.1)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -44,12 +44,39 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
    output logic [2:0]            HBURST,
    output logic [3:0]            HPROT,
    output logic [1:0]            HTRANS,
-   output logic                  HMASTLOCK
+   output logic                  HMASTLOCK,
+   // Debug Mode Control
+   input  logic                  HaltReq,
+   input  logic                  ResumeReq,
+   input  logic                  HaltOnReset,
+   input  logic                  AckHaveReset,
+   output logic                  ResumeAck,
+   output logic                  HaveReset,
+   output logic                  DebugStall,
+   input  logic                  ExecProgBuf,
+   // Debug scan chain
+   input  logic                  DebugScanEn,    // puts scannable flops into scan mode
+   output logic                  DebugScanOut,   // (misc) scan chain data out
+   output logic                  GPRScanOut,     // (GPR) scan chain data out
+   output logic                  FPRScanOut,     // (FPR) scan chain data out
+   output logic                  CSRScanOut,     // (CSR) scan chain data out
+   input  logic                  DebugScanIn,    // scan chain data in
+   input  logic                  MiscSel,        // selects general scan chain
+   input  logic                  GPRSel,         // selects GPR scan chain
+   input  logic                  FPRSel,         // selects FPR scan chain
+   input  logic                  CSRSel,         // selects CSR scan chain
+   input  logic [11:0]           DebugRegAddr,   // address for scanable regfiles (GPR, FPR, CSR)
+   input  logic                  DebugCapture,   // latches values into scan register before scanning out
+   input  logic                  DebugRegUpdate,  // writes values from scan register after scanning in	
+   input  logic [P.XLEN-1:0]     ProgBufAddr,
+   input  logic                  ProgBuffScanEn
 );
 
   logic                          StallF, StallD, StallE, StallM, StallW;
   logic                          FlushD, FlushE, FlushM, FlushW;
   logic                          TrapM, RetM;
+  logic                          DebugMode, Step;
+  logic                          ebreakEn;
 
   //  signals that must connect through DP
   logic                          IntDivE, W64E;
@@ -104,7 +131,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
 
   // memory management unit signals
   logic                          ITLBWriteF;
-  logic                          ITLBMissF;
+  logic                          ITLBMissOrUpdateAF;
   logic [P.XLEN-1:0]             SATP_REGW;
   logic                          STATUS_MXR, STATUS_SUM, STATUS_MPRV;
   logic [1:0]                    STATUS_MPP, STATUS_FS;
@@ -115,8 +142,10 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
   logic                          SelHPTW;
 
   // PMA checker signals
+  /* verilator lint_off UNDRIVEN */ // these signals are undriven in configurations without a privileged unit
   var logic [P.PA_BITS-3:0]      PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0];
   var logic [7:0]                PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0];
+  /* verilator lint_on UNDRIVEN */
 
   // IMem stalls
   logic                          IFUStallF;
@@ -146,11 +175,11 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
   logic                          LSUHREADY;
   
   logic                          BPWrongE, BPWrongM;
-  logic                          BPDirPredWrongM;
+  logic                          BPDirWrongM;
   logic                          BTAWrongM;
   logic                          RASPredPCWrongM;
   logic                          IClassWrongM;
-  logic [3:0]                    InstrClassM;
+  logic [3:0]                    IClassM;
   logic                          InstrAccessFaultF, HPTWInstrAccessFaultF, HPTWInstrPageFaultF;
   logic [2:0]                    LSUHSIZE;
   logic [2:0]                    LSUHBURST;
@@ -160,13 +189,22 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
   logic                          DCacheAccess;
   logic                          ICacheMiss;
   logic                          ICacheAccess;
-  logic                          InstrUpdateDAF;
   logic                          BigEndianM;
   logic                          FCvtIntE;
   logic                          CommittedF;
   logic                          BranchD, BranchE, JumpD, JumpE;
   logic                          DCacheStallM, ICacheStallF;
   logic                          wfiM, IntPendingM;
+  logic                          ebreakM;
+
+  // Debug mode logic
+  logic [P.XLEN-1:0]             DPC;
+  logic                          DRet;
+  logic                          DCall;
+  logic [2:0]                    DebugCause;
+  logic                          ForceBreakPoint;
+  // Debug register scan chain interconnects
+  logic [2:0]                    DebugScanReg;
 
   // instruction fetch unit: PC, branch prediction, instruction cache
   ifu #(P) ifu(.clk, .reset,
@@ -181,15 +219,17 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
     .PCLinkE, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCE, .BPWrongE,  .BPWrongM, 
     // Mem
     .CommittedF, .EPCM, .TrapVectorM, .RetM, .TrapM, .InvalidateICacheM, .CSRWriteFenceM,
-    .InstrD, .InstrM, .InstrOrigM, .PCM, .InstrClassM, .BPDirPredWrongM,
+    .InstrD, .InstrM, .InstrOrigM, .PCM, .IClassM, .BPDirWrongM,
     .BTAWrongM, .RASPredPCWrongM, .IClassWrongM,
     // Faults out
     .IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM,
     // mmu management
     .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
-    .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, .ITLBWriteF, .sfencevmaM, .ITLBMissF,
-    // pmp/pma (inside mmu) signals. 
-    .PMPCFG_ARRAY_REGW,  .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrUpdateDAF); 
+    .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, .ITLBWriteF, .sfencevmaM, .ITLBMissOrUpdateAF,
+    // pmp/pma (inside mmu) signals.
+    .PMPCFG_ARRAY_REGW,  .PMPADDR_ARRAY_REGW, .InstrAccessFaultF,
+    .DRet, .ProgBuffScanEn, .ProgBufAddr, .ProgBufScanIn(DebugScanIn),
+    .DebugScanEn(DebugScanEn & MiscSel), .DebugScanIn(DebugScanReg[0]), .DebugScanOut(DebugScanReg[1]));
     
   // integer execution unit: integer register file, datapath and controller
   ieu #(P) ieu(.clk, .reset,
@@ -214,7 +254,9 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
      // hazards
      .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
      .StructuralStallD, .LoadStallD, .StoreStallD, .PCSrcE,
-     .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .InvalidateICacheM); 
+     .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .InvalidateICacheM,
+     .DebugScanEn, .DebugScanIn(DebugScanReg[1]), .GPRScanIn(DebugScanIn), .DebugScanOut(DebugScanReg[2]), .GPRScanOut,
+     .MiscSel, .GPRSel, .DebugCapture, .DebugRegUpdate, .DebugRegAddr(DebugRegAddr[4:0]));
 
   lsu #(P) lsu(
     .clk, .reset, .StallM, .FlushM, .StallW, .FlushW,
@@ -248,9 +290,8 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
     .HPTWInstrPageFaultF,         // connects to privilege
     .StoreAmoMisalignedFaultM,    // connects to privilege
     .StoreAmoAccessFaultM,        // connects to privilege
-    .InstrUpdateDAF,
-    .PCSpillF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
-    .LSUStallM);                    
+    .PCSpillF, .ITLBMissOrUpdateAF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
+    .LSUStallM, .DebugCapture, .DebugScanEn(DebugScanEn & MiscSel), .DebugScanIn(DebugScanReg[2]), .DebugScanOut);                    
 
   if(P.BUS_SUPPORTED) begin : ebu
     ebu #(P) ebu(// IFU connections
@@ -264,19 +305,32 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
       .HREADY, .HRESP, .HCLK, .HRESETn,
       .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
       .HPROT, .HTRANS, .HMASTLOCK);
+  end else begin
+    assign {IFUHREADY, LSUHREADY, HCLK, HRESETn, HADDR, HWDATA,
+            HWSTRB, HWRITE, HSIZE, HBURST, HPROT, HTRANS, HMASTLOCK} = '0;
   end
 
   // global stall and flush control  
   hazard #(P) hzu(
-    .BPWrongE, .CSRWriteFenceM, .RetM, .TrapM,
+    .BPWrongE, .CSRWriteFenceM, .RetM, .TrapM, .DRet,
     .StructuralStallD,
     .LSUStallM, .IFUStallF,
     .FPUStallD,
     .DivBusyE, .FDivBusyE,
-    .wfiM, .IntPendingM,
+    .wfiM, .IntPendingM, .DebugStall,
     // Stall & flush outputs
     .StallF, .StallD, .StallE, .StallM, .StallW,
-    .FlushD, .FlushE, .FlushM, .FlushW);    
+    .FlushD, .FlushE, .FlushM, .FlushW);
+
+  if (P.DEBUG_SUPPORTED) begin
+    dmc debugcontrol(
+      .clk, .reset,
+      .Step, .ebreakM, .ebreakEn, .HaltReq, .ResumeReq, .HaltOnReset, .AckHaveReset,
+      .ResumeAck, .HaveReset, .DebugMode, .DebugCause, .DebugStall, .ExecProgBuf,
+      .DCall, .DRet, .ForceBreakPoint);
+  end else begin
+    assign {DebugMode, DebugCause, ResumeAck, HaveReset, DebugStall, DCall, DRet, ForceBreakPoint} = '0;
+  end
 
   // privileged unit
   if (P.ZICSR_SUPPORTED) begin:priv
@@ -288,9 +342,9 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
       .RetM, .TrapM, .sfencevmaM, .InvalidateICacheM, .DCacheStallM, .ICacheStallF,
       .InstrValidM, .CommittedM, .CommittedF,
       .FRegWriteM, .LoadStallD, .StoreStallD,
-      .BPDirPredWrongM, .BTAWrongM, .BPWrongM,
+      .BPDirWrongM, .BTAWrongM, .BPWrongM,
       .RASPredPCWrongM, .IClassWrongM, .DivBusyE, .FDivBusyE,
-      .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
+      .IClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
       .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
       .InstrMisalignedFaultM, .IllegalIEUFPUInstrD, 
       .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
@@ -300,28 +354,35 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
       .PrivilegeModeW, .SATP_REGW,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, 
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
-      .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .wfiM, .IntPendingM, .BigEndianM);
+      .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .wfiM, .IntPendingM, .BigEndianM, .ebreakM,
+      .ebreakEn, .ForceBreakPoint, .DebugMode, .DebugCause, .Step, .DPC, .DCall,
+      .DRet, .ExecProgBuf, .DebugSel(CSRSel), .DebugRegAddr, .DebugCapture,
+      .DebugRegUpdate, .DebugScanEn(DebugScanEn & CSRSel), .DebugScanIn, .DebugScanOut(CSRScanOut));
+    if (P.DEBUG_SUPPORTED) begin
+      flopenrs #(1) scantrapm (.clk, .reset, .en(DebugCapture), .d(TrapM), .q(),
+        .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DebugScanReg[0]));
+    end else begin
+      assign DebugScanReg[0] = DebugScanIn;
+    end
   end else begin
-    assign CSRReadValW      = 0;
-    assign EPCM             = 0;
-    assign TrapVectorM      = 0;
-    assign RetM             = 0;
-    assign TrapM            = 0;
-    assign wfiM             = 0;
-    assign IntPendingM      = 0;
-    assign sfencevmaM       = 0;
-    assign BigEndianM       = 0;
+    assign {CSRReadValW, PrivilegeModeW,
+            SATP_REGW, STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_MPP, STATUS_FS, FRM_REGW,
+            // PMPCFG_ARRAY_REGW, PMPADDR_ARRAY_REGW,
+            ENVCFG_CBE, ENVCFG_PBMTE, ENVCFG_ADUE,
+            EPCM, TrapVectorM, RetM, TrapM,
+            sfencevmaM, BigEndianM, wfiM, IntPendingM, CSRScanOut} = '0;
+    assign DebugScanReg[0] = DebugScanIn;
   end
 
   // multiply/divide unit
-  if (P.M_SUPPORTED | P.ZMMUL_SUPPORTED) begin:mdu
+  if (P.ZMMUL_SUPPORTED) begin:mdu
     mdu #(P) mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
       .ForwardedSrcAE, .ForwardedSrcBE, 
       .Funct3E, .Funct3M, .IntDivE, .W64E, .MDUActiveE,
       .MDUResultW, .DivBusyE); 
   end else begin // no M instructions supported
-    assign MDUResultW = 0; 
-    assign DivBusyE   = 0;
+    assign MDUResultW = '0; 
+    assign DivBusyE   = 1'b0;
   end
 
   // floating point unit
@@ -349,17 +410,18 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
       .FDivBusyE,                          // Is the divide/sqrt unit busy (stall execute stage)
       .IllegalFPUInstrD,                   // Is the instruction an illegal fpu instruction
       .SetFflagsM,                         // FPU flags (to privileged unit)
-      .FIntDivResultW); 
+      .FIntDivResultW,
+      .DebugSel(FPRSel),
+      .DebugRegAddr(DebugRegAddr[4:0]),
+      .DebugCapture,
+      .DebugRegUpdate,
+      .DebugScanEn(DebugScanEn & FPRSel),
+      .DebugScanIn,
+      .DebugScanOut(FPRScanOut));
   end else begin                           // no F_SUPPORTED or D_SUPPORTED; tie outputs low
-    assign FPUStallD        = 0;
-    assign FWriteIntE       = 0; 
-    assign FCvtIntE         = 0;
-    assign FIntResM         = 0;
-    assign FCvtIntW         = 0;
-    assign FDivBusyE        = 0;
-    assign IllegalFPUInstrD = 1;
-    assign SetFflagsM       = 0;
-    assign FpLoadStoreM     = 0;
+    assign {FPUStallD, FWriteIntE, FCvtIntE, FIntResM, FCvtIntW, FRegWriteM,
+            IllegalFPUInstrD, SetFflagsM, FpLoadStoreM,
+            FWriteDataM, FCvtIntResW, FIntDivResultW, FDivBusyE, FPRScanOut} = '0;
   end
   
 endmodule
diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv
index d82a5c0d4..bd8d6b135 100644
--- a/src/wally/wallypipelinedsoc.sv
+++ b/src/wally/wallypipelinedsoc.sv
@@ -6,7 +6,7 @@
 //
 // Purpose: System on chip including pipelined processor and uncore memories/peripherals
 //
-// Documentation: RISC-V System on Chip Design (Figure 6.20)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -27,27 +27,36 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
+module wallypipelinedsoc 
+  import cvw::*;
+#(
+  parameter cvw_t P
+)  (
   input  logic                clk, 
   input  logic                reset_ext,        // external asynchronous reset pin
   output logic                reset,            // reset synchronized to clk to prevent races on release
+  // JTAG signals                                                                                                                    
+  input  logic                 tck,
+  input  logic                 tdi,
+  input  logic                 tms,
+  output logic                 tdo,
   // AHB Interface
-  input  logic [P.AHBW-1:0]     HRDATAEXT,
-  input  logic                HREADYEXT, HRESPEXT,
-  output logic                HSELEXT,
-  output logic                HSELEXTSDC, 
+  input  logic [P.AHBW-1:0]    HRDATAEXT,
+  input  logic                 HREADYEXT, HRESPEXT,
+  output logic                 HSELEXT,
+  output logic                 HSELEXTSDC, 
   // outputs to external memory, shared with uncore memory
-  output logic                HCLK, HRESETn,
-  output logic [P.PA_BITS-1:0]  HADDR,
-  output logic [P.AHBW-1:0]     HWDATA,
-  output logic [P.XLEN/8-1:0]   HWSTRB,
-  output logic                HWRITE,
-  output logic [2:0]          HSIZE,
-  output logic [2:0]          HBURST,
-  output logic [3:0]          HPROT,
-  output logic [1:0]          HTRANS,
-  output logic                HMASTLOCK,
-  output logic                HREADY,
+  output logic                 HCLK, HRESETn,
+  output logic [P.PA_BITS-1:0] HADDR,
+  output logic [P.AHBW-1:0]    HWDATA,
+  output logic [P.XLEN/8-1:0]  HWSTRB,
+  output logic                 HWRITE,
+  output logic [2:0]           HSIZE,
+  output logic [2:0]           HBURST,
+  output logic [3:0]           HPROT,
+  output logic [1:0]           HTRANS,
+  output logic                 HMASTLOCK,
+  output logic                 HREADY,
   // I/O Interface
   input  logic                TIMECLK,          // optional for CLINT MTIME counter
   input  logic [31:0]         GPIOIN,           // inputs from GPIO
@@ -58,33 +67,123 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
   input  logic                SDCIntr,
   input  logic                SPIIn,            // SPI pins in
   output logic                SPIOut,           // SPI pins out
-  output logic [3:0]          SPICS             // SPI chip select pins                    
+  output logic [3:0]          SPICS,            // SPI chip select pins        
+  input  logic                ui_clk,
+  output logic [15:0]         dmc_trefi,
+  output logic [3:0]          dmc_tmrd,
+  output logic [3:0]          dmc_trfc,
+  output logic [3:0]          dmc_trc,
+  output logic [3:0]          dmc_trp,
+  output logic [3:0]          dmc_tras,
+  output logic [3:0]          dmc_trrd,
+  output logic [3:0]          dmc_trcd,
+  output logic [3:0]          dmc_twr,
+  output logic [3:0]          dmc_twtr,
+  output logic [3:0]          dmc_trtp,
+  output logic [3:0]          dmc_tcas,
+  output logic [3:0]          dmc_col_width,
+  output logic [3:0]          dmc_row_width,
+  output logic [1:0]          dmc_bank_width,
+  output logic [5:0]          dmc_bank_pos,
+  output logic [2:0]          dmc_dqs_sel_cal,
+  output logic [15:0]         dmc_init_cycles,
+  output logic                dmc_config_changed,
+  input  logic                PLLrefclk,
+  input  logic                PLLrfen,
+  input  logic                PLLfben,
+  output logic [5:0]          PLLclkr,
+  output logic [12:0]         PLLclkf,
+  output logic [3:0]          PLLclkod,
+  output logic [11:0]         PLLbwadj,
+  output logic                PLLtest,
+  output logic                PLLfasten,
+  input  logic                PLLlock,
+  output logic                PLLconfigdone
 );
 
   // Uncore signals
-  logic [P.AHBW-1:0]          HRDATA;           // from AHB mux in uncore
-  logic                       HRESP;            // response from AHB
-  logic                       MTimerInt, MSwInt;// timer and software interrupts from CLINT
-  logic [63:0]                MTIME_CLINT;      // from CLINT to CSRs
-  logic                       MExtInt,SExtInt;  // from PLIC
+  logic [P.AHBW-1:0]           HRDATA;            // from AHB mux in uncore
+  logic                        HRESP;             // response from AHB
+  logic                        MTimerInt, MSwInt; // timer and software interrupts from CLINT
+  logic [63:0]                 MTIME_CLINT;       // from CLINT to CSRs
+  logic                        MExtInt,SExtInt;   // from PLIC
+
+  // Debug Mode control signals
+  logic                        NdmReset;
+  logic                        HaltReq;
+  logic                        ResumeReq;
+  logic                        HaltOnReset;
+  logic                        AckHaveReset;
+  logic                        ResumeAck;
+  logic                        HaveReset;
+  logic                        DebugStall;
+  logic                        ExecProgBuf;
+
+  // Debug Module signals
+  logic                        DebugScanEn;
+  logic                        DebugScanIn;
+  logic                        GPRScanIn;
+  logic                        FPRScanIn;
+  logic                        CSRScanIn;
+  logic                        DebugScanOut;
+  logic                        MiscSel;
+  logic                        GPRSel;
+  logic                        FPRSel;
+  logic                        CSRSel;
+  logic [11:0]                 DebugRegAddr;
+  logic                        DebugCapture;
+  logic                        DebugRegUpdate;
+  logic [P.XLEN-1:0]           ProgBufAddr;
+  logic                        ProgBuffScanEn;
 
   // synchronize reset to SOC clock domain
-  synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); 
+  synchronizer resetsync(.clk, .d(reset_ext), .q(reset));
    
   // instantiate processor and internal memories
-  wallypipelinedcore #(P) core(.clk, .reset,
-    .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
-    .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
-    .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK
-   );
+  wallypipelinedcore #(P) core (
+    .clk, .reset(reset || NdmReset), .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
+    .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
+    .HPROT, .HTRANS, .HMASTLOCK, .HaltReq, .ResumeReq, .HaltOnReset, .AckHaveReset, .ResumeAck,
+    .HaveReset, .DebugStall, .ExecProgBuf, .DebugScanEn, .DebugScanOut(DebugScanIn),
+    .GPRScanOut(GPRScanIn), .FPRScanOut(FPRScanIn), .CSRScanOut(CSRScanIn),
+    .DebugScanIn(DebugScanOut), .MiscSel, .GPRSel, .FPRSel, .CSRSel, .DebugRegAddr, .DebugCapture,
+    .DebugRegUpdate, .ProgBufAddr, .ProgBuffScanEn
+  );
 
   // instantiate uncore if a bus interface exists
-  if (P.BUS_SUPPORTED) begin : uncore
-    uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK,
-      .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
-      .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC,
-      .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, 
-      .UARTSout, .MTIME_CLINT, .SDCIntr, .SPIIn, .SPIOut, .SPICS);
+  if (P.BUS_SUPPORTED) begin : uncoregen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769
+    uncore #(P) uncore (
+      .HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+      .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
+      .HSELEXTSDC, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin,
+      .UARTSout, .MTIME_CLINT, .SDCIntr, .SPIIn, .SPIOut, .SPICS, .ui_clk, .dmc_trefi, .dmc_tmrd,
+      .dmc_trfc, .dmc_trc, .dmc_trp, .dmc_tras, .dmc_trrd, .dmc_trcd, .dmc_twr, .dmc_twtr,
+      .dmc_trtp, .dmc_tcas, .dmc_col_width, .dmc_row_width, .dmc_bank_width, .dmc_bank_pos,
+      .dmc_dqs_sel_cal, .dmc_init_cycles, .dmc_config_changed, .PLLrefclk, .PLLrfen, .PLLfben,
+      .PLLclkr, .PLLclkf, .PLLclkod, .PLLbwadj, .PLLtest, .PLLfasten, .PLLlock, .PLLconfigdone
+    );
+  end else begin
+    assign {HRDATA, HREADY, HRESP, HSELEXT, HSELEXTSDC, MTimerInt, MSwInt, MExtInt, SExtInt,
+            MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS, dmc_trefi, dmc_tmrd, dmc_trfc,
+            dmc_trc, dmc_trp, dmc_tras, dmc_trrd, dmc_trcd, dmc_twr, dmc_twtr, dmc_trtp, dmc_tcas,
+            dmc_col_width, dmc_row_width, dmc_bank_width, dmc_bank_pos, dmc_dqs_sel_cal,
+            dmc_init_cycles, dmc_config_changed, PLLclkr, PLLclkf, PLLclkod, PLLbwadj, PLLtest,
+            PLLfasten, PLLconfigdone} = '0;
+  end
+
+  // instantiate debug module
+  if (P.DEBUG_SUPPORTED) begin : dm
+    dm #(P) dm (
+      .clk, .rst(reset), .tck, .tdi, .tms, .tdo, .NdmReset, .HaltReq, .ResumeReq, .HaltOnReset,
+      .AckHaveReset, .ResumeAck, .HaveReset, .DebugStall, .DebugScanEn, .DebugScanIn, .GPRScanIn,
+      .FPRScanIn, .CSRScanIn, .DebugScanOut, .MiscSel, .GPRSel, .FPRSel, .CSRSel,
+      .RegAddr(DebugRegAddr), .DebugCapture, .DebugRegUpdate, .ProgBufAddr, .ProgBuffScanEn,
+      .ExecProgBuf
+    );
+  end else begin
+    assign {tdo, HaltReq, ResumeReq, HaltOnReset, AckHaveReset, DebugScanEn, DebugScanOut, MiscSel,
+            NdmReset, GPRSel, FPRSel, CSRSel, DebugRegAddr, DebugCapture, DebugRegUpdate,
+            ProgBufAddr, ProgBuffScanEn, ExecProgBuf} = '0;
   end
 
 endmodule
diff --git a/studies/comparator.sv b/studies/comparator.sv
index 01d38181b..1f9877077 100644
--- a/studies/comparator.sv
+++ b/studies/comparator.sv
@@ -7,7 +7,7 @@
 //
 // Purpose: Branch comparison
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
diff --git a/studies/ppa/ppa.sv b/studies/ppa/ppa.sv
index 5363bb9b6..6c9311e98 100644
--- a/studies/ppa/ppa.sv
+++ b/studies/ppa/ppa.sv
@@ -693,8 +693,6 @@ module ppa_mux8_128 #(parameter WIDTH = 128) (
   assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0)); 
 endmodule
 
-// *** some way to express data-critical inputs
-
 module ppa_flop #(parameter WIDTH = 8) ( 
   input  logic             clk,
   input  logic [WIDTH-1:0] d, 
diff --git a/synthDC/Makefile b/synthDC/Makefile
index 03c3c6612..513d54dba 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -40,79 +40,14 @@ DIRS32 = rv32e rv32gc rv32imc rv32i
 DIRS64 = rv64i rv64gc
 DIRS = $(DIRS32) $(DIRS64)
 
-# k = 3 6 
-# bpred:
-# 	@$(foreach kval, $(k), rm -rf $(CONFIGDIR)/rv64gc_bpred_$(kval);)
-# 	@$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);)
-# 	@$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/config.vh;)
-# 	@$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;)
-
 configs: $(CONFIG)
 $(CONFIG):
 	@echo $(CONFIG)
 	cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR)
-#   cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR)
-	cp -r $(OLDCONFIGDIR)/deriv/$(CONFIG)/* $(CONFIGDIR)
-
-# adjust DTIM and IROM to reasonable values depending on config	
-ifneq ($(filter $(CONFIG), $(DIRS32)),)
-	sed -i "s/DTIM_RANGE.*/DTIM_RANGE	= 34\'h01FF;/g" $(CONFIGDIR)/config.vh
-	sed -i "s/IROM_RANGE.*/IROM_RANGE	= 34\'h01FF;/g" $(CONFIGDIR)/config.vh
-else ifneq ($(filter $(CONFIG), $(DIRS64)),)
-	sed -i "s/DTIM_RANGE.*/DTIM_RANGE	= 56\'h01FF;/g" $(CONFIGDIR)/config.vh
-	sed -i "s/IROM_RANGE.*/IROM_RANGE	= 56\'h01FF;/g" $(CONFIGDIR)/config.vh
-else 
-	$(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64))
-	@echo "Config not in list, RAM_RANGE will be unmodified"
-endif
-
-# if USESRAM = 1, set that in the config file, otherwise reduce sizes
-ifeq ($(USESRAM), 1)
-	sed -i 's/USE_SRAM.*/USE_SRAM = 1;/g' $(CONFIGDIR)/config.vh
+ifeq ($(MOD), orig)
+	cp -rf $(OLDCONFIGDIR)/deriv/$(CONFIG)/config.vh $(CONFIGDIR) | true
 else
-	sed -i "s/WAYSIZEINBYTES.*/WAYSIZEINBYTES = 32\'d512;/g" $(CONFIGDIR)/config.vh
-	sed -i "s/NUMWAYS.*/NUMWAYS =32\'d1;/g" $(CONFIGDIR)/config.vh
-	sed -i "s/BPRED_SIZE.*/BPRED_SIZE =32\'d5;/g" $(CONFIGDIR)/config.vh
-	sed -i "s/BTB_SIZE.*/BTB_SIZE = 32\'d5;/g" $(CONFIGDIR)/config.vh
-ifneq ($(filter $(CONFIG), $(DIRS32)),)
-	sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 = 34\'h01FF;/g" $(CONFIGDIR)/config.vh
-	sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	= 34\'h01FF;/g" $(CONFIGDIR)/config.vh
-else ifneq ($(filter $(CONFIG), $(DIRS64)),)
-	sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 = 56\'h01FF;/g" $(CONFIGDIR)/config.vh
-	sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	= 56\'h01FF;/g" $(CONFIGDIR)/config.vh
-endif
-endif
-	
-# adjust config if synthesizing with any modifications
-# This code is subtle with ifneq.  It successively turns off a larger
-# set of features in order of cycle time limiting.
-# When mod = orig, all features are ON
-# When mod = PMP0, the number of PMP entries is set to 0
-# when mod = noPriv, the privileged unit and PMP are disabled
-# when mod = noFPU, the FPU, privileged unit, and PMP are disabled
-# when mod = noMulDiv, the MDU, FPU, privileged unit, and PMP are disabled.
-# when mod = noAtomic, the Atomic, MDU, FPU, privileged unit, and PMP are disabled
-
-ifneq ($(MOD), orig)
-	# PMP 0
-	sed -i 's/PMP_ENTRIES.*\(64\|16\)/PMP_ENTRIES = 0;/' $(CONFIGDIR)/config.vh
-ifneq ($(MOD), PMP0)
-	# no priv
-	sed -i 's/ZICSR_SUPPORTED.*1/ZICSR_SUPPORTED = 0;/' $(CONFIGDIR)/config.vh
-ifneq ($(MOD), noPriv)
-	# turn off FPU 
-	sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/config.vh
-	sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/config.vh
-ifneq ($(MOD), noFPU)
-	# no muldiv
-	sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/config.vh
-ifneq ($(MOD), noMulDiv)
-	# no atomic
-	sed -i 's/1 *<< *0/0 << 0/' $(CONFIGDIR)/config.vh
-endif
-endif
-endif
-endif
+	cp -rf $(OLDCONFIGDIR)/deriv/$(CONFIG)_$(MOD)/config.vh $(CONFIGDIR) | true
 endif
 
 ifeq ($(SAIFPOWER), 1)
diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py
index d6f5933a9..354c6f70f 100755
--- a/synthDC/extractSummary.py
+++ b/synthDC/extractSummary.py
@@ -33,19 +33,28 @@ def synthsintocsv():
 
     for oneSynth in allSynths:
         descrip = specReg.findall(oneSynth)
-        width = descrip[2][:4]
-        config = descrip[2][4:]
-        if descrip[3][-2:] == 'nm':
+#        print("From " + oneSynth + " Find ")
+#        for d in descrip:
+#            print(d)
+        if (descrip[3] == "sram"):
+            base = 4
+        else:
+            base = 3
+        width = descrip[base][:4]
+        config = descrip[base][4:]
+        if descrip[base+1][-2:] == 'nm':
             mod = ''
         else:
-            mod = descrip[3]
+            mod = descrip[base+1]
             descrip = descrip[1:]
-        tech = descrip[3][:-2]
-        freq = descrip[4]
+        tech = descrip[base+1][:-2]
+        freq = descrip[base+2]
+#        print(width, config, mod, tech, freq)
         metrics = []
         for phrase in ['Path Slack', 'Design Area']:
             bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*qor*'
             bashCommand = bashCommand.format(phrase)
+#            print(bashCommand)
             try: 
                 output = subprocess.check_output(['bash','-c', bashCommand])
                 nums = metricReg.findall(str(output))
diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py
index c7d18830e..a5e8b5d6b 100755
--- a/synthDC/wallySynth.py
+++ b/synthDC/wallySynth.py
@@ -7,7 +7,12 @@
 
 def runSynth(config, mod, tech, freq, maxopt, usesram):
     global pool
-    command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(config, mod, tech, freq, maxopt, usesram)
+    if (usesram):
+            prefix = "syn_sram_"
+    else:
+            prefix = "syn_"
+    cfg = prefix + config
+    command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(cfg, mod, tech, freq, maxopt, usesram)
     pool.map(mask, [command])
 
 def mask(command):
@@ -56,7 +61,7 @@ def mask(command):
         defaultfreq = 500 if tech == 'sky90' else 1500
         freq = args.targetfreq if args.targetfreq else defaultfreq
         config = args.version if args.version else 'rv64gc'
-        for mod in ['noAtomic', 'noFPU', 'noMulDiv', 'noPriv', 'PMP0']: 
+        for mod in ['noAtomic', 'noFPU', 'noMulDiv', 'noPriv', 'pmp0']: 
             runSynth(config, mod, tech, freq, maxopt, usesram)
     else:
         defaultfreq = 500 if tech == 'sky90' else 1500
diff --git a/synthDC/wallySynthAll.sh b/synthDC/wallySynthAll.sh
index 9af40a379..f235c73e3 100755
--- a/synthDC/wallySynthAll.sh
+++ b/synthDC/wallySynthAll.sh
@@ -1,14 +1,21 @@
 # Run all Wally synthesis experiments from chapter 8
 # However, trying to run the freqsweeps at the same time maxes out licenses and some runs fail
-#./wallySynth.py --freqsweep 330 --tech sky130 
-#./wallySynth.py --freqsweep 870 --tech sky90 
-#./wallySynth.py --freqsweep 2800 --tech tsmc28psyn --usesram
+# Adding the sleep gives them time to finish.
+./wallySynth.py --freqsweep 330 --tech sky130 
+sleep 300 
+./wallySynth.py --freqsweep 870 --tech sky90 
+sleep 300 
+./wallySynth.py --freqsweep 2800 --tech tsmc28psyn --usesram
+sleep 300 
+
+# These jobs can run in parallel and take longer
 ./wallySynth.py --configsweep --tech sky130 --targetfreq 330
 ./wallySynth.py --configsweep --tech sky90 --targetfreq 870
 ./wallySynth.py --configsweep --tech tsmc28psyn --targetfreq 2800 --usesram
 ./wallySynth.py --featuresweep --tech sky130 --targetfreq 330
 ./wallySynth.py --featuresweep --tech sky90 --targetfreq 870
 ./wallySynth.py --featuresweep --tech tsmc28psyn --targetfreq 2800 --usesram
+
 # Extract summary data (run this by hand after all experiments finish)
-#./extractSummary.py --sky130freq 330 --sky90freq 870 --tsmcfreq 2800
+./extractSummary.py --sky130freq 330 --sky90freq 870 --tsmcfreq 2800
 
diff --git a/testbench/common/DCacheFlushFSM.sv b/testbench/common/DCacheFlushFSM.sv
index 152aaa173..752c8322d 100644
--- a/testbench/common/DCacheFlushFSM.sv
+++ b/testbench/common/DCacheFlushFSM.sv
@@ -29,7 +29,6 @@
 
 module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) 
   (input logic clk,
-   input logic reset,
    input logic start,
    output logic done);
 
@@ -65,13 +64,13 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P)
           .loglinebytelen(loglinebytelen), .sramlen(sramlen))
           copyShadow(.clk,
           .start,
-          .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS-1-tagstart:0]),
+          .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.ram.RAM[index][P.PA_BITS-1-tagstart:0]),
           .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
           .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
                            // these dirty bit selections would be needed if dirty is moved inside the tag array.
           //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
           //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS+tagstart]),
-          .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.RAM[index]),
+          .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.ram.RAM[index]),
           .index(index),
           .cacheWord(cacheWord),
           .CacheData(CacheData[way][index][cacheWord]),
@@ -98,7 +97,7 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P)
                   // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
                   //ShadowRAM[CacheAdr[j][i][k] >> $clog2(P.XLEN/8)] = cacheline[P.XLEN*(k+1)-1:P.XLEN*k];
                   /* verilator lint_off WIDTHTRUNC */
-                  // *** lint error: address trunc warning for shadowram index
+                  // avoid lint error: address trunc warning for shadowram index
                   ShadowRAM[(CacheAdr[j][i][l] >> $clog2(P.XLEN/8)) + {{{P.PA_BITS-32}{1'b0}}, k}] = CacheData[j][i][l][P.XLEN*k +: P.XLEN];
                   /* verilator lint_on WIDTHTRUNC */
                 end
diff --git a/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv
index b433b2ed8..80f6ed607 100644
--- a/testbench/common/instrNameDecTB.sv
+++ b/testbench/common/instrNameDecTB.sv
@@ -58,17 +58,17 @@ module instrNameDecTB(
                        else if (funct7[6:1] == 6'b010010) name = "BCLRI";
                        else if (funct7[6:1] == 6'b011010) name = "BINVI";
                        else if (funct7[6:1] == 6'b001010) name = "BSETI";
-                       else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "ZIP";
-                       else if (funct7 == 7'b0011000 && rs2 == 5'b00000) name = "AES64IM";
-                       else if (funct7 == 7'b0011000 && rs2[4] == 1'b1) name = "AES64KS1I";
-                       else if (funct7 == 7'b0001000 && rs2 == 5'b00010) name = "SHA256SIG0";
-                       else if (funct7 == 7'b0001000 && rs2 == 5'b00011) name = "SHA256SIG1";
-                       else if (funct7 == 7'b0001000 && rs2 == 5'b00000) name = "SHA256SUM0";
-                       else if (funct7 == 7'b0001000 && rs2 == 5'b00001) name = "SHA256SUM1";
-                       else if (funct7 == 7'b0001000 && rs2 == 5'b00110) name = "SHA512SIG0";
-                       else if (funct7 == 7'b0001000 && rs2 == 5'b00111) name = "SHA512SIG1";
-                       else if (funct7 == 7'b0001000 && rs2 == 5'b00100) name = "SHA512SUM0";
-                       else if (funct7 == 7'b0001000 && rs2 == 5'b00101) name = "SHA512SUM1";
+                       else if (funct7 == 7'b0000100 & rs2 == 5'b01111) name = "ZIP";
+                       else if (funct7 == 7'b0011000 & rs2 == 5'b00000) name = "AES64IM";
+                       else if (funct7 == 7'b0011000 & rs2[4] == 1'b1) name = "AES64KS1I";
+                       else if (funct7 == 7'b0001000 & rs2 == 5'b00010) name = "SHA256SIG0";
+                       else if (funct7 == 7'b0001000 & rs2 == 5'b00011) name = "SHA256SIG1";
+                       else if (funct7 == 7'b0001000 & rs2 == 5'b00000) name = "SHA256SUM0";
+                       else if (funct7 == 7'b0001000 & rs2 == 5'b00001) name = "SHA256SUM1";
+                       else if (funct7 == 7'b0001000 & rs2 == 5'b00110) name = "SHA512SIG0";
+                       else if (funct7 == 7'b0001000 & rs2 == 5'b00111) name = "SHA512SIG1";
+                       else if (funct7 == 7'b0001000 & rs2 == 5'b00100) name = "SHA512SUM0";
+                       else if (funct7 == 7'b0001000 & rs2 == 5'b00101) name = "SHA512SUM1";
                        else if (funct7 == 7'b0110000) begin
                          case (rs2)
                            5'b00000: name = "CLZ";
@@ -89,7 +89,7 @@ module instrNameDecTB(
                        else if (funct7[6:1] == 6'b010010) name = "BEXTI";
                        else if (funct7 == 7'b0010100 & rs2 == 5'b00111) name = "ORC.B";
                        else if (imm == 12'b011010000111) name = "BREV8";
-                       else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "UNZIP";
+                       else if (funct7 == 7'b0000100 & rs2 == 5'b01111) name = "UNZIP";
                        else                           name = "ILLEGAL"; 
       10'b0010011_110: if      (rd == 0 & rs2 == 0) name = "PREFETCH.I";
                        else if (rd == 0 & rs2 == 1) name = "PREFETCH.R";
@@ -181,9 +181,9 @@ module instrNameDecTB(
                        else if (funct7 == 7'b0010000) name = "SH2ADD";
                        else if (funct7 == 7'b0000101) name = "MIN";
                        else if (funct7 == 7'b0100000) name = "ORN";
-                       else if (funct7 == 7'b0000100 && rs2 == 5'b00000) name = "ZEXT.H";
-                       else if (funct7 == 7'b0000100 && op == 7'b0110011) name = "PACK";
-                       else if (funct7 == 7'b0000100 && op == 7'b0111011) name = "PACKW";
+                       else if (funct7 == 7'b0000100 & rs2 == 5'b00000) name = "ZEXT.H";
+                       else if (funct7 == 7'b0000100 & op == 7'b0110011) name = "PACK";
+                       else if (funct7 == 7'b0000100 & op == 7'b0111011) name = "PACKW";
                        else                           name = "ILLEGAL";
       10'b0110011_101: if      (funct7 == 7'b0000000) name = "SRL";
                        else if (funct7 == 7'b0000001) name = "DIVU";
diff --git a/testbench/common/instrTrackerTB.sv b/testbench/common/instrTrackerTB.sv
index 429ff8489..f4ec8523d 100644
--- a/testbench/common/instrTrackerTB.sv
+++ b/testbench/common/instrTrackerTB.sv
@@ -34,5 +34,5 @@ module instrTrackerTB(
   instrNameDecTB ddec(InstrD, InstrDName);
   instrNameDecTB edec(InstrE, InstrEName);
   instrNameDecTB mdec(InstrM, InstrMName);
-  instrNameDecTB wdec(InstrW, InstrWName); // *** delete this because InstrW is deleted from IFU
+  instrNameDecTB wdec(InstrW, InstrWName);
 endmodule
diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv
index 4104bd0ec..967cf672b 100644
--- a/testbench/common/loggers.sv
+++ b/testbench/common/loggers.sv
@@ -153,7 +153,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
     end
   end
 
-  if (P.ICACHE_SUPPORTED && I_CACHE_ADDR_LOGGER) begin : ICacheLogger
+  if (P.ICACHE_SUPPORTED & I_CACHE_ADDR_LOGGER) begin : ICacheLogger
     int    file;
     string LogFile;
     logic  resetD, resetEdge;
@@ -193,7 +193,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
   end
 
 
-  if (P.DCACHE_SUPPORTED && D_CACHE_ADDR_LOGGER) begin : DCacheLogger
+  if (P.DCACHE_SUPPORTED & D_CACHE_ADDR_LOGGER) begin : DCacheLogger
     int    file;
     string LogFile;
     logic  resetD, resetEdge;
@@ -261,11 +261,11 @@ module loggers import cvw::*; #(parameter cvw_t P,
           $fwrite(file, "BEGIN %s\n", memfilename);
           $fwrite(CFIfile, "BEGIN %s\n", memfilename);
         end
-        if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
+        if(dut.core.ifu.IClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
           direction = PCSrcM ? "t" : "n";
           $fwrite(file, "%h %s\n", dut.core.PCM, direction);
         end
-        if((|dut.core.ifu.InstrClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
+        if((|dut.core.ifu.IClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
           direction = PCSrcM ? "t" : "n";
           $fwrite(CFIfile, "%h %s\n", dut.core.PCM, direction);
         end
diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv
index 3f50d3f7c..404353909 100644
--- a/testbench/common/riscvassertions.sv
+++ b/testbench/common/riscvassertions.sv
@@ -21,52 +21,51 @@
 
 module riscvassertions import cvw::*; #(parameter cvw_t P);
   initial begin
-    assert (P.PMP_ENTRIES == 0 || P.PMP_ENTRIES==16 || P.PMP_ENTRIES==64) else $fatal(1, "Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
-    assert (P.S_SUPPORTED || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "Virtual memory requires S mode support");
-    assert (P.IDIV_BITSPERCYCLE == 1 || P.IDIV_BITSPERCYCLE==2 || P.IDIV_BITSPERCYCLE==4) else $fatal(1, "Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
-    assert (P.F_SUPPORTED || ~P.D_SUPPORTED) else $fatal(1, "Can't support double fp (D) without supporting float (F)");
-    assert (P.D_SUPPORTED || ~P.Q_SUPPORTED) else $fatal(1, "Can't support quad fp (Q) without supporting double (D)");
-    assert (P.F_SUPPORTED || ~P.ZFH_SUPPORTED) else $fatal(1, "Can't support half-precision fp (ZFH) without supporting float (F)");
-    assert (P.DCACHE_SUPPORTED || ~P.F_SUPPORTED || P.FLEN <= P.XLEN) else $fatal(1, "Data cache required to support FLEN > XLEN because AHB/DTIM bus width is XLEN");
+    assert (P.PMP_ENTRIES == 0 | P.PMP_ENTRIES==16 | P.PMP_ENTRIES==64) else $fatal(1, "Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
+    assert (P.S_SUPPORTED | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "Virtual memory requires S mode support");
+    assert (P.IDIV_BITSPERCYCLE == 1 | P.IDIV_BITSPERCYCLE==2 | P.IDIV_BITSPERCYCLE==4) else $fatal(1, "Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4");
+    assert (P.F_SUPPORTED | ~P.D_SUPPORTED) else $fatal(1, "Can't support double fp (D) without supporting float (F)");
+    assert (P.D_SUPPORTED | ~P.Q_SUPPORTED) else $fatal(1, "Can't support quad fp (Q) without supporting double (D)");
+    assert (P.F_SUPPORTED | ~P.ZFH_SUPPORTED) else $fatal(1, "Can't support half-precision fp (ZFH) without supporting float (F)");
+    assert (P.DCACHE_SUPPORTED | ~P.F_SUPPORTED | P.FLEN <= P.XLEN) else $fatal(1, "Data cache required to support FLEN > XLEN because AHB/DTIM bus width is XLEN");
     assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $fatal(1, "Exactly one of I and E must be supported");
-    assert (P.DCACHE_WAYSIZEINBYTES <= 4096 || (!P.DCACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
-    assert (P.DCACHE_LINELENINBITS >= 128 || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
+    assert (P.DCACHE_WAYSIZEINBYTES <= 4096 | (!P.DCACHE_SUPPORTED) | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
+    assert (P.DCACHE_LINELENINBITS >= 128 | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
     assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $fatal(1, "DCACHE_LINELENINBITS must be smaller than way size");
-    assert (P.ICACHE_WAYSIZEINBYTES <= 4096 || (!P.ICACHE_SUPPORTED) || P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
-    assert (P.ICACHE_LINELENINBITS >= 32 || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
+    assert (P.ICACHE_WAYSIZEINBYTES <= 4096 | (!P.ICACHE_SUPPORTED) | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
+    assert (P.ICACHE_LINELENINBITS >= 32 | (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
     assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $fatal(1, "ICACHE_LINELENINBITS must be smaller than way size");
-    assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be a power of 2");
-    assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_WAYSIZEINBYTES must be a power of 2");
-    assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be a power of 2");
-    assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_WAYSIZEINBYTES must be a power of 2");
-    assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $fatal(1, "ITLB_ENTRIES must be a power of 2");
-    assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $fatal(1, "DTLB_ENTRIES must be a power of 2");
+    assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be a power of 2");
+    assert (2**$clog2(P.DCACHE_WAYSIZEINBYTES) == P.DCACHE_WAYSIZEINBYTES | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_WAYSIZEINBYTES must be a power of 2");
+    assert (2**$clog2(P.ICACHE_LINELENINBITS) == P.ICACHE_LINELENINBITS | (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be a power of 2");
+    assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES | (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_WAYSIZEINBYTES must be a power of 2");
+    assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES | P.VIRTMEM_SUPPORTED==0) else $fatal(1, "ITLB_ENTRIES must be a power of 2");
+    assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES | P.VIRTMEM_SUPPORTED==0) else $fatal(1, "DTLB_ENTRIES must be a power of 2");
     assert (P.UNCORE_RAM_RANGE >= 64'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 64'h07FFFFFF");
-	  assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $fatal(1, "PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
-    assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $fatal(1, "S and U modes not supported if ZICSR not supported");
-    assert (P.U_SUPPORTED || (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
-    assert (P.VIRTMEM_SUPPORTED == 0 || (P.DTIM_SUPPORTED == 0 && P.IROM_SUPPORTED == 0)) else $fatal(1, "Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
-    assert (P.DCACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs dcache");
-    assert (P.ICACHE_SUPPORTED || P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs icache");
-    assert ((P.DCACHE_SUPPORTED == 0 && P.ICACHE_SUPPORTED == 0) || P.BUS_SUPPORTED) else $fatal(1, "Dcache and Icache requires DBUS_SUPPORTED.");
-    assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 || (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 16");
+	  assert (P.ZICSR_SUPPORTED == 1 | (P.PMP_ENTRIES == 0 & P.VIRTMEM_SUPPORTED == 0)) else $fatal(1, "PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
+    assert (P.ZICSR_SUPPORTED == 1 | (P.S_SUPPORTED == 0 & P.U_SUPPORTED == 0)) else $fatal(1, "S and U modes not supported if ZICSR not supported");
+    assert (P.U_SUPPORTED | (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
+    assert (P.VIRTMEM_SUPPORTED == 0 | (P.DTIM_SUPPORTED == 0 & P.IROM_SUPPORTED == 0)) else $fatal(1, "Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
+    assert (P.DCACHE_SUPPORTED | P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs dcache");
+    assert (P.ICACHE_SUPPORTED | P.VIRTMEM_SUPPORTED ==0) else $fatal(1, "Virtual memory needs icache");
+    assert ((P.DCACHE_SUPPORTED == 0 & P.ICACHE_SUPPORTED == 0) | P.BUS_SUPPORTED) else $fatal(1, "Dcache and Icache requires DBUS_SUPPORTED.");
+    assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 16");
     assert (P.DCACHE_LINELENINBITS % 4 == 0) else $fatal(1, "DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
-    assert (P.DCACHE_SUPPORTED || (P.A_SUPPORTED == 0)) else $fatal(1, "Atomic extension (A) requires cache on Wally.");
-    assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $fatal(1, "IDIV on FPU needs F_SUPPORTED");
-    assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $fatal(1, "SSTC requires S_SUPPORTED");
-    assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $fatal(1, "At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled");
-    assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $fatal(1, "ZICNTR_SUPPORTED requires ZICSR_SUPPORTED");
-    assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $fatal(1, "ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED");
-    assert ((P.ZICBOM_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOM requires DCACHE_SUPPORTED");
-    assert ((P.ZICBOZ_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOZ requires DCACHE_SUPPORTED");
-    assert ((P.SVPBMT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $fatal(1, "SVPBMT requires VIRTMEM_SUPPORTED and RV64");
-    assert ((P.SVNAPOT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $fatal(1, "SVNAPOT requires VIRTMEM_SUPPORTED and RV64");
-    assert ((P.ZCB_SUPPORTED == 0) || (P.M_SUPPORTED == 1 && (P.ZBA_SUPPORTED == 1 || P.XLEN == 32) && P.ZBB_SUPPORTED == 1)) else $fatal(1, "ZCB requires M and ZBB (and also ZBA for RV64)");
-    assert ((P.C_SUPPORTED == 0) || (P.ZCA_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0 && P.ZCD_SUPPORTED == 0)) else $fatal(1, "C and ZCA/ZCD/ZCF cannot simultaneously be supported");
-    assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $fatal(1, "ZCF or ZCD requires ZCA");
-    assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $fatal(1, "ZCF requires F");
-    assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");   
-    assert ((P.LLEN == P.XLEN) || (P.DCACHE_SUPPORTED)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache");
+    assert (P.DCACHE_SUPPORTED | (P.A_SUPPORTED == 0)) else $fatal(1, "Atomic extension (A) requires cache on Wally.");
+    assert (P.IDIV_ON_FPU == 0 | P.F_SUPPORTED) else $fatal(1, "IDIV on FPU needs F_SUPPORTED");
+    assert (P.SSTC_SUPPORTED == 0 | (P.S_SUPPORTED)) else $fatal(1, "SSTC requires S_SUPPORTED");
+    assert ((P.M_SUPPORTED == 0) | (P.ZMMUL_SUPPORTED == 1)) else $fatal(1, "M requires ZMMUL");
+    assert ((P.ZICNTR_SUPPORTED == 0) | (P.ZICSR_SUPPORTED == 1)) else $fatal(1, "ZICNTR_SUPPORTED requires ZICSR_SUPPORTED");
+    assert ((P.ZIHPM_SUPPORTED == 0) | (P.ZICNTR_SUPPORTED == 1)) else $fatal(1, "ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED");
+    assert ((P.ZICBOM_SUPPORTED == 0) | (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOM requires DCACHE_SUPPORTED");
+    assert ((P.ZICBOZ_SUPPORTED == 0) | (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOZ requires DCACHE_SUPPORTED");
+    assert ((P.ZICBOZ_SUPPORTED == 0) | (P.DTIM_SUPPORTED == 0)) else $fatal(1, "ZICBOZ incompatible with DTIM");
+    assert ((P.SVPBMT_SUPPORTED == 0) | (P.VIRTMEM_SUPPORTED == 1 & P.XLEN==64)) else $fatal(1, "SVPBMT requires VIRTMEM_SUPPORTED and RV64");
+    assert ((P.SVNAPOT_SUPPORTED == 0) | (P.VIRTMEM_SUPPORTED == 1 & P.XLEN==64)) else $fatal(1, "SVNAPOT requires VIRTMEM_SUPPORTED and RV64");
+    assert ((P.ZCA_SUPPORTED == 1) | (P.ZCD_SUPPORTED == 0 & P.ZCF_SUPPORTED == 0 & P.ZCB_SUPPORTED == 0)) else $fatal(1, "ZCB, ZCF, or ZCD requires ZCA");
+    assert ((P.ZCF_SUPPORTED == 0) | ((P.F_SUPPORTED == 1) & (P.XLEN == 32))) else $fatal(1, "ZCF requires F and XLEN == 32");
+    assert ((P.ZCD_SUPPORTED == 0) | (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");
+    assert ((P.LLEN == P.XLEN) | (P.DCACHE_SUPPORTED & P.DTIM_SUPPORTED == 0)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache");
   end
 
 endmodule
diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 0a6ae2548..de4692a36 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -46,7 +46,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   logic 						 StallE, StallM, StallW;
   logic 						 FlushD, FlushE, FlushM, FlushW;
   logic 						 TrapM, TrapW;
-  logic 						 IntrF, IntrD, IntrE, IntrM, IntrW;
   logic 						 HaltM, HaltW;
   logic [1:0] 					 PrivilegeModeW;
   logic [P.XLEN-1:0] 			 rf[NUMREGS];
@@ -269,13 +268,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   flopenrc #(1)     InterruptWReg (clk, reset, 1'b0, ~StallW, InterruptM, InterruptW);
   flopenrc #(1)     HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW);
 
-  // **** remove?  are these used?
-  flopenrc #(1)     IntrFReg (clk, reset, 1'b0, ~StallF, TrapM, IntrF);
-  flopenrc #(1)     IntrDReg (clk, reset, FlushD, ~StallD, IntrF, IntrD);
-  flopenrc #(1)     IntrEReg (clk, reset, FlushE, ~StallE, IntrD, IntrE);
-  flopenrc #(1)     IntrMReg (clk, reset, FlushM, ~StallM, IntrE, IntrM);
-  flopenrc #(1)     IntrWReg (clk, reset, FlushW, ~StallW, IntrM, IntrW);
-
   flopenrc #(12)    CSRAdrWReg (clk, reset, FlushW, ~StallW, CSRAdrM, CSRAdrW);
   flopenrc #(1)     CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW);
 
diff --git a/testbench/coverage/test_pmp_coverage.sv b/testbench/coverage/test_pmp_coverage.sv
new file mode 100644
index 000000000..2c1cbbfaa
--- /dev/null
+++ b/testbench/coverage/test_pmp_coverage.sv
@@ -0,0 +1,108 @@
+module test_pmp_coverage import cvw::*; #(parameter cvw_t P) (input clk);
+
+// Ensure the covergroup is defined correctly
+covergroup cg_priv_mode @(posedge clk);
+    coverpoint dut.core.ifu.PrivilegeModeW {
+        bins user   = {2'b00};
+        bins superv = {2'b01};
+        bins hyperv = {2'b10};
+        bins mach   = {2'b11};
+    }
+endgroup
+
+covergroup cg_PMPConfig @(posedge clk);
+    coverpoint dut.core.ifu.PMPCFG_ARRAY_REGW[0][0] {
+        bins ones    = {1};
+        bins zeros = {0};
+    }
+endgroup
+
+
+function bit [1:0] getPMPConfigSlice(int index);
+    return dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[index][4:3];
+endfunction
+
+//if (P.PMP_ENTRIES > 0) begin : pmp
+    covergroup cg_pmpcfg_mode @(posedge clk);
+            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[0][4:3] {
+                bins off   = {2'b00};
+                bins tor   = {2'b01};
+                bins na4   = {2'b10};
+                bins napot = {2'b11};
+            }
+
+
+            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[1][4:3] {
+                bins off   = {2'b00};
+                bins tor   = {2'b01};
+                bins na4   = {2'b10};
+                bins napot = {2'b11};
+            }
+
+            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[2][4:3] {
+                bins off   = {2'b00};
+                bins tor   = {2'b01};
+                bins na4   = {2'b10};
+                bins napot = {2'b11};
+            }
+
+            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[3][4:3] {
+                bins off   = {2'b00};
+                bins tor   = {2'b01};
+                bins na4   = {2'b10};
+                bins napot = {2'b11};
+            }
+
+            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[4][4:3] {
+                bins off   = {2'b00};
+                bins tor   = {2'b01};
+                bins na4   = {2'b10};
+                bins napot = {2'b11};
+            }
+
+            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[5][4:3] {
+                bins off   = {2'b00};
+                bins tor   = {2'b01};
+                bins na4   = {2'b10};
+                bins napot = {2'b11};
+            }
+
+            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[6][4:3] {
+                bins off   = {2'b00};
+                bins tor   = {2'b01};
+                bins na4   = {2'b10};
+                bins napot = {2'b11};
+            }
+
+            coverpoint dut.core.ifu.immu.immu.PMPCFG_ARRAY_REGW[7][4:3] {
+                bins off   = {2'b00};
+                bins tor   = {2'b01};
+                bins na4   = {2'b10};
+                bins napot = {2'b11};
+            }
+    endgroup
+//end
+
+
+// Ensure that the instantiation and sampling of covergroups are within the correct procedural context
+initial begin
+    cg_priv_mode privmodeCG = new();  // Instantiate the privilege mode covergroup
+    cg_PMPConfig pmpconfigCG = new(); // Instantiate the PMP config covergroup
+    cg_pmpcfg_mode pmpcfgmodeCG = new();
+
+    forever begin
+        @(posedge clk) begin
+            privmodeCG.sample();  // Sample the privilege mode covergroup
+            pmpconfigCG.sample(); // Sample the PMP config covergroupi
+	    pmpcfgmodeCG.sample();
+        end
+    end
+end
+
+
+endmodule
+
+
+
+
+
diff --git a/testbench/testbench-imperas.sv b/testbench/testbench-imperas.sv
index 27bcdb73e..c834483f2 100644
--- a/testbench/testbench-imperas.sv
+++ b/testbench/testbench-imperas.sv
@@ -110,7 +110,7 @@ module testbench;
           $error("Must specify test directory using plusarg testDir");
       end
 
-      if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+      if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.RAM);
 	  else $error("Imperas test bench requires BUS.");
 
       ProgramAddrMapFile = {testDir, "/ref/ref.elf.objdump.addr"};
@@ -149,10 +149,11 @@ module testbench;
         $display($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION));
         $fatal;
       end
+      
       void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR,            "riscv.ovpworld.org"));
       void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME,              "riscv"));
       void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT,           "RV64GC"));
-      void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH,     39));
+      void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH,     56));
       void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6));
 
       if (!rvviRefInit(elffilename)) begin
@@ -189,7 +190,7 @@ module testbench;
       end
       if (P.SDC_SUPPORTED) begin
           void'(rvviRefMemorySetVolatile(P.SDC_BASE, (P.SDC_BASE + P.SDC_RANGE)));
-      end      
+      end
       if (P.SPI_SUPPORTED) begin
           void'(rvviRefMemorySetVolatile(P.SPI_BASE, (P.SPI_BASE + P.SPI_RANGE)));
       end
@@ -324,7 +325,6 @@ module testbench;
            ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); 
 
   DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk),
-    			.reset(reset),
 	    		.start(DCacheFlushStart),
 		    	.done(DCacheFlushDone));
 
diff --git a/testbench/testbench-soc.sv b/testbench/testbench-soc.sv
deleted file mode 100644
index 320ffad41..000000000
--- a/testbench/testbench-soc.sv
+++ /dev/null
@@ -1,922 +0,0 @@
-///////////////////////////////////////////
-// testbench.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
-//
-// Purpose: Wally Testbench and helper modules
-//          Applies test programs from the riscv-arch-test and Imperas suites
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "config.vh"
-`include "tests.vh"
-`include "BranchPredictorType.vh"
-
-`ifdef USE_IMPERAS_DV
-    `include "idv/idv.svh"
-`endif
-
-import cvw::*;
-
-module testbench;
-  /* verilator lint_off WIDTHTRUNC */
-  /* verilator lint_off WIDTHEXPAND */
-  parameter DEBUG=0;
-  parameter string TEST="arch64m";
-  parameter PrintHPMCounters=0;
-  parameter BPRED_LOGGER=0;
-  parameter I_CACHE_ADDR_LOGGER=0;
-  parameter D_CACHE_ADDR_LOGGER=0;
-  parameter RISCV_DIR = "/opt/riscv";
-  parameter INSTR_LIMIT = 0;
-  
-  `ifdef USE_IMPERAS_DV
-    import idvPkg::*;
-    import rvviApiPkg::*;
-    import idvApiPkg::*;
-  `endif
-
-`include "parameter-defs.vh"
-
-  logic        clk;
-  logic        reset_ext, reset;
-  logic        ResetMem;
-
-  // DUT signals
-  logic [P.AHBW-1:0]    HRDATAEXT;
-  logic                 HREADYEXT, HRESPEXT;
-  logic                 HSELEXTSDC;
-  logic [P.PA_BITS-1:0] HADDR;
-  logic [P.AHBW-1:0]    HWDATA;
-  logic [P.XLEN/8-1:0]  HWSTRB;
-  logic                 HWRITE;
-  logic [2:0]           HSIZE;
-  logic [2:0]           HBURST;
-  logic [3:0]           HPROT;
-  logic [1:0]           HTRANS;
-  logic                 HMASTLOCK;
-  logic                 HCLK, HRESETn;
-
-  logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
-  logic        UARTSin, UARTSout;
-  logic        SPIIn, SPIOut;
-  logic [3:0]  SPICS;
-  logic        SDCIntr;
-
-  logic        HREADY;
-  logic        HSELEXT;
-
-  
-  string  ProgramAddrMapFile, ProgramLabelMapFile;
-  integer ProgramAddrLabelArray [string];
-
-  int test, i, errors, totalerrors;
-
-  string outputfile;
-  integer outputFilePointer;
-
-  string tests[];
-  logic DCacheFlushDone, DCacheFlushStart;
-  logic riscofTest; 
-  logic Validate;
-  logic SelectTest;
-  logic TestComplete;
-
-  // pick tests based on modes supported
-  initial begin
-    $display("TEST is %s", TEST);
-    //tests = '{};
-    if (P.XLEN == 64) begin // RV64
-      case (TEST)
-        "arch64i":                                tests = arch64i;
-        "arch64priv":                             tests = arch64priv;
-        "arch64c":      if (P.C_SUPPORTED) 
-                          if (P.ZICSR_SUPPORTED)  tests = {arch64c, arch64cpriv};
-                          else                    tests = {arch64c};
-        "arch64m":      if (P.M_SUPPORTED)        tests = arch64m;
-        "arch64a":      if (P.A_SUPPORTED)        tests = arch64a;
-        "arch64f":      if (P.F_SUPPORTED)        tests = arch64f;
-        "arch64d":      if (P.D_SUPPORTED)        tests = arch64d;  
-        "arch64f_fma":  if (P.F_SUPPORTED)        tests = arch64f_fma;
-        "arch64d_fma":  if (P.D_SUPPORTED)        tests = arch64d_fma;  
-        "arch64f_divsqrt":  if (P.F_SUPPORTED)        tests = arch64f_divsqrt;
-        "arch64d_divsqrt":  if (P.D_SUPPORTED)        tests = arch64d_divsqrt;  
-        "arch64zifencei":  if (P.ZIFENCEI_SUPPORTED) tests = arch64zifencei;
-        "arch64zicond":  if (P.ZICOND_SUPPORTED)  tests = arch64zicond;
-        "imperas64i":                             tests = imperas64i;
-        "imperas64f":   if (P.F_SUPPORTED)        tests = imperas64f;
-        "imperas64d":   if (P.D_SUPPORTED)        tests = imperas64d;
-        "imperas64m":   if (P.M_SUPPORTED)        tests = imperas64m;
-        "wally64a":     if (P.A_SUPPORTED)        tests = wally64a;
-        "imperas64c":   if (P.C_SUPPORTED)        tests = imperas64c;
-                        else                      tests = imperas64iNOc;
-        "custom":                                 tests = custom;
-        "wally64i":                               tests = wally64i; 
-        "wally64priv":                            tests = wally64priv;
-        "wally64periph":                          tests = wally64periph;
-        "coremark":                               tests = coremark;
-        "fpga":                                   tests = fpga;
-        "ahb64" :                                 tests = ahb64;
-        "coverage64gc" :                          tests = coverage64gc;
-        "arch64zba":     if (P.ZBA_SUPPORTED)     tests = arch64zba;
-        "arch64zbb":     if (P.ZBB_SUPPORTED)     tests = arch64zbb;
-        "arch64zbc":     if (P.ZBC_SUPPORTED)     tests = arch64zbc;
-        "arch64zbs":     if (P.ZBS_SUPPORTED)     tests = arch64zbs;
-        "arch64zicboz":  if (P.ZICBOZ_SUPPORTED)  tests = arch64zicboz;
-        "arch64zcb":     if (P.ZCB_SUPPORTED)     tests = arch64zcb;
-        "arch64zfh":     if (P.ZFH_SUPPORTED)     tests = arch64zfh;
-        "arch64zfh_fma": if (P.ZFH_SUPPORTED)     tests = arch64zfh_fma; 
-        "arch64zfh_divsqrt":     if (P.ZFH_SUPPORTED)     tests = arch64zfh_divsqrt;
-        "arch64zfaf":    if (P.ZFA_SUPPORTED)     tests = arch64zfaf;
-        "arch64zfad":    if (P.ZFA_SUPPORTED & P.D_SUPPORTED)  tests = arch64zfad;
-        "buildroot":                              tests = buildroot;
-      endcase 
-    end else begin // RV32
-      case (TEST)
-        "arch32e":                                tests = arch32e; 
-        "arch32i":                                tests = arch32i;
-        "arch32priv":                             tests = arch32priv;
-        "arch32c":      if (P.C_SUPPORTED) 
-                          if (P.ZICSR_SUPPORTED)  tests = {arch32c, arch32cpriv};
-                          else                    tests = {arch32c};
-        "arch32m":      if (P.M_SUPPORTED)        tests = arch32m;
-        "arch32a":      if (P.A_SUPPORTED)        tests = arch32a;
-        "arch32f":      if (P.F_SUPPORTED)        tests = arch32f;
-        "arch32d":      if (P.D_SUPPORTED)        tests = arch32d;
-        "arch32f_fma":  if (P.F_SUPPORTED)        tests = arch32f_fma;
-        "arch32d_fma":  if (P.D_SUPPORTED)        tests = arch32d_fma;
-        "arch32f_divsqrt":  if (P.F_SUPPORTED)        tests = arch32f_divsqrt;
-        "arch32d_divsqrt":  if (P.D_SUPPORTED)        tests = arch32d_divsqrt;  
-        "arch32zifencei":     if (P.ZIFENCEI_SUPPORTED) tests = arch32zifencei;
-        "arch32zicond":  if (P.ZICOND_SUPPORTED)  tests = arch32zicond;
-        "imperas32i":                             tests = imperas32i;
-        "imperas32f":   if (P.F_SUPPORTED)        tests = imperas32f;
-        "imperas32m":   if (P.M_SUPPORTED)        tests = imperas32m;
-        "wally32a":     if (P.A_SUPPORTED)        tests = wally32a;
-        "imperas32c":   if (P.C_SUPPORTED)        tests = imperas32c;
-                        else                      tests = imperas32iNOc;
-        "wally32i":                               tests = wally32i; 
-        "wally32priv":                            tests = wally32priv;
-        "wally32periph":                          tests = wally32periph;
-        "ahb32" :                                 tests = ahb32;
-        "embench":                                tests = embench;
-        "coremark":                               tests = coremark;
-        "arch32zba":     if (P.ZBA_SUPPORTED)     tests = arch32zba;
-        "arch32zbb":     if (P.ZBB_SUPPORTED)     tests = arch32zbb;
-        "arch32zbc":     if (P.ZBC_SUPPORTED)     tests = arch32zbc;
-        "arch32zbs":     if (P.ZBS_SUPPORTED)     tests = arch32zbs;
-        "arch32zicboz":  if (P.ZICBOZ_SUPPORTED)  tests = arch32zicboz;
-        "arch32zcb":     if (P.ZCB_SUPPORTED)     tests = arch32zcb;
-        "arch32zfh":     if (P.ZFH_SUPPORTED)     tests = arch32zfh;
-        "arch32zfh_fma": if (P.ZFH_SUPPORTED)     tests = arch32zfh_fma; 
-        "arch32zfh_divsqrt":     if (P.ZFH_SUPPORTED)     tests = arch32zfh_divsqrt;
-        "arch32zfaf":    if (P.ZFA_SUPPORTED)     tests = arch32zfaf;
-        "arch32zfad":    if (P.ZFA_SUPPORTED & P.D_SUPPORTED)  tests = arch32zfad;
-      endcase
-    end
-    if (tests.size() == 0) begin
-      $display("TEST %s not supported in this configuration", TEST);
-      $finish;
-    end
-  end // initial begin
-
-  // Model the testbench as an fsm.
-  // Do this in parts so it easier to verify
-  // part 1: build a version which echos the same behavior as the below code, but does not drive anything
-  // part 2: drive some of the controls
-  // part 3: drive all logic and remove old inital and always @ negedge clk block
-
-  typedef enum logic [3:0]{STATE_TESTBENCH_RESET,
-                           STATE_INIT_TEST,
-                           STATE_RESET_MEMORIES,
-                           STATE_RESET_MEMORIES2,
-                           STATE_LOAD_MEMORIES,
-                           STATE_RESET_TEST,
-                           STATE_RUN_TEST,
-                           STATE_COPY_RAM,
-                           STATE_CHECK_TEST,
-                           STATE_CHECK_TEST_WAIT,
-                           STATE_VALIDATE,
-                           STATE_INCR_TEST} statetype;
-  statetype CurrState, NextState;
-  logic        TestBenchReset;
-  logic [2:0]  ResetCount, ResetThreshold;
-  logic        LoadMem;
-  logic        ResetCntEn;
-  logic        ResetCntRst;
-  logic        CopyRAM;
-
-  string  signame, memfilename, bootmemfilename, pathname;
-  integer begin_signature_addr, end_signature_addr, signature_size;
-
-  assign ResetThreshold = 3'd5;
-
-  initial begin
-    TestBenchReset = 1;
-    # 100;
-    TestBenchReset = 0;
-  end
-
-  always_ff @(posedge clk)
-    if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET;
-    else CurrState <= #1 NextState;  
-
-  // fsm next state logic
-  always_comb begin
-    // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests 
-    // and tests[0] == "2" refers to WallyRiscvArchTests 
-    riscofTest = tests[0] == "1" | tests[0] == "2"; 
-    pathname = tvpaths[tests[0].atoi()];
-
-    case(CurrState)
-      STATE_TESTBENCH_RESET:                      NextState = STATE_INIT_TEST;
-      STATE_INIT_TEST:                            NextState = STATE_RESET_MEMORIES;
-      STATE_RESET_MEMORIES:                       NextState = STATE_RESET_MEMORIES2;
-      STATE_RESET_MEMORIES2:                      NextState = STATE_LOAD_MEMORIES;  // Give the reset enough time to ensure the bus is reset before loading the memories.
-      STATE_LOAD_MEMORIES:                        NextState = STATE_RESET_TEST;
-      STATE_RESET_TEST:      if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST;
-                             else                 NextState = STATE_RUN_TEST;
-      STATE_RUN_TEST:        if(TestComplete)     NextState = STATE_COPY_RAM;
-                             else                 NextState = STATE_RUN_TEST;
-      STATE_COPY_RAM:                             NextState = STATE_CHECK_TEST;
-      STATE_CHECK_TEST:      if (DCacheFlushDone) NextState = STATE_VALIDATE;
-                             else                 NextState = STATE_CHECK_TEST_WAIT;
-      STATE_CHECK_TEST_WAIT: if(DCacheFlushDone)  NextState = STATE_VALIDATE;
-                             else                 NextState = STATE_CHECK_TEST_WAIT;
-      STATE_VALIDATE:                             NextState = STATE_INIT_TEST;
-      STATE_INCR_TEST:                            NextState = STATE_INIT_TEST;
-      default:                                    NextState = STATE_TESTBENCH_RESET;
-    endcase
-  end // always_comb
-  // fsm output control logic 
-  assign reset_ext = CurrState == STATE_TESTBENCH_RESET | CurrState == STATE_INIT_TEST | 
-                     CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2 | 
-                     CurrState == STATE_LOAD_MEMORIES | CurrState ==STATE_RESET_TEST;
-  // this initialization is very expensive, only do it for coremark.  
-  assign ResetMem = (CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2) & TEST == "coremark";
-  assign LoadMem = CurrState == STATE_LOAD_MEMORIES;
-  assign ResetCntRst = CurrState == STATE_INIT_TEST;
-  assign ResetCntEn = CurrState == STATE_RESET_TEST;
-  assign Validate = CurrState == STATE_VALIDATE;
-  assign SelectTest = CurrState == STATE_INIT_TEST;
-  assign CopyRAM = TestComplete & CurrState == STATE_RUN_TEST;
-  assign DCacheFlushStart = CurrState == STATE_COPY_RAM;
-
-  // fsm reset counter
-  counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount);
-
-  ////////////////////////////////////////////////////////////////////////////////
-  // Find the test vector files and populate the PC to function label converter
-  ////////////////////////////////////////////////////////////////////////////////
-  logic [P.XLEN-1:0] testadr;
-  assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
-  assign end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
-  assign signature_size = end_signature_addr - begin_signature_addr;
-  always @(posedge clk) begin
-    if(SelectTest) begin
-      if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
-      else if(TEST == "buildroot") begin 
-        memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
-        bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
-      end
-      else            memfilename = {pathname, tests[test], ".elf.memfile"};
-      if (riscofTest) begin
-        ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
-        ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
-      end else if (TEST == "buildroot") begin
-        ProgramAddrMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.addr"};
-        ProgramLabelMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.lab"};
-      end else begin
-        ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
-        ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
-      end
-      // declare memory labels that interest us, the updateProgramAddrLabelArray task will find 
-      // the addr of each label and fill the array. To expand, add more elements to this array 
-      // and initialize them to zero (also initilaize them to zero at the start of the next test)
-      updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
-    end
-    
-  ////////////////////////////////////////////////////////////////////////////////
-  // Verify the test ran correctly by checking the memory against a known signature.
-  ////////////////////////////////////////////////////////////////////////////////
-    if(TestBenchReset) test = 1;
-    if (TEST == "coremark")
-      if (dut.core.priv.priv.EcallFaultM) begin
-        $display("Benchmark: coremark is done.");
-        $stop;
-      end
-    if(Validate) begin
-      if (TEST == "embench") begin
-        // Writes contents of begin_signature to .sim.output file
-        // this contains instret and cycles for start and end of test run, used by embench 
-        // python speed script to calculate embench speed score. 
-        // also, begin_signature contains the results of the self checking mechanism, 
-        // which will be read by the python script for error checking
-        $display("Embench Benchmark: %s is done.", tests[test]);
-        if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
-        else outputfile = {pathname, tests[test], ".sim.output"};
-        outputFilePointer = $fopen(outputfile, "w");
-        i = 0;
-        testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
-        while ($unsigned(i) < $unsigned(5'd5)) begin
-          $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
-          i = i + 1;
-        end
-        $fclose(outputFilePointer);
-        $display("Embench Benchmark: created output file: %s", outputfile);
-      end else if (TEST == "coverage64gc") begin
-        $display("Coverage tests don't get checked");
-      end else begin 
-        // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
-        // clear signature to prevent contamination from previous tests
-        if (!begin_signature_addr)
-          $display("begin_signature addr not found in %s", ProgramLabelMapFile);
-        else if (TEST != "embench") begin   // *** quick hack for embench.  need a better long term solution
-          CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors);
-          if(errors > 0) totalerrors = totalerrors + 1;
-        end
-      end
-      test = test + 1; // *** this probably needs to be moved.
-      if (test == tests.size()) begin
-        if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
-        else $display("FAIL: %d test programs had errors", totalerrors);
-        $stop; // if this is changed to $finish, wally-batch.do does not go to the next step to run coverage
-      end
-    end
-  end
-
-
-  ////////////////////////////////////////////////////////////////////////////////
-  // load memories with program image
-  ////////////////////////////////////////////////////////////////////////////////
-
-  integer ShadowIndex;
-  integer LogXLEN;
-  integer StartIndex;
-  integer EndIndex;
-  integer BaseIndex;
-  integer memFile;
-  integer readResult;
-  if (P.SDC_SUPPORTED) begin
-    always @(posedge clk) begin
-      if (LoadMem) begin
-        string romfilename, sdcfilename;
-        romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
-        sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
-        //$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
-        //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
-        // shorten sdc timers for simulation
-        //dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
-      end
-    end
-  end else if (P.IROM_SUPPORTED) begin
-    always @(posedge clk) begin
-      if (LoadMem) begin
-        $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
-      end
-    end
-  end else if (P.BUS_SUPPORTED) begin : bus_supported
-    always @(posedge clk) begin
-      if (LoadMem) begin
-        if (TEST == "buildroot") begin
-          memFile = $fopen(bootmemfilename, "rb");
-          readResult = $fread(dut.uncore.uncore.bootrom.bootrom.memory.ROM, memFile);
-          $fclose(memFile);
-          memFile = $fopen(memfilename, "rb");
-          readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM, memFile);
-          $fclose(memFile);
-        end else 
-          $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
-        if (TEST == "embench") $display("Read memfile %s", memfilename);
-      end
-      if (CopyRAM) begin
-        LogXLEN = (1 + P.XLEN/32); // 2 for rv32 and 3 for rv64
-        StartIndex = begin_signature_addr >> LogXLEN;
-        EndIndex = (end_signature_addr >> LogXLEN) + 8;
-        BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
-        for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
-          testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncore.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex];
-        end
-      end
-    end
-  end 
-  if (P.DTIM_SUPPORTED) begin
-    always @(posedge clk) begin
-      if (LoadMem) begin
-        $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
-        $display("Read memfile %s", memfilename);
-      end
-      if (CopyRAM) begin
-        LogXLEN = (1 + P.XLEN/32); // 2 for rv32 and 3 for rv64
-        StartIndex = begin_signature_addr >> LogXLEN;
-        EndIndex = (end_signature_addr >> LogXLEN) + 8;
-        BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
-        for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
-          testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.RAM[ShadowIndex - BaseIndex];
-        end
-      end
-    end
-  end
-
-  integer adrindex;
-  if (P.UNCORE_RAM_SUPPORTED)
-    always @(posedge clk) 
-      if (ResetMem)  // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory)
-        for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) 
-          dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
-
-  ////////////////////////////////////////////////////////////////////////////////
-  // Actual hardware
-  ////////////////////////////////////////////////////////////////////////////////
-
-  // instantiate device to be tested
-  assign GPIOIN = 0;
-  assign UARTSin = 1;
-  assign SPIIn = 0;
-
-  // Use bsg_dmc memory controller and LPDDR model
-  
-  logic                 ddr_ck_p;
-  logic                 ddr_ck_n;
-  logic                 ddr_cke;
-  logic [2:0]           ddr_ba;
-  logic [13:0]          ddr_addr;
-  logic                 ddr_cs;
-  logic                 ddr_ras;
-  logic                 ddr_cas;
-  logic                 ddr_we;
-  logic                 ddr_reset;
-  logic                 ddr_odt;
-  logic [P.XLEN/16-1:0] ddr_dm_oen_o;
-  logic [P.XLEN/16-1:0] ddr_dm;
-  logic [P.XLEN/16-1:0] ddr_dm_o;
-  logic [P.XLEN/16-1:0] ddr_dqs_p_oen_o;
-  logic [P.XLEN/16-1:0] ddr_dqs_p_ien_o;
-  logic [P.XLEN/16-1:0] ddr_dqs_p;
-  logic [P.XLEN/16-1:0] ddr_dqs_p_o;
-  logic [P.XLEN/16-1:0] ddr_dqs_p_i;
-  logic [P.XLEN/16-1:0] ddr_dqs_n_oen_o;
-  logic [P.XLEN/16-1:0] ddr_dqs_n_ien_o;
-  logic [P.XLEN/16-1:0] ddr_dqs_n;
-  logic [P.XLEN/16-1:0] ddr_dqs_n_o;
-  logic [P.XLEN/16-1:0] ddr_dqs_n_i;
-  logic [P.XLEN/2-1:0]  ddr_dq_oen_o;
-  logic [P.XLEN/2-1:0]  ddr_dq;
-  logic [P.XLEN/2-1:0]  ddr_dq_o;
-  logic [P.XLEN/2-1:0]  ddr_dq_i;
-  logic                 dfi_clk_2x_i;
-  logic                 dfi_clk_1x_o;
-
-  bsg_dmc_ahb #(28, P.XLEN, 32) bsg_mem_controller (
-    .HCLK, .HRESETn, .HSEL(HSELEXT),
-    .HADDR(HADDR[27:0]), .HWDATA, .HWSTRB, // FIXME: Double check that these are the right address bits
-    .HWRITE, .HTRANS, .HREADY(HREADYEXT),
-    .HRDATA(HRDATAEXT), .HRESP(HRESPEXT), .HREADYOUT(HREADYEXT),
-    .ddr_ck_p, .ddr_ck_n, .ddr_cke, .ddr_ba, .ddr_addr,
-    .ddr_cs, .ddr_ras, .ddr_cas, .ddr_we, .ddr_reset, .ddr_odt,
-    .ddr_dm_oen(ddr_dm_oen_o), .ddr_dm(ddr_dm_o),
-    .ddr_dqs_p_oen(ddr_dqs_p_oen_o), .ddr_dqs_p_ien(ddr_dqs_p_ien_o),
-    .ddr_dqs_p_out(ddr_dqs_p_o), .ddr_dqs_p_in(ddr_dqs_p_i),
-    .ddr_dqs_n_oen(ddr_dqs_n_oen_o), .ddr_dqs_n_ien(ddr_dqs_n_ien_o),
-    .ddr_dqs_n_out(ddr_dqs_n_o), .ddr_dqs_n_in(ddr_dqs_n_i),
-    .ddr_dq_oen(ddr_dq_oen_o), .ddr_dq_out(ddr_dq_o), .ddr_dq_in(ddr_dq_i),
-    .dfi_clk_2x(dfi_clk_2x_i), .dfi_clk_1x(dfi_clk_1x_o));
-
-  genvar ddr_i;
-  generate
-    for(ddr_i = 0; ddr_i < (P.XLEN/16); ddr_i++) begin: dm_io
-      assign ddr_dm[ddr_i] = !ddr_dm_oen_o[ddr_i]? ddr_dm_o[ddr_i]: 1'bz;
-    end
-    for(ddr_i = 0; ddr_i < (P.XLEN/16); ddr_i++) begin: dqs_io
-      assign ddr_dqs_p[ddr_i]   = !ddr_dqs_p_oen_o[ddr_i]? ddr_dqs_p_o[ddr_i]: 1'bz;
-      assign ddr_dqs_p_i[ddr_i] = !ddr_dqs_p_ien_o[ddr_i]? ddr_dqs_p[ddr_i]: 1'b0;
-      assign ddr_dqs_n[ddr_i]   = !ddr_dqs_n_oen_o[ddr_i]? ddr_dqs_n_o[ddr_i]: 1'bz;
-      assign ddr_dqs_n_i[ddr_i] = !ddr_dqs_n_ien_o[ddr_i]? ddr_dqs_n[ddr_i]: 1'b1;
-    end
-    for(ddr_i = 0; ddr_i < (P.XLEN/2); ddr_i++) begin: dq_io
-      assign ddr_dq[ddr_i]    = !ddr_dq_oen_o[ddr_i]? ddr_dq_o[ddr_i]: 1'bz;
-      assign ddr_dq_i[ddr_i]  = ddr_dq[ddr_i];
-    end
-    for(ddr_i = 0; ddr_i < 1; ddr_i++) begin: lpddr
-      mobile_ddr mobile_ddr_inst
-        (.Dq    (ddr_dq[32*ddr_i+31:32*ddr_i])
-        ,.Dqs   (ddr_dqs_p[4*ddr_i+3:4*ddr_i])
-        ,.Addr  (ddr_addr[13:0])
-        ,.Ba    (ddr_ba[1:0])
-        ,.Clk   (ddr_ck_p)
-        ,.Clk_n (ddr_ck_n)
-        ,.Cke   (ddr_cke)
-        ,.Cs_n  (ddr_cs)
-        ,.Ras_n (ddr_ras)
-        ,.Cas_n (ddr_cas)
-        ,.We_n  (ddr_we)
-        ,.Dm    (ddr_dm[4*ddr_i+3:4*ddr_i]));
-    end
-  endgenerate
-
-  if(P.SDC_SUPPORTED) begin : sdcard
-    // *** fix later
-/* -----\/----- EXCLUDED -----\/-----
-    sdModel sdcard
-      (.sdClk(SDCCLK),
-       .cmd(SDCCmd), 
-       .dat(SDCDat));
-
-    assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
-    assign SDCCmdIn = SDCCmd;
-    assign SDCDat = sd_dat_reg_t ? sd_dat_reg_o : sd_dat_i;
-    assign SDCDatIn = SDCDat;
- -----/\----- EXCLUDED -----/\----- */
-    assign SDCIntr = '0;
-  end else begin
-    assign SDCIntr = '0;
-  end
-
-  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
-    .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
-    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
-    .UARTSin, .UARTSout, .SDCIntr, .SPIIn, .SPIOut, .SPICS); 
-
-  // generate clock to sequence tests
-  always begin
-    clk = 1; # 5; clk = 0; # 5;
-  end
-
-  /*
-  // Print key info  each cycle for debugging
-  always @(posedge clk) begin 
-    #2;
-    $display("PCM: %x  InstrM: %x (%5s) WriteDataM: %x  IEUResultM: %x",
-         dut.core.PCM, dut.core.InstrM, InstrMName, dut.core.WriteDataM, dut.core.ieu.dp.IEUResultM);
-  end
-  */
-
-  ////////////////////////////////////////////////////////////////////////////////
-  // Support logic
-  ////////////////////////////////////////////////////////////////////////////////
-
-  // Duplicate copy of pipeline registers that are optimized out of some configurations
-  logic [31:0] NextInstrE, InstrM;
-  mux2    #(32)     FlushInstrMMux(dut.core.ifu.InstrE, dut.core.ifu.nop, dut.core.ifu.FlushM, NextInstrE);
-  flopenr #(32)     InstrMReg(clk, reset, ~dut.core.ifu.StallM, NextInstrE, InstrM);
-
-  // Track names of instructions
-  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
-  logic [31:0] InstrW;
-  flopenr #(32)    InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  InstrM, InstrW);
-  instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
-                dut.core.ifu.InstrRawF[31:0],
-                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
-                InstrM,  InstrW,
-                InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
-
-  // watch for problems such as lockup, reading unitialized memory, bad configs
-  watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset);  // check if PCW is stuck
-  ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM, 
-                                      dut.core.ifu.PCM, InstrM, dut.core.lsu.IEUAdrM, InstrMName);
-  riscvassertions #(P) riscvassertions();  // check assertions for a legal configuration
-  loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
-  loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename);
-
-  // track the current function or global label
-  if (DEBUG == 1 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : FunctionName
-    FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset),
-			      .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
-  end
-
-
-  // Termination condition
-  // terminate on a specific ECALL after li x3,1 for old Imperas tests,  *** remove this when old imperas tests are removed
-  // or sw	gp,-56(t0) for new Imperas tests
-  // or sd gp, -56(t0) 
-  // or on a jump to self infinite loop (6f) for RISC-V Arch tests
-  logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
-  if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
-  else                  assign ecf = 0;
-  assign TestComplete = ecf & 
-			    (dut.core.ieu.dp.regf.rf[3] == 1 | 
-			     (dut.core.ieu.dp.regf.we3 & 
-			      dut.core.ieu.dp.regf.a3 == 3 & 
-			      dut.core.ieu.dp.regf.wd3 == 1)) |
-           ((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
-           ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
-  //assign DCacheFlushStart =  TestComplete;
-  
-  DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));
-
-  if(P.ZICSR_SUPPORTED & INSTR_LIMIT != 0) begin
-    logic [P.XLEN-1:0] Minstret;
-    assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];  
-    always @(negedge clk) begin
-      if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret);
-      if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end
-    end
-end
-
-  ////////////////////////////////////////////////////////////////////////////////
-  // ImperasDV Co-simulator hooks
-  ////////////////////////////////////////////////////////////////////////////////
-`ifdef USE_IMPERAS_DV
-
-  rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi();
-  wallyTracer #(P) wallyTracer(rvvi);
-
-  trace2log idv_trace2log(rvvi);
-  //      trace2cov idv_trace2cov(rvvi);
-
-  // enabling of comparison types
-  trace2api #(.CMP_PC      (1),
-              .CMP_INS     (1),
-              .CMP_GPR     (1),
-              .CMP_FPR     (1),
-              .CMP_VR      (0),
-              .CMP_CSR     (1)
-              ) idv_trace2api(rvvi);
-
-  initial begin
-    int iter;
-    #1;
-    IDV_MAX_ERRORS = 3;
-
-    // Initialize REF (do this before initializing the DUT)
-    if (!rvviVersionCheck(RVVI_API_VERSION)) begin
-      $display($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION));
-      $fatal;
-    end
-    
-    void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR,            "riscv.ovpworld.org"));
-    void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME,              "riscv"));
-    void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT,           "RV64GC"));
-    void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH,     56));
-    void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6));
-
-    if (!rvviRefInit("")) begin
-      $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
-      $fatal;
-    end
-
-    // Volatile CSRs
-    void'(rvviRefCsrSetVolatile(0, 32'hC00));   // CYCLE
-    void'(rvviRefCsrSetVolatile(0, 32'hB00));   // MCYCLE
-    void'(rvviRefCsrSetVolatile(0, 32'hC02));   // INSTRET
-    void'(rvviRefCsrSetVolatile(0, 32'hB02));   // MINSTRET
-    void'(rvviRefCsrSetVolatile(0, 32'hC01));   // TIME
-    
-    // User HPMCOUNTER3 - HPMCOUNTER31
-    for (iter='hC03; iter<='hC1F; iter++) begin
-      void'(rvviRefCsrSetVolatile(0, iter));   // HPMCOUNTERx
-    end       
-    
-    // Machine MHPMCOUNTER3 - MHPMCOUNTER31
-    for (iter='hB03; iter<='hB1F; iter++) begin
-      void'(rvviRefCsrSetVolatile(0, iter));   // MHPMCOUNTERx
-    end       
-    
-    // cannot predict this register due to latency between
-    // pending and taken
-    void'(rvviRefCsrSetVolatile(0, 32'h344));   // MIP
-    void'(rvviRefCsrSetVolatile(0, 32'h144));   // SIP
-
-    // Privileges for PMA are set in the imperas.ic
-    // volatile (IO) regions are defined here
-    // only real ROM/RAM areas are BOOTROM and UNCORE_RAM
-    if (P.CLINT_SUPPORTED) begin
-      void'(rvviRefMemorySetVolatile(P.CLINT_BASE, (P.CLINT_BASE + P.CLINT_RANGE)));
-    end
-    if (P.GPIO_SUPPORTED) begin
-      void'(rvviRefMemorySetVolatile(P.GPIO_BASE, (P.GPIO_BASE + P.GPIO_RANGE)));
-    end
-    if (P.UART_SUPPORTED) begin
-      void'(rvviRefMemorySetVolatile(P.UART_BASE, (P.UART_BASE + P.UART_RANGE)));
-    end
-    if (P.PLIC_SUPPORTED) begin
-      void'(rvviRefMemorySetVolatile(P.PLIC_BASE, (P.PLIC_BASE + P.PLIC_RANGE)));
-    end
-    if (P.SDC_SUPPORTED) begin
-      void'(rvviRefMemorySetVolatile(P.SDC_BASE, (P.SDC_BASE + P.SDC_RANGE)));
-    end
-    if (P.SPI_SUPPORTED) begin
-      void'(rvviRefMemorySetVolatile(P.SPI_BASE, (P.SPI_BASE + P.SPI_RANGE)));
-    end
-
-    if(P.XLEN==32) begin
-      void'(rvviRefCsrSetVolatile(0, 32'hC80));   // CYCLEH
-      void'(rvviRefCsrSetVolatile(0, 32'hB80));   // MCYCLEH
-      void'(rvviRefCsrSetVolatile(0, 32'hC82));   // INSTRETH
-      void'(rvviRefCsrSetVolatile(0, 32'hB82));   // MINSTRETH
-    end
-
-    void'(rvviRefCsrSetVolatile(0, 32'h104));   // SIE - Temporary!!!!
-    
-    // Load memory
-    // *** RT: This section can probably be moved into the same chunk of code which
-    // loads the memories.  However I'm not sure that ImperasDV supports reloading
-    // the memories without relaunching the simulator.
-    begin
-      longint x64;
-      int     x32[2];
-      longint index;
-      string  memfilenameImperasDV, bootmemfilenameImperasDV;
-      
-      memfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/ram.bin"};
-      bootmemfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
-
-      $display("RVVI Loading bootmem.bin");
-      memFile = $fopen(bootmemfilenameImperasDV, "rb");
-      index = 'h1000 - 8;
-      while(!$feof(memFile)) begin
-        index+=8;
-        readResult = $fread(x64, memFile);
-        if (x64 == 0) continue;
-        x32[0] = x64 & 'hffffffff;
-        x32[1] = x64 >> 32;
-        rvviRefMemoryWrite(0, index+0, x32[0], 4);
-        rvviRefMemoryWrite(0, index+4, x32[1], 4);
-        //$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
-      end
-      $fclose(memFile);
-            
-      $display("RVVI Loading ram.bin");
-      memFile = $fopen(memfilenameImperasDV, "rb");
-      index = 'h80000000 - 8;
-      while(!$feof(memFile)) begin
-        index+=8;
-        readResult = $fread(x64, memFile);
-        if (x64 == 0) continue;
-        x32[0] = x64 & 'hffffffff;
-        x32[1] = x64 >> 32;
-        rvviRefMemoryWrite(0, index+0, x32[0], 4);
-        rvviRefMemoryWrite(0, index+4, x32[1], 4);
-        //$display("ram  %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
-      end
-      $fclose(memFile);
-      
-      $display("RVVI Loading Complete");
-      
-      void'(rvviRefPcSet(0, P.RESET_VECTOR)); // set BOOTROM address
-    end
-  end
-
-  always @(dut.core.priv.priv.csr.csri.MIP_REGW[7])   void'(rvvi.net_push("MTimerInterrupt",    dut.core.priv.priv.csr.csri.MIP_REGW[7]));
-  always @(dut.core.priv.priv.csr.csri.MIP_REGW[11])  void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[11]));
-  always @(dut.core.priv.priv.csr.csri.MIP_REGW[9])   void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[9]));
-  always @(dut.core.priv.priv.csr.csri.MIP_REGW[3])   void'(rvvi.net_push("MSWInterrupt",       dut.core.priv.priv.csr.csri.MIP_REGW[3]));
-  always @(dut.core.priv.priv.csr.csri.MIP_REGW[1])   void'(rvvi.net_push("SSWInterrupt",       dut.core.priv.priv.csr.csri.MIP_REGW[1]));
-  always @(dut.core.priv.priv.csr.csri.MIP_REGW[5])   void'(rvvi.net_push("STimerInterrupt",    dut.core.priv.priv.csr.csri.MIP_REGW[5]));
-
-  final begin
-    void'(rvviRefShutdown());
-  end
-
-`endif
-  ////////////////////////////////////////////////////////////////////////////////
-  // END of ImperasDV Co-simulator hooks
-  ////////////////////////////////////////////////////////////////////////////////
-
-  task automatic CheckSignature;
-    // This task must be declared inside this module as it needs access to parameter P.  There is
-    // no way to pass P to the task unless we convert it to a module.
-    
-    input string  pathname;
-    input string  TestName;
-    input logic   riscofTest;
-    input integer begin_signature_addr;
-    output integer errors;
-    int fd, code;
-    string line;
-    int siglines, sigentries;
-
-    localparam SIGNATURESIZE = 5000000;
-    integer        i;
-    logic [31:0]   sig32[0:SIGNATURESIZE];
-    logic [31:0]   parsed;
-    logic [P.XLEN-1:0] signature[0:SIGNATURESIZE];
-    string            signame;
-    logic [P.XLEN-1:0] testadr, testadrNoBase;
-    
-    // read .signature.output file and compare to check for errors
-    if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"};
-    else signame = {pathname, TestName, ".signature.output"};
-
-    // read signature file from memory and count lines.  Can't use readmemh because we need the line count
-    // $readmemh(signame, sig32);
-    fd = $fopen(signame, "r");
-    siglines = 0;
-    if (fd == 0) $display("Unable to read %s", signame);
-    else begin
-      while (!$feof(fd)) begin
-        code = $fgets(line, fd);
-        if (code != 0) begin
-          int errno;
-          string errstr;
-          errno = $ferror(fd, errstr);
-          if (errno != 0) $display("Error %d (code %d) reading line %d of %s: %s", errno, code, siglines, signame, errstr);
-          if (line.len() > 1) begin // skip blank lines
-            if ($sscanf(line, "%x", parsed) != 0) begin
-              sig32[siglines] = parsed;
-              siglines = siglines + 1; // increment if line is not blank
-            end
-          end
-        end
-      end
-      $fclose(fd);
-    end
-
-    // Check valid number of lines were read
-    if (siglines == 0) begin  
-      errors = 1; 
-      $display("Error: empty test file %s", signame);
-    end else if (P.XLEN == 64 & (siglines % 2)) begin
-      errors = 1;
-      $display("Error: RV64 signature has odd number of lines %s", signame);
-    end else errors = 0;
-
-    // copy lines into signature, converting to XLEN if necessary
-    sigentries = (P.XLEN == 32) ? siglines : siglines/2; // number of signature entries
-    for (i=0; i<sigentries; i++) begin
-      signature[i] = (P.XLEN == 32) ? sig32[i] : {sig32[i*2+1], sig32[i*2]};
-      //$display("XLEN = %d signature[%d] = %x", P.XLEN, i, signature[i]);
-    end
-
-    // Check errors
-    testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
-    testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
-    for (i=0; i<sigentries; i++) begin
-      logic [P.XLEN-1:0] sig;
-      // **************************************
-      // ***** BUG BUG BUG make sure RT undoes this.
-      //if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
-      //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
-      if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
-      //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
-      //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
-      //if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin
-      if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin  
-        errors = errors+1;
-        $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", 
-			     TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
-        $stop; // if this is changed to $finish, wally-batch.do does not get to the next step to run coverage
-      end
-    end
-    if (errors) $display("%s failed with %d errors. :(", TestName, errors);
-    else $display("%s succeeded.  Brilliant!!!", TestName);
-  endtask
-  
-  /* verilator lint_on WIDTHTRUNC */
-  /* verilator lint_on WIDTHEXPAND */
-
-endmodule
-
-/* verilator lint_on STMTDLY */
-/* verilator lint_on WIDTH */
-
-task automatic updateProgramAddrLabelArray;
-  /* verilator lint_off WIDTHTRUNC */
-  /* verilator lint_off WIDTHEXPAND */
-  input string ProgramAddrMapFile, ProgramLabelMapFile;
-  inout  integer ProgramAddrLabelArray [string];
-  // Gets the memory location of begin_signature
-  integer ProgramLabelMapFP, ProgramAddrMapFP;
-
-  ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
-  ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
-
-  if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files
-    ProgramAddrLabelArray["begin_signature"] = 0;
-    ProgramAddrLabelArray["tohost"] = 0;
-    ProgramAddrLabelArray["sig_end_canary"] = 0;
-    while (!$feof(ProgramLabelMapFP)) begin
-      string label, adrstr;
-      integer returncode;
-      returncode = $fscanf(ProgramLabelMapFP, "%s\n", label);
-      returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
-      if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
-    end
-  end
-
-//  if(ProgramAddrLabelArray["begin_signature"] == 0) $display("Couldn't find begin_signature in %s", ProgramLabelMapFile);
-//  if(ProgramAddrLabelArray["sig_end_canary"] == 0) $display("Couldn't find sig_end_canary in %s", ProgramLabelMapFile);
-
-  $fclose(ProgramLabelMapFP);
-  $fclose(ProgramAddrMapFP);
-  /* verilator lint_on WIDTHTRUNC */
-  /* verilator lint_on WIDTHEXPAND */
-endtask
-
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 035e625b7..ae33a83cc 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -33,8 +33,8 @@
     `include "idv/idv.svh"
 `endif
 
+
 import cvw::*;
-import "DPI-C" function string getenv(input string env_name);
 
 module testbench;
   /* verilator lint_off WIDTHTRUNC */
@@ -51,16 +51,30 @@ module testbench;
     import idvApiPkg::*;
   `endif
 
-`include "parameter-defs.vh"
+  `ifdef VERILATOR
+      import "DPI-C" function string getenvval(input string env_name);
+      string       RISCV_DIR = getenvval("RISCV"); // "/opt/riscv";
+  `elsif SIM_VCS 
+      import "DPI-C" function string getenv(input string env_name);
+      string       RISCV_DIR = getenv("RISCV"); // "/opt/riscv";
+  `else
+      string       RISCV_DIR = "$RISCV"; // "/opt/riscv";
+  `endif
+
+  `include "parameter-defs.vh"
 
   logic        clk;
   logic        reset_ext, reset;
   logic        ResetMem;
 
+  logic tck;
+  logic tdi;
+  logic tms;
+  logic tdo;
+
   // Variables that can be overwritten with $value$plusargs at start of simulation
-  string       TEST;
+  string       TEST, ElfFile;
   integer      INSTR_LIMIT;
-  string       RISCV_DIR = getenv("RISCV"); // "/opt/riscv";
 
   // DUT signals
   logic [P.AHBW-1:0]    HRDATAEXT;
@@ -82,6 +96,36 @@ module testbench;
   logic        SPIIn, SPIOut;
   logic [3:0]  SPICS;
   logic        SDCIntr;
+  logic        ui_clk;
+  logic [15:0] dmc_trefi;
+  logic [3:0]  dmc_tmrd;
+  logic [3:0]  dmc_trfc;
+  logic [3:0]  dmc_trc;
+  logic [3:0]  dmc_trp;
+  logic [3:0]  dmc_tras;
+  logic [3:0]  dmc_trrd;
+  logic [3:0]  dmc_trcd;
+  logic [3:0]  dmc_twr;
+  logic [3:0]  dmc_twtr;
+  logic [3:0]  dmc_trtp;
+  logic [3:0]  dmc_tcas;
+  logic [3:0]  dmc_col_width;
+  logic [3:0]  dmc_row_width;
+  logic [1:0]  dmc_bank_width;
+  logic [5:0]  dmc_bank_pos;
+  logic [2:0]  dmc_dqs_sel_cal;
+  logic [15:0] dmc_init_cycles;
+  logic        dmc_config_changed;
+  logic        PLLrefclk;
+  logic        PLLrfen, PLLfben;
+  logic [5:0]  PLLclkr;
+  logic [12:0] PLLclkf;
+  logic [3:0]  PLLclkod;
+  logic [11:0] PLLbwadj;
+  logic        PLLtest;
+  logic        PLLfasten;
+  logic        PLLlock;
+  logic        PLLconfigdone;
 
   logic        HREADY;
   logic        HSELEXT;
@@ -101,11 +145,16 @@ module testbench;
   logic Validate;
   logic SelectTest;
   logic TestComplete;
+  logic PrevPCZero;
 
   initial begin
     // look for arguments passed to simulation, or use defaults
     if (!$value$plusargs("TEST=%s", TEST))
       TEST = "none";
+    if (!$value$plusargs("ElfFile=%s", ElfFile))
+      ElfFile = "none";
+    else begin
+    end
     if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT))
       INSTR_LIMIT = 0;
     
@@ -119,7 +168,7 @@ module testbench;
                           if (P.ZICSR_SUPPORTED)  tests = {arch64c, arch64cpriv};
                           else                    tests = {arch64c};
         "arch64m":      if (P.M_SUPPORTED)        tests = arch64m;
-        "arch64a":      if (P.A_SUPPORTED)        tests = arch64a;
+        "arch64a_amo":      if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED)        tests = arch64a_amo;
         "arch64f":      if (P.F_SUPPORTED)        tests = arch64f;
         "arch64d":      if (P.D_SUPPORTED)        tests = arch64d;  
         "arch64f_fma":  if (P.F_SUPPORTED)        tests = arch64f_fma;
@@ -133,7 +182,7 @@ module testbench;
         "imperas64d":   if (P.D_SUPPORTED)        tests = imperas64d;
         "imperas64m":   if (P.M_SUPPORTED)        tests = imperas64m;
         "wally64q":     if (P.Q_SUPPORTED)        tests = wally64q;
-        "wally64a":     if (P.A_SUPPORTED)        tests = wally64a;
+        "wally64a_lrsc":     if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED)        tests = wally64a_lrsc;
         "imperas64c":   if (P.C_SUPPORTED)        tests = imperas64c;
                         else                      tests = imperas64iNOc;
         "custom":                                 tests = custom;
@@ -142,6 +191,7 @@ module testbench;
         "wally64periph":                          tests = wally64periph;
         "coremark":                               tests = coremark;
         "fpga":                                   tests = fpga;
+        "soc":                                    tests = soc;
         "ahb64" :                                 tests = ahb64;
         "coverage64gc" :                          tests = coverage64gc;
         "arch64zba":     if (P.ZBA_SUPPORTED)     tests = arch64zba;
@@ -172,7 +222,7 @@ module testbench;
                           if (P.ZICSR_SUPPORTED)  tests = {arch32c, arch32cpriv};
                           else                    tests = {arch32c};
         "arch32m":      if (P.M_SUPPORTED)        tests = arch32m;
-        "arch32a":      if (P.A_SUPPORTED)        tests = arch32a;
+        "arch32a_amo":      if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED)  tests = arch32a_amo; 
         "arch32f":      if (P.F_SUPPORTED)        tests = arch32f;
         "arch32d":      if (P.D_SUPPORTED)        tests = arch32d;
         "arch32f_fma":  if (P.F_SUPPORTED)        tests = arch32f_fma;
@@ -184,7 +234,7 @@ module testbench;
         "imperas32i":                             tests = imperas32i;
         "imperas32f":   if (P.F_SUPPORTED)        tests = imperas32f;
         "imperas32m":   if (P.M_SUPPORTED)        tests = imperas32m;
-        "wally32a":     if (P.A_SUPPORTED)        tests = wally32a;
+        "wally32a_lrsc":     if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED)        tests = wally32a_lrsc; 
         "imperas32c":   if (P.C_SUPPORTED)        tests = imperas32c;
                         else                      tests = imperas32iNOc;
         "wally32i":                               tests = wally32i; 
@@ -212,10 +262,18 @@ module testbench;
         "arch32zknh":    if (P.ZKNH_SUPPORTED)    tests = arch32zknh;
       endcase
     end
-    if (tests.size() == 0) begin
-      $display("TEST %s not supported in this configuration", TEST);
+    if (tests.size() == 0 & ElfFile == "none") begin
+      if (tests.size() == 0) begin
+        $display("TEST %s not supported in this configuration", TEST);
+      end else if(ElfFile == "none") begin
+        $display("ElfFile %s not found", ElfFile);
+      end
       $finish;
     end
+`ifdef MAKEVCD
+    $dumpfile("testbench.vcd");
+    $dumpvars;
+`endif
   end // initial begin
 
   // Model the testbench as an fsm.
@@ -244,15 +302,16 @@ module testbench;
   logic        ResetCntRst;
   logic        CopyRAM;
 
-  string  signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd;
+  string  signame, elffilename, memfilename, bootmemfilename, uartoutfilename, pathname;
   integer begin_signature_addr, end_signature_addr, signature_size;
+  integer uartoutfile;
 
   assign ResetThreshold = 3'd5;
 
   initial begin
-    TestBenchReset = 1;
-    # 100;
-    TestBenchReset = 0;
+    TestBenchReset = 1'b1;
+    # 100ns;
+    TestBenchReset = 1'b0;
   end
 
   always_ff @(posedge clk)
@@ -307,47 +366,53 @@ module testbench;
   // Find the test vector files and populate the PC to function label converter
   ////////////////////////////////////////////////////////////////////////////////
   logic [P.XLEN-1:0] testadr;
-  always_comb begin
+
+  //VCS ignores the dynamic types while processing the implicit sensitivity lists of always @*, always_comb, and always_latch
+  //procedural blocks. VCS supports the dynamic types in the implicit sensitivity list of always @* block as specified in the Section 9.2 of the IEEE Standard SystemVerilog Specification 1800-2012.
+  //To support memory load and dump task verbosity: flag : -diag sys_task_mem
+  always @(*) begin
   	begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
  	end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
   	signature_size = end_signature_addr - begin_signature_addr;
   end
+  logic EcallFaultM;
+  if (P.ZICSR_SUPPORTED)
+    assign EcallFaultM = dut.core.priv.priv.EcallFaultM;
+  else
+    assign EcallFaultM = 0;
+  
   always @(posedge clk) begin
     ////////////////////////////////////////////////////////////////////////////////
     // Verify the test ran correctly by checking the memory against a known signature.
     ////////////////////////////////////////////////////////////////////////////////
     if(TestBenchReset) test = 1;
     if (P.ZICSR_SUPPORTED & TEST == "coremark")
-      if (dut.core.priv.priv.EcallFaultM) begin
+      if (EcallFaultM) begin
         $display("Benchmark: coremark is done.");
         $stop;
       end
-    if (P.ZICSR_SUPPORTED & dut.core.ifu.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.ieu.InstrValidM) begin 
-      $display("Program fetched illegal instruction 0x00000000 from address 0x00000000.  Might be fault with no fault handler.");
-      //$stop; // presently wally32/64priv tests trigger this for reasons not yet understood.
-    end
-
-  // modifications 4/3/24 kunlin & harris to speed up Verilator
-  // For some reason, Verilator runs ~100x slower when these SelectTest and Validate codes are in the posedge clk block
-  //end // added
-  //always @(posedge SelectTest) // added
     if(SelectTest) begin
-      if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
-      else if(TEST == "buildroot") begin 
+      if (riscofTest) begin 
+        memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
+        elffilename = {pathname, tests[test], "ref/ref.elf"};
+        ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
+        ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
+      end else if(TEST == "buildroot") begin 
         memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
+        elffilename = "buildroot";
         bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
         uartoutfilename = {"logs/", TEST, "_uart.out"};
-        rmCmd = {"rm -f ", uartoutfilename};
-        $system(rmCmd); // Delete existing UARToutfile
-      end
-      else            memfilename = {pathname, tests[test], ".elf.memfile"};
-      if (riscofTest) begin
-        ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
-        ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
-      end else if (TEST == "buildroot") begin
+        uartoutfile = $fopen(uartoutfilename, "w"); // delete UART output file
         ProgramAddrMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.addr"};
         ProgramLabelMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.lab"};
+      end else if(ElfFile != "none") begin
+        elffilename = ElfFile;
+        memfilename = {ElfFile, ".memfile"};
+        ProgramAddrMapFile = {ElfFile, ".objdump.addr"};
+        ProgramLabelMapFile = {ElfFile, ".objdump.lab"};
       end else begin
+        elffilename = {pathname, tests[test], ".elf"};
+        memfilename = {pathname, tests[test], ".elf.memfile"};
         ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
         ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
       end
@@ -365,6 +430,9 @@ module testbench;
   always @(posedge Validate) // added
 `endif
     if(Validate) begin
+      if (PrevPCZero) totalerrors = totalerrors + 1; //  error if PC is stuck at zero
+      if (TEST == "buildroot")
+        $fclose(uartoutfile);
       if (TEST == "embench") begin
         // Writes contents of begin_signature to .sim.output file
         // this contains instret and cycles for start and end of test run, used by embench 
@@ -385,22 +453,33 @@ module testbench;
         $display("Embench Benchmark: created output file: %s", outputfile);
       end else if (TEST == "coverage64gc") begin
         $display("Coverage tests don't get checked");
+      end else if (ElfFile != "none") begin
+        $display("Single Elf file tests are not signatured verified.");
+`ifdef VERILATOR // this macro is defined when verilator is used
+        $finish; // Simulator Verilator needs $finish to terminate simulation.
+`elsif SIM_VCS // this macro is defined when vcs is used
+        $finish; // Simulator VCS needs $finish to terminate simulation.
+`else
+         $stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
+`endif
       end else begin 
         // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
         // clear signature to prevent contamination from previous tests
         if (!begin_signature_addr)
           $display("begin_signature addr not found in %s", ProgramLabelMapFile);
-        else if (TEST != "embench") begin   // *** quick hack for embench.  need a better long term solution
+        else if (TEST != "embench") begin 
           CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors);
           if(errors > 0) totalerrors = totalerrors + 1;
         end
       end
-      test = test + 1; // *** this probably needs to be moved.
+      test = test + 1; 
       if (test == tests.size()) begin
         if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
         else $display("FAIL: %d test programs had errors", totalerrors);
 `ifdef VERILATOR // this macro is defined when verilator is used
         $finish; // Simulator Verilator needs $finish to terminate simulation.
+`elsif SIM_VCS // this macro is defined when vcs is used
+        $finish; // Simulator VCS needs $finish to terminate simulation.
 `else
          $stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
 `endif
@@ -429,10 +508,10 @@ module testbench;
         string romfilename, sdcfilename;
         romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
         sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
-        //$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
+        //$readmemh(romfilename, dut.uncoregen.uncore.bootrom.bootrom.memory.ROM);
         //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
         // shorten sdc timers for simulation
-        //dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
+        //dut.uncoregen.uncore.sdc.SDC.LimitTimers = 1;
       end
     end
   end else if (P.IROM_SUPPORTED) begin
@@ -446,13 +525,21 @@ module testbench;
       if (LoadMem) begin
         if (TEST == "buildroot") begin
           memFile = $fopen(bootmemfilename, "rb");
-          readResult = $fread(dut.uncore.uncore.bootrom.bootrom.memory.ROM, memFile);
+          if (memFile == 0) begin
+            $display("Error: Could not open file %s", memfilename);
+            $finish;
+          end
+          readResult = $fread(dut.uncoregen.uncore.bootrom.bootrom.memory.ROM, memFile);
           $fclose(memFile);
           memFile = $fopen(memfilename, "rb");
-          readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM, memFile);
+          if (memFile == 0) begin
+            $display("Error: Could not open file %s", memfilename);
+            $finish;
+          end
+          readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.ram.RAM, memFile);
           $fclose(memFile);
         end else 
-          $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+          $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.ram.RAM);
         if (TEST == "embench") $display("Read memfile %s", memfilename);
       end
       if (CopyRAM) begin
@@ -461,7 +548,7 @@ module testbench;
         EndIndex = (end_signature_addr >> LogXLEN) + 8;
         BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
         for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
-          testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncore.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex];
+          testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncoregen.uncore.ram.ram.memory.ram.RAM[ShadowIndex - BaseIndex];
         end
       end
     end
@@ -469,7 +556,7 @@ module testbench;
   if (P.DTIM_SUPPORTED) begin
     always @(posedge clk) begin
       if (LoadMem) begin
-        $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
+        $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.ram.RAM);
         $display("Read memfile %s", memfilename);
       end
       if (CopyRAM) begin
@@ -478,7 +565,7 @@ module testbench;
         EndIndex = (end_signature_addr >> LogXLEN) + 8;
         BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
         for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
-          testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.RAM[ShadowIndex - BaseIndex];
+          testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.ram.RAM[ShadowIndex - BaseIndex];
         end
       end
     end
@@ -486,32 +573,178 @@ module testbench;
 
   integer adrindex;
   if (P.UNCORE_RAM_SUPPORTED)
-    always @(posedge clk) 
+    always @(posedge clk)
       if (ResetMem)  // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory)
         for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) 
-          dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = 0;
+          dut.uncoregen.uncore.ram.ram.memory.ram.RAM[adrindex] = '0;
 
   ////////////////////////////////////////////////////////////////////////////////
   // Actual hardware
   ////////////////////////////////////////////////////////////////////////////////
 
   // instantiate device to be tested
-  assign GPIOIN = 0;
-  assign UARTSin = 1;
-  assign SPIIn = 0;
-
-  if(P.EXT_MEM_SUPPORTED) begin
-    ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) 
-    ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), 
-      .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
-  end else begin 
-    assign HREADYEXT = 1;
-    assign {HRESPEXT, HRDATAEXT} = 0;
-  end
+  assign GPIOIN = '0;
+  assign UARTSin = 1'b1;
+  assign SPIIn = 1'b0;
+
+  genvar ddr_i;
+  generate
+    if(P.EXT_MEM_SUPPORTED) begin
+      if (P.BSG_DMC_SUPPORTED) begin
+        `ifdef USE_BSG
+          import bsg_dmc_pkg::bsg_dmc_s;
+          `include "bsg_dmc.svh"
+
+          localparam dq_width = 32;
+          localparam dq_group = dq_width/8;
+          
+          // DDR wires
+          wire  [dq_width-1:0]  ddr_dq;
+          wire  [dq_group-1:0]  ddr_dqs_p;
+          wire                  ddr_ck_p;
+          wire                  ddr_ck_n;
+          wire                  ddr_cke;
+          wire  [2:0]           ddr_ba;
+          wire  [15:0]          ddr_addr;
+          wire                  ddr_cs_n;
+          wire                  ddr_ras_n;
+          wire                  ddr_cas_n;
+          wire                  ddr_we_n;
+          wire                  ddr_reset_n;
+          wire                  ddr_odt;
+          wire  [dq_group-1:0]  ddr_dm;
+          // DDR tristate i/o and enables
+          wire  [dq_group-1:0]  ddr_dm_oen_o;
+          wire  [dq_group-1:0]  ddr_dm_o;
+          wire  [dq_group-1:0]  ddr_dqs_p_oen_o;
+          wire  [dq_group-1:0]  ddr_dqs_p_ien_o;
+          wire  [dq_group-1:0]  ddr_dqs_p_o;
+          wire  [dq_group-1:0]  ddr_dqs_p_i;
+          wire  [dq_group-1:0]  ddr_dqs_n_oen_o;
+          wire  [dq_group-1:0]  ddr_dqs_n_ien_o;
+          wire  [dq_group-1:0]  ddr_dqs_n_o;
+          wire  [dq_group-1:0]  ddr_dqs_n_i;
+          wire  [dq_width-1:0]  ddr_dq_oen_o;
+          wire  [dq_width-1:0]  ddr_dq_o;
+          wire  [dq_width-1:0]  ddr_dq_i;
+          logic                 dfi_clk_2x_i;
+          logic                 dfi_clk_1x_o;
+
+          // Wire up dmc_config to config registers
+          bsg_dmc_s dmc_config;
+          always_comb begin
+            dmc_config.trefi        = dmc_trefi;
+            dmc_config.tmrd         = dmc_tmrd;
+            dmc_config.trfc         = dmc_trfc;
+            dmc_config.trc          = dmc_trc;
+            dmc_config.trp          = dmc_trp;
+            dmc_config.tras         = dmc_tras;
+            dmc_config.trrd         = dmc_trrd;
+            dmc_config.trcd         = dmc_trcd;
+            dmc_config.twr          = dmc_twr;
+            dmc_config.twtr         = dmc_twtr;
+            dmc_config.trtp         = dmc_trtp;
+            dmc_config.tcas         = dmc_tcas;
+            dmc_config.col_width    = dmc_col_width;
+            dmc_config.row_width    = dmc_row_width;
+            dmc_config.bank_width   = dmc_bank_width;
+            dmc_config.bank_pos     = dmc_bank_pos;
+            dmc_config.dqs_sel_cal  = dmc_dqs_sel_cal;
+            dmc_config.init_cycles  = dmc_init_cycles;
+          end
+
+          always #2.5ns ui_clk = ~ui_clk; // ui_clk must be <= 208 MHz
+          always #1.25ns dfi_clk_2x_i = ~dfi_clk_2x_i; // dfi_clk_2x must be 2x ui_clk
+
+          // Initialize bsg_dmc
+          initial begin: bsg_dmc_config
+            force ram.dmc.dmc_clk_rst_gen.btc_async_reset.tag_data_reg.data_r = 0;
+            force ram.dmc.dmc_clk_rst_gen.dly_lines[0].dly_line_inst.ctrl_rrr = 31;
+            force ram.dmc.dmc_clk_rst_gen.dly_lines[1].dly_line_inst.ctrl_rrr = 31;
+            force ram.dmc.dmc_clk_rst_gen.dly_lines[2].dly_line_inst.ctrl_rrr = 31;
+            force ram.dmc.dmc_clk_rst_gen.dly_lines[3].dly_line_inst.ctrl_rrr = 31;
+            force ram.dmc.dmc_clk_rst_gen.clk_gen_ds_inst.reset_i = 1'b1;
+            force ram.dmc.dmc_clk_rst_gen.clk_gen_ds_inst.strobe_r = 1'b0;
+            ui_clk = 1'b0;
+            dfi_clk_2x_i = 1'b0;
+            #100ns;
+            force ram.dmc.dmc_clk_rst_gen.clk_gen_ds_inst.reset_i = 1'b0;
+            force ram.dmc.dmc_clk_rst_gen.clk_gen_ds_inst.strobe_r = 1'b1;
+          end
+          bsg_dmc_ahb #(
+            .AHB_ADDR_SIZE(28),
+            .AHB_DATA_SIZE(P.XLEN),
+            .DQ_DATA_SIZE(dq_width),
+            .BURST_LEN(8)
+          ) ram (
+            .dmc_config,
+            .dmc_config_changed,
+            .HCLK, .HRESETn, .HSEL(HSELEXT),
+            .HADDR(HADDR[27:0]), .HWDATA, .HWSTRB, .HBURST,
+            .HWRITE, .HTRANS, .HREADY,
+            .HRDATA(HRDATAEXT), .HRESP(HRESPEXT), .HREADYOUT(HREADYEXT),
+            .ui_clk,
+            .ddr_ck_p_o(ddr_ck_p), .ddr_ck_n_o(ddr_ck_n), .ddr_cke_o(ddr_cke),
+            .ddr_ba_o(ddr_ba), .ddr_addr_o(ddr_addr),
+            .ddr_cs_n_o(ddr_cs_n), .ddr_ras_n_o(ddr_ras_n), .ddr_cas_n_o(ddr_cas_n),
+            .ddr_we_n_o(ddr_we_n), .ddr_reset_n_o(ddr_reset_n), .ddr_odt_o(ddr_odt),
+            .ddr_dm_oen_o,
+            .ddr_dm_o,
+            .ddr_dqs_p_oen_o,
+            .ddr_dqs_p_ien_o,
+            .ddr_dqs_p_o,
+            .ddr_dqs_p_i,
+            .ddr_dqs_n_oen_o,
+            .ddr_dqs_n_ien_o,
+            .ddr_dqs_n_o,
+            .ddr_dqs_n_i,
+            .ddr_dq_oen_o,
+            .ddr_dq_o,
+            .ddr_dq_i,
+            .dfi_clk_2x_i,
+            .dfi_clk_1x_o);
+          for(ddr_i = 0; ddr_i < dq_group; ddr_i++) begin: dm_io
+            assign ddr_dm[ddr_i] = !ddr_dm_oen_o[ddr_i]? ddr_dm_o[ddr_i]: 1'bz;
+          end
+          for(ddr_i = 0; ddr_i < dq_group; ddr_i++) begin: dqs_io
+            assign ddr_dqs_p[ddr_i]   = !ddr_dqs_p_oen_o[ddr_i]? ddr_dqs_p_o[ddr_i]: 1'bz;
+            assign ddr_dqs_p_i[ddr_i] = !ddr_dqs_p_ien_o[ddr_i]? ddr_dqs_p[ddr_i]: 1'b0;
+            assign ddr_dqs_n_i[ddr_i] = ~ddr_dqs_p_i[ddr_i];
+          end
+          for(ddr_i = 0; ddr_i < dq_width; ddr_i++) begin: dq_io
+            assign ddr_dq[ddr_i]    = !ddr_dq_oen_o[ddr_i]? ddr_dq_o[ddr_i]: 1'bz;
+            assign ddr_dq_i[ddr_i]  = ddr_dq[ddr_i];
+          end
+          for(ddr_i = 0; ddr_i < 2; ddr_i++) begin: lpddr
+            mobile_ddr mobile_ddr_inst (
+              .Dq(ddr_dq[16*ddr_i+15:16*ddr_i]),
+              .Dqs(ddr_dqs_p[2*ddr_i+1:2*ddr_i]),
+              .Addr(ddr_addr[13:0]),
+              .Ba(ddr_ba[1:0]),
+              .Clk(ddr_ck_p),
+              .Clk_n(ddr_ck_n),
+              .Cke(ddr_cke),
+              .Cs_n(ddr_cs_n),
+              .Ras_n(ddr_ras_n),
+              .Cas_n(ddr_cas_n),
+              .We_n(ddr_we_n),
+              .Dm(ddr_dm[2*ddr_i+1:2*ddr_i]));
+          end
+        `endif
+      end else begin
+        ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
+        ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), 
+          .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
+      end
+    end else begin
+      assign HREADYEXT = 1;
+      assign {HRESPEXT, HRDATAEXT} = 0;
+    end
+  endgenerate
 
   if(P.SDC_SUPPORTED) begin : sdcard
-    // *** fix later
-/* -----\/----- EXCLUDED -----\/-----
+    // JP: Add back sd card when sd card AHB implementation done
+    /* -----\/----- EXCLUDED -----\/-----
     sdModel sdcard
       (.sdClk(SDCCLK),
        .cmd(SDCCmd), 
@@ -521,20 +754,46 @@ module testbench;
     assign SDCCmdIn = SDCCmd;
     assign SDCDat = sd_dat_reg_t ? sd_dat_reg_o : sd_dat_i;
     assign SDCDatIn = SDCDat;
- -----/\----- EXCLUDED -----/\----- */
-    assign SDCIntr = 0;
+    -----/\----- EXCLUDED -----/\----- */
+    assign SDCIntr = 1'b0;
   end else begin
-    assign SDCIntr = 0;
+    assign SDCIntr = 1'b0;
+  end
+
+  if (P.PLL_SUPPORTED) begin : PLL
+    // TODO: use behavioral PLL model. We should still use regular clock for test though
+    assign PLLrefclk = clk;
+    assign PLLrfen   = clk;
+    assign PLLfben   = clk;
+    assign PLLlock   = 1'b1;
+  end else begin : PLL
+    assign PLLrefclk = clk;
+    assign PLLrfen   = clk;
+    assign PLLfben   = clk;
+    assign PLLlock   = 1'b1;
   end
 
-  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
+  // Change these if testing debug
+  assign tck = 0;
+  assign tdi = 0;
+  assign tms = 0;
+
+  wallypipelinedsoc #(P) dut(
+    .clk, .reset_ext, .reset, .tck, .tdi, .tms, .tdo,
+    .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
     .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
     .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
-    .UARTSin, .UARTSout, .SDCIntr, .SPIIn, .SPIOut, .SPICS); 
+    .UARTSin, .UARTSout, .SDCIntr, .SPIIn, .SPIOut, .SPICS,
+    .ui_clk, .dmc_trefi, .dmc_tmrd, .dmc_trfc, .dmc_trc, .dmc_trp, .dmc_tras, .dmc_trrd,
+    .dmc_trcd, .dmc_twr, .dmc_twtr, .dmc_trtp, .dmc_tcas, .dmc_col_width, .dmc_row_width,
+    .dmc_bank_width, .dmc_bank_pos, .dmc_dqs_sel_cal, .dmc_init_cycles, .dmc_config_changed,
+    .PLLrefclk, .PLLrfen, .PLLfben, .PLLclkr, .PLLclkf, .PLLclkod, .PLLbwadj,
+    .PLLtest, .PLLfasten, .PLLlock, .PLLconfigdone
+  ); 
 
   // generate clock to sequence tests
   always begin
-    clk = 1; # 5; clk = 0; # 5;
+    clk = 1'b1; # 5ns; clk = 1'b0; # 5ns;
   end
 
   /*
@@ -574,50 +833,49 @@ module testbench;
     loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename, TEST);
 
   // track the current function or global label
-  if (DEBUG == 1 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : FunctionName
+  if (DEBUG > 0 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : FunctionName
     FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset),
 			      .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
   end
 
   // Append UART output to file for tests
-  always @(posedge clk) begin
-    if (P.UART_SUPPORTED & TEST == "buildroot") begin
-      if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin
-        memFile = $fopen(uartoutfilename, "ab");
-        $fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din);
-        $fclose(memFile);
+  if (P.UART_SUPPORTED) begin: uart_logger
+    always @(posedge clk) begin
+      if (TEST == "buildroot") begin
+        if (~dut.uncoregen.uncore.uartgen.uart.MEMWb & dut.uncoregen.uncore.uartgen.uart.uartPC.A == 3'b000 & ~dut.uncoregen.uncore.uartgen.uart.uartPC.DLAB) begin
+          $fwrite(uartoutfile, "%c", dut.uncoregen.uncore.uartgen.uart.uartPC.Din); // append characters one at a time so we see a consistent log appearing during the run
+          $fflush(uartoutfile);
+        end
       end
     end
   end
 
   // Termination condition
-  // terminate on a specific ECALL after li x3,1 for old Imperas tests,  *** remove this when old imperas tests are removed
-  // or sw	gp,-56(t0) for new Imperas tests
-  // or sd gp, -56(t0) 
-  // or on a jump to self infinite loop (6f) for RISC-V Arch tests
-  logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
-  if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
-  else                  assign ecf = 0;
-  always_comb begin
-  	TestComplete = ecf & 
-			    (dut.core.ieu.dp.regf.rf[3] == 1 | 
-			     (dut.core.ieu.dp.regf.we3 & 
-			      dut.core.ieu.dp.regf.a3 == 3 & 
-			      dut.core.ieu.dp.regf.wd3 == 1)) |
-           ((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
-           ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
-  //assign DCacheFlushStart =  TestComplete;
-  end
-  
-  DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));
+  // Terminate on 
+  // 1. jump to self loop (0x0000006f)
+  // 2. a store word writes to the address "tohost"
+  // 3. or PC is stuck at 0
+
+
+  always @(posedge clk) begin
+  //  if (reset) PrevPCZero <= 0;
+  //  else if (dut.core.InstrValidM) PrevPCZero <= (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0);
+    TestComplete <= ((InstrM == 32'h6f) & dut.core.InstrValidM ) |
+		   ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW"); // |
+    //   (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero));
+   // if (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero)
+    //  $error("Program fetched illegal instruction 0x00000000 from address 0x00000000 twice in a row.  Usually due to fault with no fault handler.");
+  end 
+
+  DCacheFlushFSM #(P) DCacheFlushFSM(.clk, .start(DCacheFlushStart), .done(DCacheFlushDone));
 
   if(P.ZICSR_SUPPORTED) begin
     logic [P.XLEN-1:0] Minstret;
     assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];  
     always @(negedge clk) begin
       if (INSTR_LIMIT > 0) begin
-        if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret);
-        if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end
+        if((Minstret != 0) & (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret);
+        if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $finish; end
       end
     end
 end
@@ -631,7 +889,7 @@ end
   wallyTracer #(P) wallyTracer(rvvi);
 
   trace2log idv_trace2log(rvvi);
-  //      trace2cov idv_trace2cov(rvvi);
+  trace2cov idv_trace2cov(rvvi);
 
   // enabling of comparison types
   trace2api #(.CMP_PC      (1),
@@ -642,10 +900,17 @@ end
               .CMP_CSR     (1)
               ) idv_trace2api(rvvi);
 
+  string filename;
   initial begin
+    // imperasDV requires the elffile be defined at the begining of the simulation.
     int iter;
+    longint x64;
+    int     x32[2];
+    longint index;
+    string  memfilenameImperasDV, bootmemfilenameImperasDV;
     #1;
     IDV_MAX_ERRORS = 3;
+    elffilename = ElfFile;
 
     // Initialize REF (do this before initializing the DUT)
     if (!rvviVersionCheck(RVVI_API_VERSION)) begin
@@ -659,9 +924,57 @@ end
     void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH,     56));
     void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6));
 
-    if (!rvviRefInit("")) begin
-      $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
-      $fatal;
+    if(elffilename == "buildroot") filename = "";    
+    else filename = elffilename;
+
+    // use the ImperasDV rvviRefInit to load the reference model with an elf file
+    if(elffilename != "none") begin
+      if (!rvviRefInit(filename)) begin
+        $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
+        $fatal;
+      end
+    end else begin // for buildroot use the binary instead to load the reference model.
+      if (!rvviRefInit("")) begin // still have to call with nothing
+        $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
+        $fatal;
+      end      
+      
+      memfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/ram.bin"};
+      bootmemfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
+
+      $display("RVVI Loading bootmem.bin");
+      memFile = $fopen(bootmemfilenameImperasDV, "rb");
+      index = 'h1000 - 8;
+      while(!$feof(memFile)) begin
+        index+=8;
+        readResult = $fread(x64, memFile);
+        if (x64 == 0) continue;
+        x32[0] = x64 & 'hffffffff;
+        x32[1] = x64 >> 32;
+        rvviRefMemoryWrite(0, index+0, x32[0], 4);
+        rvviRefMemoryWrite(0, index+4, x32[1], 4);
+        //$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
+      end
+      $fclose(memFile);
+            
+      $display("RVVI Loading ram.bin");
+      memFile = $fopen(memfilenameImperasDV, "rb");
+      index = 'h80000000 - 8;
+      while(!$feof(memFile)) begin
+        index+=8;
+        readResult = $fread(x64, memFile);
+        if (x64 == 0) continue;
+        x32[0] = x64 & 'hffffffff;
+        x32[1] = x64 >> 32;
+        rvviRefMemoryWrite(0, index+0, x32[0], 4);
+        rvviRefMemoryWrite(0, index+4, x32[1], 4);
+        //$display("ram  %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
+      end
+      $fclose(memFile);
+      
+      $display("RVVI Loading Complete");
+      
+      void'(rvviRefPcSet(0, P.RESET_VECTOR)); // set BOOTROM address
     end
 
     // Volatile CSRs
@@ -717,53 +1030,6 @@ end
 
     void'(rvviRefCsrSetVolatile(0, 32'h104));   // SIE - Temporary!!!!
     
-    // Load memory
-    // *** RT: This section can probably be moved into the same chunk of code which
-    // loads the memories.  However I'm not sure that ImperasDV supports reloading
-    // the memories without relaunching the simulator.
-    begin
-      longint x64;
-      int     x32[2];
-      longint index;
-      string  memfilenameImperasDV, bootmemfilenameImperasDV;
-      
-      memfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/ram.bin"};
-      bootmemfilenameImperasDV = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
-
-      $display("RVVI Loading bootmem.bin");
-      memFile = $fopen(bootmemfilenameImperasDV, "rb");
-      index = 'h1000 - 8;
-      while(!$feof(memFile)) begin
-        index+=8;
-        readResult = $fread(x64, memFile);
-        if (x64 == 0) continue;
-        x32[0] = x64 & 'hffffffff;
-        x32[1] = x64 >> 32;
-        rvviRefMemoryWrite(0, index+0, x32[0], 4);
-        rvviRefMemoryWrite(0, index+4, x32[1], 4);
-        //$display("boot %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
-      end
-      $fclose(memFile);
-            
-      $display("RVVI Loading ram.bin");
-      memFile = $fopen(memfilenameImperasDV, "rb");
-      index = 'h80000000 - 8;
-      while(!$feof(memFile)) begin
-        index+=8;
-        readResult = $fread(x64, memFile);
-        if (x64 == 0) continue;
-        x32[0] = x64 & 'hffffffff;
-        x32[1] = x64 >> 32;
-        rvviRefMemoryWrite(0, index+0, x32[0], 4);
-        rvviRefMemoryWrite(0, index+4, x32[1], 4);
-        //$display("ram  %08X x32[0]=%08X x32[1]=%08X", index, x32[0], x32[1]);
-      end
-      $fclose(memFile);
-      
-      $display("RVVI Loading Complete");
-      
-      void'(rvviRefPcSet(0, P.RESET_VECTOR)); // set BOOTROM address
-    end
   end
 
   always @(dut.core.priv.priv.csr.csri.MIP_REGW[7])   void'(rvvi.net_push("MTimerInterrupt",    dut.core.priv.priv.csr.csri.MIP_REGW[7]));
@@ -853,26 +1119,20 @@ end
     testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
     testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
     for (i=0; i<sigentries; i++) begin
-      logic [P.XLEN-1:0] sig;
-      // **************************************
-      // ***** BUG BUG BUG make sure RT undoes this.
-      //if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
-      //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
-      if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
-      //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
-      //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
-      //if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin
       if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin  
         errors = errors+1;
-        $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", 
-			     TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
+        $display("  Error on test %s result %d: adr = %h sim (D$) %h signature = %h", 
+			     TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]);
         $stop; // if this is changed to $finish, wally-batch.do does not get to the next step to run coverage
       end
     end
     if (errors) $display("%s failed with %d errors. :(", TestName, errors);
     else $display("%s succeeded.  Brilliant!!!", TestName);
   endtask
-  
+ 
+`ifdef PMP_COVERAGE
+test_pmp_coverage #(P) pmp_inst(clk);
+`endif
   /* verilator lint_on WIDTHTRUNC */
   /* verilator lint_on WIDTHEXPAND */
 
@@ -903,7 +1163,7 @@ task automatic updateProgramAddrLabelArray;
       returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
       if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
     end
-  end
+  end 
 
 //  if(ProgramAddrLabelArray["begin_signature"] == 0) $display("Couldn't find begin_signature in %s", ProgramLabelMapFile);
 //  if(ProgramAddrLabelArray["sig_end_canary"] == 0) $display("Couldn't find sig_end_canary in %s", ProgramLabelMapFile);
diff --git a/testbench/testbench_fp.sv b/testbench/testbench_fp.sv
index f124ec334..f800a9fed 100644
--- a/testbench/testbench_fp.sv
+++ b/testbench/testbench_fp.sv
@@ -30,7 +30,7 @@ import cvw::*;
 module testbench_fp;
    // Two parameters TEST, TEST_SIZE used with testfloat.do in sim dir
    // to run specific precisions (e.g., quad or all)
-   parameter string TEST="none";
+   parameter string TEST="none"; // choices are cvtint, cvtfp, cmp, add, sub, mul, div, sqrt, fma; all does not check properly
    parameter string TEST_SIZE="all";
 
   `include "parameter-defs.vh"   
@@ -51,16 +51,16 @@ module testbench_fp;
    logic [31:0] 		errors=0;                   // how many errors
    logic [31:0] 		VectorNum=0;                // index for test vector
    logic [31:0] 		FrmNum=0;                   // index for rounding mode
-   logic [P.FLEN*4+7:0] 	TestVectors[MAXVECTORS-1:0];     // list of test vectors
+   logic [P.Q_LEN*4+7:0] 	TestVectors[MAXVECTORS-1:0];     // list of test vectors
 
    logic [1:0] 			FmtVal;                     // value of the current Fmt
    logic [2:0] 			UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
    logic                        WriteIntVal;                // value of the current WriteInt
-   logic [P.FLEN-1:0] 		X, Y, Z;                    // inputs read from TestFloat
+   logic [P.Q_LEN-1:0] 		X, Y, Z;                    // inputs read from TestFloat
    logic [P.FLEN-1:0] 		XPostBox;                   // inputs read from TestFloat
    logic [P.XLEN-1:0] 		SrcA;                       // integer input
-   logic [P.FLEN-1:0] 		Ans;                        // correct answer from TestFloat
-   logic [P.FLEN-1:0] 		Res;                        // result from other units
+   logic [P.Q_LEN-1:0] 		Ans;                        // correct answer from TestFloat
+   logic [P.Q_LEN-1:0] 		Res;                        // result from other units
    logic [4:0] 			AnsFlg;                     // correct flags read from testfloat
    logic [4:0] 			ResFlg, Flg;                // Result flags
    logic [P.FMTBITS-1:0] 	ModFmt;                     // format - 10 = half, 00 = single, 01 = double, 11 = quad
@@ -98,8 +98,8 @@ module testbench_fp;
    logic [P.NE+1:0] 		Se;
    logic 			ASticky;
    logic 			KillProd; 
-   logic [$clog2(3*P.NF+5)-1:0] SCnt;
-   logic [3*P.NF+3:0] 		Sm;       
+   logic [$clog2(P.FMALEN+1)-1:0] SCnt;
+   logic [P.FMALEN-1:0] 		Sm;       
    logic 			InvA;
    logic 			NegSum;
    logic 			As;
@@ -124,6 +124,9 @@ module testbench_fp;
    logic 			CheckNow;                   // Final check
    logic 			FMAop;                      // Is this a FMA operation?
 
+   logic [P.NE-2:0]             BiasE;                              // Bias of exponent
+   logic [P.LOGFLEN-1:0]        NfE;                                // Number of fractional bits
+
    // FSM for testing each item per clock
    typedef enum logic [2:0] {S0, Start, S2, Done} statetype;
    statetype state, nextstate;   
@@ -146,7 +149,7 @@ module testbench_fp;
    //    sub    - test subtraction
    //    div    - test division
    //    sqrt   - test square root
-   //    all    - test all of the above
+   //    all    - test all of the above < doesn't report errors properly >
    
    initial begin
       // Information displayed for user on what is simulating
@@ -671,7 +674,7 @@ module testbench_fp;
       FrmVal = Frm[FrmNum];
    end
 
-   // modify the format signal if only 2 percisions supported
+   // modify the format signal if only 2 precisions supported
    //    - 1 for the larger precision
    //    - 0 for the smaller precision
    always_comb begin
@@ -690,7 +693,7 @@ module testbench_fp;
                                  .XSubnorm, .ZSubnorm, 
                                  .XZero, .YZero, .ZZero,
                                  .XInf, .YInf, .ZInf, .XExpMax,
-                                 .X, .Y, .Z, .XPostBox);
+                                 .X, .Y, .Z, .XPostBox, .NfE, .BiasE);
 
    ///////////////////////////////////////////////////////////////////////////////////////////////
 
@@ -733,14 +736,14 @@ module testbench_fp;
    if (TEST === "cmp" | TEST === "all") begin: fcmp
       fcmp #(P) fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Zfa(1'b0), .Xs, .Ys, .Xe, .Ye, 
                    .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes),
-                   .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
+                   .XNaN, .YNaN, .XSNaN, .YSNaN, .X(X[P.FLEN-1:0]), .Y(Y[P.FLEN-1:0]), .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
    end
    
    if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt
       fdivsqrt #(P) fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), 
 			     .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
 			     .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), 
-			     .XNaNE(XNaN), .YNaNE(YNaN), 
+			     .XNaNE(XNaN), .YNaNE(YNaN), .NfE, .BiasE,
 			     .FDivStartE(DivStart), .IDivStartE(1'b0), .W64E(1'b0),
 			     .StallM(1'b0), .DivStickyM(DivSticky), .FDivBusyE, .UeM(DivCalcExp),
 			     .UmM(Quot),
@@ -974,8 +977,9 @@ module testbench_fp;
       if (~(ResMatch & FlagMatch) & CheckNow & (Ans[0] !== 1'bx)) begin
          errors += 1;
          $display("\nError in %s", Tests[TestNum]);
-         $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);	 
-         $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
+         $display("TestNum %d VectorNum %d OpCtrl %d", TestNum, VectorNum, OpCtrl[TestNum]);	 
+         $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", 
+            X[P.FLEN-1:0], Y[P.FLEN-1:0], Z[P.FLEN-1:0], SrcA, Res[P.FLEN-1:0], ResFlg, Ans[P.FLEN-1:0], AnsFlg);
          $stop;
       end
 
@@ -1012,14 +1016,14 @@ endmodule
 
 module readvectors import cvw::*; #(parameter cvw_t P) (
 		    input logic 		clk,
-		    input logic [P.FLEN*4+7:0] 	TestVector,
+		    input logic [P.Q_LEN*4+7:0] 	TestVector,
 		    input logic [P.FMTBITS-1:0] ModFmt,
 		    input logic [1:0] 		Fmt,
 		    input logic [2:0] 		Unit,
 		    input logic [31:0] 		VectorNum,
 		    input logic [31:0] 		TestNum,
 		    input logic [2:0] 		OpCtrl,
-		    output logic [P.FLEN-1:0] 	Ans,
+   	    output logic [P.Q_LEN-1:0] 	Ans,
 		    output logic [P.XLEN-1:0] 	SrcA,
 		    output logic [4:0] 		AnsFlg,
 		    output logic 		Xs, Ys, Zs, // sign bits of XYZ
@@ -1031,7 +1035,10 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
 		    output logic 		XZero, YZero, ZZero, // is XYZ zero
 		    output logic 		XInf, YInf, ZInf, // is XYZ infinity
 		    output logic 		XExpMax,
-		    output logic [P.FLEN-1:0] 	X, Y, Z, XPostBox
+		    output logic [P.Q_LEN-1:0] 	X, Y, Z,
+          output logic [P.FLEN-1:0]  XPostBox,
+	       output logic [P.NE-2:0] BiasE,                              // Bias of exponent
+          output logic [P.LOGFLEN-1:0] NfE                           // Number of fractional bits
 		    );
 
    localparam Q_LEN = 32'd128;
@@ -1048,7 +1055,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
       case (Unit)
 	`FMAUNIT:
           case (Fmt)
-            2'b11: begin // quad
+            2'b11: if (P.Q_SUPPORTED) begin // quad
                if (OpCtrl === `FMA_OPCTRL) begin
 		  X = TestVector[8+4*(P.Q_LEN)-1:8+3*(P.Q_LEN)];
 		  Y = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
@@ -1371,9 +1378,9 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
    assign ZEn = (Unit == `FMAUNIT);
    assign FPUActive = 1'b1;
    
-   unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .FPUActive, .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
+   unpack #(P) unpack(.X(X[P.FLEN-1:0]), .Y(Y[P.FLEN-1:0]), .Z(Z[P.FLEN-1:0]), .Fmt(ModFmt), .FPUActive, .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
                       .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
                       .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
-                      .XEn, .YEn, .ZEn, .XExpMax, .XPostBox);
+                      .XEn, .YEn, .ZEn, .XExpMax, .XPostBox, .Bias(BiasE), .Nf(NfE));
 
 endmodule
diff --git a/testbench/tests.vh b/testbench/tests.vh
index 8dfd69415..ba37e9fe2 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -72,6 +72,59 @@ string tvpaths[] = '{
     "pmpadrdecs"
   };
 
+  string wallycov64i[] = '{
+    `WALLYTEST,
+    "rv64i_m/I/src/WALLY-COV-lh.S",
+    "rv64i_m/I/src/WALLY-COV-srli.S",
+    "rv64i_m/I/src/WALLY-COV-srai.S",
+    "rv64i_m/I/src/WALLY-COV-or.S",
+    "rv64i_m/I/src/WALLY-COV-sra.S",
+    "rv64i_m/I/src/WALLY-COV-sll.S",
+    "rv64i_m/I/src/WALLY-COV-slti.S",
+    "rv64i_m/I/src/WALLY-COV-bne.S",
+    "rv64i_m/I/src/WALLY-COV-bltu.S",
+    "rv64i_m/I/src/WALLY-COV-srliw.S",
+    "rv64i_m/I/src/WALLY-COV-slliw.S",
+    "rv64i_m/I/src/WALLY-COV-sw.S",
+    "rv64i_m/I/src/WALLY-COV-sraiw.S",
+    "rv64i_m/I/src/WALLY-COV-sltu.S",
+    "rv64i_m/I/src/WALLY-COV-addiw.S",
+    "rv64i_m/I/src/WALLY-COV-slli.S",
+    "rv64i_m/I/src/WALLY-COV-beq.S",
+    "rv64i_m/I/src/WALLY-COV-sd.S",
+    "rv64i_m/I/src/WALLY-COV-auipc.S",
+    "rv64i_m/I/src/WALLY-COV-bge.S",
+    "rv64i_m/I/src/WALLY-COV-sltiu.S",
+    "rv64i_m/I/src/WALLY-COV-lui.S",
+    "rv64i_m/I/src/WALLY-COV-lw.S",
+    "rv64i_m/I/src/WALLY-COV-lwu.S",
+    "rv64i_m/I/src/WALLY-COV-slt.S",
+    "rv64i_m/I/src/WALLY-COV-blt.S",
+    "rv64i_m/I/src/WALLY-COV-addw.S",
+    "rv64i_m/I/src/WALLY-COV-lb.S",
+    "rv64i_m/I/src/WALLY-COV-xori.S",
+    "rv64i_m/I/src/WALLY-COV-addi.S",
+    "rv64i_m/I/src/WALLY-COV-xor.S",
+    "rv64i_m/I/src/WALLY-COV-jal.S",
+    "rv64i_m/I/src/WALLY-COV-sb.S",
+    "rv64i_m/I/src/WALLY-COV-ld.S",
+    "rv64i_m/I/src/WALLY-COV-lhu.S",
+    "rv64i_m/I/src/WALLY-COV-andi.S",
+    "rv64i_m/I/src/WALLY-COV-ori.S",
+    "rv64i_m/I/src/WALLY-COV-sub.S",
+    "rv64i_m/I/src/WALLY-COV-and.S",
+    "rv64i_m/I/src/WALLY-COV-sh.S",
+    "rv64i_m/I/src/WALLY-COV-srlw.S",
+    "rv64i_m/I/src/WALLY-COV-sraw.S",
+    "rv64i_m/I/src/WALLY-COV-subw.S",
+    "rv64i_m/I/src/WALLY-COV-sllw.S",
+    "rv64i_m/I/src/WALLY-COV-jalr.S",
+    "rv64i_m/I/src/WALLY-COV-lbu.S",
+    "rv64i_m/I/src/WALLY-COV-add.S",
+    "rv64i_m/I/src/WALLY-COV-srl.S",
+    "rv64i_m/I/src/WALLY-COV-bgeu.S"
+  };
+
   string buildroot[] = '{
     `BUILDROOT,
     "buildroot"
@@ -874,12 +927,12 @@ string imperas32f[] = '{
     "rv64i_m/Q/src/WALLY-q-01.S"
   };
 
- string wally64a[] = '{
+ string wally64a_lrsc[] = '{
     `WALLYTEST,
     "rv64i_m/privilege/src/WALLY-lrsc-01.S"
   };
 
- string wally32a[] = '{
+ string wally32a_lrsc[] = '{
     `WALLYTEST,
     "rv32i_m/privilege/src/WALLY-lrsc-01.S"
  };
@@ -921,7 +974,7 @@ string imperas32f[] = '{
     "rv64i_m/Zicond/src/czero.nez-01.S"
     };
 
-  string arch32a[] = '{
+  string arch32a_amo[] = '{
     `RISCVARCHTEST,
     "rv32i_m/A/src/amoadd.w-01.S",
     "rv32i_m/A/src/amoand.w-01.S",
@@ -1083,7 +1136,7 @@ string imperas32f[] = '{
     "rv64i_m/M/src/remw-01.S"
    };
 
-  string arch64a[] = '{
+  string arch64a_amo[] = '{
     `RISCVARCHTEST,
     "rv64i_m/A/src/amoadd.w-01.S",
     "rv64i_m/A/src/amoand.w-01.S",
@@ -1202,10 +1255,206 @@ string imperas32f[] = '{
 
   string arch64f_fma[] = '{
     `RISCVARCHTEST,
-    //"rv64i_m/F/src/fmadd_b15-01.S",
-    "rv64i_m/F/src/fmsub_b15-01.S"
-    // "rv64i_m/F/src/fnmadd_b15-01.S",
-    // "rv64i_m/F/src/fnmsub_b15-01.S"
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-001.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-002.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-003.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-004.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-005.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-006.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-007.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-008.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-009.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-010.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-011.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-012.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-013.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-014.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-015.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-016.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-017.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-018.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-019.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-020.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-021.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-022.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-023.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-024.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-025.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-026.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-027.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-028.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-029.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-030.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-031.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-032.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-033.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-034.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-035.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-036.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-037.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-038.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-039.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-040.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-041.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-042.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-043.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-044.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-045.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-046.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-047.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-048.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-049.S",
+    // "rv64i_m/F/src/fmadd_b15/fmadd_b15-050.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-001.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-002.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-003.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-004.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-005.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-006.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-007.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-008.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-009.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-010.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-011.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-012.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-013.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-014.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-015.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-016.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-017.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-018.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-019.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-020.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-021.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-022.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-023.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-024.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-025.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-026.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-027.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-028.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-029.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-030.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-031.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-032.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-033.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-034.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-035.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-036.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-037.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-038.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-039.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-040.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-041.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-042.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-043.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-044.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-045.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-046.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-047.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-048.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-049.S",
+    "rv64i_m/F/src/fmsub_b15/fmsub_b15-050.S"
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-001.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-002.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-003.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-004.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-005.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-006.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-007.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-008.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-009.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-010.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-011.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-012.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-013.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-014.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-015.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-016.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-017.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-018.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-019.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-020.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-021.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-022.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-023.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-024.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-025.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-026.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-027.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-028.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-029.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-030.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-031.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-032.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-033.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-034.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-035.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-036.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-037.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-038.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-039.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-040.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-041.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-042.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-043.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-044.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-045.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-046.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-047.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-048.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-049.S",
+    // "rv64i_m/F/src/fnmadd_b15/fnmadd_b15-050.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-001.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-002.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-003.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-004.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-005.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-006.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-007.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-008.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-009.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-010.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-011.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-012.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-013.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-014.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-015.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-016.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-017.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-018.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-019.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-020.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-021.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-022.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-023.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-024.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-025.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-026.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-027.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-028.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-029.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-030.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-031.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-032.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-033.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-034.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-035.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-036.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-037.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-038.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-039.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-040.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-041.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-042.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-043.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-044.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-045.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-046.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-047.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-048.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-049.S",
+    // "rv64i_m/F/src/fnmsub_b15/fnmsub_b15-050.S"
   };
 
     string arch64zfh_fma[] = '{
@@ -1254,6 +1503,24 @@ string imperas32f[] = '{
     "rv64i_m/F/src/fadd_b7-01.S",
     "rv64i_m/F/src/fadd_b8-01.S",
     "rv64i_m/F/src/fclass_b1-01.S",
+    "rv64i_m/F/src/fcvt.s.l_b25-01.S", 
+    "rv64i_m/F/src/fcvt.s.l_b26-01.S",
+    "rv64i_m/F/src/fcvt.s.lu_b25-01.S",
+    "rv64i_m/F/src/fcvt.s.lu_b26-01.S",
+    "rv64i_m/F/src/fcvt.l.s_b1-01.S",
+    "rv64i_m/F/src/fcvt.l.s_b22-01.S",
+    "rv64i_m/F/src/fcvt.l.s_b23-01.S",
+    "rv64i_m/F/src/fcvt.l.s_b24-01.S",
+    "rv64i_m/F/src/fcvt.l.s_b27-01.S",
+    "rv64i_m/F/src/fcvt.l.s_b28-01.S",
+    "rv64i_m/F/src/fcvt.l.s_b29-01.S",
+    "rv64i_m/F/src/fcvt.lu.s_b1-01.S",
+    "rv64i_m/F/src/fcvt.lu.s_b22-01.S",
+    "rv64i_m/F/src/fcvt.lu.s_b23-01.S",
+    "rv64i_m/F/src/fcvt.lu.s_b24-01.S",
+    "rv64i_m/F/src/fcvt.lu.s_b27-01.S",
+    "rv64i_m/F/src/fcvt.lu.s_b28-01.S",
+    "rv64i_m/F/src/fcvt.lu.s_b29-01.S",
     "rv64i_m/F/src/fcvt.s.w_b25-01.S",
     "rv64i_m/F/src/fcvt.s.w_b26-01.S",
     "rv64i_m/F/src/fcvt.s.wu_b25-01.S",
@@ -1570,7 +1837,7 @@ string imperas32f[] = '{
   string arch64d[] = '{
     `RISCVARCHTEST,
     // for speed
-   "rv64i_m/D/src/fadd.d_b10-01.S",
+    "rv64i_m/D/src/fadd.d_b10-01.S",
     "rv64i_m/D/src/fadd.d_b1-01.S",
     "rv64i_m/D/src/fadd.d_b11-01.S",
     "rv64i_m/D/src/fadd.d_b12-01.S",
@@ -1737,7 +2004,6 @@ string arch64zcb[] = '{
       "rv64i_m/C/src/clbu-01.S",
       "rv64i_m/C/src/clh-01.S",
       "rv64i_m/C/src/clhu-01.S",
-      "rv64i_m/C/src/clbu-01.S",
       "rv64i_m/C/src/csb-01.S",
       "rv64i_m/C/src/csh-01.S",
       "rv64i_m/C/src/csext.b-01.S",
@@ -1754,7 +2020,6 @@ string arch32zcb[] = '{
       "rv32i_m/C/src/clbu-01.S",
       "rv32i_m/C/src/clh-01.S",
       "rv32i_m/C/src/clhu-01.S",
-      "rv32i_m/C/src/clbu-01.S",
       "rv32i_m/C/src/csb-01.S",
       "rv32i_m/C/src/csh-01.S",
       "rv32i_m/C/src/csext.b-01.S",
@@ -1899,10 +2164,206 @@ string arch64zknh[] = '{
 
   string arch32f_fma[] = '{
     `RISCVARCHTEST,
-    "rv32i_m/F/src/fmadd_b15-01.S"
-    //"rv32i_m/F/src/fmsub_b15-01.S",
-    // "rv32i_m/F/src/fnmadd_b15-01.S",
-    // "rv32i_m/F/src/fnmsub_b15-01.S"
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-001.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-002.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-003.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-004.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-005.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-006.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-007.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-008.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-009.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-010.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-011.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-012.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-013.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-014.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-015.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-016.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-017.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-018.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-019.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-020.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-021.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-022.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-023.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-024.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-025.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-026.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-027.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-028.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-029.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-030.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-031.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-032.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-033.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-034.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-035.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-036.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-037.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-038.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-039.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-040.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-041.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-042.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-043.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-044.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-045.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-046.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-047.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-048.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-049.S",
+    // "rv32i_m/F/src/fmadd_b15/fmadd_b15-050.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-001.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-002.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-003.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-004.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-005.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-006.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-007.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-008.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-009.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-010.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-011.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-012.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-013.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-014.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-015.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-016.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-017.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-018.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-019.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-020.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-021.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-022.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-023.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-024.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-025.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-026.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-027.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-028.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-029.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-030.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-031.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-032.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-033.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-034.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-035.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-036.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-037.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-038.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-039.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-040.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-041.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-042.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-043.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-044.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-045.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-046.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-047.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-048.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-049.S",
+    "rv32i_m/F/src/fmsub_b15/fmsub_b15-050.S"
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-001.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-002.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-003.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-004.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-005.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-006.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-007.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-008.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-009.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-010.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-011.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-012.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-013.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-014.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-015.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-016.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-017.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-018.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-019.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-020.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-021.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-022.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-023.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-024.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-025.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-026.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-027.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-028.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-029.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-030.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-031.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-032.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-033.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-034.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-035.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-036.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-037.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-038.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-039.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-040.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-041.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-042.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-043.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-044.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-045.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-046.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-047.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-048.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-049.S",
+    // "rv32i_m/F/src/fnmadd_b15/fnmadd_b15-050.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-001.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-002.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-003.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-004.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-005.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-006.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-007.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-008.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-009.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-010.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-011.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-012.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-013.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-014.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-015.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-016.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-017.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-018.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-019.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-020.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-021.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-022.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-023.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-024.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-025.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-026.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-027.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-028.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-029.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-030.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-031.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-032.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-033.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-034.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-035.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-036.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-037.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-038.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-039.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-040.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-041.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-042.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-043.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-044.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-045.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-046.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-047.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-048.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-049.S",
+    // "rv32i_m/F/src/fnmsub_b15/fnmsub_b15-050.S"
   };
 
   string arch32f_divsqrt[] = '{
@@ -1931,6 +2392,7 @@ string arch64zknh[] = '{
 
   string arch32f[] = '{
     `RISCVARCHTEST,
+    "rv32i_m/F/src/fadd_b11-01.S",
     "rv32i_m/F/src/fadd_b10-01.S",
     "rv32i_m/F/src/fadd_b1-01.S",
     "rv32i_m/F/src/fadd_b11-01.S",
@@ -2206,8 +2668,9 @@ string arch64zknh[] = '{
     };
 
   string arch32zfaf[] = '{
-    //`RISCVARCHTEST,
-    `WALLYTEST,
+    `RISCVARCHTEST,
+    "rv32i_m/F_Zfa/src/fround_b1-01.S",
+    "rv32i_m/F_Zfa/src/froundnx_b1-01.S",
     "rv32i_m/F_Zfa/src/fleq_b1-01.S",
     "rv32i_m/F_Zfa/src/fleq_b19-01.S", 
     "rv32i_m/F_Zfa/src/fli.s-01.S",
@@ -2219,12 +2682,14 @@ string arch64zknh[] = '{
     "rv32i_m/F_Zfa/src/fminm_b19-01.S",
     "rv32i_m/F_Zfa/src/fmaxm_b1-01.S",
     "rv32i_m/F_Zfa/src/fmaxm_b19-01.S"
-/*    "rv32i_m/F_Zfa/src/fround_b1-01.S" */
   };
 
   string arch32zfad[] = '{
-    //`RISCVARCHTEST,
-    `WALLYTEST,
+    `RISCVARCHTEST,
+    "rv32i_m/D_Zfa/src/fround_b1-01.S",
+    "rv32i_m/D_Zfa/src/froundnx_b1-01.S",
+    "rv32i_m/D_Zfa/src/fround.d_b1-01.S",
+    "rv32i_m/D_Zfa/src/froundnx.d_b1-01.S",
     "rv32i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S",
     "rv32i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S",
     "rv32i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S",
@@ -2256,12 +2721,12 @@ string arch64zknh[] = '{
     "rv32i_m/D_Zfa/src/fmvh.x.d_b27-01.S",
     "rv32i_m/D_Zfa/src/fmvh.x.d_b28-01.S",
     "rv32i_m/D_Zfa/src/fmvh.x.d_b29-01.S"
-/*    "rv32i_m/D_Zfa/src/fround_b1-01.S" */
   };
 
   string arch64zfaf[] = '{
-    //`RISCVARCHTEST,
-    `WALLYTEST,
+    `RISCVARCHTEST,
+    "rv64i_m/F_Zfa/src/fround_b1-01.S",
+    "rv64i_m/F_Zfa/src/froundnx_b1-01.S",
     "rv64i_m/F_Zfa/src/fleq_b1-01.S",
     "rv64i_m/F_Zfa/src/fleq_b19-01.S", 
     "rv64i_m/F_Zfa/src/fli.s-01.S",
@@ -2271,14 +2736,16 @@ string arch64zknh[] = '{
     "rv64i_m/F_Zfa/src/fminm_b19-01.S",
     "rv64i_m/F_Zfa/src/fmaxm_b1-01.S",
     "rv64i_m/F_Zfa/src/fmaxm_b19-01.S"
-/*    "rv64i_m/F_Zfa/src/fround_b1-01.S" */
   };
 
   string arch64zfad[] = '{
-    //`RISCVARCHTEST,
-    `WALLYTEST,
+    `RISCVARCHTEST,
+    "rv64i_m/D_Zfa/src/fround_b1-01.S",
+    "rv64i_m/D_Zfa/src/froundnx_b1-01.S",
+    "rv64i_m/D_Zfa/src/fround.d_b1-01.S",
+    "rv64i_m/D_Zfa/src/froundnx.d_b1-01.S",
     "rv64i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S",
-//    "rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S", // temporarily excluded because Sail produces wrong signature  https://github.com/riscv/sail-riscv/issues/388
+    "rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S", 
     "rv64i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S",
     "rv64i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S",
     "rv64i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S",
@@ -2293,7 +2760,7 @@ string arch64zknh[] = '{
     "rv64i_m/D_Zfa/src/fminm_b19-01.S",
     "rv64i_m/D_Zfa/src/fmaxm_b1-01.S",
     "rv64i_m/D_Zfa/src/fmaxm_b19-01.S"
-/*     "rv64i_m/D_Zfa/src/fround_b1-01.S" */
+
   };
 
   string arch32d_fma[] = '{
@@ -2703,11 +3170,18 @@ string arch32zfh_fma[] = '{
 
  string custom[] = '{
     `CUSTOM,
-    "simple",
-    "debug",
-    "cacheTest"
+    "lpddr_test"
+    // "simple",
+    // "debug",
+    // "cacheTest"
  };
-  string testsBP64[] = '{
+
+ string soc[] = '{
+    `CUSTOM,
+    "lpddr_test"
+ };
+
+ string testsBP64[] = '{
     `IMPERASTEST,
     "rv64BP/simple"
 //    "rv64BP/mmm",
diff --git a/testbench/wallywrapper.sv b/testbench/wallywrapper.sv
index 990ebfe74..00ad71fa3 100644
--- a/testbench/wallywrapper.sv
+++ b/testbench/wallywrapper.sv
@@ -26,51 +26,105 @@
 
 `include "config.vh"
 
-import cvw::*;
 
-module wallywrapper;
+
+module wallywrapper import cvw::*;(
+  input logic clk,
+  input logic reset_ext,
+  input logic SPIIn,
+  input logic SDCIntr
+);
  
 `include "parameter-defs.vh"
 
-  logic        clk;
-  logic        reset_ext, reset;
+  logic reset;
+
+  logic tck;
+  logic tdi;
+  logic tms;
+  logic tdo;
 
   logic [P.AHBW-1:0]    HRDATAEXT;
-  logic                HREADYEXT, HRESPEXT;
+  logic                 HREADYEXT, HRESPEXT;
   logic [P.PA_BITS-1:0] HADDR;
   logic [P.AHBW-1:0]    HWDATA;
   logic [P.XLEN/8-1:0]  HWSTRB;
-  logic                HWRITE;
-  logic [2:0]          HSIZE;
-  logic [2:0]          HBURST;
-  logic [3:0]          HPROT;
-  logic [1:0]          HTRANS;
-  logic                HMASTLOCK;
-  logic                HCLK, HRESETn;
+  logic                 HWRITE;
+  logic [2:0]           HSIZE;
+  logic [2:0]           HBURST;
+  logic [3:0]           HPROT;
+  logic [1:0]           HTRANS;
+  logic                 HMASTLOCK;
+  logic                 HCLK, HRESETn;
 
   logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
   logic        UARTSin, UARTSout;
-  logic        SPIIn, SPIOut;
+  logic        SPIOut;
   logic [3:0]  SPICS;
-  logic        SDCIntr;
+  logic        ui_clk;
+  logic [15:0] dmc_trefi;
+  logic [3:0]  dmc_tmrd;
+  logic [3:0]  dmc_trfc;
+  logic [3:0]  dmc_trc;
+  logic [3:0]  dmc_trp;
+  logic [3:0]  dmc_tras;
+  logic [3:0]  dmc_trrd;
+  logic [3:0]  dmc_trcd;
+  logic [3:0]  dmc_twr;
+  logic [3:0]  dmc_twtr;
+  logic [3:0]  dmc_trtp;
+  logic [3:0]  dmc_tcas;
+  logic [3:0]  dmc_col_width;
+  logic [3:0]  dmc_row_width;
+  logic [1:0]  dmc_bank_width;
+  logic [5:0]  dmc_bank_pos;
+  logic [2:0]  dmc_dqs_sel_cal;
+  logic [15:0] dmc_init_cycles;
+  logic        dmc_config_changed;
+  logic        PLLrefclk;
+  logic        PLLrfen, PLLfben;
+  logic [5:0]  PLLclkr;
+  logic [12:0] PLLclkf;
+  logic [3:0]  PLLclkod;
+  logic [11:0] PLLbwadj;
+  logic        PLLtest;
+  logic        PLLfasten;
+  logic        PLLlock;
+  logic        PLLconfigdone;
 
   logic        HREADY;
   logic        HSELEXT;
   logic        HSELEXTSDC;
-  
-  
+
+
   // instantiate device to be tested
+  assign tck = 0;
+  assign tdi = 0;
+  assign tms = 0;
+
   assign GPIOIN = 0;
   assign UARTSin = 1;
 
-    assign HREADYEXT = 1;
-    assign HRESPEXT = 0;
-    assign HRDATAEXT = 0;
+  assign HREADYEXT = 1;
+  assign HRESPEXT = 0;
+  assign HRDATAEXT = 0;
 
+  assign ui_clk = 0;
+  assign PLLrefclk = 0;
+  assign PLLrfen = 0;
+  assign PLLfben = 0;
+  assign PLLlock = 1;
 
-  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HSELEXTSDC,
-                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
-                        .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
-                        .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SDCIntr); 
+  wallypipelinedsoc #(P) dut(
+    .clk, .reset_ext, .reset, .tck, .tdi, .tms, .tdo, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT,
+    .HSELEXTSDC, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
+    .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SDCIntr,
+    .ui_clk, .dmc_trefi, .dmc_tmrd, .dmc_trfc, .dmc_trc, .dmc_trp, .dmc_tras, .dmc_trrd,
+    .dmc_trcd, .dmc_twr, .dmc_twtr, .dmc_trtp, .dmc_tcas, .dmc_col_width, .dmc_row_width,
+    .dmc_bank_width, .dmc_bank_pos, .dmc_dqs_sel_cal, .dmc_init_cycles, .dmc_config_changed,
+    .PLLrefclk, .PLLrfen, .PLLfben, .PLLclkr, .PLLclkf, .PLLclkod, .PLLbwadj,
+    .PLLtest, .PLLfasten, .PLLlock, .PLLconfigdone
+  );
 
 endmodule
diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S
index 3fe499abd..aa3cc438f 100644
--- a/tests/coverage/csrwrites.S
+++ b/tests/coverage/csrwrites.S
@@ -38,8 +38,8 @@ main:
     csrrw t1, menvcfg, t0
     csrrw t2, senvcfg, t0
 
-    # testing FIOM with different privelege modes
-    # setting environment config (to both 1 and 0) in each privelege mode
+    # testing FIOM with different privilege modes
+    # setting environment config (to both 1 and 0) in each privilege mode
     csrsi menvcfg, 1
     li a0, 1
     ecall               # enter supervisor mode
diff --git a/tests/custom/lpddrtest/Makefile b/tests/custom/lpddrtest/Makefile
index 71710fcb5..0280a08cd 100644
--- a/tests/custom/lpddrtest/Makefile
+++ b/tests/custom/lpddrtest/Makefile
@@ -1,8 +1,8 @@
 TARGETDIR	:= lpddr_test
 TARGET		:= $(TARGETDIR)/$(TARGETDIR).elf
 ROOT		:= ..
-LIBRARY_DIRS	:= ${ROOT}/crt0
-LIBRARY_FILES	:= crt0
+LIBRARY_DIRS	:= ${ROOT}/crt0 ${ROOT}/../../soc/fsbl
+LIBRARY_FILES	:= crt0 fsbl
 
 MARCH           :=-march=rv64imfdczicbom
 MABI            :=-mabi=lp64d
@@ -10,10 +10,8 @@ LINKER          := ${ROOT}/linker8000-0000.x
 LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
 
 CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany  -mstrict-align -O2
+AS=riscv64-unknown-elf-as
 CC=riscv64-unknown-elf-gcc
 DA=riscv64-unknown-elf-objdump -d
 
-
 include $(ROOT)/makefile.inc
-
-
diff --git a/tests/custom/lpddrtest/header.h b/tests/custom/lpddrtest/header.h
index 7e83cb22d..b4b8d962b 100644
--- a/tests/custom/lpddrtest/header.h
+++ b/tests/custom/lpddrtest/header.h
@@ -1,5 +1,7 @@
 #ifndef __header
 #define __header
 
+void config_pll();
+void config_bsg_dmc();
 void lpddr_test();
 #endif
diff --git a/tests/custom/lpddrtest/lpddr_test.s b/tests/custom/lpddrtest/lpddr_test.s
index a77d9081f..e6eb08fc1 100644
--- a/tests/custom/lpddrtest/lpddr_test.s
+++ b/tests/custom/lpddrtest/lpddr_test.s
@@ -1,29 +1,30 @@
 .section .text
 .globl lpddr_test
 .type lpddr_test, @function
-lpddr_test:
-	li t1, 0x90000000
-        addi t5, t1, 0
-	li t2, 0xAABBCCDD00112233
 
+lpddr_test:        
+        li t1, 0x90000000
+        addi t5, t1, 0
+        li t2, 0x0ABCDEF012345678
         li t3, 10
         li t4, 0
-loop_write:     
+loop_write:
         beq t4, t3, done_write
         sd t2, 0(t5)
         addi t5, t5, 8
         addi t4, t4, 1
         j loop_write
-done_write:   
-	
+done_write:
         li t4, 0
         addi t5, t1, 0
-loop_read:     
+loop_read:
         beq t4, t3, done_read
         ld t6, 0(t5)
         addi t5, t5, 8
         addi t4, t4, 1
         j loop_read
-done_read:      
-	ret
-	
+done_read:
+        bne t6, t2, lpddr_test
+tohost:
+        la t0, tohost
+        sw t2, 0(t0)
diff --git a/tests/custom/lpddrtest/main.c b/tests/custom/lpddrtest/main.c
index feafa5f75..0b3bed91b 100644
--- a/tests/custom/lpddrtest/main.c
+++ b/tests/custom/lpddrtest/main.c
@@ -1,6 +1,8 @@
 #include "header.h"
 
 int main(){
+  config_pll();
+  config_bsg_dmc();
   lpddr_test();  
   return 0;
 }
diff --git a/tests/debug/simple/Makefile b/tests/debug/simple/Makefile
new file mode 100644
index 000000000..a59d66698
--- /dev/null
+++ b/tests/debug/simple/Makefile
@@ -0,0 +1,14 @@
+TARGET = simple
+
+$(TARGET).objdump: $(TARGET)
+	riscv64-unknown-elf-objdump -S -D $(TARGET).elf > $(TARGET).objdump
+
+    
+$(TARGET): $(TARGET).c Makefile
+	riscv64-unknown-elf-gcc -o $(TARGET).elf -g\
+	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
+	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
+	  -Ttest.ld $(TARGET).c 
+
+clean:
+	rm -f $(TARGET).elf $(TARGET).objdump
diff --git a/tests/debug/simple/make.bak b/tests/debug/simple/make.bak
new file mode 100644
index 000000000..be8214e5e
--- /dev/null
+++ b/tests/debug/simple/make.bak
@@ -0,0 +1,15 @@
+TARGET = simple
+
+$(TARGET).objdump: $(TARGET)
+	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
+	spike $(TARGET)
+    
+$(TARGET): $(TARGET).c Makefile
+	riscv64-unknown-elf-gcc -o $(TARGET) -g\
+	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
+	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
+	  -T../../../examples/C/common/test.ld -I../../../examples/C/common/ \
+	  $(TARGET).c ../../../examples/C/common/crt.S ../../../examples/C/common/syscalls.c
+
+clean:
+	rm -f $(TARGET) $(TARGET).objdump
diff --git a/tests/debug/simple/openocd.cfg b/tests/debug/simple/openocd.cfg
new file mode 100644
index 000000000..40a9ed4e5
--- /dev/null
+++ b/tests/debug/simple/openocd.cfg
@@ -0,0 +1,37 @@
+# OpenOCD config file for Core V Wally
+# can find example material in /usr/share/openocd/scripts/
+
+adapter driver ftdi
+
+# when multiple adapters with the same vid_pid are connected (ex: arty-a7 and usb-jtag)
+# need to specify which usb port to drive
+# find numerical path using command "lsusb -t" (<bus>-<port>)
+adapter usb location 1-10.2
+
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 0
+
+#TODO: figure out which of these bits need to be set
+# data MSB..LSB       direction (1:out) MSB..LSB
+# 0000'0000'0011'0000 0000'0000'0011'1011
+ftdi layout_init 0x0030 0x003b
+#ftdi layout_init 0x0008 0x001b
+
+transport select jtag
+adapter speed 1000
+#ftdi tdo_sample_edge falling
+
+set _CHIPNAME cvw
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1002AC05
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x8000000 -work-area-size 0x4000 -work-area-backup 0
+
+# enable memory access error reports
+riscv set_enable_virt2phys off
+riscv set_enable_virtual off
+
+init
+halt
+
diff --git a/tests/debug/simple/simple.c b/tests/debug/simple/simple.c
new file mode 100644
index 000000000..8f734dca4
--- /dev/null
+++ b/tests/debug/simple/simple.c
@@ -0,0 +1,18 @@
+
+int main() {
+
+  // This is just random simple instructions
+  // to test the RISC-V debug gdb
+  asm("li a0, 0x1000");
+  asm("addi a1, a0, 0x100");
+  asm("addi a2, a1, 0x200");
+  asm("li a3, 0x4000000");
+  asm("sw a0, 0(a3)");
+  asm("sw a1, 4(a3)");
+  asm("lw a4, 0(a3)");
+  asm("lw a5, 4(a3)");
+  asm("lw a5, 4(a3)");
+  asm("nop");
+  while(1);
+
+}
diff --git a/tests/debug/simple/simple.elf b/tests/debug/simple/simple.elf
new file mode 100755
index 000000000..086b418db
Binary files /dev/null and b/tests/debug/simple/simple.elf differ
diff --git a/tests/debug/simple/test.ld b/tests/debug/simple/test.ld
new file mode 100644
index 000000000..3c7091084
--- /dev/null
+++ b/tests/debug/simple/test.ld
@@ -0,0 +1,25 @@
+
+OUTPUT_ARCH( "riscv" )
+
+ENTRY(main)
+
+/*----------------------------------------------------------------------*/
+/* Sections                                                             */
+/*----------------------------------------------------------------------*/
+
+MEMORY {
+
+       ram(wxa!ri): ORIGIN = 0x80000000, LENGTH = 0x4000
+
+}
+
+SECTIONS {
+
+	 .text :
+	 {
+	 	 *(.text*)
+	 }
+	 > ram
+	   . = ALIGN(4);
+
+}
diff --git a/testbench/fp/case.sh b/tests/fp/case.sh
similarity index 100%
rename from testbench/fp/case.sh
rename to tests/fp/case.sh
diff --git a/tests/fp/combined_IF_vectors/extract_arch_vectors.py b/tests/fp/combined_IF_vectors/extract_arch_vectors.py
index e25a2c83e..d0fd3ab9c 100755
--- a/tests/fp/combined_IF_vectors/extract_arch_vectors.py
+++ b/tests/fp/combined_IF_vectors/extract_arch_vectors.py
@@ -194,7 +194,7 @@ def create_vectors(my_config):
                 # get answer from Ref...signature
                 # answers span two lines and are reversed
                 answer = src_file2.readline().strip()
-                print(f"Answer: {answer}")
+                # print(f"Answer: {answer}")
                 #print(answer1,answer2)
                 if not (answer == "6f5ca309"): # if there is still stuff to read
                     # parse through .S file
@@ -239,9 +239,9 @@ def create_vectors(my_config):
             while reading:
                 # get answer and flags from Ref...signature
                 answer = src_file2.readline()
-                print(answer)
+                #print(answer)
                 packed = src_file2.readline()[6:]
-                print("Packed: ", packed)
+                #print("Packed: ", packed)
                 if len(packed.strip())>0: # if there is still stuff to read
                     # print("packed")
                     # parse through .S file
diff --git a/tests/fp/quad/fp_dataset.py b/tests/fp/quad/fp_dataset.py
new file mode 100755
index 000000000..d095d58f7
--- /dev/null
+++ b/tests/fp/quad/fp_dataset.py
@@ -0,0 +1,4966 @@
+from riscv_isac.log import logger
+import itertools
+import struct
+import random
+import sys
+import math
+from decimal import *
+import os
+sys.set_int_max_str_digits(10000)
+
+fzero       = ['0x00000000', '0x80000000']
+fminsubnorm = ['0x00000001', '0x80000001']
+fsubnorm    = ['0x00000002', '0x80000002', '0x007FFFFE', '0x807FFFFE', '0x00555555', '0x80555555']
+fmaxsubnorm = ['0x007FFFFF', '0x807FFFFF']
+fminnorm    = ['0x00800000', '0x80800000']
+fnorm       = ['0x00800001', '0x80800001', '0x00855555', '0x80855555', '0x008AAAAA', '0x808AAAAA', '0x55000000', '0xD5000000', '0x2A000000', '0xAA000000']# ***single,double and quad don't match
+fmaxnorm    = ['0x7F7FFFFF', '0xFF7FFFFF']
+finfinity   = ['0x7F800000', '0xFF800000']
+fdefaultnan = ['0x7FC00000', '0xFFC00000']
+fqnan       = ['0x7FC00001', '0xFFC00001', '0x7FC55555', '0xFFC55555']
+fsnan       = ['0x7F800001', '0xFF800001', '0x7FAAAAAA', '0xFFAAAAAA']
+fone        = ['0x3F800000', '0xBF800000']
+
+dzero       = ['0x0000000000000000', '0x8000000000000000']
+dminsubnorm = ['0x0000000000000001', '0x8000000000000001']
+dsubnorm    = ['0x0000000000000002', '0x8000000000000002','0x0008000000000000', '0x0008000000000002', '0x0001000000000000', '0x8001000000000000','0x8001000000000003','0x8001000000000007'] # ***missing 2nd largest and walking subnorms
+dmaxsubnorm = ['0x000FFFFFFFFFFFFF', '0x800FFFFFFFFFFFFF']
+dminnorm    = ['0x0010000000000000', '0x8010000000000000']
+dnorm       = ['0x0010000000000002', '0x8010000000000002', '0x0011000000000000', '0x8011000000000000', '0x0018000000000000', '0x8018000000000000','0x8018000000000005','0x8018000000000007']
+dmaxnorm    = ['0x7FEFFFFFFFFFFFFF', '0xFFEFFFFFFFFFFFFF']
+dinfinity   = ['0x7FF0000000000000', '0xFFF0000000000000']
+ddefaultnan = ['0x7FF8000000000000', '0xFFF8000000000000']
+dqnan       = ['0x7FF8000000000001', '0xFFF8000000000001', '0x7FFC000000000001', '0xFFFC000000000001']
+dsnan       = ['0x7FF0000000000001', '0xFFF0000000000001', '0x7FF4AAAAAAAAAAAA', '0xFFF4AAAAAAAAAAAA']
+done        = ['0x3FF0000000000000', '0xBF80000000000000']
+
+qzero       = ['0x00000000000000000000000000000000', '0x80000000000000000000000000000000']
+qminsubnorm = ['0x00000000000000000000000000000001', '0x80000000000000000000000000000001']
+qsubnorm    = ['0x00000000000000000000000000000002','0x80000000000000000000000000000002','0x0000FFFFFFFFFFFFFFFFFFFFFFFFFFFE','0x8000FFFFFFFFFFFFFFFFFFFFFFFFFFFE','0x00008000000000000000000000000000', '0x00008000000000000000000000000002', '0x00001000000000000000000000000000', '0x80001000000000000000000000000000','0x80001000000000000000000000000003','0x80001000000000000000000000000007']
+qmaxsubnorm = ['0x0000FFFFFFFFFFFFFFFFFFFFFFFFFFFF', '0x8000FFFFFFFFFFFFFFFFFFFFFFFFFFFF']
+qminnorm    = ['0x00010000000000000000000000000000', '0x80010000000000000000000000000000']
+qnorm       = ['0x00010000000000000000000000000002', '0x80010000000000000000000000000002','0x00011000000000000000000000000000', '0x80011000000000000000000000000000', '0x00018000000000000000000000000000', '0x80018000000000000000000000000000','0x80018000000000000000000000000005','0x80018000000000000000000000000007']
+qmaxnorm    = ['0x7FFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF', '0xFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFF']
+qinfinity   = ['0x7FFF0000000000000000000000000000', '0xFFFF0000000000000000000000000000']
+qdefaultnan = ['0x7FFF8000000000000000000000000000', '0xFFFF8000000000000000000000000000']
+qqnan       = ['0x7FFF8000000000000000000000000001', '0xFFFF8000000000000000000000000001']
+qsnan       = ['0x7FFF0000000000000000000000000001', '0xFFFF0000000000000000000000000001', '0x7FFF4AAAAAAAAAAAAAAAAAAAAAAAAAA', '0xFFFF4AAAAAAAAAAAAAAAAAAAAAAAAAAA']
+qone        = ['0x3FFF0000000000000000000000000000', '0xBFFF0000000000000000000000000000']
+
+rounding_modes = ['0','1','2','3','4']
+
+sanitise_cvpt = lambda rm,x,iflen,flen,c: x + ' fcsr == '+hex(rm<<5) + ' and rm_val == 7 ' \
+                + ('' if iflen == flen else ''.join([' and rs'+str(x)+'_nan_prefix == 0x' \
+                + 'f'*int((flen-iflen)/4) for x in range(1,c+1)]))
+
+sanitise_norm = lambda rm,x,iflen,flen,c: x + ' fcsr == 0'\
+                + ('' if iflen == flen else ''.join([' and rs'+str(x)+'_nan_prefix == 0x' \
+                + 'f'*int((flen-iflen)/4) for x in range(1,c+1)]))
+
+sanitise_norm_nopref = lambda rm,x,iflen,flen,c: x + ' fcsr == 0'
+sanitise_nopref = lambda rm,x,iflen,flen,c: x + ' fcsr == 0 and rm_val == 7'
+
+get_sanitise_func = lambda opcode: sanitise_norm if any([x in opcode for x in \
+        ['fsgnj','fle','flt','feq','fclass','flw','fsw','fld','fsd','flq','fsq','fmin','fmax']]) else \
+        (sanitise_norm_nopref if 'fmv' in opcode else ( sanitise_nopref if any([opcode.endswith(x) \
+        for x in ['.l','.w','.lu','.wu']]) else sanitise_cvpt))
+
+def num_explain(flen,num):
+    num_dict = {
+        tuple(fzero)         : 'fzero',
+        tuple(fminsubnorm)     : 'fminsubnorm',
+        tuple(fsubnorm)     : 'fsubnorm',
+        tuple(fmaxsubnorm)     : 'fmaxsubnorm',
+        tuple(fminnorm)     : 'fminnorm',
+        tuple(fnorm)         : 'fnorm',
+        tuple(fmaxnorm)     : 'fmaxnorm',
+        tuple(finfinity)     : 'finfinity',
+        tuple(fdefaultnan)     : 'fdefaultnan',
+        tuple(fqnan)         : 'fqnan',
+        tuple(fsnan)         : 'fsnan',
+        tuple(fone)         : 'fone',
+        tuple(dzero)         : 'dzero',
+        tuple(dminsubnorm)     : 'dminsubnorm',
+        tuple(dsubnorm)     : 'dsubnorm',
+        tuple(dmaxsubnorm)     : 'dmaxsubnorm',
+        tuple(dminnorm)     : 'dminnorm',
+        tuple(dnorm)         : 'dnorm',
+        tuple(dmaxnorm)     : 'dmaxnorm',
+        tuple(dinfinity)     : 'dinfinity',
+        tuple(ddefaultnan)     : 'ddefaultnan',
+        tuple(dqnan)         : 'dqnan',
+        tuple(dsnan)         : 'dsnan',
+        tuple(done)         : 'done',
+        tuple(qzero)         : 'qzero',
+        tuple(qminsubnorm)     : 'qminsubnorm',
+        tuple(qsubnorm)     : 'qsubnorm',
+        tuple(qmaxsubnorm)     : 'qmaxsubnorm',
+        tuple(qminnorm)     : 'qminnorm',
+        tuple(qnorm)         : 'qnorm',
+        tuple(qmaxnorm)     : 'qmaxnorm',
+        tuple(qinfinity)     : 'qinfinity',
+        tuple(qdefaultnan)     : 'qdefaultnan',
+        tuple(qqnan)         : 'qqnan',
+        tuple(qsnan)         : 'qsnan',
+        tuple(qone)         : 'qone'
+    }
+    num_list = list(num_dict.items())
+    for i in range(len(num_list)):
+        if(('0x'+num[2:].upper()) in num_list[i][0]):
+            return(num_list[i][1])
+
+    if flen == 32:
+        e_sz = 8
+        m_sz = 23
+    elif flen == 64:
+        e_sz = 11
+        m_sz = 52
+    elif flen == 128:
+        e_sz = 15
+        m_sz = 112
+
+    bin_val = bin(int('1'+num[2:],16))[3:]
+    sgn = bin_val[0]
+    exp = bin_val[1:e_sz+1]
+    man = bin_val[e_sz+1:]
+
+    if(int(exp,2)!=0):
+        return('fnorm' if flen==32 else 'dnorm' if flen == 64 else 'qnorm')
+    else:
+        return('fsubnorm' if flen==32 else 'dsubnorm' if flen == 64 else 'qsubnorm')
+
+def extract_fields(flen, hexstr, postfix):
+    if flen == 32:
+        e_sz = 8
+        m_sz = 23
+    elif flen == 64:
+        e_sz = 11
+        m_sz = 52
+    elif flen == 128:
+        e_sz = 15
+        m_sz = 112
+    bin_val = bin(int('1'+hexstr[2:],16))[3:]
+    sgn = bin_val[0]
+    exp = bin_val[1:e_sz+1]
+    man = bin_val[e_sz+1:]
+    if flen == 32:
+        string = 'fs'+postfix+' == '+str(sgn) +\
+                 ' and fe'+postfix+' == '+'0x'+str(hex(int('1'+exp,2))[3:]) +\
+                 ' and fm'+postfix+' == '+'0x'+str(hex(int('10'+man,2))[3:])
+    elif flen == 64:
+        string = 'fs'+postfix+' == '+str(sgn) +\
+                 ' and fe'+postfix+' == '+'0x'+str(hex(int('10'+exp,2))[3:]) +\
+                 ' and fm'+postfix+' == '+'0x'+str(hex(int('1'+man,2))[3:])
+    elif flen == 128: 
+        string = 'fs' + postfix + ' == ' + str(sgn) + \
+                 ' and fe' + postfix + ' == ' + '0x' + str(hex(int('10' + exp, 2))[3:]) + \
+                 ' and fm' + postfix + ' == ' + '0x' + str(hex(int('1' + man, 2))[3:])
+
+    return string
+
+def fields_dec_converter(flen, hexstr):                            # IEEE-754 Hex -> Decimal Converter
+
+    if flen == 32:
+        e_sz = 8
+        m_sz = 23
+    elif flen == 64:
+        e_sz = 11
+        m_sz = 52
+    elif flen == 128:
+        e_sz = 15
+        m_sz = 112
+    bin_val = bin(int('1'+hexstr[2:],16))[3:]
+    sgn = bin_val[0]
+    exp = bin_val[1:e_sz+1]
+    man = bin_val[e_sz+1:]
+
+    num=''
+    if(int(sgn)==1):
+        sign = '-'
+    elif(int(sgn)==0):
+        sign = '+'
+
+    exp_str = '*pow(2,'
+
+    if(flen == 32):
+        if((int(exp,2)-127)<-126):
+            conv_num = 0.0
+            exp_str+= str(-126)+')'
+        elif((int(exp,2)-127)>=-126):
+            conv_num = 1.0
+            exp_str+= str(int(exp,2)-127)+')'
+    elif(flen == 64):
+        if((int(exp,2)-1023)<-1022):
+            conv_num = 0.0
+            exp_str+= str(-1022)+')'
+        elif((int(exp,2)-1023)>=-1022):
+            conv_num = 1.0
+            exp_str+= str(int(exp,2)-1023)+')'
+    elif flen == 128: 
+        #print(int(exp,2))
+        if (int(exp, 2) - 16383) < -16382:
+            conv_num = 0.0
+            exp_str += str(-16382) + ')'
+        elif (int(exp, 2) - 16383) >= -16382:
+            conv_num = 1.0
+            exp_str += str(int(exp, 2)-16383) + ')'
+    for i in range(len(man)):
+        conv_num+= (1/(pow(2,i+1)))*int(man[i])
+
+    num = sign + str(conv_num) + exp_str
+    if(flen == 32):
+        if(eval(num) > 1e-45 or eval(num)<-1e-45):
+            return(eval(num))
+        else:
+            return(eval(sign+'1e-45'))
+    elif(flen == 64):
+        #print(num)
+        return eval(num)
+    elif(flen == 128):
+        #print(num)
+        return eval(num)
+
+def floatingPoint_tohex(flen,float_no):                            # Decimal -> IEEE-754 Hex Converter
+
+    if(flen==32):
+        if(str(float_no)=='-inf'):
+            return(finfinity[1])
+        elif(str(float_no)=='inf'):
+            return(finfinity[0])
+    elif(flen==64):
+        if(str(float_no)=='-inf'):
+            return(dinfinity[1])
+        elif(str(float_no)=='inf'):
+            return(dinfinity[0])
+    elif(flen==128):
+        if(str(float_no)=='-inf'):
+            return(qinfinity[1])
+        elif(str(float_no)=='inf'):
+            return(qinfinity[0])
+
+    float_no=float.hex(float_no)
+    num="N"
+
+    a=float.fromhex(float_no)
+
+    sign=0
+    if(a<0 or str(a)[0]=='-'):
+        sign=1
+    nor=float.hex(a)                                    # Normalized Number
+
+    if(flen==32):
+        if(int(nor.split("p")[1])<-126):                        # Checking Underflow of Exponent
+            exp_bin=('0'*8)                            # Exponent of Subnormal numbers
+            exp_sn=int(nor.split("p")[1])
+            num="SN"
+        elif(int(nor.split("p")[1])>127):                        # Checking Overflow of Exponent
+            if(sign==0):
+                return "0x7f7fffff"                        # Most Positive Value
+            else:
+                return "0xff7fffff"                        # Most Negative Value
+        else:                                        # Converting Exponent to 8-Bit Binary
+            exp=int(nor.split("p")[1])+127
+            exp_bin=('0'*(8-(len(bin(exp))-2)))+bin(exp)[2:]
+    elif(flen==64):
+        check_sn = nor.split("p")[0].split(".")[0]
+        if(int(check_sn[len(check_sn)-1])==0):                    # Checking Underflow of Exponent
+            exp_bin=('0'*11)                            # Exponent of Subnormal numbers
+            exp_sn=int(nor.split("p")[1])
+            num="SN"
+        elif(int(nor.split("p")[1])>1023):                        # Checking Overflow of Exponent
+            if(sign==0):
+                return "0x7FEFFFFFFFFFFFFF"                    # Most Positive Value
+            else:
+                return "0xFFEFFFFFFFFFFFFF"                    # Most Negative Value
+        else:                                        # Converting Exponent to 8-Bit Binary
+            exp=int(nor.split("p")[1])+1023
+            exp_bin=('0'*(11-(len(bin(exp))-2)))+bin(exp)[2:]
+    elif(flen==128):
+        check_sn = nor.split("p")[0].split(".")[0]
+        if(int(check_sn[len(check_sn)-1])==0):                    # Checking Underflow of Exponent
+            exp_bin=('0'*15)                            # Exponent of Subnormal numbers
+            exp_sn=int(nor.split("p")[1])
+            num="SN"
+        elif(int(nor.split("p")[1])>16383):                        # Checking Overflow of Exponent
+            if(sign==0):
+                return "0x7FFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF"                    # Most Positive Value
+            else:
+                return "0xFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFF"                    # Most Negative Value
+        else:                                        # Converting Exponent to 8-Bit Binary
+            exp=int(nor.split("p")[1])+16383
+            exp_bin=('0'*(15-(len(bin(exp))-2)))+bin(exp)[2:]
+
+    if(num=="SN"):
+        if(sign==0):
+            mant="0x"+float_no.split("p")[0][4:]
+        else:
+            mant="0x"+float_no.split("p")[0][5:]
+    else:
+        if(sign==0):
+            mant="0x"+nor.split("p")[0][4:]
+        else:
+            mant="0x"+nor.split("p")[0][5:]
+
+    if(flen==32):
+        mant_bin=bin(int('1'+mant[2:],16))[3:]
+        if(num == "SN"):
+            mant_bin='1'+bin(int('1'+mant[2:],16))[3:]
+            while(exp_sn!=-127):
+                exp_sn+=1
+                mant_bin = '0'+mant_bin
+        binary="0b"
+        binary=binary+str(sign)+exp_bin+mant_bin[0:23]
+        hex_tp=hex(int(binary,2))
+        hex_tp=hex_tp.replace('0x','0x'+'0'*(8-(len(hex_tp)-2)))
+    elif(flen==64):
+        mant_bin=bin(int('1'+mant[2:],16))[3:]
+        if(num == "SN"):
+            mant_bin=bin(int('1'+mant[2:],16))[3:]
+        binary="0b"
+        binary=binary+str(sign)+exp_bin+mant_bin[0:52]
+        hex_tp=hex(int(binary,2))
+        hex_tp=hex_tp.replace('0x','0x'+'0'*(16-(len(hex_tp)-2)))
+    elif(flen==128):
+        mant_bin=bin(int('1'+mant[2:],16))[3:]
+        if(num == "SN"):
+            mant_bin=bin(int('1'+mant[2:],16))[3:]
+        binary="0b"
+        binary=binary+str(sign)+exp_bin+mant_bin[0:111]
+        hex_tp=hex(int(binary,2))
+        hex_tp=hex_tp.replace('0x','0x'+'0'*(32-(len(hex_tp)-2)))
+
+    return(hex_tp)
+
+def unique_cpts(x):
+    d = {}
+    for i in range(len(x)):                            # Returning a List Of Unique Coverpoints
+        if(d.get(x[i],"None") == "None"):
+            d[x[i]] = 1
+        else:
+            d[x[i]]+=1
+    return(list(d.keys()))
+
+def comments_parser(coverpoints):
+    cvpts = []
+    for coverpoint in coverpoints:
+        cvpt = coverpoint.split("#")[0]
+        comment = coverpoint.split("#")[1]
+        cvpts.append((cvpt+ " #nosat",comment))
+    return cvpts
+
+def softfloat_sub(a, b):
+    cmd = "$WALLY/examples/fp/fpcalc/fpcalc " + a + " - " + b
+    result = os.system(cmd)
+    print("cmd = ", cmd, "returns result = ", result)
+    return result
+
+# rs1, rs3, result are hexadecimal strings
+def gen_rs2(iflen,opcode,rs1,rs3,result):
+    if opcode in 'fadd':
+        rs2 = softfloat_sub(result, rs1)
+    elif opcode in 'fsub':
+        rs2 = rs1 - fields_dec_converter(iflen,result[i][0])
+    elif opcode in 'fmul':
+        rs2 = fields_dec_converter(iflen,result[i][0])/rs1
+    elif opcode in 'fdiv':
+        if fields_dec_converter(iflen,result[i][0]) != 0:
+            rs2 = rs1/fields_dec_converter(iflen,result[i][0])
+    elif opcode in 'fsqrt':
+        rs2 = fields_dec_converter(iflen,result[i][0])*fields_dec_converter(iflen,result[i][0])
+    elif opcode in 'fmadd':
+        rs2 = (fields_dec_converter(iflen,result[i][0]) - rs3)/rs1
+    elif opcode in 'fnmadd':
+        rs2 = (rs3 - fields_dec_converter(iflen,result[i][0]))/rs1
+    elif opcode in 'fmsub':
+        rs2 = (fields_dec_converter(iflen,result[i][0]) + rs3)/rs1
+    elif opcode in 'fnmsub':
+        rs2 = -1*(rs3 + fields_dec_converter(iflen,result[i][0]))/rs1
+    return rs2
+
+def ibm_b1(flen, iflen, opcode, ops):
+    '''
+    IBM Model B1 Definition:
+        Test all combinations of floating-point basic types, positive and negative, for
+        each of the inputs. The basic types are Zero, One, MinSubNorm, SubNorm,
+        MaxSubNorm, MinNorm, Norm, MaxNorm, Infinity, DefaultNaN, QNaN, and
+        SNaN.
+
+    :param iflen: Size of the floating point source operands for the instruction
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+
+    Abstract Dataset Description:
+        Operands =>
+        [Zero, One, MinSubNorm, SubNorm, MaxSubNorm, MinNorm, Norm, MaxNorm, Infinity, DefaultNaN, QNaN, SNaN]
+
+    Implementation:
+        - Dependent on the value of iflen, a predefined dataset of floating point values are added.
+        - Using the itertools package, an iterative multiplication is performed with two lists to create an exhaustive combination of all the operand values.
+        - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+        - Coverpoints are then appended with the respective rounding mode for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    if iflen == 32:
+        basic_types = fzero + fminsubnorm + [fsubnorm[0], fsubnorm[3]] +\
+            fmaxsubnorm + fminnorm + [fnorm[0], fnorm[3]] + fmaxnorm + \
+            finfinity + fdefaultnan + [fqnan[0], fqnan[3]] + \
+            [fsnan[0], fsnan[3]] + fone
+    elif iflen == 64:
+        basic_types = dzero + dminsubnorm + [dsubnorm[0], dsubnorm[1]] +\
+            dmaxsubnorm + dminnorm + [dnorm[0], dnorm[1]] + dmaxnorm + \
+            dinfinity + ddefaultnan + [dqnan[0], dqnan[1]] + \
+            [dsnan[0], dsnan[1]] + done
+    elif iflen == 128:
+        basic_types = qzero + qminsubnorm + [qsubnorm[0], qsubnorm[1]] + \
+                      qmaxsubnorm + qminnorm + [qnorm[0], qnorm[1]] + qmaxnorm + \
+                      qinfinity + qdefaultnan + [qqnan[0], qqnan[1]] + \
+                      [qsnan[0], qsnan[1]] + qone
+    else:
+        logger.error('Invalid iflen value!')
+        sys.exit(1)
+
+    # the following creates a cross product for ops number of variables
+    b1_comb = list(itertools.product(*ops*[basic_types]))
+    coverpoints = []
+    for c in b1_comb:
+        cvpt = ""
+        for x in range(1, ops+1):
+#            cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x))) + " and "
+        if opcode.split('.')[0] in ["fadd","fsub","fmul","fdiv","fsqrt","fmadd","fnmadd","fmsub","fnmsub","fcvt","fmv"]:
+            cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        elif opcode.split('.')[0] in \
+            ["fclass","flt","fmax","fsgnjn","fmin","fsgnj","feq","flw","fsw","fsgnjx","fld","fle","fsd","flq","fsq"]: #***missing fsd and flq,fsq
+            cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        else:
+            return "Invalid Opcode"
+
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        coverpoints.append(cvpt)
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64) if iflen == 64 else str(128)) + '-bit coverpoints using Model B1 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+    return coverpoints
+
+def ibm_b2(flen, iflen, opcode, ops, int_val = 100, seed = -1): #***Quad support isn't possible due to python limitations, come back later : fpcalc/quadmath/lookuptable
+    '''
+    IBM Model B2 Definition:
+            This model tests final results that are very close, measured in Hamming
+            distance, to the specified boundary values. Each boundary value is taken as a
+            base value, and the model enumerates over small deviations from the base, by
+            flipping one bit of the significand.
+
+
+    :param iflen: Size of the floating point source operands
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param int_val: Number to define the range in which the random value is to be generated.  (Predefined to 100)
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :type int_val: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Final Results = [Zero, One, MinSubNorm, MaxSubNorm, MinNorm, MaxNorm]
+            Operand1 {operation} Operand2 = Final Results
+
+    Implementation:
+            - Hamming distance is calculated using an xor operation between a number in the dataset and a number generated using walking ones operation.
+            - A random operand value for one of the operands is assigned and based on the result and operation under consideration, the next operand is calculated.
+            - These operand values are treated as decimal numbers until their derivation after which they are converted into their respective IEEE754 hexadecimal floating point formats using the “floatingPoint_tohex” function.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with the respective rounding mode for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    if iflen == 32:
+        flip_types = fzero + fone + fminsubnorm + fmaxsubnorm + fminnorm + fmaxnorm
+        b = '0x00000010'
+        e_sz = 8
+        m_sz = 23
+    elif iflen == 64:
+        flip_types = dzero + done + dminsubnorm + dmaxsubnorm + dminnorm + dmaxnorm
+        b = '0x0000000000000010'
+        e_sz = 11
+        m_sz = 52
+    elif iflen == 128:
+        flip_types = qzero + qone + qminsubnorm + qmaxsubnorm + qminnorm + qmaxnorm
+        b = '0x00000000000000000000000000000010'
+        e_sz = 15
+        m_sz = 112
+
+    result = []
+    b2_comb = []
+    opcode = opcode.split('.')[0]
+
+    if seed == -1:
+        if opcode in 'fadd':
+            random.seed(0)
+        elif opcode in 'fsub':
+            random.seed(1)
+        elif opcode in 'fmul':
+            random.seed(2)
+        elif opcode in 'fdiv':
+            random.seed(3)
+        elif opcode in 'fsqrt':
+            random.seed(4)
+        elif opcode in 'fmadd':
+            random.seed(5)
+        elif opcode in 'fnmadd':
+            random.seed(6)
+        elif opcode in 'fmsub':
+            random.seed(7)
+        elif opcode in 'fnmsub':
+            random.seed(8)
+    else:
+        random.seed(seed)
+
+    for i in range(len(flip_types)):
+        k=1
+        for j in range (1,24):
+            #print('{:010b}'.format(k))
+            result.append(['0x'+hex(eval(bin(int('1'+flip_types[i][2:], 16))) ^ eval('0b'+'{:023b}'.format(k)))[3:],' | Result = '+num_explain(iflen, '0x'+str(hex(eval(bin(int('1'+flip_types[i][2:], 16))))[3:]))+'(0x'+str(hex(eval(bin(int('1'+flip_types[i][2:], 16))))[3:])+')^'+str('0x'+hex(eval('0b'+'1'+'{:024b}'.format(k)))[3:])])
+            k=k*2
+
+    for i in range(len(result)):
+        bin_val = bin(int('1'+result[i][0][2:],16))[3:]
+        rsgn = bin_val[0]
+        rexp = bin_val[1:e_sz+1]
+        rman = bin_val[e_sz+1:]
+        rs1_exp = rs3_exp = rexp
+        rs1_bin = bin(random.randrange(1,int_val))
+        print(rs1_bin)
+        rs3_bin = bin(random.randrange(1,int_val))
+        rs1_bin = ('0b0'+rexp+('0'*(m_sz-(len(rs1_bin)-2)))+rs1_bin[2:])
+        rs3_bin = ('0b0'+rexp+('0'*(m_sz-(len(rs3_bin)-2)))+rs3_bin[2:])
+        rs1 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs1_bin[2:],2))[3:])
+        #print(rs1)
+        rs3 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs3_bin[2:],2))[3:])
+        rs2 = gen_rs2(iflen,opcode,"3FFF8000000000000000000000000000","3FFF4000000000000000000000000000","3FFF8800000000000000000000000000")
+        # if opcode in 'fadd':
+        #     rs2 = fields_dec_converter(iflen,result[i][0]) - rs1
+        # elif opcode in 'fsub':
+        #     rs2 = rs1 - fields_dec_converter(iflen,result[i][0])
+        # elif opcode in 'fmul':
+        #     rs2 = fields_dec_converter(iflen,result[i][0])/rs1
+        # elif opcode in 'fdiv':
+        #     if fields_dec_converter(iflen,result[i][0]) != 0:
+        #         rs2 = rs1/fields_dec_converter(iflen,result[i][0])
+        # elif opcode in 'fsqrt':
+        #     rs2 = fields_dec_converter(iflen,result[i][0])*fields_dec_converter(iflen,result[i][0])
+        # elif opcode in 'fmadd':
+        #     rs2 = (fields_dec_converter(iflen,result[i][0]) - rs3)/rs1
+        # elif opcode in 'fnmadd':
+        #     rs2 = (rs3 - fields_dec_converter(iflen,result[i][0]))/rs1
+        # elif opcode in 'fmsub':
+        #     rs2 = (fields_dec_converter(iflen,result[i][0]) + rs3)/rs1
+        # elif opcode in 'fnmsub':
+        #     rs2 = -1*(rs3 + fields_dec_converter(iflen,result[i][0]))/rs1
+
+        if(iflen==32):
+            m = struct.unpack('f', struct.pack('f', rs2))[0]
+        elif(iflen==64):
+            m = rs2
+        elif(iflen==128):
+            m = rs2
+
+        if opcode in ['fadd','fsub','fmul','fdiv']:
+            b2_comb.append((floatingPoint_tohex(iflen,rs1),floatingPoint_tohex(iflen,m)))
+        elif opcode in 'fsqrt':
+            b2_comb.append((floatingPoint_tohex(iflen,m),))
+        elif opcode in ['fmadd','fnmadd','fmsub','fnmsub']:
+            b2_comb.append((floatingPoint_tohex(iflen,rs1),floatingPoint_tohex(iflen,m),floatingPoint_tohex(iflen,rs3)))
+    #print("b2_comb",b2_comb)
+    coverpoints = []
+    k=0
+    for c in b2_comb:
+        cvpt = ""
+        for x in range(1, ops+1):
+#            cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += result[k][1]
+        coverpoints.append(cvpt)
+        k=k+1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64) if iflen == 64 else str(128)) + '-bit coverpoints using Model B2 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+    #print(rs1)
+    #return coverpoints
+
+def ibm_b3(flen,iflen, opcode, ops, seed=-1):
+    '''
+    IBM Model B3 Definition:
+            This model tests all combinations of the sign, significand’s LSB, guard bit & sticky bit of the intermediate result.
+
+    :param iflen: Size of the floating source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Intermediate Result is chosen at random
+            Intermediate Result = [All possible combinations of Sign, LSB, Guard and Sticky are taken]
+            Operand1 {operation} Operand2 = Intermediate Results
+
+    Implementation:
+            - The Sticky bit is 1 if there were non-zero digits to the right of the guard digit, hence the lsb list is subjected to that condition.
+            - Float_val [ a list of numbers ] extracted from the fields_dec_converter is checked for the LSB. If it is a negative number, then the list ieee754_num is appended with splitting the p character and first 10 characters in the 0th split + ‘p’ + other part of the split. “p” specifies the maximum available number in python and used in 64 bit architecture. If we require a digit more than thea number, then we represent it using a string because an int
+            - Now the ir_dataset is initialized and since the ieee754_num list has the same element twice [ first is just the number and second is with sign ], hence we loop that array, considering only multiples of 2 elements from it. If the sign is ‘-’, then then the index is updated with 1 else if it is ‘+’, then it is updated with 0 complying with the IEEE standards.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    opcode = opcode.split('.')[0]
+    getcontext().prec = 40
+
+    if seed == -1:
+        if opcode in 'fadd':
+            random.seed(0)
+        elif opcode in 'fsub':
+            random.seed(1)
+        elif opcode in 'fmul':
+            random.seed(2)
+        elif opcode in 'fdiv':
+            random.seed(3)
+        elif opcode in 'fsqrt':
+            random.seed(4)
+        elif opcode in 'fmadd':
+            random.seed(5)
+        elif opcode in 'fnmadd':
+            random.seed(6)
+        elif opcode in 'fmsub':
+            random.seed(7)
+        elif opcode in 'fnmsub':
+            random.seed(8)
+    else:
+        random.seed(seed)
+
+    if iflen == 32:
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_num = []
+        lsb = []
+        for i in fsubnorm+fnorm:
+            if int(i[-1],16)%2 == 1:
+                lsb.append('1')
+                lsb.append('1')
+            else:
+                lsb.append('0')
+                lsb.append('0')
+            float_val = float.hex(fields_dec_converter(32,i))
+            if float_val[0] != '-':
+                ieee754_num.append(float_val.split('p')[0][0:10]+'p'+float_val.split('p')[1])
+                ieee754_num.append('-'+float_val.split('p')[0][0:10]+'p'+float_val.split('p')[1])
+            else:
+                ieee754_num.append(float_val.split('p')[0][0:11]+'p'+float_val.split('p')[1])
+                ieee754_num.append(float_val.split('p')[0][1:11]+'p'+float_val.split('p')[1])
+
+        ir_dataset = []
+        for k in range(len(ieee754_num)):
+            for i in range(2,16,2):
+                grs = '{:04b}'.format(i)
+                if ieee754_num[k][0] == '-': sign = '1'
+                else: sign = '0'
+                ir_dataset.append([ieee754_num[k].split('p')[0]+str(i)+'p'+ieee754_num[k].split('p')[1],' | Guard = '+grs[0]+' Sticky = '+grs[2]+' Sign = '+sign+' LSB = '+lsb[k]])
+
+        for i in range(len(ir_dataset)):
+            ir_dataset[i][0] = float.fromhex(ir_dataset[i][0])
+
+    elif iflen == 64:
+        maxdec = '1.7976931348623157e+308'
+        maxnum = float.fromhex('0x1.fffffffffffffp+1023')
+        ieee754_num = []
+        lsb = []
+        for i in dsubnorm+dnorm:
+            if int(i[-1],16)%2 == 1:
+                lsb.append('1')
+                lsb.append('1')
+            else:
+                lsb.append('0')
+                lsb.append('0')
+            float_val = str(fields_dec_converter(64,i))
+            if float_val[0] != '-':
+                ieee754_num.append(float_val)
+                ieee754_num.append('-'+float_val)
+            else:
+                ieee754_num.append(float_val)
+                ieee754_num.append(float_val[1:])
+
+        ir_dataset = []
+        for k in range(len(ieee754_num)):
+            for i in range(2,16,2):
+                grs = '{:04b}'.format(i)
+                if ieee754_num[k][0] == '-': sign = '1'
+                else: sign = '0'
+                ir_dataset.append([str(Decimal(ieee754_num[k].split('e')[0])+Decimal(pow(i*16,-14)))+'e'+ieee754_num[k].split('e')[1],' | Guard = '+grs[0]+' Sticky = '+grs[2]+' Sign = '+sign+' LSB = '+lsb[k]])
+    elif iflen == 128:
+        maxdec = '1.7976931348623157e+308' # not used in the program
+        ieee754_maxnorm_quad = '0x1.fffffffffffffffffffffffffffffp+16383'
+        significand = ieee754_maxnorm_quad.split('p')[0][2:]  # Remove the "0x" prefix
+        exponent = int(ieee754_maxnorm_quad.split('p')[1], 16)
+        int_part, frac_part = significand.split('.')
+        int_value = int(int_part, 16)
+        frac_value = Decimal(int(frac_part, 16)) / Decimal(16 ** len(frac_part))
+
+        # Combine the integer and fractional parts
+        decimal_significand = Decimal(int_value) + frac_value
+
+        # Construct the maximum quad precision value
+        maxnum = decimal_significand * Decimal(2) **Decimal(exponent)
+        ieee754_num = []
+        lsb = []
+        for i in qsubnorm+qnorm:
+            if int(i[-1],16)%2 == 1:
+                lsb.append('1')
+                lsb.append('1')
+            else:
+                lsb.append('0')
+                lsb.append('0')
+            float_val = str(fields_dec_converter(128,i))
+            if float_val[0] != '-':
+                ieee754_num.append(float_val)
+                ieee754_num.append('-'+float_val)
+            else:
+                ieee754_num.append(float_val)
+                ieee754_num.append(float_val[1:])
+
+        ir_dataset = []
+        for k in range(len(ieee754_num)):
+            for i in range(2, 16, 2):
+                grs = '{:04b}'.format(i)
+                if ieee754_num[k][0] == '-':
+                    sign = '1'
+                else:
+                    sign = '0'
+
+                # Check if the 'e' character exists in the string
+                if 'e' in ieee754_num[k]:
+                    significand = ieee754_num[k].split('e')[0]
+                    exponent = ieee754_num[k].split('e')[1]
+                    ir_value = str(Decimal(significand) + Decimal(pow(i * 16, -14))) + 'e' + exponent
+                else:
+                    # If 'e' is not present, assume the entire string represents the significand
+                    significand = ieee754_num[k]
+                    ir_value = str(Decimal(significand) + Decimal(pow(i * 16, -14)))
+
+                ir_dataset.append([ir_value, ' | Guard = ' + grs[0] + ' Sticky = ' + grs[2] + ' Sign = ' + sign + ' LSB = ' + lsb[k]])
+        
+    b4_comb = []
+
+    for i in range(len(ir_dataset)):
+        rs1 = Decimal(str(random.uniform(1, float(maxnum))))
+        rs3 = Decimal(str(random.uniform(1, float(maxnum))))
+        if opcode in 'fadd':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0] - rs1
+            elif iflen == 64 or iflen == 128:
+                rs2 = Decimal(ir_dataset[i][0]) - Decimal(rs1)
+        elif opcode in 'fsub':
+            if iflen == 32:
+                rs2 = rs1 - ir_dataset[i][0]
+            elif iflen == 64 or iflen == 128:
+                rs2 = Decimal(rs1) - Decimal(ir_dataset[i][0])
+        elif opcode in 'fmul':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]/rs1
+            elif iflen == 64 or iflen == 128:
+                rs2 = Decimal(ir_dataset[i][0])/Decimal(rs1)
+        elif opcode in 'fdiv':
+            if iflen == 32:
+                rs2 = rs1/ir_dataset[i][0]
+            elif iflen == 64 or iflen == 128:
+                rs2 = Decimal(rs1)/Decimal(ir_dataset[i][0])
+        elif opcode in 'fsqrt':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]*ir_dataset[i][0]
+            elif iflen == 64 or iflen == 128:
+                rs2 = Decimal(ir_dataset[i][0])*Decimal(ir_dataset[i][0])
+        elif opcode in 'fmadd':
+            if iflen == 32:
+                rs2 = (ir_dataset[i][0] - rs3)/rs1
+            elif iflen == 64 or iflen == 128:
+                rs2 = (Decimal(ir_dataset[i][0]) - Decimal(rs3))/Decimal(rs1)
+        elif opcode in 'fnmadd':
+            if iflen == 32:
+                rs2 = (rs3 - ir_dataset[i][0])/rs1
+            elif iflen == 64 or iflen == 128:
+                rs2 = (Decimal(rs3) - Decimal(ir_dataset[i][0]))/Decimal(rs1)
+        elif opcode in 'fmsub':
+            if iflen == 32:
+                rs2 = (ir_dataset[i][0] + rs3)/rs1
+            elif iflen == 64 or iflen == 128:
+                rs2 = (Decimal(ir_dataset[i][0]) + Decimal(rs3))/Decimal(rs1)
+        elif opcode in 'fnmsub':
+            if iflen == 32:
+                rs2 = -1*(rs3 + ir_dataset[i][0])/rs1
+            elif iflen == 64 or iflen == 128:
+                rs2 = -1*(Decimal(rs3) + Decimal(ir_dataset[i][0]))/Decimal(rs1)
+
+        if(iflen==32):
+            x1 = struct.unpack('f', struct.pack('f', rs1))[0]
+            x2 = struct.unpack('f', struct.pack('f', rs2))[0]
+            x3 = struct.unpack('f', struct.pack('f', rs3))[0]
+        elif(iflen==64):
+            x1 = rs1
+            x2 = rs2
+            x3 = rs3
+        elif(iflen==128):
+            x1 = rs1
+            x2 = rs2
+            x3 = rs3
+
+        if opcode in ['fadd','fsub','fmul','fdiv']:
+            b4_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2))))
+        elif opcode in 'fsqrt':
+            b4_comb.append((floatingPoint_tohex(iflen,float(rs2)),))
+        elif opcode in ['fmadd','fnmadd','fmsub','fnmsub']:
+            b4_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2)),floatingPoint_tohex(iflen,float(rs3))))
+
+    coverpoints = []
+    k = 0
+    for c in b4_comb:
+        for rm in range(5):
+            cvpt = ""
+            for x in range(1, ops+1):
+#                        cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+                cvpt += (extract_fields(iflen,c[x-1],str(x)))
+                cvpt += " and "
+            # cvpt += 'rm_val == '+str(rm)
+            cvpt = sanitise(rm,cvpt,iflen,flen,ops)
+            cvpt += ' # '
+            for y in range(1, ops+1):
+                cvpt += 'rs'+str(y)+'_val=='
+                cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+                if(y != ops):
+                    cvpt += " and "
+            cvpt += ir_dataset[k][1]
+            coverpoints.append(cvpt)
+        k=k+1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64) if iflen ==64 else str(128)) + '-bit coverpoints using Model B3 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b4(flen, iflen, opcode, ops, seed=-1): #***overflow , write individual computational functions to prevent overflow -- check for test-breaking
+    '''
+    IBM Model B4 Definition:
+            This model creates a test-case for each of the following constraints on the
+            intermediate results:
+
+            1. All the numbers in the range [+MaxNorm – 3 ulp, +MaxNorm + 3 ulp]
+            2. All the numbers in the range [-MaxNorm - 3 ulp, -MaxNorm + 3 ulp]
+            3. A random number that is larger than +MaxNorm + 3 ulp
+            4. A random number that is smaller than -MaxNorm – 3 ulp
+            5. One number for every exponent in the range [MaxNorm.exp - 3, MaxNorm.exp + 3] for positive and negative numbers
+
+    :param flen: Size of the floating point registers
+    :param iflen: Size of the floating point source operands for the operation
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Intermediate Results = [[MaxNorm-3 ulp, MaxNorm+3 ulp], [-MaxNorm-3 ulp, -MaxNorm+3 ulp], Random Num > MaxNorm+3 ulp, Random Num < -MaxNorm-3 ulp, [MaxNorm.exp-3, MaxNorm.exp+3]]
+            Operand1 {operation} Operand2 = Intermediate Results
+
+    Implementation:
+            - The intermediate results dataset is populated in accordance with the abstract dataset defined above.
+            - Intermediate results can be out of the range of what is representable in the specified format; they should only be viewed numerically. Inorder to represent numbers that went out of range of the maximum representable number in python, the “Decimal” module was utilized.
+            - These operand values are treated as decimal numbers until their derivation after which they are converted into their respective IEEE754 hexadecimal floating point formats using the “floatingPoint_tohex” function.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    opcode = opcode.split('.')[0]
+    getcontext().prec = 40
+
+    if seed == -1:
+        if opcode in 'fadd':
+            random.seed(0)
+        elif opcode in 'fsub':
+            random.seed(1)
+        elif opcode in 'fmul':
+            random.seed(2)
+        elif opcode in 'fdiv':
+            random.seed(3)
+        elif opcode in 'fsqrt':
+            random.seed(4)
+        elif opcode in 'fmadd':
+            random.seed(5)
+        elif opcode in 'fnmadd':
+            random.seed(6)
+        elif opcode in 'fmsub':
+            random.seed(7)
+        elif opcode in 'fnmsub':
+            random.seed(8)
+    else:
+        random.seed(seed)
+
+    if iflen == 32:
+        ieee754_maxnorm_p = '0x1.7fffffp+127'
+        ieee754_maxnorm_n = '0x1.7ffffep+127'
+        maxnum = float.fromhex(ieee754_maxnorm_p)
+        ir_dataset = []
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([ieee754_maxnorm_p.split('p')[0]+str(i)+'p'+ieee754_maxnorm_p.split('p')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Maxnorm + '+str(int(grs[0:3],2))+' ulp'])
+            ir_dataset.append([ieee754_maxnorm_n.split('p')[0]+str(i)+'p'+ieee754_maxnorm_n.split('p')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Maxnorm - '+str(int(grs[0:3],2))+' ulp'])
+        for i in range(-3,4):
+            ir_dataset.append([ieee754_maxnorm_p.split('p')[0]+'p'+str(127+i),' | Exponent = '+str(127+i)+' Number = +ve'])
+            ir_dataset.append(['-'+ieee754_maxnorm_n.split('p')[0]+'p'+str(127+i),' | Exponent = '+str(127+i)+' Number = -ve'])
+        for i in range(len(ir_dataset)):
+            ir_dataset[i][0] = float.fromhex(ir_dataset[i][0])
+    elif iflen == 64:
+        maxnum = float.fromhex('0x1.fffffffffffffp+1023')
+        maxdec_p = str(maxnum)
+        maxdec_n = str(float.fromhex('0x1.ffffffffffffep+1023'))
+        ir_dataset = []
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(maxdec_p.split('e')[0])+Decimal(pow(i*16,-14)))+'e'+maxdec_p.split('e')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Maxnorm + '+str(int(grs[0:3],2))+' ulp'])
+            ir_dataset.append([str(Decimal(maxdec_n.split('e')[0])+Decimal(pow(i*16,-14)))+'e'+maxdec_n.split('e')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Maxnorm - '+str(int(grs[0:3],2))+' ulp'])
+        for i in range(-3,4):
+            ir_dataset.append([str(random.uniform(1,maxnum)).split('e')[0]+'e'+str(int(math.log(pow(2,1023+i),10))),' | Exponent = '+str(1023+i)+' Number = +ve'])
+            ir_dataset.append([str(-1*random.uniform(1,maxnum)).split('e')[0]+'e'+str(int(math.log(pow(2,1023+i),10))),' | Exponent = '+str(1023+i)+' Number = -ve'])
+
+    b4_comb = []
+
+    for i in range(len(ir_dataset)):
+        rs1 = random.uniform(1,maxnum)
+        rs3 = random.uniform(1,maxnum)
+        if opcode in 'fadd':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0] - rs1
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0]) - Decimal(rs1)
+        elif opcode in 'fsub':
+            if iflen == 32:
+                rs2 = rs1 - ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(rs1) - Decimal(ir_dataset[i][0])
+        elif opcode in 'fmul':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]/rs1
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0])/Decimal(rs1)
+        elif opcode in 'fdiv':
+            if iflen == 32:
+                rs2 = rs1/ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(rs1)/Decimal(ir_dataset[i][0])
+        elif opcode in 'fsqrt':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]*ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0])*Decimal(ir_dataset[i][0])
+        elif opcode in 'fmadd':
+            if iflen == 32:
+                rs2 = (ir_dataset[i][0] - rs3)/rs1
+            elif iflen == 64:
+                rs2 = (Decimal(ir_dataset[i][0]) - Decimal(rs3))/Decimal(rs1)
+        elif opcode in 'fnmadd':
+            if iflen == 32:
+                rs2 = (rs3 - ir_dataset[i][0])/rs1
+            elif iflen == 64:
+                rs2 = (Decimal(rs3) - Decimal(ir_dataset[i][0]))/Decimal(rs1)
+        elif opcode in 'fmsub':
+            if iflen == 32:
+                rs2 = (ir_dataset[i][0] + rs3)/rs1
+            elif iflen == 64:
+                rs2 = (Decimal(ir_dataset[i][0]) + Decimal(rs3))/Decimal(rs1)
+        elif opcode in 'fnmsub':
+            if iflen == 32:
+                rs2 = -1*(rs3 + ir_dataset[i][0])/rs1
+            elif iflen == 64:
+                rs2 = -1*(Decimal(rs3) + Decimal(ir_dataset[i][0]))/Decimal(rs1)
+
+        if(iflen==32):
+            x1 = struct.unpack('f', struct.pack('f', rs1))[0]
+            x2 = struct.unpack('f', struct.pack('f', rs2))[0]
+            x3 = struct.unpack('f', struct.pack('f', rs3))[0]
+        elif(iflen==64):
+            x1 = rs1
+            x2 = rs2
+            x3 = rs3
+
+        if opcode in ['fadd','fsub','fmul','fdiv']:
+            b4_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2))))
+        elif opcode in 'fsqrt':
+            b4_comb.append((floatingPoint_tohex(iflen,float(rs2)),))
+        elif opcode in ['fmadd','fnmadd','fmsub','fnmsub']:
+            b4_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2)),floatingPoint_tohex(iflen,float(rs3))))
+
+    coverpoints = []
+    k = 0
+    for c in b4_comb:
+        for rm in range(5):
+            cvpt = ""
+            for x in range(1, ops+1):
+#                        cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+                cvpt += (extract_fields(iflen,c[x-1],str(x)))
+                cvpt += " and "
+            # cvpt += 'rm_val == '+str(rm)
+            cvpt = sanitise(rm,cvpt,iflen,flen,ops)
+            cvpt += ' # '
+            for y in range(1, ops+1):
+                cvpt += 'rs'+str(y)+'_val=='
+                cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+                if(y != ops):
+                    cvpt += " and "
+            cvpt += ir_dataset[k][1]
+            coverpoints.append(cvpt)
+        k=k+1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) + '-bit coverpoints using Model B4 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b5(flen, iflen, opcode, ops, seed=-1):#***overflow
+    '''
+    IBM Model B5 Definition:
+            This model creates a test-case for each of the following constraints on the intermediate results:
+            1. All the numbers in the range [+MinSubNorm – 3 ulp, +MinSubNorm + 3 ulp]
+            2. All the numbers in the range [-MinSubNorm - 3 ulp, -MinSubNorm + 3 ulp]
+            3. All the numbers in the range [MinNorm – 3 ulp, MinNorm + 3 ulp]
+            4. All the numbers in the range [-MinSubNorm - 3 ulp, -MinSubNorm + 3 ulp]
+            5. All the numbers in the range [MinNorm – 3 ulp, MinNorm + 3 ulp]
+            6. All the numbers in the range [-MinNorm - 3 ulp, -MinNorm + 3 ulp]
+            7. A random number in the range (0, MinSubNorm)
+            8. A random number in the range (-MinSubNorm, -0)
+            9. One number for every exponent in the range [MinNorm.exp, MinNorm.exp + 5]
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Intermediate Results = [+MinSubNorm – 3 ulp, +MinSubNorm + 3 ulp],  [-MinSubNorm - 3 ulp, -MinSubNorm + 3 ulp] , [MinNorm – 3 ulp, MinNorm + 3 ulp] , [-MinNorm - 3 ulp, -MinNorm + 3 ulp] , Random Num in (0, MinSubNorm), Random Num in (-MinSubNorm, -0), One Num for every exp in [MinNorm.exp, MinNorm.exp + 5]]
+            Operand1 {operation} Operand2 = Intermediate Results
+
+    Implementation:
+            - The intermediate results dataset is populated in accordance with the abstract dataset defined above.
+            - Intermediate results can be out of the range of what is representable in the specified format; they should only be viewed numerically. Inorder to represent numbers that went out of range of the maximum representable number in python, the “Decimal” module was utilized.
+            - These operand values are treated as decimal numbers until their derivation after which they are converted into their respective IEEE754 hexadecimal floating point formats using the “floatingPoint_tohex” function.
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+
+    opcode = opcode.split('.')[0]
+    getcontext().prec = 40
+    if iflen == 32:
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.000001p-126'
+        ir_dataset = []
+        for i in range(0,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([ieee754_minsubnorm.split('p')[0]+str(i)+'p'+ieee754_minsubnorm.split('p')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Minsubnorm + '+str(int(grs[0:3],2))+' ulp'])
+        ieee754_minnorm = '0x1.000000p-126'
+        for i in range(0,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([ieee754_minnorm.split('p')[0]+str(i)+'p'+ieee754_minnorm.split('p')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Minnorm + '+str(int(grs[0:3],2))+' ulp'])
+        minnorm_Exp = ['0x1.000000p-126','0x1.000000p-125','0x1.000000p-124','0x1.000000p-123','0x1.000000p-122','0x1.000000p-121']
+        for i in minnorm_Exp:
+            ir_dataset.append([i,' | Exponent = MinNorm.exp + '+str(126+int(i.split('p')[1]))])
+        n = len(ir_dataset)
+        for i in range(n):
+            ir_dataset[i][0] = float.fromhex(ir_dataset[i][0])
+            ir_dataset.append([-1*ir_dataset[i][0],ir_dataset[i][1]])
+
+    elif iflen == 64:
+        maxdec = '1.7976931348623157e+308'
+        maxnum = float.fromhex('0x1.fffffffffffffp+1023')
+        minsubdec = '5e-324'
+        ir_dataset = []
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(minsubdec.split('e')[0])+Decimal(pow(i*16,-14)))+'e'+minsubdec.split('e')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Minsubnorm + '+str(int(grs[0:3],2))+' ulp'])
+        minnormdec = '2.2250738585072014e-308'
+        ir_dataset.append([minsubdec, ' | Guard = 0 Round = 0 Sticky = 0 --> Minsubnorm + 0 ulp'])
+        ir_dataset.append([minnormdec,' | Guard = 0 Round = 0 Sticky = 0 --> Minnorm + 0 ulp'])
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(minnormdec.split('e')[0])+Decimal(pow(i*16,-14)))+'e'+minnormdec.split('e')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Minnorm + '+str(int(grs[0:3],2))+' ulp'])
+        minnorm_Exp = ['4.450147717014403e-308','8.900295434028806e-308','1.780059086805761e-307','3.560118173611522e-307','7.120236347223044e-307']
+
+        k = 1
+        for i in minnorm_Exp:
+            ir_dataset.append([i,' | Exponent = MinNorm.exp + '+str(k)])
+            k += 1
+        n = len(ir_dataset)
+        for i in range(n):
+            ir_dataset.append(['-'+ir_dataset[i][0],ir_dataset[i][1]])
+
+    if seed == -1:
+        if opcode in 'fadd':
+            random.seed(0)
+        elif opcode in 'fsub':
+            random.seed(1)
+        elif opcode in 'fmul':
+            random.seed(2)
+        elif opcode in 'fdiv':
+            random.seed(3)
+        elif opcode in 'fsqrt':
+            random.seed(4)
+        elif opcode in 'fmadd':
+            random.seed(5)
+        elif opcode in 'fnmadd':
+            random.seed(6)
+        elif opcode in 'fmsub':
+            random.seed(7)
+        elif opcode in 'fnmsub':
+            random.seed(8)
+    else:
+        random.seed(seed)
+
+    b5_comb = []
+
+    for i in range(len(ir_dataset)):
+        rs1 = random.uniform(1,maxnum)
+        rs3 = random.uniform(1,maxnum)
+        if opcode in 'fadd':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0] - rs1
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0]) - Decimal(rs1)
+        elif opcode in 'fsub':
+            if iflen == 32:
+                rs2 = rs1 - ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(rs1) - Decimal(ir_dataset[i][0])
+        elif opcode in 'fmul':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]/rs1
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0])/Decimal(rs1)
+        elif opcode in 'fdiv':
+            if iflen == 32:
+                rs2 = rs1/ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(rs1)/Decimal(ir_dataset[i][0])
+        elif opcode in 'fsqrt':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]*ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0])*Decimal(ir_dataset[i][0])
+        elif opcode in 'fmadd':
+            if iflen == 32:
+                rs2 = (ir_dataset[i][0] - rs3)/rs1
+            elif iflen == 64:
+                rs2 = (Decimal(ir_dataset[i][0]) - Decimal(rs3))/Decimal(rs1)
+        elif opcode in 'fnmadd':
+            if iflen == 32:
+                rs2 = (rs3 - ir_dataset[i][0])/rs1
+            elif iflen == 64:
+                rs2 = (Decimal(rs3) - Decimal(ir_dataset[i][0]))/Decimal(rs1)
+        elif opcode in 'fmsub':
+            if iflen == 32:
+                rs2 = (ir_dataset[i][0] + rs3)/rs1
+            elif iflen == 64:
+                rs2 = (Decimal(ir_dataset[i][0]) + Decimal(rs3))/Decimal(rs1)
+        elif opcode in 'fnmsub':
+            if iflen == 32:
+                rs2 = -1*(rs3 + ir_dataset[i][0])/rs1
+            elif iflen == 64:
+                rs2 = -1*(Decimal(rs3) + Decimal(ir_dataset[i][0]))/Decimal(rs1)
+
+        if(iflen==32):
+            x1 = struct.unpack('f', struct.pack('f', rs1))[0]
+            x2 = struct.unpack('f', struct.pack('f', rs2))[0]
+            x3 = struct.unpack('f', struct.pack('f', rs3))[0]
+        elif(iflen==64):
+            x1 = rs1
+            x2 = rs2
+            x3 = rs3
+
+        if opcode in ['fadd','fsub','fmul','fdiv']:
+            b5_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2))))
+        elif opcode in 'fsqrt':
+            b5_comb.append((floatingPoint_tohex(iflen,float(rs2)),))
+        elif opcode in ['fmadd','fnmadd','fmsub','fnmsub']:
+            b5_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2)),floatingPoint_tohex(iflen,float(rs3))))
+
+    coverpoints = []
+    k = 0
+    for c in b5_comb:
+        for rm in range(5):
+            cvpt = ""
+            for x in range(1, ops+1):
+#                        cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+                cvpt += (extract_fields(iflen,c[x-1],str(x)))
+                cvpt += " and "
+            # cvpt += 'rm_val == '+str(rm)
+            cvpt = sanitise(rm,cvpt,iflen,flen,ops)
+            cvpt += ' # '
+            for y in range(1, ops+1):
+                cvpt += 'rs'+str(y)+'_val=='
+                cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+                if(y != ops):
+                    cvpt += " and "
+            cvpt += ir_dataset[k][1]
+            coverpoints.append(cvpt)
+        k=k+1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) + '-bit coverpoints using Model B5 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b6(flen, iflen, opcode, ops, seed=-1):#***underflow. 
+    '''
+    IBM Model B6 Definition:
+            This model tests intermediate results in the space between –MinSubNorm and
+            +MinSubNorm. For each of the following ranges, we select 8 random test cases,
+            one for every combination of the LSB, guard bit, and sticky bit.
+
+            1. -MinSubNorm < intermediate < -MinSubNorm / 2
+            2. -MinSubNorm / 2 <= intermediate < 0
+            3. 0 < intermediate <= +MinSubNorm / 2
+            4. +MinSubNorm / 2 < intermediate < +MinSubNorm
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Intermediate Results = [Random number ∈ (-MinSubNorm, -MinSubNorm/2), Random number ∈ (-MinSubNorm/2, 0), Random number ∈ (0, +MinSubNorm/2), Random number ∈ (+MinSubNorm/2, +MinSubNorm)]
+            {All 8 combinations of guard, round and sticky bit are tested for every number}
+            Operand1 {operation} Operand2 = Intermediate Results
+
+    Implementation:
+            - The intermediate results dataset is populated in accordance with the abstract dataset defined above.
+            - Intermediate results can be out of the range of what is representable in the specified format; they should only be viewed numerically. Inorder to represent numbers that went out of range of the maximum representable number in python, the “Decimal” module was utilized.
+            - These operand values are treated as decimal numbers until their derivation after which they are converted into their respective IEEE754 hexadecimal floating point formats using the “floatingPoint_tohex” function.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    opcode = opcode.split('.')[0]
+    getcontext().prec = 40
+
+    if seed == -1:
+        if opcode in 'fmul':
+            random.seed(0)
+        elif opcode in 'fdiv':
+            random.seed(1)
+        elif opcode in 'fmadd':
+            random.seed(2)
+        elif opcode in 'fnmadd':
+            random.seed(3)
+        elif opcode in 'fmsub':
+            random.seed(4)
+        elif opcode in 'fnmsub':
+            random.seed(5)
+    else:
+        random.seed(seed)
+
+    if iflen == 32:
+        ir_dataset = []
+        ieee754_minsubnorm_n = '-0x0.000001p-127'
+        minnum = float.fromhex(ieee754_minsubnorm_n)
+        r=str(random.uniform(minnum,minnum/2))
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(r.split('e')[0])+Decimal(pow(i*16,-7)))+'e'+r.split('e')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> IR ∈ (-MinSubNorm, -MinSubNorm / 2)'])
+        r=str(random.uniform(minnum/2,0))
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(r.split('e')[0])+Decimal(pow(i*16,-7)))+'e'+r.split('e')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> IR ∈ (-MinSubNorm / 2, 0)'])
+        r=str(random.uniform(0,abs(minnum/2)))
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(r.split('e')[0])+Decimal(pow(i*16,-7)))+'e'+r.split('e')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> IR ∈ (0, +MinSubNorm / 2)'])
+        r=str(random.uniform(abs(minnum/2),abs(minnum)))
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(r.split('e')[0])+Decimal(pow(i*16,-7)))+'e'+r.split('e')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> IR ∈ (+MinSubNorm / 2, +MinSubNorm)'])
+    elif iflen == 64:
+        ir_dataset = []
+        ieee754_minsubnorm_n = '-0x0.0000000000001p-1022'
+        minnum = float.fromhex(ieee754_minsubnorm_n)
+        r=str("{:.2e}".format(random.uniform(minnum,minnum/2)))
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(r.split('e')[0])+Decimal(pow(i*16,-14))),' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> IR ∈ (-MinSubNorm, -MinSubNorm / 2)'])
+        r=str("{:.2e}".format(random.uniform(minnum/2,0)))
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(r.split('e')[0])+Decimal(pow(i*16,-14))),' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> IR ∈ (-MinSubNorm / 2, 0)'])
+        r=str("{:.2e}".format(random.uniform(0,abs(minnum/2))))
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(r.split('e')[0])+Decimal(pow(i*16,-14))),' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> IR ∈ (0, +MinSubNorm / 2)'])
+        r=str("{:.2e}".format(random.uniform(abs(minnum/2),abs(minnum))))
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(r.split('e')[0])+Decimal(pow(i*16,-14))),' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> IR ∈ (+MinSubNorm / 2, +MinSubNorm)'])
+    elif iflen == 128:
+        ir_dataset = []
+        ieee754_minsubnorm_n = '-0x0.0000000000000000000000000001p-16382'
+        minnum = float.fromhex(ieee754_minsubnorm_n)
+        r=str("{:.2e}".format(random.uniform(minnum,minnum/2)))
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(r.split('e')[0])+Decimal(pow(i*16,-14))),' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> IR ∈ (-MinSubNorm, -MinSubNorm / 2)'])
+        r=str("{:.2e}".format(random.uniform(minnum/2,0)))
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(r.split('e')[0])+Decimal(pow(i*16,-14))),' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> IR ∈ (-MinSubNorm / 2, 0)'])
+        r=str("{:.2e}".format(random.uniform(0,abs(minnum/2))))
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(r.split('e')[0])+Decimal(pow(i*16,-14))),' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> IR ∈ (0, +MinSubNorm / 2)'])
+        r=str("{:.2e}".format(random.uniform(abs(minnum/2),abs(minnum))))
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(r.split('e')[0])+Decimal(pow(i*16,-14))),' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> IR ∈ (+MinSubNorm / 2, +MinSubNorm)'])
+    b6_comb = []
+
+    for i in range(len(ir_dataset)):
+        rs1 = random.uniform(0,1e-30)
+        rs3 = random.uniform(0,1e-30)
+
+        if opcode in 'fmul':
+                rs2 = Decimal(ir_dataset[i][0])/Decimal(rs1)
+        elif opcode in 'fdiv':
+                rs2 = Decimal(rs1)/Decimal(ir_dataset[i][0])
+        elif opcode in 'fmadd':
+                rs2 = (Decimal(ir_dataset[i][0]) - Decimal(rs3))/Decimal(rs1)
+        elif opcode in 'fnmadd':
+                rs2 = (Decimal(rs3) - Decimal(ir_dataset[i][0]))/Decimal(rs1)
+        elif opcode in 'fmsub':
+                rs2 = (Decimal(ir_dataset[i][0]) + Decimal(rs3))/Decimal(rs1)
+        elif opcode in 'fnmsub':
+                rs2 = -1*(Decimal(rs3) + Decimal(ir_dataset[i][0]))/Decimal(rs1)
+
+        if(iflen==32):
+            x1 = struct.unpack('f', struct.pack('f', rs1))[0]
+            x2 = struct.unpack('f', struct.pack('f', rs2))[0]
+            x3 = struct.unpack('f', struct.pack('f', rs3))[0]
+        elif(iflen==64):
+            x1 = rs1
+            x2 = rs2
+            x3 = rs3
+        elif(iflen==128):
+            x1 = rs1
+            x2 = rs2
+            x3 = rs3
+
+        if opcode in ['fmul','fdiv']:
+            b6_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2))))
+        elif opcode in ['fmadd','fnmadd','fmsub','fnmsub']:
+            b6_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2)),floatingPoint_tohex(iflen,float(rs3))))
+
+    #print(*b6_comb,sep='\n')
+    coverpoints = []
+    k=0
+
+    for c in b6_comb:
+        for rm in range(5):
+            cvpt = ""
+            for x in range(1, ops+1):
+#                        cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+                cvpt += (extract_fields(iflen,c[x-1],str(x)))
+                cvpt += " and "
+            cvpt = sanitise(rm,cvpt,iflen,flen,ops)
+            # cvpt += 'rm_val == '+str(rm)
+            cvpt += ' # '
+            for y in range(1, ops+1):
+                cvpt += 'rs'+str(y)+'_val=='
+                cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+                if(y != ops):
+                    cvpt += " and "
+            cvpt += ir_dataset[k][1]
+            coverpoints.append(cvpt)
+        k=k+1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64) if iflen == 64 else str(128)) + '-bit coverpoints using Model B6 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b7(flen, iflen, opcode, ops, seed=-1):#***overflow
+    '''
+    IBM Model B7 Definition:
+            This model checks that the sticky bit is calculated correctly in each of the following cases (for every possible combination in the table). The Guard bit should always be 0, and the sign positive, so that miscalculation of the sticky bit will alter the final result.
+            Mask in Extra bits
+
+            .. code-block::
+
+                1000...000
+                0100...000
+                …
+                0000...010
+                0000...001
+                0000000000
+
+    :param flen: Size of the floating point registers
+    :param iflen: Size of the floating point source operands for the operation
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Intermediate Results = [ieee754_maxnorm, maxnum, maxdec, maxnum]
+            {It assures the calculation of sticky bit for every possible combination in the table}
+            Operand1 {operation} Operand2 = Intermediate Results
+
+    Implementation:
+            - The Sticky bit is calculated in each case. The guard bit here is always assumed to be zero and the sign is positive, so that miscalculation of the sticky bit will alter the final result.
+            - In the intermediate result dataset, the elements are appended as elements before the character ‘p’ and then the binary equivalent of ‘010’ + pow(2,i).
+            - Finally on the extra bits, it is masked with the comment created in the previous point. All the first character of each element is converted to its floating point equivalent in a loop
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    opcode = opcode.split('.')[0]
+    getcontext().prec = 60
+    if iflen == 32:
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_num = []
+        for i in fsubnorm+fnorm:
+            float_val = float.hex(fields_dec_converter(32,i))
+            if float_val[0] != '-':
+                ieee754_num.append(float_val.split('p')[0][0:10]+'p'+float_val.split('p')[1])
+        ir_dataset = []
+        for k in range(len(ieee754_num)):
+            for i in range(0,20):
+                comment = (20-i)*'0' + '1' + i*'0'
+                ir_dataset.append([ieee754_num[k].split('p')[0]+hex(int('010'+'{:021b}'.format(pow(2,i)),2))[2:]+'p'+ieee754_num[k].split('p')[1],' | Mask on extra bits ---> ' + comment])
+        n = len(ir_dataset)
+        for i in range(n):
+            ir_dataset[i][0] = float.fromhex(ir_dataset[i][0])
+
+    elif iflen == 64:
+        maxdec = '1.7976931348623157e+308'
+        maxnum = float.fromhex('0x1.fffffffffffffp+1023')
+        ieee754_num = []
+        for i in dsubnorm+dnorm:
+            float_val = fields_dec_converter(64,i)
+            if float_val > 0:
+                ieee754_num.append(str(float_val))
+
+        ir_dataset = []
+        for l in range(len(ieee754_num)):
+            for k in range(1,13):
+                for i in range(4):
+                    comment = (k*(i+1))*'0' + '1' + (51-(k*(i+1)))*'0'
+                    ir_dataset.append([str(Decimal(ieee754_num[l].split('e')[0])+Decimal(pow(16,-14))+Decimal(pow(pow(2,3-i)*16,-14-k)))+'e'+ieee754_num[l].split('e')[1],' | Mask on extra bits ---> ' + comment])
+
+    if seed == -1:
+        if opcode in 'fadd':
+            random.seed(0)
+        elif opcode in 'fsub':
+            random.seed(1)
+        elif opcode in 'fmul':
+            random.seed(2)
+        elif opcode in 'fdiv':
+            random.seed(3)
+        elif opcode in 'fsqrt':
+            random.seed(4)
+        elif opcode in 'fmadd':
+            random.seed(5)
+        elif opcode in 'fnmadd':
+            random.seed(6)
+        elif opcode in 'fmsub':
+            random.seed(7)
+        elif opcode in 'fnmsub':
+            random.seed(8)
+    else:
+        random.seed(seed)
+
+    b7_comb = []
+
+    for i in range(len(ir_dataset)):
+        rs1 = random.uniform(1,maxnum)
+        rs3 = random.uniform(1,maxnum)
+        if opcode in 'fadd':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0] - rs1
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0]) - Decimal(rs1)
+        elif opcode in 'fsub':
+            if iflen == 32:
+                rs2 = rs1 - ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(rs1) - Decimal(ir_dataset[i][0])
+        elif opcode in 'fmul':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]/rs1
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0])/Decimal(rs1)
+        elif opcode in 'fdiv':
+            if iflen == 32:
+                rs2 = rs1/ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(rs1)/Decimal(ir_dataset[i][0])
+        elif opcode in 'fsqrt':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]*ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0])*Decimal(ir_dataset[i][0])
+        elif opcode in 'fmadd':
+            if iflen == 32:
+                rs2 = (ir_dataset[i][0] - rs3)/rs1
+            elif iflen == 64:
+                rs2 = (Decimal(ir_dataset[i][0]) - Decimal(rs3))/Decimal(rs1)
+        elif opcode in 'fnmadd':
+            if iflen == 32:
+                rs2 = (rs3 - ir_dataset[i][0])/rs1
+            elif iflen == 64:
+                rs2 = (Decimal(rs3) - Decimal(ir_dataset[i][0]))/Decimal(rs1)
+        elif opcode in 'fmsub':
+            if iflen == 32:
+                rs2 = (ir_dataset[i][0] + rs3)/rs1
+            elif iflen == 64:
+                rs2 = (Decimal(ir_dataset[i][0]) + Decimal(rs3))/Decimal(rs1)
+        elif opcode in 'fnmsub':
+            if iflen == 32:
+                rs2 = -1*(rs3 + ir_dataset[i][0])/rs1
+            elif iflen == 64:
+                rs2 = -1*(Decimal(rs3) + Decimal(ir_dataset[i][0]))/Decimal(rs1)
+
+        if(iflen==32):
+            x1 = struct.unpack('f', struct.pack('f', rs1))[0]
+            x2 = struct.unpack('f', struct.pack('f', rs2))[0]
+            x3 = struct.unpack('f', struct.pack('f', rs3))[0]
+        elif(iflen==64):
+            x1 = rs1
+            x2 = rs2
+            x3 = rs3
+
+        if opcode in ['fadd','fsub','fmul','fdiv']:
+            b7_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2))))
+        elif opcode in 'fsqrt':
+            b7_comb.append((floatingPoint_tohex(iflen,float(rs2)),))
+        elif opcode in ['fmadd','fnmadd','fmsub','fnmsub']:
+            b7_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2)),floatingPoint_tohex(iflen,float(rs3))))
+
+    coverpoints = []
+    k = 0
+    for c in b7_comb:
+        cvpt = ""
+        for x in range(1, ops+1):
+#                       cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        # cvpt += 'rm_val == 3'
+        cvpt = sanitise(3,cvpt,iflen,flen,ops)
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += ir_dataset[k][1]
+        coverpoints.append(cvpt)
+        k=k+1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) + '-bit coverpoints using Model B7 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b8(flen, iflen, opcode, ops, seed=-1):#***overflow
+    '''
+    IBM Model B8 Definition:
+            This model targets numbers that are on the edge of a rounding boundary. These boundaries may vary depending on the rounding mode. These numbers include floating-point numbers and midpoints between floating-point numbers. In order to target the vicinity of these numbers, we test the following constraints on the extra bits of the intermediate result:
+
+            1. All values of extra-bits in the range [000...00001, 000...00011]
+            2. All values of extra-bits in the range [111...11100, 111...11111]
+
+            For each value selected above, test all the combinations on the LSB of the significand, the guard bit, and the sticky bit (if the number of extra bits is not finite).
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Intermediate Results = [For every Subnormal and Normal number, 8 combinations of guard, round and sticky bit are appended, along with 6 combinations(3 positive, 3 negative) of the mask on extra bits]
+            Operand1 {operation} Operand2 = Intermediate Results
+
+    Implementation:
+            - The intermediate results dataset is populated in accordance with the abstract dataset defined above. The coverpoints can be increased by increasing the dataset of normal and subnormal numbers.
+            - Intermediate results can be out of the range of what is representable in the specified format; they should only be viewed numerically. Inorder to represent numbers that went out of range of the maximum representable number in python, the “Decimal” module was utilized.
+            - These operand values are treated as decimal numbers until their derivation after which they are converted into their respective IEEE754 hexadecimal floating point formats using the “floatingPoint_tohex” function.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    opcode = opcode.split('.')[0]
+    getcontext().prec = 60
+    if iflen == 32:
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_num = []
+        for i in fsubnorm+fnorm:
+            float_val = float.hex(fields_dec_converter(32,i))
+            if float_val[0] != '-':
+                ieee754_num.append(float_val.split('p')[0][0:10]+'p'+float_val.split('p')[1])
+        ir_dataset = []
+        # print(*ieee754_num, sep = '\n')
+        for k in range(len(ieee754_num)):
+            for i in range(1,4):
+                for j in range(1,8):
+                    grs = '{:03b}'.format(j)
+                    ir_dataset.append([ieee754_num[k].split('p')[0]+hex(int('{:03b}'.format(j)+19*'0'+'{:02b}'.format(i),2))[2:]+'p'+ieee754_num[k].split('p')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Mask On Extra Bits: '+19*'0'+'{:02b}'.format(i)])
+                    ir_dataset.append([ieee754_num[k].split('p')[0]+hex(int('{:03b}'.format(j)+19*'1'+'{:02b}'.format(i),2))[2:]+'p'+ieee754_num[k].split('p')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Mask On Extra Bits: '+19*'1'+'{:02b}'.format(i)])
+        n = len(ir_dataset)
+        for i in range(n):
+            ir_dataset[i][0] = float.fromhex(ir_dataset[i][0])
+
+    elif iflen == 64:
+        maxdec = '1.7976931348623157e+308'
+        maxnum = float.fromhex('0x1.fffffffffffffp+1023')
+        ieee754_num = []
+        for i in dsubnorm+dnorm:
+            float_val = float.hex(fields_dec_converter(64,i))
+            if float_val[0] != '-':
+                ieee754_num.append(float_val.split('p')[0][0:17]+'p'+float_val.split('p')[1])
+        ir_dataset = []
+        for k in range(len(ieee754_num)):
+            for i in range(1,4):
+                for j in range(1,8):
+                    grs = '{:03b}'.format(j)
+                    ir_dataset.append([ieee754_num[k].split('p')[0]+hex(int('010'+19*'0'+'{:02b}'.format(i),2))[2:]+'p'+ieee754_num[k].split('p')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Mask On Extra Bits: '+19*'0'+'{:02b}'.format(i)])
+                    ir_dataset.append([ieee754_num[k].split('p')[0]+hex(int('010'+19*'1'+'{:02b}'.format(i),2))[2:]+'p'+ieee754_num[k].split('p')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Mask On Extra Bits: '+19*'1'+'{:02b}'.format(i)])
+        n = len(ir_dataset)
+        for i in range(n):
+            ir_dataset[i][0] = float.fromhex(ir_dataset[i][0])
+
+    if seed == -1:
+        if opcode in 'fadd':
+            random.seed(0)
+        elif opcode in 'fsub':
+            random.seed(1)
+        elif opcode in 'fmul':
+            random.seed(2)
+        elif opcode in 'fdiv':
+            random.seed(3)
+        elif opcode in 'fsqrt':
+            random.seed(4)
+        elif opcode in 'fmadd':
+            random.seed(5)
+        elif opcode in 'fnmadd':
+            random.seed(6)
+        elif opcode in 'fmsub':
+            random.seed(7)
+        elif opcode in 'fnmsub':
+            random.seed(8)
+    else:
+        random.seed(seed)
+
+    b8_comb = []
+
+    for i in range(len(ir_dataset)):
+        rs1 = random.uniform(1,ir_dataset[i][0])
+        rs3 = random.uniform(1,ir_dataset[i][0])
+        if opcode in 'fadd':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0] - rs1
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0]) - Decimal(rs1)
+        elif opcode in 'fsub':
+            if iflen == 32:
+                rs2 = rs1 - ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(rs1) - Decimal(ir_dataset[i][0])
+        elif opcode in 'fmul':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]/rs1
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0])/Decimal(rs1)
+        elif opcode in 'fdiv':
+            if iflen == 32:
+                rs2 = rs1/ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(rs1)/Decimal(ir_dataset[i][0])
+        elif opcode in 'fsqrt':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]*ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0])*Decimal(ir_dataset[i][0])
+        elif opcode in 'fmadd':
+            if iflen == 32:
+                rs2 = (ir_dataset[i][0] - rs3)/rs1
+            elif iflen == 64:
+                rs2 = (Decimal(ir_dataset[i][0]) - Decimal(rs3))/Decimal(rs1)
+        elif opcode in 'fnmadd':
+            if iflen == 32:
+                rs2 = (rs3 - ir_dataset[i][0])/rs1
+            elif iflen == 64:
+                rs2 = (Decimal(rs3) - Decimal(ir_dataset[i][0]))/Decimal(rs1)
+        elif opcode in 'fmsub':
+            if iflen == 32:
+                rs2 = (ir_dataset[i][0] + rs3)/rs1
+            elif iflen == 64:
+                rs2 = (Decimal(ir_dataset[i][0]) + Decimal(rs3))/Decimal(rs1)
+        elif opcode in 'fnmsub':
+            if iflen == 32:
+                rs2 = -1*(rs3 + ir_dataset[i][0])/rs1
+            elif iflen == 64:
+                rs2 = -1*(Decimal(rs3) + Decimal(ir_dataset[i][0]))/Decimal(rs1)
+
+        if(iflen==32):
+            x1 = struct.unpack('f', struct.pack('f', rs1))[0]
+            x2 = struct.unpack('f', struct.pack('f', rs2))[0]
+            x3 = struct.unpack('f', struct.pack('f', rs3))[0]
+        elif(iflen==64):
+            x1 = rs1
+            x2 = rs2
+            x3 = rs3
+
+        if opcode in ['fadd','fsub','fmul','fdiv']:
+            b8_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2))))
+        elif opcode in 'fsqrt':
+            b8_comb.append((floatingPoint_tohex(iflen,float(rs2)),))
+        elif opcode in ['fmadd','fnmadd','fmsub','fnmsub']:
+            b8_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2)),floatingPoint_tohex(iflen,float(rs3))))
+
+    coverpoints = []
+    k=0
+    for c in b8_comb:
+        for rm in range(5):
+            cvpt = ""
+            for x in range(1, ops+1):
+#                        cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+                cvpt += (extract_fields(iflen,c[x-1],str(x)))
+                cvpt += " and "
+            cvpt = sanitise(rm,cvpt,iflen,flen,ops)
+            # cvpt += 'rm_val == '+str(rm)
+            cvpt += ' # '
+            for y in range(1, ops+1):
+                cvpt += 'rs'+str(y)+'_val=='
+                cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+                if(y != ops):
+                    cvpt += " and "
+            cvpt += ir_dataset[k][1]
+            coverpoints.append(cvpt)
+        k=k+1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) + '-bit coverpoints using Model B8 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b9(flen, iflen, opcode, ops):
+    '''
+    IBM Model B9 Definition:
+            This model tests special patterns in the significands of the input operands. Each
+            of the input operands should contain one of the following patterns (each
+            sequence can be of length 0 up to the number of bits in the significand – the
+            more interesting cases will be chosen).
+
+            1. A sequence of leading zeroes
+            2. A sequence of leading ones
+            3. A sequence of trailing zeroes
+            4. A sequence of trailing ones
+            5. A small number of 1s as compared to 0s
+            6. A small number of 0s as compared to 1s
+            7. A "checkerboard" pattern (for example 00110011... or 011011011...)
+            8. Long sequences of 1s
+            9. Long sequences of 0s
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+
+    Abstract Dataset Description:
+            Operand1, Operand2 ∈ [A sequence of leading zeroes, A sequence of leading ones, A sequence of trailing zeroes, A sequence of trailing ones, A small number of 1s as compared to 0s, A small number of 0s as compared to 1s, A "checkerboard" pattern (for example 00110011... or 011011011...), Long sequences of 1s, Long sequences of 0s]
+
+    Implementation:
+            - The rs1 array is appended with the elements of flip types and then for each iteration, the respective sign, mantissa and exponent is computed.
+            - A nested loop is initialized, assuming the rs1 mantissa as the base number and rs2 sign and rs2 exponent is obtained directly from the rs1 sign and rs1 exponent. Rs2 mantissa is calculated by adding the iteration number in the beginning of rs1 mantissa. This is done respectively for each repeating pattern.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    opcode = opcode.split('.')[0]
+
+    if iflen == 32:
+        flip_types = fzero + fone + fminsubnorm + fmaxsubnorm + fminnorm + fmaxnorm
+        e_sz=8
+    elif iflen == 64:
+        flip_types = dzero + done + dminsubnorm + dmaxsubnorm + dminnorm + dmaxnorm
+        e_sz=11
+    elif iflen == 128:
+        flip_types = qzero + qone + qminsubnorm + qmaxsubnorm + qminnorm + qmaxnorm
+        e_sz=15
+
+    rs1 = []
+    b9_comb = []
+    comment = []
+    if ops == 2:
+        for i in range(len(flip_types)):
+            rs1.append(flip_types[i])
+        for i in range(len(rs1)):
+            bin_val = bin(int('1'+rs1[i][2:],16))[3:]
+            rs1_sgn = bin_val[0]
+            rs1_exp = bin_val[1:e_sz+1]
+            rs1_man = bin_val[e_sz+1:]
+
+            for j in range(len(rs1_man)):
+                rs2_sgn = rs1_sgn
+                rs2_exp = rs1_exp
+                rs2_man = '0'*j + rs1_man[j:]                        # Leading 0s
+                rs2 = fields_dec_converter(32,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b9_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(' | Leading zeroes ---> rs2_man = '+rs2_man)
+                b9_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(' | Leading zeroes ---> rs1_man = '+rs2_man)
+
+                rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Leading 1s
+                rs2 = fields_dec_converter(32,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b9_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(' | Leading ones ---> rs2_man = '+rs2_man)
+                b9_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(' | Leading ones ---> rs1_man = '+rs2_man)
+
+                rs2_man = rs1_man[0:j] + '0'*(len(rs1_man)-j)        # Trailing 0s
+                rs2 = fields_dec_converter(32,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b9_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(' | Trailing zeroes ---> rs2_man = '+rs2_man)
+                b9_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(' | Trailing zeroes ---> rs1_man = '+rs2_man)
+
+                rs2_man = '0'*j + '1'*(len(rs1_man)-j)        # Trailing 1s
+                rs2 = fields_dec_converter(32,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b9_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(' | Trailing ones ---> rs2_man = '+rs2_man)
+                b9_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(' | Trailing ones ---> rs1_man = '+rs2_man)
+
+            for j in range(len(rs1_man)-math.ceil(0.1*len(rs1_man)),len(rs1_man)):
+                rs2_sgn = rs1_sgn
+                rs2_exp = rs1_exp
+                rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Long sequence of 1s
+                rs2 = fields_dec_converter(32,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b9_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(' | Long sequence of ones ---> rs2_man = '+rs2_man)
+                b9_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(' | Long sequence of ones ---> rs1_man = '+rs2_man)
+
+                rs2_man = '0'*j + '1'*(len(rs1_man)-j)                        # Long sequence of 0s
+                rs2 = fields_dec_converter(32,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b9_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(' | Long sequence of zeroes ---> rs2_man = '+rs2_man)
+                b9_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(' | Long sequence of zeroes ---> rs1_man = '+rs2_man)
+
+            chkrbrd = ['011','110','0011','1100','0111','1000','010','101','0110','1001']
+            for j in chkrbrd:
+                rs2_sgn = rs1_sgn
+                rs2_exp = rs1_exp
+                rs2_man = j
+                for k in range(math.ceil(len(rs1_man)/len(j))):
+                    rs2_man += j
+                rs2_man = rs2_man[0:iflen-e_sz-1]
+                rs2 = fields_dec_converter(32,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b9_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(' | Checkerboard pattern ---> rs2_man = '+rs2_man)
+                b9_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(' | Checkerboard pattern ---> rs1_man = '+rs2_man)
+
+    else:
+        for i in range(len(flip_types)):
+            rs1.append(flip_types[i])
+        for i in range(len(rs1)):
+            bin_val = bin(int('1'+rs1[i][2:],16))[3:]
+            rs1_sgn = bin_val[0]
+            rs1_exp = bin_val[1:e_sz+1]
+            rs1_man = bin_val[e_sz+1:]
+
+            if rs1_sgn != '1':
+                for j in range(len(rs1_man)):
+                    rs2_sgn = rs1_sgn
+                    rs2_exp = rs1_exp
+                    rs2_man = '0'*j + rs1_man[j:]                        # Leading 0s
+                    rs2 = fields_dec_converter(32,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b9_comb.append((floatingPoint_tohex(iflen,rs2),))
+                    comment.append(' | Leading zeroes ---> rs1_man = '+rs2_man)
+
+                    rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Leading 1s
+                    rs2 = fields_dec_converter(32,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b9_comb.append((floatingPoint_tohex(iflen,rs2),))
+                    comment.append(' | Leading ones ---> rs1_man = '+rs2_man)
+
+                    rs2_man = rs1_man[0:j] + '0'*(len(rs1_man)-j)        # Trailing 0s
+                    rs2 = fields_dec_converter(32,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b9_comb.append((floatingPoint_tohex(iflen,rs2),))
+                    comment.append(' | Trailing zeroes ---> rs1_man = '+rs2_man)
+
+                    rs2_man = '0'*j + '1'*(len(rs1_man)-j)        # Trailing 1s
+                    rs2 = fields_dec_converter(32,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b9_comb.append((floatingPoint_tohex(iflen,rs2),))
+                    comment.append(' | Trailing ones ---> rs1_man = '+rs2_man)
+        rs1_sgn = '0'
+        for j in range(iflen-e_sz-1-math.ceil(0.1*(iflen-e_sz-1)), iflen-e_sz-1):
+            rs2_sgn = rs1_sgn
+            rs2_exp = rs1_exp
+            rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Long sequence of 1s
+            rs2 = fields_dec_converter(32,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+            b9_comb.append((floatingPoint_tohex(iflen,rs2),))
+            comment.append(' | Long sequence of ones ---> rs1_man = '+rs2_man)
+
+            rs2_man = '0'*j + '1'*(len(rs1_man)-j)                        # Long sequence of 0s
+            rs2 = fields_dec_converter(32,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+            b9_comb.append((floatingPoint_tohex(iflen,rs2),))
+            comment.append(' | Long sequence of zeroes ---> rs1_man = '+rs2_man)
+
+        chkrbrd = ['011','110','0011','1100','0111','1000','010','101','0110','1001']
+        for j in chkrbrd:
+            rs2_sgn = rs1_sgn
+            rs2_exp = rs1_exp
+            rs2_man = j
+            for k in range(math.ceil(len(rs1_man)/len(j))):
+                rs2_man += j
+            rs2_man = rs2_man[0:iflen-e_sz-1]
+            rs2 = fields_dec_converter(32,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+            b9_comb.append((floatingPoint_tohex(iflen,rs2),))
+            comment.append(' | Checkerboard pattern ---> rs1_man = '+rs2_man)
+
+    coverpoints = []
+    k = 0
+    for c in b9_comb:
+        cvpt = ""
+        for x in range(1, ops+1):
+#                    cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        # cvpt += 'rm_val == 0'
+        cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += comment[k]
+        coverpoints.append(cvpt)
+        k += 1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) if iflen == 64 else str(128) + '-bit coverpoints using Model B9 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b10(flen, iflen, opcode, ops, N=-1, seed=-1):#***overflow
+    '''
+    IBM Model B10 Definition:
+            This model tests every possible value for a shift between the input operands.
+            1.  A value smaller than -(p + 4)
+            2. All the values in the range [-(p + 4) , (p + 4)]
+            3. A value larger than (p + 4)
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param N: No. of sets of coverpoints to be generated. (Predefined to -1. Set to 2)
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :type N: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Operand1 = [Random Number]
+            Operand2 = [A value smaller than -(op1.exp+4), All values in the range [-(op1.exp+4), (op1.exp+4)], A value larger than +(op1.exp+4)]
+
+    Implementation:
+            - The exponent values of operand 1 and operand 2 obey the shift defined above. The mantissa value is randomly chosen and appended with the exponent derived.
+            - Simultaneously, we convert these numbers into their corresponding IEEE754 floating point formats.
+            - These operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with rounding mode ‘0’ for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    opcode = opcode.split('.')[0]
+
+    if iflen == 32:
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        exp_max = 255
+    elif iflen == 64:
+        maxdec = '1.7976931348623157e+308'
+        maxnum = float.fromhex('0x1.fffffffffffffp+1023')
+        exp_max = 1023
+
+    if N == -1:
+        N = 2
+
+    if seed == -1:
+        if opcode in 'fadd':
+            random.seed(0)
+        elif opcode in 'fsub':
+            random.seed(1)
+    else:
+        random.seed(seed)
+
+    b10_comb = []
+    comment = []
+    for i in range(1,N):
+        rs1 = random.uniform(1,maxnum/1000)
+        rs2 = random.uniform(1,maxnum/1000)
+        rs1_exp = str(rs1).split('e')[1]
+
+        rs2_exp = -1*random.randrange(int(math.log(pow(10,int(rs1_exp)),2))+4, exp_max)
+        rs2_num = str(rs2).split('e')[0] + 'e' + str(int(math.log(pow(2,int(rs2_exp)),10)))
+        b10_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2_num))))
+        comment.append(' | Exponent = '+ str(rs2_exp) + ' --> A value smaller than -(p + 4)')
+
+        for j in range(-(int(math.log(pow(10,int(rs1_exp)),2))+4),+(int(math.log(pow(10,int(rs1_exp)),2))+4)):
+            rs2_num = str(rs2).split('e')[0] + 'e' + str(int(math.log(pow(2,int(j)),10)))
+            b10_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2_num))))
+            comment.append(' | Exponent = '+ str(j) + ' --> Values in the range [-(p + 4) , (p + 4)]')
+
+        rs2_exp = random.randrange(int(math.log(pow(10,int(rs1_exp)),2))+4, exp_max)
+        rs2_num = str(rs2).split('e')[0] + 'e' + str(int(math.log(pow(2,int(rs2_exp)),10)))
+        b10_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2_num))))
+        comment.append(' | Exponent = '+ str(rs2_exp) + ' --> A value larger than (p + 4)')
+
+    coverpoints = []
+    k = 0
+    for c in b10_comb:
+        cvpt = ""
+        for x in range(1, ops+1):
+#                    cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        # cvpt += 'rm_val == 0'
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += comment[k]
+        coverpoints.append(cvpt)
+        k += 1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) + '-bit coverpoints using Model B10 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b11(flen, iflen, opcode, ops, N=-1, seed=-1):#***overflow
+    '''
+    IBM Model B11 Definition:
+            In this model we test the combination of different shift values between the
+            inputs, with special patterns in the significands of the inputs.
+            Significands of Input1 and Input2: as in model (B9) "Special Significands on
+            Inputs"
+
+            Shift: as in model (B10) "Shift - Add"
+            We test both effective operations: addition and subtraction.
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Operand1, Operand2 ∈ Abstract Dataset in B9 + Abstract Dataset in B10
+
+    Implementation:
+            - A culmination of the techniques used in the implementations of Model B9 and Model B10 are used to form the dataset.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    opcode = opcode.split('.')[0]
+
+    if iflen == 32:
+        flip_types = fzero + fone + fminsubnorm + fmaxsubnorm + fminnorm + fmaxnorm
+        e_sz=8
+        exp_max = 255
+    elif iflen == 64:
+        flip_types = dzero + done + dminsubnorm + dmaxsubnorm + dminnorm + dmaxnorm
+        e_sz=11
+        exp_max = 1023 #not used
+    elif iflen == 128:
+        flip_types = qzero + qone + qminsubnorm + qmaxsubnorm + qminnorm + qmaxnorm
+        e_sz=15
+
+
+    if seed == -1:
+        if opcode in 'fadd':
+            random.seed(0)
+        elif opcode in 'fsub':
+            random.seed(1)
+    else:
+        random.seed(seed)
+
+    rs1 = []
+    b11_comb = []
+    comment = []
+    if ops == 2:
+        for i in range(len(flip_types)):
+            rs1.append(flip_types[i])
+        for i in range(len(rs1)):
+            bin_val = bin(int('1'+rs1[i][2:],16))[3:]
+            rs1_sgn = bin_val[0]
+            rs1_exp = bin_val[1:e_sz+1]
+            rs1_man = bin_val[e_sz+1:]
+
+            if int(rs1_exp,2) < 4: rs2_exp = -127
+            else : rs2_exp = random.randrange(-127,int(rs1_exp,2)-131)
+            comment_str = ' | Exponent = '+ str(rs2_exp) + ' --> A value smaller than (p - 4)'
+            rs2_exp += 127
+            if iflen == 32: rs2_exp = '{:08b}'.format(rs2_exp)
+            elif iflen == 64: rs2_exp = '{:011b}'.format(rs2_exp)
+            elif iflen == 128: rs2_exp = '{:015b}'.format(rs2_exp)
+            for j in range(len(rs1_man)):
+                rs2_sgn = rs1_sgn
+                rs2_man = '0'*j + rs1_man[j:]                        # Leading 0s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(comment_str + ' | Leading zeroes ---> rs2_man = '+rs2_man)
+                b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(comment_str + ' | Leading zeroes ---> rs1_man = '+rs2_man)
+
+                rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Leading 1s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(comment_str + ' | Leading ones ---> rs2_man = '+rs2_man)
+                b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(comment_str + ' | Leading ones ---> rs1_man = '+rs2_man)
+
+                rs2_man = rs1_man[0:j] + '0'*(len(rs1_man)-j)        # Trailing 0s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(comment_str + ' | Trailing zeroes ---> rs2_man = '+rs2_man)
+                b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(comment_str + ' | Trailing zeroes ---> rs1_man = '+rs2_man)
+
+                rs2_man = '0'*j + '1'*(len(rs1_man)-j)        # Trailing 1s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(comment_str + ' | Trailing ones ---> rs2_man = '+rs2_man)
+                b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(comment_str + ' | Trailing ones ---> rs1_man = '+rs2_man)
+
+            for j in range(len(rs1_man)-math.ceil(0.1*len(rs1_man)),len(rs1_man)):
+                rs2_sgn = rs1_sgn
+                rs2_exp = rs1_exp
+                rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Long sequence of 1s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(comment_str + ' | Long sequence of ones ---> rs2_man = '+rs2_man)
+                b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(comment_str + ' | Long sequence of ones ---> rs1_man = '+rs2_man)
+
+                rs2_man = '0'*j + '1'*(len(rs1_man)-j)                        # Long sequence of 0s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(comment_str + ' | Long sequence of zeroes ---> rs2_man = '+rs2_man)
+                b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(comment_str + ' | Long sequence of zeroes ---> rs1_man = '+rs2_man)
+
+            chkrbrd = ['011','110','0011','1100','0111','1000','010','101','0110','1001']
+            for j in chkrbrd:
+                rs2_sgn = rs1_sgn
+                rs2_exp = rs1_exp
+                rs2_man = j
+                for k in range(math.ceil(len(rs1_man)/len(j))):
+                    rs2_man += j
+                rs2_man = rs2_man[0:iflen-e_sz-1]
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(comment_str + ' | Checkerboard pattern ---> rs2_man = '+rs2_man)
+                b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(comment_str + ' | Checkerboard pattern ---> rs1_man = '+rs2_man)
+
+            if int(rs1_exp,2) >= 250: rs2_exp = 127
+            else : rs2_exp = random.randrange(int(rs1_exp,2)-123,127)
+            comment_str = ' | Exponent = '+ str(rs2_exp) + ' --> A value greater than (p + 4)'
+            rs2_exp += 127
+            if iflen == 32: rs2_exp = '{:08b}'.format(rs2_exp)
+            elif iflen == 64: rs2_exp = '{:011b}'.format(rs2_exp)
+            elif iflen == 128: rs2_exp = '{:015b}'.format(rs2_exp)
+            for j in range(len(rs1_man)):
+                rs2_sgn = rs1_sgn
+                rs2_man = '0'*j + rs1_man[j:]                        # Leading 0s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(comment_str + ' | Leading zeroes ---> rs2_man = '+rs2_man)
+                b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(comment_str + ' | Leading zeroes ---> rs1_man = '+rs2_man)
+
+                rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Leading 1s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(comment_str + ' | Leading ones ---> rs2_man = '+rs2_man)
+                b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(comment_str + ' | Leading ones ---> rs1_man = '+rs2_man)
+
+                rs2_man = rs1_man[0:j] + '0'*(len(rs1_man)-j)        # Trailing 0s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(comment_str + ' | Trailing zeroes ---> rs2_man = '+rs2_man)
+                b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(comment_str + ' | Trailing zeroes ---> rs1_man = '+rs2_man)
+
+                rs2_man = '0'*j + '1'*(len(rs1_man)-j)        # Trailing 1s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(comment_str + ' | Trailing ones ---> rs2_man = '+rs2_man)
+                b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(comment_str + ' | Trailing ones ---> rs1_man = '+rs2_man)
+
+            for j in range(len(rs1_man)-math.ceil(0.1*len(rs1_man)),len(rs1_man)):
+                rs2_sgn = rs1_sgn
+                rs2_exp = rs1_exp
+                rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Long sequence of 1s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(comment_str + ' | Long sequence of ones ---> rs2_man = '+rs2_man)
+                b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(comment_str + ' | Long sequence of ones ---> rs1_man = '+rs2_man)
+
+                rs2_man = '0'*j + '1'*(len(rs1_man)-j)                        # Long sequence of 0s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(comment_str + ' | Long sequence of zeroes ---> rs2_man = '+rs2_man)
+                b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(comment_str + ' | Long sequence of zeroes ---> rs1_man = '+rs2_man)
+
+            chkrbrd = ['011','110','0011','1100','0111','1000','010','101','0110','1001']
+            for j in chkrbrd:
+                rs2_sgn = rs1_sgn
+                rs2_exp = rs1_exp
+                rs2_man = j
+                for k in range(math.ceil(len(rs1_man)/len(j))):
+                    rs2_man += j
+                rs2_man = rs2_man[0:iflen-e_sz-1]
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                comment.append(comment_str + ' | Checkerboard pattern ---> rs2_man = '+rs2_man)
+                b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                comment.append(comment_str + ' | Checkerboard pattern ---> rs1_man = '+rs2_man)
+
+            ul = int(rs1_exp,2)-123
+            ll = int(rs1_exp,2)-131
+            if int(rs1_exp,2) >= 250: ul = 127
+            if int(rs1_exp,2) < 4: ll = -127
+            for expval in range (ll, ul):
+                rs2_exp = expval
+                comment_str = ' | Exponent = '+ str(rs2_exp) + ' --> Values in the range (p - 4) to (p + 4)'
+                rs2_exp += 127
+                if iflen == 32: rs2_exp = '{:08b}'.format(rs2_exp)
+                elif iflen == 64: rs2_exp = '{:011b}'.format(rs2_exp)
+                elif iflen == 128: rs2_exp = '{:015b}'.format(rs2_exp)
+                for j in range(len(rs1_man)):
+                    rs2_sgn = rs1_sgn
+                    rs2_man = '0'*j + rs1_man[j:]                        # Leading 0s
+                    rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                    comment.append(comment_str + ' | Leading zeroes ---> rs2_man = '+rs2_man)
+                    b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                    comment.append(comment_str + ' | Leading zeroes ---> rs1_man = '+rs2_man)
+
+                    rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Leading 1s
+                    rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                    comment.append(comment_str + ' | Leading ones ---> rs2_man = '+rs2_man)
+                    b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                    comment.append(comment_str + ' | Leading ones ---> rs1_man = '+rs2_man)
+
+                    rs2_man = rs1_man[0:j] + '0'*(len(rs1_man)-j)        # Trailing 0s
+                    rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                    comment.append(comment_str + ' | Trailing zeroes ---> rs2_man = '+rs2_man)
+                    b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                    comment.append(comment_str + ' | Trailing zeroes ---> rs1_man = '+rs2_man)
+
+                    rs2_man = '0'*j + '1'*(len(rs1_man)-j)        # Trailing 1s
+                    rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                    comment.append(comment_str + ' | Trailing ones ---> rs2_man = '+rs2_man)
+                    b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                    comment.append(comment_str + ' | Trailing ones ---> rs1_man = '+rs2_man)
+
+                for j in range(len(rs1_man)-math.ceil(0.1*len(rs1_man)),len(rs1_man)):
+                    rs2_sgn = rs1_sgn
+                    rs2_exp = rs1_exp
+                    rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Long sequence of 1s
+                    rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                    comment.append(comment_str + ' | Long sequence of ones ---> rs2_man = '+rs2_man)
+                    b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                    comment.append(comment_str + ' | Long sequence of ones ---> rs1_man = '+rs2_man)
+
+                    rs2_man = '0'*j + '1'*(len(rs1_man)-j)                        # Long sequence of 0s
+                    rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                    comment.append(comment_str + ' | Long sequence of zeroes ---> rs2_man = '+rs2_man)
+                    b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                    comment.append(comment_str + ' | Long sequence of zeroes ---> rs1_man = '+rs2_man)
+
+                chkrbrd = ['011','110','0011','1100','0111','1000','010','101','0110','1001']
+                for j in chkrbrd:
+                    rs2_sgn = rs1_sgn
+                    rs2_exp = rs1_exp
+                    rs2_man = j
+                    for k in range(math.ceil(len(rs1_man)/len(j))):
+                        rs2_man += j
+                    rs2_man = rs2_man[0:iflen-e_sz-1]
+                    rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b11_comb.append((rs1[i],floatingPoint_tohex(iflen,rs2)))
+                    comment.append(comment_str + ' | Checkerboard pattern ---> rs2_man = '+rs2_man)
+                    b11_comb.append((floatingPoint_tohex(iflen,rs2),rs1[i]))
+                    comment.append(comment_str + ' | Checkerboard pattern ---> rs1_man = '+rs2_man)
+
+    coverpoints = []
+    k = 0
+    for c in b11_comb:
+        cvpt = ""
+        for x in range(1, ops+1):
+#                    cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        # cvpt += 'rm_val == 0'
+        cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += comment[k]
+        coverpoints.append(cvpt)
+        k += 1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64) if iflen == 64 else str(128)) + '-bit coverpoints using Model B11 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b12(flen, iflen, opcode, ops, seed=-1):#***overflow
+    '''
+    IBM Model B12 Definition:
+            This model tests every possible value for cancellation.
+            For the difference between the exponent of the intermediate result and the
+            maximum between the exponents of the inputs, test all values in the range:
+            [-p, +1].
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Intermediate Result - Operand.Exp ∈ [-p, +1]
+            Operand1 {operation} Operand2 = Intermediate Results
+
+    Implementation:
+            - The exponent values of operand 1 and operand 2 obey the shift defined above. The mantissa value is randomly chosen and appended with the exponent derived.
+            - Simultaneously, we convert these numbers into their corresponding IEEE754 floating point formats.
+            - These operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with rounding mode ‘0’ for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+
+    opcode = opcode.split('.')[0]
+    getcontext().prec = 40
+    if iflen == 32:
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.000001p-126'
+        minsubnorm = float.fromhex(ieee754_minsubnorm)
+        ieee754_maxsubnorm = '0x0.7fffffp-126'
+        maxsubnorm = float.fromhex(ieee754_maxsubnorm)
+
+    elif iflen == 64:
+        ieee754_maxnorm = '0x1.fffffffffffffp+1023'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.0000000000001p-1022'
+        minsubnorm = float.fromhex(ieee754_minsubnorm)
+        ieee754_maxsubnorm = '0x0.fffffffffffffp-1022'
+        maxsubnorm = float.fromhex(ieee754_maxsubnorm)
+
+    if seed == -1:
+        if opcode in 'fadd':
+            random.seed(0)
+        elif opcode in 'fsub':
+            random.seed(1)
+    else:
+        random.seed(seed)
+
+    b12_comb = []
+
+    for i in range(50):
+        if opcode in 'fadd': rs1 = -1*random.uniform(minsubnorm,maxnum)
+        elif opcode in 'fsub': rs1 = random.uniform(minsubnorm,maxnum)
+        ir = random.uniform(1,maxnum)
+        if opcode in 'fadd':
+            if iflen == 32:
+                rs2 = ir - rs1
+            elif iflen == 64:
+                rs2 = Decimal(ir) - Decimal(rs1)
+        elif opcode in 'fsub':
+            if iflen == 32:
+                rs2 = rs1 - ir
+            elif iflen == 64:
+                rs2 = Decimal(rs1) - Decimal(ir)
+
+        if(iflen==32):
+            x1 = struct.unpack('f', struct.pack('f', rs1))[0]
+            x2 = struct.unpack('f', struct.pack('f', rs2))[0]
+        elif(iflen==64):
+            x1 = rs1
+            x2 = rs2
+
+        if opcode in ['fadd','fsub']:
+            b12_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2))))
+
+    coverpoints = []
+    comment = ' | Add: Cancellation'
+    for c in b12_comb:
+        cvpt = ""
+        for x in range(1, ops+1):
+#                    cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        # cvpt += 'rm_val == 0'
+        cvpt += ' # '
+        for y in range(1, 3):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += comment
+        coverpoints.append(cvpt)
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) + '-bit coverpoints using Model B12 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b13(flen, iflen, opcode, ops, seed=-1):#***overflow
+    '''
+    IBM Model B13 Definition:
+            This model tests all combinations of cancellation values as in model (B12), with
+            all possible unbiased exponent values of subnormal results.
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Intermediate Result - Operand.Exp ∈ [-p, +1] (The exponent for the intermediate result is chosen such that it is a subnormal number)
+            Operand1 {operation} Operand2 = Intermediate Results
+
+    Implementation:
+            - The implementation procedure for Model B12 is repeated with a revised exponent range as defined above.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+
+    opcode = opcode.split('.')[0]
+    getcontext().prec = 40
+    if iflen == 32:
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.000001p-126'
+        minsubnorm = float.fromhex(ieee754_minsubnorm)
+        ieee754_maxsubnorm = '0x0.7fffffp-126'
+        maxsubnorm = float.fromhex(ieee754_maxsubnorm)
+
+    elif iflen == 64:
+        ieee754_maxnorm = '0x1.fffffffffffffp+1023'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.0000000000001p-1022'
+        minsubnorm = float.fromhex(ieee754_minsubnorm)
+        ieee754_maxsubnorm = '0x0.fffffffffffffp-1022'
+        maxsubnorm = float.fromhex(ieee754_maxsubnorm)
+
+    if seed == -1:
+        if opcode in 'fadd':
+            random.seed(0)
+        elif opcode in 'fsub':
+            random.seed(1)
+    else:
+        random.seed(seed)
+
+    b13_comb = []
+
+    for i in range(200):
+        rs1 = random.uniform(minsubnorm,maxnum)
+        ir = random.uniform(minsubnorm,maxsubnorm)
+        if opcode in 'fadd':
+            if iflen == 32:
+                rs2 = ir - rs1
+            elif iflen == 64:
+                rs2 = Decimal(ir) - Decimal(rs1)
+        elif opcode in 'fsub':
+            if iflen == 32:
+                rs2 = rs1 - ir
+            elif iflen == 64:
+                rs2 = Decimal(rs1) - Decimal(ir)
+
+        if(iflen==32):
+            x1 = struct.unpack('f', struct.pack('f', rs1))[0]
+            x2 = struct.unpack('f', struct.pack('f', rs2))[0]
+        elif(iflen==64):
+            x1 = rs1
+            x2 = rs2
+
+        if opcode in ['fadd','fsub']:
+            b13_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2))))
+
+    coverpoints = []
+    comment = ' | Add: Cancellation ---> Subnormal result'
+    for c in b13_comb:
+        cvpt = ""
+        for x in range(1, 3):
+#                    cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        # cvpt += 'rm_val == 0'
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += comment
+        coverpoints.append(cvpt)
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) + '-bit coverpoints using Model B13 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b14(flen, iflen, opcode, ops, N=-1, seed=-1):#***overflow
+    '''
+    IBM Model B14 Definition:
+            This model tests every possible value for a shift between the addends of the multiply-add operation.
+            For the difference between the unbiased exponent of the addend and the
+            unbiased exponent of the result of the multiplication, test the following values:
+
+            1. A value smaller than -(2* p + 1)
+            2. All the values in the range [-(2*p +1), (p +1) ]
+            3. A value larger than (p + 1)
+
+            We test both effective operations: addition and subtraction. The end values tested are selected to be greater by one than the largest possible shift in which
+            the smaller addend may affect the result.
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param N: No. of sets of coverpoints to be generated. (Predefined to -1. Set to 2)
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :type N: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Shift between the addends of the multiply-add operation = [ A value smaller than -(2* p + 1), All the values in the range [-(2*p +1), (p +1), A value larger than (p + 1) ] → Condition 1
+            Operand 1, 2 = Random
+            Operand 3 = Condition 1
+
+    Implementation:
+            - The shift between the two addends are constrained by the conditions mentioned in the dataset above.
+            - Operands 1 and 2 are randomly obtained. But Operand 3 is obtained by ensuring the shift conditions.
+            - Once the dataset is formed, these operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with rounding mode ‘0’ for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    opcode = opcode.split('.')[0]
+
+    if iflen == 32:
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        exp_max = 127
+        mant_bits = 23
+        limnum = maxnum
+
+    elif iflen == 64:
+        maxdec = '1.7976931348623157e+308'
+        maxnum = float.fromhex('0x1.fffffffffffffp+1023')
+        exp_max = 1022
+        ieee754_limnum = '0x1.fffffffffffffp+507'
+        mant_bits = 52
+        limnum = float.fromhex(ieee754_limnum)
+
+    if N == -1:
+        N = 2
+
+    if seed == -1:
+        if opcode in 'fmadd':
+            random.seed(0)
+        elif opcode in 'fmsub':
+            random.seed(1)
+        elif opcode in 'fnmadd':
+            random.seed(2)
+        elif opcode in 'fnmsub':
+            random.seed(3)
+    else:
+        random.seed(seed)
+
+    b14_comb = []
+    comment = []
+    for i in range(1,N):
+        rs1 = random.uniform(1,limnum)
+        rs2 = random.uniform(1,limnum)
+        rs3 = random.uniform(1,limnum)
+        mul_exp = int(str(rs1*rs2).split('e')[1])
+        mul_exp = int(math.log(pow(2,int(mul_exp)),10))
+
+        if mul_exp-((2*mant_bits)+1) > -1*exp_max:
+            rs3_exp = random.randrange(-1*exp_max,mul_exp-((2*mant_bits)+1))
+            rs3_num = float.hex(float(str(rs3).split('e')[0])).split('p')[0]+'p'+str(int(float.hex(float(str(rs3).split('e')[0])).split('p')[1])+rs3_exp)
+            rs3_num = float.fromhex(rs3_num)
+            b14_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2)),floatingPoint_tohex(iflen,float(rs3_num))))
+            comment.append(' | Multiplicand Exponent = '+str(mul_exp)+', Addend exponent = '+ str(int(float.hex(float(str(rs3).split('e')[0])).split('p')[1])+rs3_exp) + ' --> Difference smaller than -(2*p + 1)')
+
+        if mul_exp-((2*mant_bits)+1) < -1*exp_max: exp1 = -1*exp_max
+        else: exp1 = mul_exp-((2*mant_bits)+1)
+        if mul_exp+mant_bits+1 > exp_max: exp2 = exp_max
+        else: exp2 = mul_exp+mant_bits+1
+        for j in range(exp1, exp2):
+            rs3_num = float.hex(float(str(rs3).split('e')[0])).split('p')[0]+'p'+str(int(float.hex(float(str(rs3).split('e')[0])).split('p')[1])+j)
+            rs3_num = float.fromhex(rs3_num)
+            b14_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2)),floatingPoint_tohex(iflen,float(rs3_num))))
+            comment.append(' | Multiplicand Exponent = '+str(mul_exp)+', Addend exponent = '+ str(int(float.hex(float(str(rs3).split('e')[0])).split('p')[1])+j) + ' --> Values in the range [-(2*p + 1) , (p + 1)]')
+
+        rs3_exp = random.randrange(exp2, exp_max)
+        rs3_num = float.hex(float(str(rs3).split('e')[0])).split('p')[0]+'p'+str(int(float.hex(float(str(rs3).split('e')[0])).split('p')[1])+rs3_exp)
+        rs3_num = float.fromhex(rs3_num)
+        b14_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2)),floatingPoint_tohex(iflen,float(rs3_num))))
+        comment.append(' | Multiplicand Exponent = '+str(mul_exp)+', Addend exponent = '+ str(int(float.hex(float(str(rs3).split('e')[0])).split('p')[1])+rs3_exp) + ' --> A value larger than (p + 1)')
+
+    coverpoints = []
+    k = 0
+    for c in b14_comb:
+        cvpt = ""
+        for x in range(1, 4):
+#                    cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        # cvpt += 'rm_val == 0'
+        cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        cvpt += ' # '
+        for y in range(1, 4):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += comment[k]
+        coverpoints.append(cvpt)
+        k += 1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) + '-bit coverpoints using Model B14 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b15(flen, iflen, opcode, ops, N=-1, seed=-1):#***overflow
+    '''
+    IBM Model B15 Definition:
+            In this model we test the combination of different shift values between the
+            addends, with special patterns in the significands of the addends.
+            For the significand of the addend and for the multiplication result we take the
+            cases defined in model (B9) "Special Significands on Inputs"
+            For the shift we take the cases defined in model (B14) "Shift – multiply-add".
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Operand 1, 2 = Random
+            Operand 3 ∈ Abstract Dataset in B9 + Abstract Dataset in B14
+
+    Implementation:
+            - Here the condition is imposed that if the value of the ops variable is 3, then each of the elements in the flip types is iterated and split into their respective sign, mantissa and exponent part.
+            - A mul variable is initialized and parsed to the field_dec_converter for each rs1 value in the list. Next the loop is run for the mantissa parts generated for rs1 values, where it is checked for certain patterns like the leading 0’s, leading 1’s, trailing 0’s and trailing 1’s.
+            - The checkerboard list is declared with the probable sequences for rs2. Here the sign and exponent are extracted from the rs1 values. Mantissa part is derived from the checkerboard list. Consecutively, if the iflen value differs, then the range available varies.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with rounding mode “0” for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    opcode = opcode.split('.')[0]
+
+    if iflen == 32:
+        flip_types = fzero + fone + fminsubnorm + fmaxsubnorm + fminnorm + fmaxnorm
+        e_sz=8
+        exp_max = 255
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        exp_max = 127
+        mant_bits = 23
+        limnum = maxnum
+    elif iflen == 64:
+        flip_types = dzero + done + dminsubnorm + dmaxsubnorm + dminnorm + dmaxnorm
+        e_sz=11
+        exp_max = 1023
+        maxdec = '1.7976931348623157e+308'
+        maxnum = float.fromhex('0x1.fffffffffffffp+1023')
+        exp_max = 1022
+        ieee754_limnum = '0x1.fffffffffffffp+507'
+        mant_bits = 52
+        limnum = float.fromhex(ieee754_limnum)
+
+    if seed == -1:
+        if opcode in 'fmadd':
+            random.seed(0)
+        elif opcode in 'fnmadd':
+            random.seed(1)
+        elif opcode in 'fmsub':
+            random.seed(2)
+        elif opcode in 'fnmsub':
+            random.seed(3)
+    else:
+        random.seed(seed)
+
+    rs1 = []
+    b15_comb = []
+    comment = []
+    if ops == 3:
+        for i in range(len(flip_types)):
+            rs1.append(flip_types[i])
+        for i in range(len(rs1)):
+            bin_val = bin(int('1'+rs1[i][2:],16))[3:]
+            rs1_sgn = bin_val[0]
+            rs1_exp = bin_val[1:e_sz+1]
+            rs1_man = bin_val[e_sz+1:]
+
+            if iflen == 32:
+                if int(rs1_exp,2) < 65: rs2_exp = 0
+                else : rs2_exp = random.randrange(0,int(rs1_exp,2)-65)
+                comment_str = ' | Exponent = '+ str(rs2_exp-127) + ' --> Difference smaller than -(2p + 1)'
+                rs2_exp = '{:08b}'.format(rs2_exp)
+            elif iflen == 64:
+                if int(rs1_exp,2) < 129: rs2_exp = 0
+                else : rs2_exp = random.randrange(0,int(rs1_exp,2)-129)
+                comment_str = ' | Exponent = '+ str(rs2_exp-1023) + ' --> Difference smaller than -(2p + 1)'
+                rs2_exp = '{:011b}'.format(rs2_exp)
+            mul = fields_dec_converter(iflen,rs1[i])
+            rs1_act = random.uniform(1,limnum)
+            rs2_act = mul/rs1_act
+            for j in range(len(rs1_man)):
+                rs2_sgn = rs1_sgn
+                rs2_man = '0'*j + rs1_man[j:]                        # Leading 0s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                comment.append(comment_str + ' | Leading zeroes ---> rs3_man = '+rs2_man)
+
+                rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Leading 1s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                comment.append(comment_str + ' | Leading ones ---> rs3_man = '+rs2_man)
+
+                rs2_man = rs1_man[0:j] + '0'*(len(rs1_man)-j)        # Trailing 0s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                comment.append(comment_str + ' | Trailing zeroes ---> rs3_man = '+rs2_man)
+
+                rs2_man = '0'*j + '1'*(len(rs1_man)-j)        # Trailing 1s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                comment.append(comment_str + ' | Trailing ones ---> rs3_man = '+rs2_man)
+
+            for j in range(len(rs1_man)-math.ceil(0.1*len(rs1_man)),len(rs1_man)):
+                rs2_sgn = rs1_sgn
+                rs2_exp = rs1_exp
+                rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Long sequence of 1s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                comment.append(comment_str + ' | Long sequence of ones ---> rs3_man = '+rs2_man)
+
+                rs2_man = '0'*j + '1'*(len(rs1_man)-j)                        # Long sequence of 0s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                comment.append(comment_str + ' | Long sequence of zeroes ---> rs3_man = '+rs2_man)
+
+            chkrbrd = ['011','110','0011','1100','0111','1000','010','101','0110','1001']
+            for j in chkrbrd:
+                rs2_sgn = rs1_sgn
+                rs2_exp = rs1_exp
+                rs2_man = j
+                for k in range(math.ceil(len(rs1_man)/len(j))):
+                    rs2_man += j
+                rs2_man = rs2_man[0:iflen-e_sz-1]
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                comment.append(comment_str + ' | Checkerboard pattern ---> rs3_man = '+rs2_man)
+
+            if iflen == 32:
+                if int(rs1_exp,2) > 222: rs2_exp = 255
+                else : rs2_exp = random.randrange(int(rs1_exp,2)+33, 255)
+                comment_str = ' | Exponent = '+ str(rs2_exp-127) + ' --> Difference greater than (p + 1)'
+                rs2_exp = '{:08b}'.format(rs2_exp)
+            elif iflen == 64:
+                if int(rs1_exp,2) > 958: rs2_exp = 1023
+                else : rs2_exp = random.randrange(int(rs1_exp,2)+65, 1023)
+                comment_str = ' | Exponent = '+ str(rs2_exp-1023) + ' --> Difference greater than (p + 1)'
+                rs2_exp = '{:011b}'.format(rs2_exp)
+            mul = fields_dec_converter(iflen,rs1[i])
+            rs1_act = random.uniform(1,limnum)
+            rs2_act = mul/rs1_act
+            for j in range(len(rs1_man)):
+                rs2_sgn = rs1_sgn
+                rs2_man = '0'*j + rs1_man[j:]                        # Leading 0s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                comment.append(comment_str + ' | Leading zeroes ---> rs3_man = '+rs2_man)
+
+                rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Leading 1s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                comment.append(comment_str + ' | Leading ones ---> rs3_man = '+rs2_man)
+
+                rs2_man = rs1_man[0:j] + '0'*(len(rs1_man)-j)        # Trailing 0s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                comment.append(comment_str + ' | Trailing zeroes ---> rs3_man = '+rs2_man)
+
+                rs2_man = '0'*j + '1'*(len(rs1_man)-j)        # Trailing 1s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                comment.append(comment_str + ' | Trailing ones ---> rs3_man = '+rs2_man)
+
+            for j in range(len(rs1_man)-math.ceil(0.1*len(rs1_man)),len(rs1_man)):
+                rs2_sgn = rs1_sgn
+                rs2_exp = rs1_exp
+                rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Long sequence of 1s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                comment.append(comment_str + ' | Long sequence of ones ---> rs3_man = '+rs2_man)
+
+                rs2_man = '0'*j + '1'*(len(rs1_man)-j)                        # Long sequence of 0s
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                comment.append(comment_str + ' | Long sequence of zeroes ---> rs3_man = '+rs2_man)
+
+            chkrbrd = ['011','110','0011','1100','0111','1000','010','101','0110','1001']
+            for j in chkrbrd:
+                rs2_sgn = rs1_sgn
+                rs2_exp = rs1_exp
+                rs2_man = j
+                for k in range(math.ceil(len(rs1_man)/len(j))):
+                    rs2_man += j
+                rs2_man = rs2_man[0:iflen-e_sz-1]
+                rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                comment.append(comment_str + ' | Checkerboard pattern ---> rs3_man = '+rs2_man)
+
+            if iflen == 32:
+                ul = int(rs1_exp,2)+33
+                ll = int(rs1_exp,2)-65
+                if int(rs1_exp,2) >= 222: ul = 255
+                if int(rs1_exp,2) < 65: ll = 0
+            elif iflen == 64:
+                ul = int(rs1_exp,2)+65
+                ll = int(rs1_exp,2)-129
+                if int(rs1_exp,2) >= 958: ul = 1023
+                if int(rs1_exp,2) < 129: ll = 0
+            for expval in range (ll, ul):
+                rs2_exp = expval
+                if iflen == 32:
+                    comment_str = ' | Exponent = '+ str(rs2_exp-127) + ' --> Difference between -(2p+1) and (p+1)'
+                    rs2_exp = '{:08b}'.format(rs2_exp)
+                elif iflen == 64:
+                    comment_str = ' | Exponent = '+ str(rs2_exp-1023) + ' --> Difference between -(2p+1) and (p+1)'
+                    rs2_exp = '{:011b}'.format(rs2_exp)
+                mul = fields_dec_converter(iflen,rs1[i])
+                rs1_act = random.uniform(1,limnum)
+                rs2_act = mul/rs1_act
+
+                for j in range(len(rs1_man)):
+                    rs2_sgn = rs1_sgn
+                    rs2_man = '0'*j + rs1_man[j:]                        # Leading 0s
+                    rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                    comment.append(comment_str + ' | Leading zeroes ---> rs3_man = '+rs2_man)
+
+                    rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Leading 1s
+                    rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                    comment.append(comment_str + ' | Leading ones ---> rs3_man = '+rs2_man)
+
+                    rs2_man = rs1_man[0:j] + '0'*(len(rs1_man)-j)        # Trailing 0s
+                    rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                    comment.append(comment_str + ' | Trailing zeroes ---> rs3_man = '+rs2_man)
+
+                    rs2_man = '0'*j + '1'*(len(rs1_man)-j)        # Trailing 1s
+                    rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                    comment.append(comment_str + ' | Trailing ones ---> rs3_man = '+rs2_man)
+
+                for j in range(len(rs1_man)-math.ceil(0.1*len(rs1_man)),len(rs1_man)):
+                    rs2_sgn = rs1_sgn
+                    rs2_exp = rs1_exp
+                    rs2_man = '1'*j + '0'*(len(rs1_man)-j)                        # Long sequence of 1s
+                    rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                    comment.append(comment_str + ' | Long sequence of ones ---> rs3_man = '+rs2_man)
+
+                    rs2_man = '0'*j + '1'*(len(rs1_man)-j)                        # Long sequence of 0s
+                    rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                    comment.append(comment_str + ' | Long sequence of zeroes ---> rs3_man = '+rs2_man)
+
+                chkrbrd = ['011','110','0011','1100','0111','1000','010','101','0110','1001']
+                for j in chkrbrd:
+                    rs2_sgn = rs1_sgn
+                    rs2_exp = rs1_exp
+                    rs2_man = j
+                    for k in range(math.ceil(len(rs1_man)/len(j))):
+                        rs2_man += j
+                    rs2_man = rs2_man[0:iflen-e_sz-1]
+                    rs2 = fields_dec_converter(iflen,'0x'+hex(int('1'+rs2_sgn+rs2_exp+rs2_man,2))[3:])
+                    b15_comb.append((floatingPoint_tohex(iflen,float(rs1_act)),floatingPoint_tohex(iflen,float(rs2_act)),floatingPoint_tohex(iflen,float(rs2))))
+                    comment.append(comment_str + ' | Checkerboard pattern ---> rs3_man = '+rs2_man)
+
+    coverpoints = []
+    k = 0
+    for c in b15_comb:
+        cvpt = ""
+        for x in range(1, 4):
+#                    cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        # cvpt += 'rm_val == 0'
+        cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += comment[k]
+        coverpoints.append(cvpt)
+        k += 1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) + '-bit coverpoints using Model B15 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b16(flen, iflen, opcode, ops, seed=-1):#***overflow
+    '''
+    IBM Model B16 Definition:
+            This model tests every possible value for cancellation.
+            For the difference between the exponent of the intermediate result and the
+            maximum between the exponents of the addend and the multiplication result,
+            test all values in the range:
+            [-(2 * p + 1), 1].
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Intermediate Result.exp - max(addend.exp, multiplication result.exp) ∈ [-(2 * p + 1), 1] → Condition 1
+            Operand 1 {operation 1} Operand 2 {operation 2} Operand 3 = Condition 1
+
+    Implementation:
+            - Random values of operands 1 and 2 are obtained from the random library.
+            - Since the objective of the test is to cancel the operands among each other constrained by the above condition, the intermediate result is calculated by the multiplication of operand 1 and 2.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with rounding mode “0” for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+
+    opcode = opcode.split('.')[0]
+    getcontext().prec = 40
+    if iflen == 32:
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.000001p-126'
+        minsubnorm = float.fromhex(ieee754_minsubnorm)
+        ieee754_maxsubnorm = '0x0.7fffffp-126'
+        maxsubnorm = float.fromhex(ieee754_maxsubnorm)
+        limnum = maxnum
+
+    elif iflen == 64:
+        ieee754_maxnorm = '0x1.fffffffffffffp+1023'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.0000000000001p-1022'
+        minsubnorm = float.fromhex(ieee754_minsubnorm)
+        ieee754_maxsubnorm = '0x0.fffffffffffffp-1022'
+        maxsubnorm = float.fromhex(ieee754_maxsubnorm)
+        ieee754_limnum = '0x1.fffffffffffffp+507'
+        limnum = float.fromhex(ieee754_limnum)
+
+    if seed == -1:
+        if opcode in 'fmadd':
+            random.seed(0)
+        elif opcode in 'fmsub':
+            random.seed(1)
+        elif opcode in 'fnmadd':
+            random.seed(2)
+        elif opcode in 'fnmsub':
+            random.seed(3)
+    else:
+        random.seed(seed)
+
+    b17_comb = []
+
+    for i in range(200):
+        rs1 = random.uniform(minsubnorm,limnum)
+        rs2 = random.uniform(minsubnorm,limnum)
+        ir = random.uniform(minsubnorm,rs1*rs2)
+
+        if opcode in 'fmadd':
+            if iflen == 32:
+                rs3 = ir - rs1*rs2
+            elif iflen == 64:
+                rs3 = Decimal(ir) - Decimal(rs1)*Decimal(rs2)
+        elif opcode in 'fnmadd':
+            if iflen == 32:
+                rs3 = -1*rs1*rs2 - ir
+            elif iflen == 64:
+                rs3 = -1*Decimal(rs1)*Decimal(rs2) - Decimal(ir)
+        elif opcode in 'fmsub':
+            if iflen == 32:
+                rs3 = rs1*rs2 - ir
+            elif iflen == 64:
+                rs3 = Decimal(rs1)*Decimal(rs2) - Decimal(ir)
+        elif opcode in 'fnmsub':
+            if iflen == 32:
+                rs3 = ir + rs1*rs2
+            elif iflen == 64:
+                rs3 = Decimal(ir) + Decimal(rs1)*Decimal(rs2)
+
+        if(iflen==32):
+            x1 = struct.unpack('f', struct.pack('f', rs1))[0]
+            x2 = struct.unpack('f', struct.pack('f', rs2))[0]
+        elif(iflen==64):
+            x1 = rs1
+            x2 = rs2
+
+        result = []
+        if opcode in ['fmadd','fmsub','fnmadd','fnmsub']:
+            b17_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2)),floatingPoint_tohex(iflen,float(rs3))))
+
+    coverpoints = []
+    comment = ' | Multiply-Add: Cancellation'
+    for c in b17_comb:
+        cvpt = ""
+        for x in range(1, 4):
+#                    cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        # cvpt += 'rm_val == 0'
+        cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += comment
+        coverpoints.append(cvpt)
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) + '-bit coverpoints using Model B16 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b17(flen, iflen, opcode, ops, seed=-1):#***overflow
+    '''
+    IBM Model B17 Definition:
+            This model tests all combinations of cancellation values as in model (B16), with
+            all possible unbiased exponent values of subnormal results.
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Intermediate Result.exp - max(addend.exp, multiplication result.exp) ∈ [-(2 * p + 1), 1] → Condition 1 (Exponents are subnormal)
+            Operand 1 {operation 1} Operand 2 {operation 2} Operand 3 = Condition 1
+
+    Implementation:
+            - It functions the same as model B16 with calculating the additional unbiased exponent values of subnormal results.
+            - Operands 1 and 2 are randomly initialized in the range and the subsequent operator value is found.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with rounding mode “0” for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+
+    opcode = opcode.split('.')[0]
+    getcontext().prec = 40
+    if iflen == 32:
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.000001p-126'
+        minsubnorm = float.fromhex(ieee754_minsubnorm)
+        ieee754_maxsubnorm = '0x0.7fffffp-126'
+        maxsubnorm = float.fromhex(ieee754_maxsubnorm)
+        limnum = maxnum
+
+    elif iflen == 64:
+        ieee754_maxnorm = '0x1.fffffffffffffp+1023'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.0000000000001p-1022'
+        minsubnorm = float.fromhex(ieee754_minsubnorm)
+        ieee754_maxsubnorm = '0x0.fffffffffffffp-1022'
+        maxsubnorm = float.fromhex(ieee754_maxsubnorm)
+        ieee754_limnum = '0x1.fffffffffffffp+507'
+        limnum = float.fromhex(ieee754_limnum)
+
+    if seed == -1:
+        if opcode in 'fmadd':
+            random.seed(0)
+        elif opcode in 'fmsub':
+            random.seed(1)
+        elif opcode in 'fnmadd':
+            random.seed(2)
+        elif opcode in 'fnmsub':
+            random.seed(3)
+    else:
+        random.seed(seed)
+
+    b17_comb = []
+
+    for i in range(200):
+        rs1 = random.uniform(minsubnorm,limnum)
+        rs2 = random.uniform(minsubnorm,limnum)
+        ir = random.uniform(minsubnorm,maxsubnorm)
+        if ir > rs1*rs2: ir = random.uniform(minsubnorm,rs1*rs2)
+
+        if opcode in 'fmadd':
+            if iflen == 32:
+                rs3 = ir - rs1*rs2
+            elif iflen == 64:
+                rs3 = Decimal(ir) - Decimal(rs1)*Decimal(rs2)
+        elif opcode in 'fnmadd':
+            if iflen == 32:
+                rs3 = -1*rs1*rs2 - ir
+            elif iflen == 64:
+                rs3 = -1*Decimal(rs1)*Decimal(rs2) - Decimal(ir)
+        elif opcode in 'fmsub':
+            if iflen == 32:
+                rs3 = rs1*rs2 - ir
+            elif iflen == 64:
+                rs3 = Decimal(rs1)*Decimal(rs2) - Decimal(ir)
+        elif opcode in 'fnmsub':
+            if iflen == 32:
+                rs3 = ir + rs1*rs2
+            elif iflen == 64:
+                rs3 = Decimal(ir) + Decimal(rs1)*Decimal(rs2)
+
+        if(iflen==32):
+            x1 = struct.unpack('f', struct.pack('f', rs1))[0]
+            x2 = struct.unpack('f', struct.pack('f', rs2))[0]
+        elif(iflen==64):
+            x1 = rs1
+            x2 = rs2
+
+        result = []
+        if opcode in ['fmadd','fmsub','fnmadd','fnmsub']:
+            b17_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2)),floatingPoint_tohex(iflen,float(rs3))))
+
+    coverpoints = []
+    comment = ' | Multiply-Add: Cancellation ---> Subnormal result '
+    for c in b17_comb:
+        cvpt = ""
+        for x in range(1, 4):
+#                    cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        # cvpt += 'rm_val == 0'
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += comment
+        coverpoints.append(cvpt)
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) + '-bit coverpoints using Model B17 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b18(flen, iflen, opcode, ops, seed=-1):#***overflow
+    '''
+    IBM Model B18 Definition:
+            This model checks different cases where the multiplication causes some event
+            in the product while the addition cancels this event.
+
+            1. Product: Enumerate all options for LSB, Guard and Sticky bit.  Intermediate Result: Exact (Guard and Sticky are zero).
+            2. Product: Take overflow values from (B4) "Overflow".  Intermediate Result: No overflow
+            3. Product: Take underflow values from model (B5) "Underflow".  Intermediate Result: No underflow
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Implementation:
+            - Firstly, cancellation using the B3 model as base is performed.
+            - Next model is the replica of the B4 model which takes into account the overflow of value for guard, round and sticky bits
+            - The final model is obtained from the B5 model and different operations are done for underflow in decimal format.
+            - The operand values are calculated using the intermediate results dataset and then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with rounding mode “0” for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    opcode = opcode.split('.')[0]
+    getcontext().prec = 40
+
+    if seed == -1:
+        if opcode in 'fmadd':
+            random.seed(0)
+        elif opcode in 'fnmadd':
+            random.seed(1)
+        elif opcode in 'fmsub':
+            random.seed(2)
+        elif opcode in 'fnmsub':
+            random.seed(3)
+    else:
+        random.seed(seed)
+
+    # Cancellation of B3
+    if iflen == 32:
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_num = []
+        lsb = []
+        for i in fsubnorm+fnorm:
+            if int(i[-1],16)%2 == 1:
+                lsb.append('1')
+                lsb.append('1')
+            else:
+                lsb.append('0')
+                lsb.append('0')
+            float_val = float.hex(fields_dec_converter(32,i))
+            if float_val[0] != '-':
+                ieee754_num.append(float_val.split('p')[0][0:10]+'p'+float_val.split('p')[1])
+                ieee754_num.append('-'+float_val.split('p')[0][0:10]+'p'+float_val.split('p')[1])
+            else:
+                ieee754_num.append(float_val.split('p')[0][0:11]+'p'+float_val.split('p')[1])
+                ieee754_num.append(float_val.split('p')[0][1:11]+'p'+float_val.split('p')[1])
+
+        ir_dataset = []
+        for k in range(len(ieee754_num)):
+            for i in range(2,16,2):
+                grs = '{:04b}'.format(i)
+                if ieee754_num[k][0] == '-': sign = '1'
+                else: sign = '0'
+                ir_dataset.append([ieee754_num[k].split('p')[0]+str(i)+'p'+ieee754_num[k].split('p')[1],' | Guard = '+grs[0]+' Sticky = '+grs[2]+' Sign = '+sign+' LSB = '+lsb[k] + ': Multiply add - Guard & Sticky Cancellation'])
+
+        for i in range(len(ir_dataset)):
+            ir_dataset[i][0] = float.fromhex(ir_dataset[i][0])
+
+    elif iflen == 64:
+        maxdec = '1.7976931348623157e+308'
+        maxnum = float.fromhex('0x1.fffffffffffffp+1023')
+        ieee754_num = []
+        lsb = []
+        for i in dsubnorm+dnorm:
+            if int(i[-1],16)%2 == 1:
+                lsb.append('1')
+                lsb.append('1')
+            else:
+                lsb.append('0')
+                lsb.append('0')
+            float_val = str(fields_dec_converter(64,i))
+            if float_val[0] != '-':
+                ieee754_num.append(float_val)
+                ieee754_num.append('-'+float_val)
+            else:
+                ieee754_num.append(float_val)
+                ieee754_num.append(float_val[1:])
+
+        ir_dataset = []
+        for k in range(len(ieee754_num)):
+            for i in range(2,16,2):
+                grs = '{:04b}'.format(i)
+                if ieee754_num[k][0] == '-': sign = '1'
+                else: sign = '0'
+                ir_dataset.append([str(Decimal(ieee754_num[k].split('e')[0])+Decimal(pow(i*16,-14)))+'e'+ieee754_num[k].split('e')[1],' | Guard = '+grs[0]+' Sticky = '+grs[2]+' Sign = '+sign+' LSB = '+lsb[k] + ': Multiply add - Guard & Sticky Cancellation'])
+
+    b18_comb = []
+
+    for i in range(len(ir_dataset)):
+        rs1 = random.uniform(1,maxnum)
+        res = '0x1.7ffff0p+100'
+        res = float.fromhex(res)
+        if opcode in 'fmadd':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]/rs1
+                rs3 = res - ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0])/Decimal(rs1)
+                rs3 = Decimal(res) - Decimal(ir_dataset[i][0])
+        elif opcode in 'fnmadd':
+            if iflen == 32:
+                rs2 = -1*ir_dataset[i][0]/rs1
+                rs3 = -1*res + ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = -1*Decimal(ir_dataset[i][0])/Decimal(rs1)
+                rs3 = -1*Decimal(res) - Decimal(ir_dataset[i][0])
+        elif opcode in 'fmsub':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]/rs1
+                rs3 = ir_dataset[i][0] - res
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0])/Decimal(rs1)
+                rs3 = Decimal(ir_dataset[i][0]) - Decimal(res)
+        elif opcode in 'fnmsub':
+            if iflen == 32:
+                rs2 = -1*ir_dataset[i][0]/rs1
+                rs3 = res - ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = -1*Decimal(ir_dataset[i][0])/Decimal(rs1)
+                rs3 = Decimal(res) - Decimal(ir_dataset[i][0])
+
+        if(iflen==32):
+            x1 = struct.unpack('f', struct.pack('f', rs1))[0]
+            x2 = struct.unpack('f', struct.pack('f', rs2))[0]
+            x3 = struct.unpack('f', struct.pack('f', rs3))[0]
+        elif(iflen==64):
+            x1 = rs1
+            x2 = rs2
+            x3 = rs3
+
+        if opcode in ['fmadd','fnmadd','fmsub','fnmsub']:
+            b18_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2)),floatingPoint_tohex(iflen,float(rs3))))
+    ir_dataset1 = ir_dataset
+
+        # Cancellation of B4
+    if iflen == 32:
+        ieee754_maxnorm_p = '0x1.7fffffp+127'
+        ieee754_maxnorm_n = '0x1.7ffffep+127'
+        maxnum = float.fromhex(ieee754_maxnorm_p)
+        ir_dataset = []
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([ieee754_maxnorm_p.split('p')[0]+str(i)+'p'+ieee754_maxnorm_p.split('p')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Maxnorm + '+str(int(grs[0:3],2))+' ulp' + ': Multiply add - Overflow Cancellation'])
+            ir_dataset.append([ieee754_maxnorm_n.split('p')[0]+str(i)+'p'+ieee754_maxnorm_n.split('p')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Maxnorm - '+str(int(grs[0:3],2))+' ulp' + ': Multiply add - Overflow Cancellation'])
+        for i in range(len(ir_dataset)):
+            ir_dataset[i][0] = float.fromhex(ir_dataset[i][0])
+    elif iflen == 64:
+        maxnum = float.fromhex('0x1.fffffffffffffp+1023')
+        maxdec_p = str(maxnum)
+        maxdec_n = str(float.fromhex('0x1.ffffffffffffep+1023'))
+        ir_dataset = []
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(maxdec_p.split('e')[0])+Decimal(pow(i*16,-14)))+'e'+maxdec_p.split('e')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Maxnorm + '+str(int(grs[0:3],2))+' ulp' + ': Multiply add - Overflow Cancellation'])
+            ir_dataset.append([str(Decimal(maxdec_n.split('e')[0])+Decimal(pow(i*16,-14)))+'e'+maxdec_n.split('e')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Maxnorm - '+str(int(grs[0:3],2))+' ulp' + ': Multiply add - Overflow Cancellation'])
+
+    for i in range(len(ir_dataset)):
+        rs1 = random.uniform(1,maxnum)
+        res = '0x1.7ffff0p+100'
+        res = float.fromhex(res)
+        if opcode in 'fmadd':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]/rs1
+                rs3 = res - ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0])/Decimal(rs1)
+                rs3 = Decimal(res) - Decimal(ir_dataset[i][0])
+        elif opcode in 'fnmadd':
+            if iflen == 32:
+                rs2 = -1*ir_dataset[i][0]/rs1
+                rs3 = -1*res + ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = -1*Decimal(ir_dataset[i][0])/Decimal(rs1)
+                rs3 = -1*Decimal(res) - Decimal(ir_dataset[i][0])
+        elif opcode in 'fmsub':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]/rs1
+                rs3 = ir_dataset[i][0] - res
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0])/Decimal(rs1)
+                rs3 = Decimal(ir_dataset[i][0]) - Decimal(res)
+        elif opcode in 'fnmsub':
+            if iflen == 32:
+                rs2 = -1*ir_dataset[i][0]/rs1
+                rs3 = res - ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = -1*Decimal(ir_dataset[i][0])/Decimal(rs1)
+                rs3 = Decimal(res) - Decimal(ir_dataset[i][0])
+
+        if(iflen==32):
+            x1 = struct.unpack('f', struct.pack('f', rs1))[0]
+            x2 = struct.unpack('f', struct.pack('f', rs2))[0]
+            x3 = struct.unpack('f', struct.pack('f', rs3))[0]
+        elif(iflen==64):
+            x1 = rs1
+            x2 = rs2
+            x3 = rs3
+
+        if opcode in ['fmadd','fnmadd','fmsub','fnmsub']:
+            b18_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2)),floatingPoint_tohex(iflen,float(rs3))))
+    ir_dataset2 = ir_dataset
+
+    # Cancellation of B5
+    if iflen == 32:
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.000001p-126'
+        ir_dataset = []
+        for i in range(0,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([ieee754_minsubnorm.split('p')[0]+str(i)+'p'+ieee754_minsubnorm.split('p')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Minsubnorm + '+str(int(grs[0:3],2))+' ulp' + ': Multiply add - Underflow Cancellation'])
+        ieee754_minnorm = '0x1.000000p-126'
+        for i in range(0,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([ieee754_minnorm.split('p')[0]+str(i)+'p'+ieee754_minnorm.split('p')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Minnorm + '+str(int(grs[0:3],2))+' ulp' + ': Multiply add - Underflow Cancellation'])
+        n = len(ir_dataset)
+        for i in range(n):
+            ir_dataset[i][0] = float.fromhex(ir_dataset[i][0])
+            ir_dataset.append([-1*ir_dataset[i][0],ir_dataset[i][1]])
+
+    elif iflen == 64:
+        maxdec = '1.7976931348623157e+308'
+        maxnum = float.fromhex('0x1.fffffffffffffp+1023')
+        minsubdec = '5e-324'
+        ir_dataset = []
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(minsubdec.split('e')[0])+Decimal(pow(i*16,-14)))+'e'+minsubdec.split('e')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Minsubnorm + '+str(int(grs[0:3],2))+' ulp' + ': Multiply add - Underflow Cancellation'])
+        minnormdec = '2.2250738585072014e-308'
+        ir_dataset.append([minsubdec, ' | Guard = 0 Round = 0 Sticky = 0 --> Minsubnorm + 0 ulp'])
+        ir_dataset.append([minnormdec,' | Guard = 0 Round = 0 Sticky = 0 --> Minnorm + 0 ulp'])
+        for i in range(2,16,2):
+            grs = '{:04b}'.format(i)
+            ir_dataset.append([str(Decimal(minnormdec.split('e')[0])+Decimal(pow(i*16,-14)))+'e'+minnormdec.split('e')[1],' | Guard = '+grs[0]+' Round = '+grs[1]+' Sticky = '+grs[2]+' --> Minnorm + '+str(int(grs[0:3],2))+' ulp' + ': Multiply add - Underflow Cancellation'])
+        n = len(ir_dataset)
+        for i in range(n):
+            ir_dataset.append(['-'+ir_dataset[i][0],ir_dataset[i][1]])
+
+    for i in range(len(ir_dataset)):
+        rs1 = random.uniform(1,maxnum)
+        res = '0x1.7ffff0p+100'
+        res = float.fromhex(res)
+        if opcode in 'fmadd':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]/rs1
+                rs3 = res - ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0])/Decimal(rs1)
+                rs3 = Decimal(res) - Decimal(ir_dataset[i][0])
+        elif opcode in 'fnmadd':
+            if iflen == 32:
+                rs2 = -1*ir_dataset[i][0]/rs1
+                rs3 = -1*res + ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = -1*Decimal(ir_dataset[i][0])/Decimal(rs1)
+                rs3 = -1*Decimal(res) - Decimal(ir_dataset[i][0])
+        elif opcode in 'fmsub':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]/rs1
+                rs3 = ir_dataset[i][0] - res
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0])/Decimal(rs1)
+                rs3 = Decimal(ir_dataset[i][0]) - Decimal(res)
+        elif opcode in 'fnmsub':
+            if iflen == 32:
+                rs2 = -1*ir_dataset[i][0]/rs1
+                rs3 = res - ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = -1*Decimal(ir_dataset[i][0])/Decimal(rs1)
+                rs3 = Decimal(res) - Decimal(ir_dataset[i][0])
+
+        if(iflen==32):
+            x1 = struct.unpack('f', struct.pack('f', rs1))[0]
+            x2 = struct.unpack('f', struct.pack('f', rs2))[0]
+            x3 = struct.unpack('f', struct.pack('f', rs3))[0]
+        elif(iflen==64):
+            x1 = rs1
+            x2 = rs2
+            x3 = rs3
+
+        if opcode in ['fmadd','fnmadd','fmsub','fnmsub']:
+            b18_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2)),floatingPoint_tohex(iflen,float(rs3))))
+    ir_dataset3 = ir_dataset
+
+    ir_dataset = ir_dataset1 + ir_dataset2 + ir_dataset3
+    coverpoints = []
+    k = 0
+    for c in b18_comb:
+        cvpt = ""
+        for x in range(1, ops+1):
+#                    cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        # cvpt += 'rm_val == 0'
+        cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += ir_dataset[k][1]
+        coverpoints.append(cvpt)
+        k=k+1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) + '-bit coverpoints using Model B18 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b19(flen, iflen, opcode, ops, seed=-1):#***overflow
+    '''
+    IBM Model B19 Definition:
+            This model checks various possible differences between the two inputs.
+            A test-case will be created for each combination of the following  table::
+
+                First input    Second input    Difference between exponents    Difference between significands
+                +Normal        +Normal         >0                              >0
+                -Normal        -Normal         =0                              =0
+                +SubNormal     +SubNormal      <0                              <0
+                -SubNormal     -SubNormal
+                0              0
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Operand1 {operation} Operand2  = Derived from the table above
+
+    Implementation:
+            - Normal (positive and negative), subnormal (positive and negative) arrays are randomly initialized within their respectively declared ranges.
+            - The difference between exponents and significands are formed as per the conditions in the table.
+            - All possible combinations of the table are used in creating the test-cases.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+
+    opcode = opcode.split('.')[0]
+    getcontext().prec = 40
+    if iflen == 32:
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.000001p-126'
+        minsubnorm = float.fromhex(ieee754_minsubnorm)
+        ieee754_maxsubnorm = '0x0.7fffffp-126'
+        maxsubnorm = float.fromhex(ieee754_maxsubnorm)
+        limnum = maxnum
+
+    elif iflen == 64:
+        ieee754_maxnorm = '0x1.fffffffffffffp+1023'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.0000000000001p-1022'
+        minsubnorm = float.fromhex(ieee754_minsubnorm)
+        ieee754_maxsubnorm = '0x0.fffffffffffffp-1022'
+        maxsubnorm = float.fromhex(ieee754_maxsubnorm)
+        ieee754_limnum = '0x1.fffffffffffffp+507'
+        limnum = float.fromhex(ieee754_limnum)
+
+    if seed == -1:
+        if opcode in 'fmin':
+            random.seed(0)
+        elif opcode in 'fmax':
+            random.seed(1)
+        elif opcode in 'flt':
+            random.seed(2)
+        elif opcode in 'feq':
+            random.seed(3)
+        elif opcode in 'fle':
+            random.seed(3)
+    else:
+        random.seed(seed)
+
+    b19_comb = []
+    comment = []
+    normal = []
+    normal_neg = []
+    sub_normal = []
+    sub_normal_neg = []
+    zero = [[0e0,'Zero']]
+    for i in range(5):
+        normal.append([random.uniform(1,maxnum),'Normal'])
+        normal_neg.append([random.uniform(-1*maxnum,-1),'-Normal'])
+        sub_normal.append([random.uniform(minsubnorm,maxsubnorm),'Subnormal'])
+        sub_normal_neg.append([random.uniform(-1*maxsubnorm,-1*minsubnorm),'-Subnormal'])
+
+    all_num = normal + normal_neg + sub_normal + sub_normal_neg + zero
+    for i in all_num:
+        for j in all_num:
+            if i[0] != 0:
+                i_sig = str(i[0]).split('e')[0]
+                i_exp = str(i[0]).split('e')[1]
+            else:
+                i_sig = '0'
+                i_exp = '0'
+            if j[0] != 0:
+                j_sig = str(j[0]).split('e')[0]
+                j_exp = str(j[0]).split('e')[1]
+            else:
+                j_sig = '0'
+                j_exp = '0'
+            if float(i_sig) >= float(j_sig): sig_sign = '>='
+            else: sig_sign = '<'
+            if float(i_exp) >= float(j_exp): exp_sign = '>='
+            else: exp_sign = '<'
+            rs1 = float(i_sig+'e'+i_exp)
+            rs2 = float(j_sig+'e'+j_exp)
+            b19_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2))))
+            comment.append(' | rs1 --> ' + i[1] + ', rs2 --> ' + j[1] + ', rs1_sigificand ' + sig_sign + ' rs2_significand' + ', rs1_exp ' + exp_sign + ' rs2_exp')
+            rs1 = float(i_sig+'e'+j_exp)
+            rs2 = float(j_sig+'e'+i_exp)
+            b19_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2))))
+            comment.append(' | rs1 --> ' + j[1] + ', rs2 --> ' + i[1] + ', rs1_sigificand ' + sig_sign + ' rs2_significand' + ', rs2_exp ' + exp_sign + ' rs1_exp')
+            rs1 = float(j_sig+'e'+i_exp)
+            rs2 = float(i_sig+'e'+j_exp)
+            b19_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2))))
+            comment.append(' | rs1 --> ' + j[1] + ', rs2 --> ' + i[1] + ', rs2_sigificand ' + sig_sign + ' rs1_significand' + ', rs1_exp ' + exp_sign + ' rs2_exp')
+            rs1 = float(i_sig+'e'+j_exp)
+            rs2 = float(j_sig+'e'+j_exp)
+            b19_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2))))
+            comment.append(' | rs1 --> ' + j[1] + ', rs2 --> ' + j[1] + ', rs1_sigificand ' + sig_sign + ' rs2_significand' + ', rs1_exp = rs2_exp')
+            rs1 = float(i_sig+'e'+i_exp)
+            rs2 = float(i_sig+'e'+j_exp)
+            b19_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2))))
+            comment.append(' | rs1 --> ' + i[1] + ', rs2 --> ' + j[1] + ', rs1_sigificand = rs2_significand' + ', rs1_exp ' + exp_sign + ' rs2_exp')
+            rs1 = float(i_sig+'e'+i_exp)
+            rs2 = float(i_sig+'e'+i_exp)
+            b19_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2))))
+            comment.append(' | rs1 --> ' + i[1] + ', rs2 --> ' + i[1] + ', rs1_sigificand = rs2_significand, rs1_exp = rs2_exp')
+
+    coverpoints = []
+    k = 0
+    for c in b19_comb:
+        cvpt = ""
+        for x in range(1, 3):
+#                    cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        if opcode in ["fadd","fsub","fmul","fdiv","fsqrt","fmadd","fnmadd","fmsub","fnmsub","fcvt","fmv"]:
+            cvpt = sanitise(0,cvpt,iflen,flen,ops)
+            # cvpt += 'rm_val == 0'
+        elif opcode in ["fclass","flt","fmax","fsgnjn","fle","fmin","fsgnj","feq",
+                    "flw","fsw","fsgnjx","fld","fsd"]:
+            cvpt = sanitise(0,cvpt,iflen,flen,ops)
+            # cvpt += 'rm_val == 1'
+        # elif opcode in []:
+            # cvpt = sanitise(2,cvpt,iflen,flen)
+            # cvpt += 'rm_val == 2'
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += comment[k]
+        coverpoints.append(cvpt)
+        k += 1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) + '-bit coverpoints using Model B19 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b20(flen, iflen, opcode, ops, seed=-1):#***overflow
+    '''
+    IBM Model B20 Definition:
+            This model will create test-cases such that the significand of the intermediate results will cover each of the following patterns:
+
+            Mask on the intermediate result significand (excluding the leading “1” )
+
+            .. code-block::
+
+                xxx...xxx10
+                xxx...xx100
+                xxx...x1000
+                …
+                xx1...00000
+                x10...00000
+                100...00000
+                000...00000
+
+            The sticky bit of the intermediate result should always be 0. In case of the remainder operation, we will look at the result of the division in order to find the interesting test-cases.
+            Operation: Divide, Square-root.
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Intermediate Results = [Random bits are taken initially to form xxx...xxx10. The pattern described above is then formed]
+            Operand1 {operation} Operand2 = Intermediate Results
+
+    Implementation:
+            - A loop is initiated where random bits are obtained for which the subsequent sign, exponent is calculated for the intermediate value and stored in the ir_dataset.
+            - Operand 1 (rs1) is randomly initialized in the range (1, limnum) and the subsequent operator value is found.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    opcode = opcode.split('.')[0]
+    getcontext().prec = 60
+
+    if seed == -1:
+        if opcode in 'fdiv':
+            random.seed(1)
+        elif opcode in 'fsqrt':
+            random.seed(2)
+    else:
+        random.seed(seed)
+
+    if iflen == 32:
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.000001p-126'
+        minsubnorm = float.fromhex(ieee754_minsubnorm)
+        ieee754_maxsubnorm = '0x0.7fffffp-126'
+        maxsubnorm = float.fromhex(ieee754_maxsubnorm)
+        limnum = maxnum
+        ir_dataset = []
+        for i in range(1,21,1):
+            for k in range(5):
+                bits = random.getrandbits(i)
+                bits = bin(bits)[2:]
+                front_zero = i-len(bits)
+                bits = '0'*front_zero + bits
+                trailing_zero = 22-i
+                sig = bits+'1'+'0'*trailing_zero
+
+                exp = random.getrandbits(8)
+                exp = '{:08b}'.format(exp)
+
+                sgn = random.getrandbits(1)
+                sgn = '{:01b}'.format(sgn)
+
+                ir_bin = ('0b'+sgn+exp+sig)
+                ir = fields_dec_converter(iflen,'0x'+hex(int('1'+ir_bin[2:],2))[3:])
+                ir_dataset.append([ir, ' | Intermediate result significand: ' + sig + '  Pattern: ' + 'X'*i + '1' + '0'*trailing_zero])
+
+        sig = '1'+'0'*22
+        exp = random.getrandbits(8)
+        exp = '{:08b}'.format(exp)
+        sgn = random.getrandbits(1)
+        sgn = '{:01b}'.format(sgn)
+        ir_bin = ('0b'+sgn+exp+sig)
+        ir = fields_dec_converter(iflen,'0x'+hex(int('1'+ir_bin[2:],2))[3:])
+        ir_dataset.append([ir, 'Intermediate result significand: '+ sig + '  Pattern: ' + '1' + '0'*22])
+
+        sig = '0'*23
+        exp = random.getrandbits(8)
+        exp = '{:08b}'.format(exp)
+        sgn = random.getrandbits(1)
+        sgn = '{:01b}'.format(sgn)
+        ir_bin = ('0b'+sgn+exp+sig)
+        ir = fields_dec_converter(iflen,'0x'+hex(int('1'+ir_bin[2:],2))[3:])
+        ir_dataset.append([ir, 'Intermediate result significand: '+ sig + '  Pattern: ' + '0' + '0'*22])
+
+    elif iflen == 64:
+        ieee754_maxnorm = '0x1.fffffffffffffp+1023'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.0000000000001p-1022'
+        minsubnorm = float.fromhex(ieee754_minsubnorm)
+        ieee754_maxsubnorm = '0x0.fffffffffffffp-1022'
+        maxsubnorm = float.fromhex(ieee754_maxsubnorm)
+        ieee754_limnum = '0x1.fffffffffffffp+507'
+        limnum = float.fromhex(ieee754_limnum)
+        ieee754_num = []
+        ir_dataset = []
+        for i in range(1,50,1):
+            for k in range(5):
+                bits = random.getrandbits(i)
+                bits = bin(bits)[2:]
+                front_zero = i-len(bits)
+                bits = '0'*front_zero + bits
+                trailing_zero = 51-i
+                sig = bits+'1'+'0'*trailing_zero
+
+                exp = random.getrandbits(11)
+                exp = '{:011b}'.format(exp)
+
+                sgn = random.getrandbits(1)
+                sgn = '{:01b}'.format(sgn)
+
+                ir_bin = ('0b'+sgn+exp+sig)
+                ir = fields_dec_converter(iflen,'0x'+hex(int('1'+ir_bin[2:],2))[3:])
+                ir_dataset.append([ir, ' | Intermediate result significand: ' + sig + '  Pattern: ' + 'X'*i + '1' + '0'*trailing_zero])
+
+        sig = '1'+'0'*51
+        exp = random.getrandbits(8)
+        exp = '{:08b}'.format(exp)
+        sgn = random.getrandbits(1)
+        sgn = '{:01b}'.format(sgn)
+        ir_bin = ('0b'+sgn+exp+sig)
+        ir = fields_dec_converter(iflen,'0x'+hex(int('1'+ir_bin[2:],2))[3:])
+        ir_dataset.append([ir, 'Intermediate result significand: '+ sig + '  Pattern: ' + '1' + '0'*51])
+
+        sig = '0'*52
+        exp = random.getrandbits(8)
+        exp = '{:08b}'.format(exp)
+        sgn = random.getrandbits(1)
+        sgn = '{:01b}'.format(sgn)
+        ir_bin = ('0b'+sgn+exp+sig)
+        ir = fields_dec_converter(iflen,'0x'+hex(int('1'+ir_bin[2:],2))[3:])
+        ir_dataset.append([ir, 'Intermediate result significand: ' + sig + '  Pattern: ' + '0' + '0'*52])
+
+    b8_comb = []
+    for i in range(len(ir_dataset)):
+        rs1 = random.uniform(1, limnum)
+        if opcode in 'fdiv':
+            if iflen == 32:
+                rs2 = rs1/ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(rs1)/Decimal(ir_dataset[i][0])
+        elif opcode in 'fsqrt':
+            if iflen == 32:
+                rs2 = ir_dataset[i][0]*ir_dataset[i][0]
+            elif iflen == 64:
+                rs2 = Decimal(ir_dataset[i][0])*Decimal(ir_dataset[i][0])
+
+        if(iflen==32):
+            x1 = struct.unpack('f', struct.pack('f', rs1))[0]
+            x2 = struct.unpack('f', struct.pack('f', rs2))[0]
+        elif(iflen==64):
+            x1 = rs1
+            x2 = rs2
+
+        if opcode in ['fdiv']:
+            b8_comb.append((floatingPoint_tohex(iflen,float(rs1)),floatingPoint_tohex(iflen,float(rs2))))
+        elif opcode in 'fsqrt':
+            b8_comb.append((floatingPoint_tohex(iflen,float(rs2)),))
+
+    coverpoints = []
+    k=0
+    for c in b8_comb:
+        cvpt = ""
+        for x in range(1, ops+1):
+#                    cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        # cvpt += 'rm_val == 0'
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += ir_dataset[k][1]
+        coverpoints.append(cvpt)
+        k=k+1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) + '-bit coverpoints using Model B20 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b21(flen, iflen, opcode, ops):
+    '''
+    IBM Model B21 Definition:
+            This model will test the Divide By Zero exception flag. For the operations divide and remainder, a test case will be created for each of the possible combinations from the following table:
+
+            First Operand : 0, Random non-zero number, Infinity, NaN
+            Second Operand : 0, Random non-zero number, Infinity, NaN
+
+            Operation: Divide, Remainder
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+
+    Abstract Dataset Description:
+            Final Results = [ Zero, Subnorm, Norm, Infinity, DefaultNaN, QNaN, SNaN ]
+
+    Implementation:
+            - The basic_types dataset is accumulated with the combinations of the abstract dataset description.
+            - Using python’s package itertools, a permutation of all possible combinations as a pair is computed for basic_types dataset..
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+    '''
+    sanitise = get_sanitise_func(opcode)
+    if iflen == 32:
+        basic_types = fzero + fsubnorm + fnorm + finfinity + fdefaultnan + [fqnan[0], fqnan[3]] + \
+                [fsnan[0], fsnan[3]]
+    elif iflen == 64:
+        basic_types = dzero + dsubnorm + dnorm +\
+            dinfinity + ddefaultnan + [dqnan[0], dqnan[1]] + \
+            [dsnan[0], dsnan[1]]
+    elif iflen == 128:
+        basic_types = qzero + qsubnorm + qnorm +\
+            qinfinity + qdefaultnan + [qqnan[0], qqnan[1]] + \
+            [qsnan[0], qsnan[1]]
+    else:
+        logger.error('Invalid iflen value!')
+        sys.exit(1)
+
+    # the following creates a cross product for ops number of variables
+    b21_comb = list(itertools.product(*ops*[basic_types]))
+    coverpoints = []
+    for c in b21_comb:
+        cvpt = ""
+        for x in range(1, ops+1):
+#            cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        if opcode.split('.')[0] in ["fdiv"]:
+            cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        coverpoints.append(cvpt)
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64) if iflen == 64 else str(128)) + '-bit coverpoints using Model B21 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b22(flen, iflen, opcode, ops, seed=10):#***overflow
+    '''
+    IBM Model B22 Definition:
+            This model creates test cases for each of the following exponents (unbiased):
+
+            1. Smaller than -3
+            2. All the values in the range [-3, integer width+3]
+            3. Larger than integer width + 3
+
+            For each exponent two cases will be randomly chosen, positive and negative.
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to -1. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Operand1 = [Smaller than -3, All the values in the range [-3, integer width+3], Larger than integer width + 3]
+
+    Implementation:
+            - Random bits are calculated and appended to obtain the exponent ranges defined in case 2.
+            - To satisfy case 1 and case 3, similar steps are performed outside the loop and hence updated in the loop.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+
+    opcode = opcode.split('.')[0] + '.' + opcode.split('.')[1]
+    if opcode[2] == 's': iflen = 32
+    elif opcode[2] == 'd': iflen = 64
+    elif opcode[2] == 'q': iflen = 128
+    getcontext().prec = 40
+    xlen = 0
+
+    if opcode in 'fcvt.w':
+        xlen = 32
+    elif opcode in 'fcvt.l':
+        xlen = 64
+    elif opcode in 'fcvt.wu':
+        xlen = 32
+    elif opcode in 'fcvt.lu':
+        xlen = 64
+
+    if seed == -1:
+        if opcode in 'fcvt.w':
+            random.seed(0)
+        elif opcode in 'fcvt.l':
+            random.seed(1)
+        elif opcode in 'fcvt.wu':
+            random.seed(2)
+        elif opcode in 'fcvt.lu':
+            random.seed(3)
+    else:
+        random.seed(seed)
+
+    b22_comb = []
+
+    if iflen == 32:
+        ieee754_maxnorm = '0x1.7fffffp+127'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.000001p-126'
+        minsubnorm = float.fromhex(ieee754_minsubnorm)
+        ieee754_maxsubnorm = '0x0.7fffffp-126'
+        maxsubnorm = float.fromhex(ieee754_maxsubnorm)
+        limnum = maxnum
+        op_dataset = []
+        for i in range(124,xlen+130,1):
+            bits = random.getrandbits(23)
+            bits = bin(bits)[2:]
+            front_zero = 23-len(bits)
+            sig = '0'*front_zero + bits
+
+            exp = i
+            exp = '{:08b}'.format(exp)
+
+            sgn = random.getrandbits(1)
+            sgn = '{:01b}'.format(sgn)
+
+            ir_bin = ('0b'+sgn+exp+sig)
+            op = fields_dec_converter(iflen,'0x'+hex(int('1'+ir_bin[2:],2))[3:])
+            op_dataset.append([op, ' | Exponent: ' + str(int(exp,2)-127) + ', Exponent in the range [-3, integer width+3]'])
+            b22_comb.append((floatingPoint_tohex(iflen,float(op)),))
+
+        bits = random.getrandbits(23)
+        bits = bin(bits)[2:]
+        front_zero = 23-len(bits)
+        sig = '0'*front_zero + bits
+        exp = random.randint(0,124)
+        exp = '{:08b}'.format(exp)
+        sgn = random.getrandbits(1)
+        sgn = '{:01b}'.format(sgn)
+        ir_bin = ('0b'+sgn+exp+sig)
+        op = fields_dec_converter(iflen,'0x'+hex(int('1'+ir_bin[2:],2))[3:])
+        op_dataset.append([op, ' | Exponent: ' + str(int(exp,2)-127) + ', Exponent less than -3'])
+        b22_comb.append((floatingPoint_tohex(iflen,float(op)),))
+
+        bits = random.getrandbits(23)
+        bits = bin(bits)[2:]
+        front_zero = 23-len(bits)
+        sig = '0'*front_zero + bits
+        exp = random.randint(xlen+130,255)
+        exp = '{:08b}'.format(exp)
+        sgn = random.getrandbits(1)
+        sgn = '{:01b}'.format(sgn)
+        ir_bin = ('0b'+sgn+exp+sig)
+        op = fields_dec_converter(iflen,'0x'+hex(int('1'+ir_bin[2:],2))[3:])
+        op_dataset.append([op, ' | Exponent: ' + str(int(exp,2)-127) + ', Exponent greater than (integer width+3)'])
+        b22_comb.append((floatingPoint_tohex(iflen,float(op)),))
+
+    elif iflen == 64:
+        ieee754_maxnorm = '0x1.fffffffffffffp+1023'
+        maxnum = float.fromhex(ieee754_maxnorm)
+        ieee754_minsubnorm = '0x0.0000000000001p-1022'
+        minsubnorm = float.fromhex(ieee754_minsubnorm)
+        ieee754_maxsubnorm = '0x0.fffffffffffffp-1022'
+        maxsubnorm = float.fromhex(ieee754_maxsubnorm)
+        ieee754_limnum = '0x1.fffffffffffffp+507'
+        limnum = float.fromhex(ieee754_limnum)
+        op_dataset = []
+        for i in range(1020,xlen+1026,1):
+            bits = random.getrandbits(52)
+            bits = bin(bits)[2:]
+            front_zero = 52-len(bits)
+            sig = '0'*front_zero + bits
+
+            exp = i
+            exp = '{:011b}'.format(exp)
+
+            sgn = random.getrandbits(1)
+            sgn = '{:01b}'.format(sgn)
+
+            ir_bin = ('0b'+sgn+exp+sig)
+            op = fields_dec_converter(iflen,'0x'+hex(int('1'+ir_bin[2:],2))[3:])
+            op_dataset.append([op, ' | Exponent: ' + str(int(exp,2)-1023) + ', Exponent in the range [-3, integer width+3]'])
+            b22_comb.append((floatingPoint_tohex(iflen,float(op)),))
+
+        bits = random.getrandbits(52)
+        bits = bin(bits)[2:]
+        front_zero = 52-len(bits)
+        sig = '0'*front_zero + bits
+        exp = random.randint(0,1020)
+        exp = '{:011b}'.format(exp)
+        sgn = random.getrandbits(1)
+        sgn = '{:01b}'.format(sgn)
+        ir_bin = ('0b'+sgn+exp+sig)
+        op = fields_dec_converter(iflen,'0x'+hex(int('1'+ir_bin[2:],2))[3:])
+        op_dataset.append([op, ' | Exponent: ' + str(int(exp,2)-1023) + ', Exponent less than -3'])
+        b22_comb.append((floatingPoint_tohex(iflen,float(op)),))
+
+        bits = random.getrandbits(52)
+        bits = bin(bits)[2:]
+        front_zero = 52-len(bits)
+        sig = '0'*front_zero + bits
+        exp = random.randint(xlen+1026,2047)
+        exp = '{:011b}'.format(exp)
+        sgn = random.getrandbits(1)
+        sgn = '{:01b}'.format(sgn)
+        ir_bin = ('0b'+sgn+exp+sig)
+        op = fields_dec_converter(iflen,'0x'+hex(int('1'+ir_bin[2:],2))[3:])
+        op_dataset.append([op, ' | Exponent: ' + str(int(exp,2)-1023) + ', Exponent greater than (integer width+3)'])
+        b22_comb.append((floatingPoint_tohex(iflen,float(op)),))
+
+    coverpoints = []
+    k=0
+    for c in b22_comb:
+        cvpt = ""
+        for x in range(1, 2):
+#                    cvpt += 'rs'+str(x)+'_val=='+str(c[x-1]) # uncomment this if you want rs1_val instead of individual fields
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        # cvpt += 'rm_val == 0'
+        cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += op_dataset[k][1]
+        coverpoints.append(cvpt)
+        k=k+1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+ \
+    (str(32) if iflen == 32 else str(64)) + '-bit coverpoints using Model B22 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b23(flen, iflen, opcode, ops):
+    '''
+    IBM Model B23 Definition:
+            This model creates boundary cases for the rounding to integers that might cause Overflow.
+            A test case will be created with inputs equal to the maximum integer number in the destination's format (MaxInt), or close to it. In particular, the following FP numbers will be used:
+
+            1. ±MaxInt
+            2. ±MaxInt ± 0.01 (¼)
+            3. ±MaxInt ± 0.1 (½)
+            4. ±MaxInt ± 0.11 (¾)
+            5. ±MaxInt ± 1
+
+            Rounding Mode: All
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+
+    Abstract Dataset Description:
+            Operand 1 = [ MaxInt-4, MaxInt+5 ]
+
+    Implementation:
+            - In the range of (-4,5), the dataset array is appended with the hexadecimal equivalent of maxnum plus the iteration number in a string format. The next highest encoding of the hexadecimal value is calculated.
+            - This is done with different values of maxnum for iflen=32 or iflen=64.
+            - Since this model is meant for floating point conversion instructions, only one operand is expected.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+
+    opcode = opcode.split('.')[0] + '.' + opcode.split('.')[1]
+
+    getcontext().prec = 40
+
+    operations = ['+','-']
+    nums = [0,100,200,800,1600]
+    dataset = []
+
+    if iflen == 32:
+        maxnum = 0x4f000000                                        # MaxInt (2**31-1) in IEEE 754 Floating Point Representation
+
+        for i in range(-4,5):
+                    dataset.append((hex(int(maxnum)+i),"| MaxInt + ({})".format(str(i))))
+    elif iflen == 64:
+        maxnum = 0x43e0000000000000
+
+        for i in range(-4,5):
+                    dataset.append((hex(int(maxnum)+i),"| MaxInt + ({})".format(str(i))))
+    elif iflen == 128:
+        maxnum = 0x40fc0000000000000000000000000000
+
+        for i in range(-4,5):
+                    dataset.append((hex(int(maxnum)+i),"| MaxInt + ({})".format(str(i))))
+    
+
+    coverpoints = []
+    k=0
+    for c in dataset:
+        for rm in range(0,5):
+            cvpt = ""
+            for x in range(1, ops+1):
+                cvpt += (extract_fields(iflen,c[0],str(x)))
+                cvpt += " and "
+            # cvpt += 'rm_val == '
+            if "fmv" in opcode or opcode in "fcvt.d.s":
+                cvpt = sanitise(0,cvpt,iflen,flen,ops)
+                # cvpt += '0'
+            else:
+                cvpt = sanitise(rm,cvpt,iflen,flen,ops)
+                # cvpt += str(rm)
+            cvpt += ' # '
+            for y in range(1, ops+1):
+                cvpt += 'rs'+str(y)+'_val=='
+                cvpt += num_explain(iflen, c[0]) + '(' + str(c[0]) + ')'
+                if(y != ops):
+                    cvpt += " and "
+            cvpt += " "+c[1]
+            coverpoints.append(cvpt)
+            k=k+1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+\
+    (str(32) if iflen == 32 else str(64) if iflen == 64 else str(128)) + '-bit coverpoints using Model B23 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return (coverpoints)
+
+def ibm_b24(flen,iflen, opcode, ops):
+    '''
+    IBM Model B24 Definition:
+            This model creates boundary cases for rounding to integer that might cause major loss of accuracy.
+
+            A test-case will be created for each of the following inputs:
+
+            1. ±0
+            2. ±0 ± 0.01 (¼)
+            3. ±0 ± 0.1 (½)
+            4. ±0 ± 0.11 (¾)
+            5. ±1
+            6. ±1 + 0.01 (¼)
+            7. ±1 + 0.1 (½)
+            8. ±1 + 0.11 (¾)
+
+            Rounding Mode: All
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+
+    Abstract Dataset Description:
+            Operand 1 = [±0,  ±0 ± 0.01, ±0 ± 0.1, ±0 ± 0.11, ±1, ±1 + 0.01, ±1 + 0.1, ±1 + 0.11]
+
+    Implementation:
+            - A nested loop with 4 stages is initiated to iterate each element in minimums, nums, operations1 and operations2 for the two operands. This is done to form the dataset defined above.
+            - Depending on the value of iflen, these values are then converted into their respective IEEE 754 hexadecimal values.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+
+    opcode = opcode.split('.')[0] + '.' + opcode.split('.')[1]
+
+    getcontext().prec = 40
+
+    operations = ['+','-']
+    nums = [0,0.01,0.1,0.11]
+    minnums = [0,1]
+    dataset = []
+
+    for minnum in minnums:
+        for num in nums:
+            for op1 in operations:
+                for op2 in operations:
+                    dataset.append((eval(op1+str(minnum)+op2+str(num)),op1+str(minnum)+op2+str(num)))
+
+    b24_comb = []
+
+    for data in dataset:
+        float_no = float(data[0])
+        hex_value = floatingPoint_tohex(iflen, float_no)
+        b24_comb.append((hex_value, data[1]))
+        #t = "{:e}".format(data[0])
+        #b24_comb.append((floatingPoint_tohex(iflen,float(t)),data[1]))
+
+    b24_comb = set(b24_comb)
+
+    coverpoints = []
+    k=0
+    for c in b24_comb:
+        for rm in range(0,5):
+            cvpt = ""
+            for x in range(1, ops+1):
+                cvpt += (extract_fields(iflen,c[x-1],str(x)))
+                cvpt += " and "
+            # cvpt += 'rm_val == '
+            if "fmv" in opcode or opcode in "fcvt.d.s" or opcode in "fcvt.q.d" or opcode in "fcvt.q.s":
+                cvpt = sanitise(0,cvpt,iflen,flen,ops)
+                # cvpt += '0'
+            else:
+                cvpt = sanitise(rm,cvpt,iflen,flen,ops)
+                # cvpt += str(rm)
+            cvpt += ' # '
+            for y in range(1, ops+1):
+                cvpt += 'rs'+str(y)+'_val=='
+                cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+                if(y != ops):
+                    cvpt += " and "
+            cvpt += " | "+c[1]
+            coverpoints.append(cvpt)
+            k=k+1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+\
+    (str(32) if iflen == 32 else str(64) if iflen == 64 else str(128)) + '-bit coverpoints using Model B24 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return (coverpoints)
+
+def ibm_b25(flen, iflen, opcode, ops, seed=10):
+    '''
+    IBM Model B25 Definition:
+            This model creates a test-case for each of the following inputs(wherever applicable):
+
+            1. ±MaxInt
+            2. ±0
+            3. ±1
+            4. Random number
+
+    :param flen: Size of the floating point registers
+    :param iflen: Size of the floating point source operands for the operation
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to 10)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Operand 1 = [±MaxInt, ±0, ±1, Random number]
+
+    Implementation:
+            - The dataset is formed as per the dataset description.
+            - rand_num is initialized to a random number in the range (1, maxnum).
+            - Since this model is for an integer to floating point conversion instruction, the operands are presented in decimal format.
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    is_unsigned = opcode.endswith("u")
+    random.seed(seed)
+    getcontext().prec = 40
+
+    operations = ['+','-']
+    nums = [0,0.01,0.1,0.11]
+
+    dataset = [(0,"0"),(1,"1")] +( [(-1,"-1")] if not is_unsigned else [])
+
+    bitwidth = iflen if is_unsigned else iflen-1
+    maxnum = 2**(bitwidth)-1
+
+    dataset.append((maxnum,"MaxInt"))
+    if not is_unsigned:
+        dataset.append((-1*maxnum,"-MaxInt"))
+    rand_num = int(random.uniform(1,maxnum))
+    dataset.append((rand_num,"+ve Random Number"))
+    if not is_unsigned:
+        dataset.append((-1*rand_num,"-ve Random Number"))
+
+    b25_comb = []
+
+    for data in dataset:
+        b25_comb.append((int(data[0]),data[1]))
+
+    coverpoints = []
+    k=0
+    for c in b25_comb:
+        for rm in range(0,5):
+            cvpt = ""
+            for x in range(1, ops+1):
+                cvpt += "rs1_val == "+str(c[x-1])
+                cvpt += " and "
+            # cvpt += 'rm_val == '
+            if "fmv" in opcode or opcode in "fcvt.d.wu":
+                cvpt = sanitise(0,cvpt,iflen,flen,ops)
+                # cvpt += str(0)
+            else:
+                cvpt = sanitise(rm,cvpt,iflen,flen,ops)
+                # cvpt += str(rm)
+            cvpt += ' # Number = '
+            cvpt += c[1]
+            coverpoints.append(cvpt)
+            k=k+1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+\
+    (str(32) if iflen == 32 else str(64) if iflen == 64 else str(128)) + '-bit coverpoints using Model B25 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return (coverpoints)
+
+def ibm_b26(xlen, opcode, ops, seed=10):
+    '''
+    IBM Model B26 Definition:
+            This model creates a test-case for each possible value of the number of significant bits in the input operand (which is an integer). A test is created with an example from each of the following
+            ranges: [0], [1], [2,3], [4,7], [8,15], …, [(MaxInt+1)/2, MaxInt]
+
+    :param xlen: Size of the integer registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to 10)
+
+    :type xlen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Operand 1 = Random number in [0], [1], [2,3], [4,7], [8,15], …, [(MaxInt+1)/2, MaxInt]
+
+    Implementation:
+            - A random number is chosen in the ranges defined above.
+            - Since this model is for an integer to floating point conversion instruction, the operands are presented in decimal format.
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    random.seed(seed)
+    dataset = [(0," # Number in [0]"),(1," # Number in [1]")]
+
+    i = 3
+    while(i<=2**(xlen-1)-1):
+        rand_num = random.randint(int((i+1)/2),i)
+        dataset.append((rand_num," # Random number chosen in the range: ["+str(int((i+1)/2))+", "+str(i)+"]"))
+        i = i*2+1
+
+    coverpoints = []
+    k=0
+    for c in dataset:
+        for rm in range(0,5):
+            cvpt = ""
+            for x in range(1, ops+1):
+                cvpt += "rs1_val == "+str(c[x-1])
+                cvpt += " and "
+            # cvpt += 'rm_val == '
+            if "fmv" in opcode or opcode in "fcvt.d.wu" or opcode in "fcvt.q.wu":
+                cvpt = sanitise(0,cvpt,xlen,xlen,ops)
+                # cvpt += str(0)
+            else:
+                cvpt = sanitise(rm,cvpt,xlen,xlen,ops)
+                # cvpt += str(rm)
+            cvpt += c[1]
+            coverpoints.append(cvpt)
+            k=k+1
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+\
+    (str(32) if xlen == 32 else str(64) if xlen == 64 else str(128)) + '-bit coverpoints using Model B26 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b27(flen, iflen, opcode, ops, seed=10):
+    '''
+    IBM Model B27 Definition:
+            This model tests the conversion of NaNs from a wider format to a narrow one. Each combination from the following table will create one test case (N represents the number of bits in the significand of the destination's format):
+            [SNaN, QNaN]
+
+            ==================== ========================================================= =====================
+            Value of the operand The N-1 MSB bits of the significand (excluding the first) The rest of the bits
+            ==================== ========================================================= =====================
+            QNaN         All 0                                                       All 0
+            SNan                 Not all 0                                                 Not all 0
+            ==================== ========================================================= =====================
+
+    :param iflen: Size of the floating point source operands for the operation
+    :param flen: Size of the floating point registers
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to 10)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Operand 1 = [ SNaN, QNaN ]
+
+    Implementation:
+            - Dataset is the combination of snan and qnan values predefined at random initially.
+            - Depending on the value of iflen, these values are then converted into their respective IEEE 754 hexadecimal values.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    opcode = opcode.split('.')[0] + '.' + opcode.split('.')[1]
+
+    if iflen == 32:
+        dataset = fsnan + fqnan
+    elif iflen == 64:
+        dataset = dsnan + dqnan
+    elif iflen == 128:
+        dataset = qsnan + qqnan
+
+    coverpoints = []
+    for c in dataset:
+        cvpt = ""
+        for x in range(1, ops+1):
+            cvpt += (extract_fields(iflen,c,str(x)))
+            cvpt += " and "
+        # cvpt += 'rm_val == 0'
+        cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c) + '(' + str(c) + ')'
+            if(y != ops):
+                cvpt += " and "
+        coverpoints.append(cvpt)
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+\
+    (str(32) if iflen == 32 else str(64) if iflen == 64 else str(128)) + '-bit coverpoints using Model B27 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b28(flen, iflen, opcode, ops, seed=10):
+    '''
+    IBM Model B28 Definition:
+            This model tests the conversion of a floating point number to an integral value, represented in floating-point format. A test case will be created for each of the following inputs:
+
+            1. +0
+            2. A random number in the range (+0, +1)
+            3. +1
+            4. Every value in the range (1.00, 10.11] (1 to 2.75 in jumps of 0.25)
+            5. A random number in the range (+1, +1.11..11*2^precision)
+            6. +1.11..11*2^precision
+            7. +Infinity
+            8. NaN
+            9. -0
+            10. A random number in the range (-1, -0)
+            11. -1
+            12. Every value in the range [-10.11, -1.00)
+            13. A random number in the range (-1.11..11*2^precision , -1)
+            14.-1.11..11*2^precision
+            15. –Infinity
+
+    :param flen: Size of the floating point registers
+    :param iflen: Size of the floating point source operands for the operation
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to 10. Actual value is set with respect to the opcode calling the function)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Operand 1 = [ ±0, ±1, ±Infinity, Default NaN, A random number in the range (+0, +1), Every value in the range (1.00, 10.11] (1 to 2.75 in jumps of 0.25), A random number in the range (+1, +1.11..11*2^precision), ±1.11..11*2^precision, A random number in the range (-1, -0), Every value in the range [-10.11, -1.00), A random number in the range (-1.11..11*2^precision , -1) ]
+
+    Implementation:
+            - According to the given inputs, all cases are declared and appended to the dataset for iflen=32 and iflen=64.
+            - Random numbers are obtained in the respective ranges and for absolute values, it is inherited from the dataset definition.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with rounding mode “0” for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    random.seed(seed)
+    opcode = opcode.split('.')[0] + '.' + opcode.split('.')[1]
+    dataset = []
+
+    if iflen == 32:
+        dataset.append((fzero[0],"+0"))
+        dataset.append((floatingPoint_tohex(32,float(random.uniform(0,1))),"A random number in the range (+0, +1)"))
+        dataset.append((fone[0],"+1"))
+        for i in range(125,300,25):
+            dataset.append((floatingPoint_tohex(32, i/100),"Number = "+str(i/100)+" => Number ∈ (1,2.75]"))
+        dataset.append((floatingPoint_tohex(32,float(random.uniform(1,2**31-1))),"A random number in the range (+1, +1.11..11*2^precision)"))
+        dataset.append((floatingPoint_tohex(32,float(2**31-1)),"MaxInt"))
+        dataset.append((finfinity[0],"+Infinity"))
+
+        dataset.append((fsnan[0],"Signaling NaN"))
+        dataset.append((fqnan[0],"Quiet NaN"))
+
+        dataset.append((fzero[1],"-0"))
+        dataset.append((floatingPoint_tohex(32,float(random.uniform(-1,0))),"A random number in the range (-1, -0)"))
+        dataset.append((fone[1],"-1"))
+        for i in range(-275,-100,25):
+            dataset.append((floatingPoint_tohex(32, i/100),"Number = "+str(i/100)+" => Number ∈ [-2.75,-1)"))
+        dataset.append((floatingPoint_tohex(32,float(random.uniform(-2**31-1,-1))),"A random number in the range (-1.11..11*2^precision, -1)"))
+        dataset.append((floatingPoint_tohex(32,float(-2**31-1)),"-MaxInt"))
+        dataset.append((finfinity[1],"-Infinity"))
+
+    elif iflen == 64:
+        dataset.append((dzero[0],"+0"))
+        dataset.append((floatingPoint_tohex(64,float(random.uniform(0,1))),"A random number in the range (+0, +1)"))
+        dataset.append((done[0],"+1"))
+        for i in range(125,300,25):
+            dataset.append((floatingPoint_tohex(64, i/100),"Number = "+str(i/100)+" => Number ∈ (1,2.75]"))
+        dataset.append((floatingPoint_tohex(64,float(random.uniform(1,2**63-1))),"A random number in the range (+1, +1.11..11*2^precision)"))
+        dataset.append((floatingPoint_tohex(64,float(2**63-1)),"MaxInt"))
+        dataset.append((dinfinity[0],"+Infinity"))
+
+        dataset.append((dsnan[0],"Signaling NaN"))
+        dataset.append((dqnan[0],"Quiet NaN"))
+
+        dataset.append((dzero[1],"-0"))
+        dataset.append((floatingPoint_tohex(64,float(random.uniform(-1,0))),"A random number in the range (-1, -0)"))
+        dataset.append((done[1],"-1"))
+        for i in range(-275,-100,25):
+            dataset.append((floatingPoint_tohex(64, i/100),"Number = "+str(i/100)+" => Number ∈ [-2.75,-1)"))
+        dataset.append((floatingPoint_tohex(64,float(random.uniform(-2**63-1,-1))),"A random number in the range (-1.11..11*2^precision, -1)"))
+        dataset.append((floatingPoint_tohex(64,float(-2**63-1)),"-MaxInt"))
+        dataset.append((dinfinity[1],"-Infinity"))
+    elif iflen == 128:
+        dataset.append((qzero[0],"+0"))
+        dataset.append((floatingPoint_tohex(128,float(random.uniform(0,1))),"A random number in the range (+0, +1)"))
+        dataset.append((qone[0],"+1"))
+        for i in range(125,300,25):
+            dataset.append((floatingPoint_tohex(128, i/100),"Number = "+str(i/100)+" => Number ∈ (1,2.75]"))
+        dataset.append((floatingPoint_tohex(128,float(random.uniform(1,2**127-1))),"A random number in the range (+1, +1.11..11*2^precision)"))
+        dataset.append((floatingPoint_tohex(128,float(2**127-1)),"MaxInt"))
+        dataset.append((qinfinity[0],"+Infinity"))
+
+        dataset.append((qsnan[0],"Signaling NaN"))
+        dataset.append((qqnan[0],"Quiet NaN"))
+
+        dataset.append((qzero[1],"-0"))
+        dataset.append((floatingPoint_tohex(128,float(random.uniform(-1,0))),"A random number in the range (-1, -0)"))
+        dataset.append((qone[1],"-1"))
+        for i in range(-275,-100,25):
+            dataset.append((floatingPoint_tohex(128, i/100),"Number = "+str(i/100)+" => Number ∈ [-2.75,-1)"))
+        dataset.append((floatingPoint_tohex(128,float(random.uniform(-2**127-1,-1))),"A random number in the range (-1.11..11*2^precision, -1)"))
+        dataset.append((floatingPoint_tohex(128,float(-2**127-1)),"-MaxInt"))
+        dataset.append((qinfinity[1],"-Infinity"))
+
+    coverpoints = []
+    for c in dataset:
+        cvpt = ""
+        for x in range(1, ops+1):
+            cvpt += (extract_fields(iflen,c[x-1],str(x)))
+            cvpt += " and "
+        # cvpt += 'rm_val == 0'
+        cvpt = sanitise(0,cvpt,iflen,flen,ops)
+        cvpt += ' # '
+        for y in range(1, ops+1):
+            cvpt += 'rs'+str(y)+'_val=='
+            cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+            if(y != ops):
+                cvpt += " and "
+        cvpt += " | "+c[1]
+        coverpoints.append(cvpt)
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+\
+    (str(32) if iflen == 32 else str(64) if iflen == 64 else str(128)) + '-bit coverpoints using Model B28 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
+
+def ibm_b29(flen, iflen, opcode, ops, seed=10):
+    '''
+    IBM Model B29 Definition:
+            This model checks different cases of rounding of the floating point number. A test will be created for each possible combination of the Sign, LSB, Guard bit and the Sticky bit (16 cases for each operation).
+
+            Rounding Mode: All
+
+    :param flen: Size of the floating point registers
+    :param iflen: Size of the floating point source operands for the operation
+    :param opcode: Opcode for which the coverpoints are to be generated
+    :param ops: No. of Operands taken by the opcode
+    :param seed: Initial seed value of the random library. (Predefined to 10)
+
+    :type iflen: int
+    :type flen: int
+    :type opcode: str
+    :type ops: int
+    :param seed: int
+
+    Abstract Dataset Description:
+            Operand 1 = [All possible combinations of Sign, LSB, Guard and Sticky are taken]
+
+    Implementation:
+            - A random mantissa is obtained and is iterated for each sign in each digit in the binary number.
+            - The exponent is always maintained at -3, in order to facilitate the shift process that occurs during the actual conversion.
+            - The respective hexadecimal values are appended to the dataset along with the respective  Least, Guard and Sticky bit value wherever available.
+            - The operand values are then passed into the extract_fields function to get individual fields in a floating point number (sign, exponent and mantissa).
+            - Coverpoints are then appended with all rounding modes for that particular opcode.
+
+    '''
+    sanitise = get_sanitise_func(opcode)
+    random.seed(seed)
+    sgns = ["0","1"]
+    dataset = []
+    if iflen == 32:
+        mant = random.getrandbits(20)
+        mant = '{:020b}'.format(mant)
+        for sgn in sgns:
+            for i in range(8):
+                LeastGuardSticky = '{:03b}'.format(i)
+                hexnum = "0x" + hex(int("1"+sgn + "01111100" + mant + LeastGuardSticky,2))[3:]
+                dataset.append((hexnum,"Exp = -3; Sign = {}; LSB = {}; Guard = {}; Sticky = {}"\
+                    .format(sgn,LeastGuardSticky[0],LeastGuardSticky[1],LeastGuardSticky[2])))
+    elif iflen == 64:
+        mant = random.getrandbits(49)
+        mant = '{:049b}'.format(mant)
+        for sgn in sgns:
+            for i in range(8):
+                LeastGuardSticky = '{:03b}'.format(i)
+                hexnum = "0x" + hex(int("1"+sgn + "01111111100" + mant + LeastGuardSticky,2))[3:]
+                dataset.append((hexnum,"Exp = -3; Sign = {}; LSB = {}; Guard = {}; Sticky = {}"\
+                    .format(sgn,LeastGuardSticky[0],LeastGuardSticky[1],LeastGuardSticky[2])))
+    elif iflen == 128:
+        mant = random.getrandbits(49)
+        mant = '{:049b}'.format(mant)
+        for sgn in sgns:
+            for i in range(8):
+                LeastGuardSticky = '{:03b}'.format(i)
+                hexnum = "0x" + hex(int("1"+sgn + "011111111111100" + mant + LeastGuardSticky,2))[3:]
+                dataset.append((hexnum,"Exp = -3; Sign = {}; LSB = {}; Guard = {}; Sticky = {}"\
+                    .format(sgn,LeastGuardSticky[0],LeastGuardSticky[1],LeastGuardSticky[2])))
+
+    coverpoints = []
+    for c in dataset:
+        for rm in range(0,5):
+            cvpt = ""
+            for x in range(1, ops+1):
+                cvpt += (extract_fields(iflen,c[x-1],str(x)))
+                cvpt += " and "
+            # cvpt += 'rm_val == '
+            if "fmv" in opcode or "fcvt.d.s" in opcode:
+                cvpt = sanitise(0,cvpt,iflen,flen,ops)
+                # cvpt += '0'
+            else:
+                cvpt = sanitise(rm,cvpt,iflen,flen,ops)
+                # cvpt += str(rm)
+            cvpt += ' # '
+            for y in range(1, ops+1):
+                cvpt += 'rs'+str(y)+'_val=='
+                cvpt += num_explain(iflen, c[y-1]) + '(' + str(c[y-1]) + ')'
+                if(y != ops):
+                    cvpt += " and "
+            cvpt += " | "+c[1]
+            coverpoints.append(cvpt)
+
+    mess='Generated'+ (' '*(5-len(str(len(coverpoints)))))+ str(len(coverpoints)) +' '+\
+    (str(32) if iflen == 32 else str(64) if iflen == 64 else str(128)) + '-bit coverpoints using Model B29 for '+opcode+' !'
+    logger.debug(mess)
+    coverpoints = comments_parser(coverpoints)
+
+    return coverpoints
diff --git a/tests/fp/quad/fpdatasetgen.py b/tests/fp/quad/fpdatasetgen.py
new file mode 100755
index 000000000..6208b1ba3
--- /dev/null
+++ b/tests/fp/quad/fpdatasetgen.py
@@ -0,0 +1,14 @@
+#!/usr/bin/python
+
+from fp_dataset import *
+#coverpoints=ibm_b1(128, 128, 'fadd.q', 2) #ibm_b1(flen, iflen, opcode, ops)
+coverpoints=ibm_b2(128,128,'fadd.q',2) #ibm_b2(flen, iflen, opcode, ops, int_val = 100, seed = -1)
+#coverpoints=ibm_b2(32,32,'fadd.s',2) #ibm_b2(flen, iflen, opcode, ops,seed = -1)
+#print(coverpoints)
+#quad_precision_hex = "0x3ff00000000000000000000000000001"  # Example quad precision hexadecimal value
+#quad_precision_dec = fields_dec_converter(128, quad_precision_hex)
+#print(quad_precision_dec)
+for cvpts in coverpoints:
+    print(cvpts)
+    print("\n")
+print(len(coverpoints))
diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile
index 26ec99954..89dd6835e 100644
--- a/tests/riscof/Makefile
+++ b/tests/riscof/Makefile
@@ -9,7 +9,7 @@ current_dir = $(shell pwd)
 #XLEN    ?= 64
 
 all: root arch32 wally32 arch32e arch64 wally64
-wally-riscv-arch-test: root wally32 wally64
+wally-riscv-arch-test: root wally64 wally32
 
 root:
 	mkdir -p $(work_dir)
diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py
index 878e25d4f..eeb024d36 100644
--- a/tests/riscof/sail_cSim/riscof_sail_cSim.py
+++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py
@@ -52,6 +52,7 @@ def build(self, isa_yaml, platform_yaml):
         ispec = utils.load_yaml(isa_yaml)['hart0']
         self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
         self.isa = 'rv' + self.xlen
+        self.sailargs = ' '
         self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 '))
         if "I" in ispec["ISA"]:
             self.isa += 'i'
@@ -67,6 +68,8 @@ def build(self, isa_yaml, platform_yaml):
             self.isa += 'f'
         if "D" in ispec["ISA"]:
             self.isa += 'd'
+        if "Zcb" in ispec["ISA"]:   # for some strange reason, Sail requires a command line argument to enable Zcb
+            self.sailargs += "--enable-zcb"
         objdump = "riscv64-unknown-elf-objdump".format(self.xlen)
         if shutil.which(objdump) is None:
             logger.error(objdump+": executable not found. Please check environment setup.")
@@ -112,7 +115,8 @@ def runTests(self, testList, cgf_file=None):
                 reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test))
                 execute += 'cut -c-{0:g} {1} > {2}'.format(8, reference_output, sig_file) #use cut to remove comments when copying
             else:
-                execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
+                execute += self.sail_exe[self.xlen] + ' -z268435455 -i ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
+#                execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
 
             cov_str = ' '
             for label in testentry['coverage_labels']:
diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml
index 1879440ed..1e2474023 100644
--- a/tests/riscof/spike/spike_rv32gc_isa.yaml
+++ b/tests/riscof/spike/spike_rv32gc_isa.yaml
@@ -1,8 +1,6 @@
 hart_ids: [0]
 hart0:
-  ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
-#  ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs
-#  ISA: RV32IMAFDCZicsr_Zicboz_Zifencei_Zca_Zba_Zbb_Zbc_Zbs # _Zbkb_Zcb
+  ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
   physical_addr_sz: 32
   User_Spec_Version: '2.3'
   supported_xlen: [32]
@@ -27,4 +25,4 @@ hart0:
               legal:
                 - extensions[25:0] bitmask [0x000112D, 0x0000000]
               wr_illegal:
-                - Unchanged
\ No newline at end of file
+                - Unchangedcd 
\ No newline at end of file
diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml
index b8fabebde..5b3f2f47d 100644
--- a/tests/riscof/spike/spike_rv64gc_isa.yaml
+++ b/tests/riscof/spike/spike_rv64gc_isa.yaml
@@ -1,8 +1,6 @@
 hart_ids: [0]
 hart0:
-#  ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb
-#  ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb
-  ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
+  ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
   physical_addr_sz: 56
   User_Spec_Version: '2.3'
   supported_xlen: [64]
diff --git a/tests/testgen/Makefile b/tests/testgen/Makefile
new file mode 100644
index 000000000..0e10048af
--- /dev/null
+++ b/tests/testgen/Makefile
@@ -0,0 +1,39 @@
+#all:
+#	./covergen.py
+#	cd ../riscof; make wally-riscv-arch-test
+#	cd ../../sim; make memfiles
+
+CEXT		:= c
+CPPEXT		:= cpp
+AEXT		:= s
+SEXT		:= S
+SRCEXT 		:= \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\)
+#SRCS = $(wildcard *.S)
+#PROGS = $(patsubst %.S,%,$(SRCS))
+SRCDIR = ${WALLY}/tests/functcov/rv64/I
+SRCEXT = S
+SOURCES		?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort)
+OBJEXT = elf
+OBJECTS		:= $(SOURCES:.$(SEXT)=.$(OBJEXT))
+
+all: 
+	./covergen.py
+	make build
+
+build: $(OBJECTS)
+
+%.elf.objdump: %.elf
+
+# Change many things if bit width isn't 64
+$(SRCDIR)/%.elf: $(SRCDIR)/%.$(SEXT) 
+	riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom -mabi=lp64 -mcmodel=medany \
+	    -nostartfiles -T${WALLY}/examples/link/link.ld $<
+	riscv64-unknown-elf-objdump -S -D $@ > $@.objdump
+	riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile
+	extractFunctionRadix.sh $@.objdump
+    
+clean:
+	rm -f ${SRCDIR}/*.elf ${SRCDIR}/*.objdump ${SRCDIR}/*.addr *${SRCDIR}/.lab ${SRCDIR}/*.memfile
+
+
+
diff --git a/tests/testgen/covergen.py b/tests/testgen/covergen.py
index b17afb3b7..1e06e7b9c 100755
--- a/tests/testgen/covergen.py
+++ b/tests/testgen/covergen.py
@@ -14,134 +14,301 @@
 from random import randint 
 from random import seed
 from random import getrandbits
+import os
+import re
 
 ##################################
 # functions
 ##################################
 
-def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen):
-  rdval = randint(0, 2**xlen-1)
-  lines = "\n# Testcase " + str(desc) + "\n"
-  lines = lines + "li x" + str(rd) + ", MASK_XLEN(" + formatstr.format(rdval) + ")  # initialize rd to a random value that should get changed\n"
-  lines = lines + "li x" + str(rs1) + ", MASK_XLEN(" + formatstr.format(rs1val) + ")  # initialize rs1 to a random value \n"
-  lines = lines + "li x" + str(rs2) + ", MASK_XLEN(" + formatstr.format(rs2val) + ") # initialize rs2 to a random value\n"
-  lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", x" + str(rs2) + " # perform operation\n" 
-  f.write(lines)
-
-def make_cp_rd(rd, test, storecmd, xlen):
-  rs1 = randint(0, 31)
-  rs2 = randint(0, 31)
-  rs1val = randint(0, 2**xlen-1)
-  rs2val = randint(0, 2**xlen-1)
-  desc = "cp_rd (Test destination rd = x" + str(rd) + ")"
-  writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
-
-def make_cp_rs1(rs1, test, storecmd, xlen):
-  rd = randint(0, 31)
-  rs2 = randint(0, 31)
-  rs1val = randint(0, 2**xlen-1)
-  rs2val = randint(0, 2**xlen-1)
-  desc = "cp_rs1 (Test source rs1 = x" + str(rs1) + ")"
-  writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
-
-def make_cp_rs2(rs2, test, storecmd, xlen):
-  rd = randint(0, 31)
-  rs1 = randint(0, 31)
-  rs1val = randint(0, 2**xlen-1)
-  rs2val = randint(0, 2**xlen-1)
-  desc = "cp_rs2 (Test source rs2 = x" + str(rs2) + ")"
-  writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
-
-def make_cmp_rd_rs1(r, test, storecmd, xlen):
-  rd = r
-  rs1 = r
-  rs2 = randint(0, 31)
-  rs1val = randint(0, 2**xlen-1)
-  rs2val = randint(0, 2**xlen-1)
-  desc = "cmp_rd_rs1 (Test destination rd = source rs1 = x" + str(r) + ")"
-  writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
-
-def make_cmp_rd_rs2(r, test, storecmd, xlen):
-  rd = r
-  rs1 = randint(0, 31)
-  rs2 = r
-  rs1val = randint(0, 2**xlen-1)
-  rs2val = randint(0, 2**xlen-1)
-  desc = "cmp_rd_rs2 (Test destination rd = source rs2 = x" + str(r) + ")"
-  writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
-
-def make_cmp_rd_rs1_rs2(r, test, storecmd, xlen):
-  rd = r
-  rs1 = r
-  rs2 = r
-  rs1val = randint(0, 2**xlen-1)
-  rs2val = randint(0, 2**xlen-1)
-  desc = "cmp_rd_rs1_rs2 (Test destination rd = source rs1 = source rs2 = x" + str(r) + ")"
-  writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
-
-def make_cp_gpr_hazard(test, storecmd, xlen):
-  rs1val = randint(0, 2**xlen-1)
-  rs2val = randint(0, 2**xlen-1)
-  desc = "cp_gpr_hazard"
-  writeCovVector(desc, 20, 21, 22, rs1val, rs2val, test, storecmd, xlen)
-  lines = test + " x23, x22, x20 # RAW\n" 
-  lines = lines + test + " x22, x23, x20 # WAR\n" 
-  lines = lines + test + " x22, x21, x20 # WAW\n" 
-  f.write(lines)
-
-def make_cp_rs1_maxvals(test, storecmd, xlen):
-  for rs1val in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]:
-    rd = randint(1, 31)
-    rs1 = randint(0, 31)
-    rs2 = randint(0, 31)
-    rs2val = randint(0, 2**xlen-1)
-    desc = "cp_rs1_maxvals (rs1 = " + str(rs1val) + ")"
-    writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
+def shiftImm(imm, xlen):
+  imm = imm % xlen
+  return str(imm)
 
-def make_cp_rs2_maxvals(test, storecmd, xlen):
-  for rs2val in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]:
-    rd = randint(1, 31)
-    rs1 = randint(0, 31)
-    rs2 = randint(0, 31)
-    rs1val = randint(0, 2**xlen-1)
-    desc = "cp_rs2_maxvals (rs2 = " + str(rs2val) + ")"
-    writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
+def signedImm12(imm):
+  imm = imm % pow(2, 12)
+  if (imm & 0x800):
+    imm = imm - 0x1000
+  return str(imm)
 
+def signedImm20(imm):
+  imm = imm % pow(2, 20)
+  if (imm & 0x80000):
+    imm = imm - 0x100000
+  return str(imm)
 
-def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen):
-  rdval = randint(0, 2**xlen-1)
+def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen):
   lines = "\n# Testcase " + str(desc) + "\n"
-  lines = lines + "li x" + str(rd) + ", MASK_XLEN(" + formatstr.format(rdval) + ")  # initialize rd to a random value that should get changed\n"
-  lines = lines + "li x" + str(rs1) + ", MASK_XLEN(" + formatstr.format(rs1val) + ")  # initialize rs1 to a random value \n"
-  lines = lines + "li x" + str(rs2) + ", MASK_XLEN(" + formatstr.format(rs2val) + ") # initialize rs2 to a random value\n"
-  lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", x" + str(rs2) + " # perform operation\n" 
+  if (rs1val < 0):
+    rs1val = rs1val + 2**xlen
+  if (rs2val < 0):
+    rs2val = rs2val + 2**xlen
+  lines = lines + "li x" + str(rd) + ", " + formatstr.format(rdval) + " # initialize rd to a random value that should get changed\n"
+  if (test in rtype):
+    lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value \n"
+    lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2 to a random value\n"
+    lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", x" + str(rs2) + " # perform operation\n" 
+  elif (test in shiftitype):
+    lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value \n"
+    lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + shiftImm(immval, xlen) + " # perform operation\n"
+  elif (test in itype):
+    lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value \n"
+    lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # perform operation\n"
+  elif (test in loaditype):#["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]
+    lines = lines + "auipc x" + str(rs1) + ", 0x20" + " # add upper immediate value to pc \n"
+    lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # add immediate to lower part of rs1 \n"
+    lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n"
+  elif (test in stypes):#["sb", "sh", "sw", "sd"]
+    #lines = lines + test + " x" + str(rs2) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n"
+    #lines = lines + test + " x" + str(rs2) + ", " "0(x" + str(rs1) + ") # perform operation \n"
+    print("Error: %s type not implemented yet" % test)
+  elif (test in btypes):#["beq", "bne", "blt", "bge", "bltu", "bgeu"]
+    if (randint(1,100) > 50):
+      rs1val = rs2val
+      lines = lines + "# same values in both registers\n"
+    lines = lines + "nop\n"
+    lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value that should get changed\n"
+    lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2 to a random value that should get changed\n"
+    lines = lines + test + " x" + str(rs1) + ", x" + str(rs2) + ", some_label_for_sb_types_" + str(immval) + "+4" + " # perform operation \n"
+    lines = lines + "addi x0, x1, 1\n"
+    lines = lines + "some_label_for_sb_types_" + str(immval) + ":\n"
+    lines = lines + "addi x0, x2, 2\n"
+    lines = lines + "nop\nnop\nnop\nnop\nnop\n"
+  else:
+    pass
+    #print("Error: %s type not implemented yet" % test)
   f.write(lines)
 
+def randomize():
+    rs1 = randint(1, 31)
+    rs2 = randint(1, 31)
+    # choose rd that is different than rs1 and rs2
+    rd = rs1
+    while (rd == rs1 or rd == rs2):
+      rd = randint(1, 31)
+    rd = randint(1, 31)
+    rs1val = randint(0, 2**xlen-1)
+    rs2val = randint(0, 2**xlen-1)
+    immval = randint(0, 2**xlen-1)
+    rdval = randint(0, 2**xlen-1)
+    return [rs1, rs2, rd, rs1val, rs2val, immval, rdval]
+
+def make_rd(test, storecmd, xlen):
+  for r in range(32):
+    [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+    desc = "cp_rd (Test destination rd = x" + str(r) + ")"
+    writeCovVector(desc, rs1, rs2, r, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
 
-def write_rtype_arith_vectors(test, storecmd, xlen):
+def make_rs1(test, storecmd, xlen):
   for r in range(32):
-    make_cp_rd(r, test, storecmd, xlen)
+    [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+    desc = "cp_rs1 (Test source rs1 = x" + str(r) + ")"
+    writeCovVector(desc, r, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
+
+def make_rs2(test, storecmd, xlen):
   for r in range(32):
-    make_cp_rs1(r, test, storecmd, xlen)
+    [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+    desc = "cp_rs2 (Test source rs2 = x" + str(r) + ")"
+    writeCovVector(desc, rs1, r, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
+
+def make_rd_rs1(test, storecmd, xlen):
   for r in range(32):
-    make_cp_rs2(r, test, storecmd, xlen)  
+    [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+    desc = "cmp_rd_rs1 (Test rd = rs1 = x" + str(r) + ")"
+    writeCovVector(desc, r, rs2, r, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
+
+def make_rd_rs2(test, storecmd, xlen):
   for r in range(32):
-    make_cmp_rd_rs2(r, test, storecmd, xlen)
+    [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+    desc = "cmp_rd_rs2 (Test rd = rs1 = x" + str(r) + ")"
+    writeCovVector(desc, rs1, r, r, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
+
+def make_rd_rs1_rs2(test, storecmd, xlen):
   for r in range(32):
-    make_cmp_rd_rs1(r, test, storecmd, xlen)
+    [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+    desc = "cmp_rd_rs1_rs2 (Test rd = rs1 = rs2 = x" + str(r) + ")"
+    writeCovVector(desc, r, r, r, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
+
+def make_rs1_rs2(test, storecmd, xlen):
   for r in range(32):
-    make_cmp_rd_rs1_rs2(r, test, storecmd, xlen)
-  make_cp_gpr_hazard(test, storecmd, xlen)
-  make_cp_rs1_maxvals(test, storecmd, xlen)
-  make_cp_rs2_maxvals(test, storecmd, xlen)
+    [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+    desc = "cmp_rd_rs1_rs2 (Test rs1 = rs2 = x" + str(r) + ")"
+    writeCovVector(desc, r, r, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
+
+def make_rs1_maxvals(test, storecmd, xlen):
+   for v in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]:
+    [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+    desc = "cp_rs1_maxvals (Test source rs1 value = " + hex(v) + ")"
+    writeCovVector(desc, rs1, rs2, rd, v, rs2val, immval, rdval, test, storecmd, xlen)
+
+def make_rs2_maxvals(test, storecmd, xlen):
+   for v in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]:
+    [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+    desc = "cp_rs2_maxvals (Test source rs2 value = " + hex(v) + ")"
+    writeCovVector(desc, rs1, rs2, rd, rs1val, v, immval, rdval, test, storecmd, xlen)
+
+def make_rd_maxvals(test, storecmd, xlen):
+   for v in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]:
+    [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+    desc = "cp_rd_maxvals (Test rd value = " + hex(v) + ")"
+    writeCovVector(desc, rs1, 0, rd, v, rs2val, immval, rdval, test, storecmd, xlen)
+
+def make_rd_rs1_eqval(test, storecmd, xlen):
+  [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+  desc = "cmp_rdm_rs1_eqval (Test rs1 = rd = " + hex(rs1val) + ")"
+  writeCovVector(desc, rs1, 0, rd, rdval, rs2val, immval, rdval, test, storecmd, xlen)
+
+def make_rd_rs2_eqval(test, storecmd, xlen):
+  [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+  desc = "cmp_rd_rs2_eqval (Test rs2 = rd = " + hex(rs2val) + ")"
+  writeCovVector(desc, 0, rs2, rd, rs1val, rdval, immval, rdval, test, storecmd, xlen)
+
+def make_rs1_rs2_eqval(test, storecmd, xlen):
+  [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+  desc = "cmp_rs1_rs2_eqval (Test rs1 = rs2 = " + hex(rs1val) + ")"
+  writeCovVector(desc, rs1, rs2, rd, rs1val, rs1val, immval, rdval, test, storecmd, xlen)
+
+#def make_cp_gpr_hazard(test, storecmd, xlen):
+#  pass # *** to be implemented ***
+
+def make_rs1_sign(test, storecmd, xlen):
+   for v in [1, -1]:
+    [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+    rs1val = abs(rs1val % 2**(xlen-1)) * v;
+    desc = "cp_rs1_sign (Test source rs1 value = " + hex(rs1val) + ")"
+    writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
+
+def make_rs2_sign(test, storecmd, xlen):
+  for v in [1, -1]:
+    [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+    rs2val = abs(rs2val % 2**(xlen-1)) * v;
+    desc = "cp_rs2_sign (Test source rs2 value = " + hex(rs2val) + ")"
+    writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
+
+def make_cr_rs1_rs2_sign(test, storecmd, xlen):
+  for v1 in [1, -1]:
+    for v2 in [1, -1]:
+      [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
+      rs1val = abs(rs1val % 2**(xlen-1)) * v1;
+      rs2val = abs(rs2val % 2**(xlen-1)) * v2;
+      desc = "cr_rs1_rs2 (Test source rs1 = " + hex(rs1val) + " rs2 = " + hex(rs2val) + ")"
+      writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
+
+def write_tests(coverpoints, test, storecmd, xlen):
+  for coverpoint in coverpoints:
+    if (coverpoint == "cp_asm_count"):
+      pass
+    elif (coverpoint == "cp_rd"):
+      make_rd(test, storecmd, xlen)
+    elif (coverpoint == "cp_rs1"):
+      make_rs1(test, storecmd, xlen)
+    elif (coverpoint == "cp_rs2"):
+      make_rs2(test, storecmd, xlen)
+    elif (coverpoint == "cmp_rd_rs1"):
+      make_rd_rs1(test, storecmd, xlen)
+    elif (coverpoint == "cmp_rd_rs2"):
+      make_rd_rs2(test, storecmd, xlen)
+    elif (coverpoint == "cmp_rd_rs1_rs2"):
+      make_rd_rs1_rs2(test, storecmd, xlen)
+    elif (coverpoint == "cmp_rd_rs1_eq"):
+      pass # duplicate of cmp_rd_rs1
+    elif (coverpoint == "cmp_rd_rs2_eq"):
+      pass # duplicate of cmp_rd_rs2
+    elif (coverpoint == "cmp_rs1_rs2_eq"):
+      make_rs1_rs2(test, storecmd, xlen)
+    elif (coverpoint == "cp_rs1_maxvals"):
+      make_rs1_maxvals(test, storecmd, xlen)
+    elif (coverpoint == "cp_rs2_maxvals"):
+      make_rs2_maxvals(test, storecmd, xlen)
+    elif (coverpoint == "cp_rd_maxvals"):
+      make_rd_maxvals(test, storecmd, xlen)
+    elif (coverpoint == "cmp_rd_rs1_eqval"):
+      make_rd_rs1_eqval(test, storecmd, xlen)
+    elif (coverpoint == "cmp_rd_rs2_eqval"):
+      make_rd_rs2_eqval(test, storecmd, xlen)
+    elif (coverpoint == "cmp_rs1_rs2_eqval"):
+      make_rs1_rs2_eqval(test, storecmd, xlen)
+    elif (coverpoint == "cp_rs1_sign"):
+      make_rs1_sign(test, storecmd, xlen)
+    elif (coverpoint == "cp_rs2_sign"):
+      make_rs2_sign(test, storecmd, xlen)
+    elif (coverpoint == "cp_rd_sign"):
+      pass #TODO hope already covered by rd_maxvals
+    elif (coverpoint == "cr_rs1_rs2"):
+      make_cr_rs1_rs2_sign(test, storecmd, xlen)
+    elif (coverpoint == "cp_rs1_toggle"):
+      pass #TODO toggle not needed and seems to be covered by other things
+    elif (coverpoint == "cp_rs2_toggle"):
+      pass #TODO toggle not needed and seems to be covered by other things
+    elif (coverpoint == "cp_rd_toggle"):
+      pass #TODO toggle not needed and seems to be covered by other things
+    elif (coverpoint == "cp_gpr_hazard"):
+      pass #TODO not yet implemented
+    elif (coverpoint == "cp_imm_sign"):
+      pass #TODO
+    elif (coverpoint == "cr_rs1_imm"):
+      pass #TODO (not if crosses are not needed)
+    elif (coverpoint == "cp_imm_ones_zeros"):
+      pass #TODO
+    elif (coverpoint == "cp_mem_hazard"):
+      pass #TODO
+    elif (coverpoint == "cp_imm_zero"):
+      pass #TODO
+    elif (coverpoint == "cp_mem_unaligned"):
+      pass #TODO
+    elif (coverpoint == "cp_offset"):
+      pass #TODO
+    elif (coverpoint == "cr_nord_rs1_rs2"):
+      pass #TODO (not if crosses are not needed)
+    elif (coverpoint == "cp_imm_shift"):
+      pass #TODO
+    elif (coverpoint == "cp_rd_boolean"):
+      pass #TODO
+    else:
+      print("Warning: " + coverpoint + " not implemented yet for " + test)
+      
+def getcovergroups(coverdefdir, coverfiles):
+  coverpoints = {}
+  curinstr = ""
+  for coverfile in coverfiles:
+    coverfile = coverdefdir + "/" + coverfile + "_coverage.svh"
+    f = open(coverfile, "r")
+    for line in f:
+      m = re.search(r'cp_asm_count.*\"(.*)"', line)
+      if (m):
+#        if (curinstr != ""):
+#          print(curinstr + ": " + str(coverpoints[curinstr]))
+        curinstr = m.group(1)
+        coverpoints[curinstr] = []
+      m = re.search("\s*(\S+) :", line)
+      if (m):
+        coverpoints[curinstr].append(m.group(1))
+    f.close()
+    print(coverpoints)
+    return coverpoints
 
 ##################################
 # main body
 ##################################
 
 # change these to suite your tests
-rtests = ["ADD", "SUB", "SLT", "SLTU", "XOR"]
-tests = rtests
+riscv = os.environ.get("RISCV")
+coverdefdir = riscv+"/ImperasDV-OpenHW/Imperas/ImpProprietary/source/host/riscvISACOV/source/coverage";
+#coverfiles = ["RV64I", "RV64M", "RV64A", "RV64C", "RV64F", "RV64D"] # add more later
+coverfiles = ["RV64I"] # add more later
+rtype = ["add", "sub", "sll", "slt", "sltu", "xor", "srl", "sra", "or", "and",
+          "addw", "subw", "sllw", "srlw", "sraw"
+          "mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu",
+          "mulw", "divw", "divuw", "remw", "remuw"]
+loaditype = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]
+shiftitype = ["slli", "srli", "srai"]
+itype = ["addi", "slti", "sltiu", "xori", "ori", "andi"]
+stypes = ["sb", "sh", "sw", "sd"]
+btypes = ["beq", "bne", "blt", "bge", "bltu", "bgeu"]
+# TODO: auipc missing, check whatelse is missing in ^these^ types
+
+coverpoints = getcovergroups(coverdefdir, coverfiles)
+
 author = "David_Harris@hmc.edu"
 xlens = [64]
 numrand = 3
@@ -160,13 +327,14 @@ def write_rtype_arith_vectors(test, storecmd, xlen):
   else:
     storecmd = "sd"
     wordsize = 8
-  for test in tests:
-#    corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
-#            2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
-    corners = [0, 1, 2**(xlen)-1]
-    pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/"
+  for test in coverpoints.keys():
+#    pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/"
+    WALLY = os.environ.get('WALLY')
+    pathname = WALLY+"/tests/functcov/rv" + str(xlen) + "/I/"
+    cmd = "mkdir -p " + pathname
+    os.system(cmd)
     basename = "WALLY-COV-" + test 
-    fname = pathname + "src/" + basename + ".S"
+    fname = pathname + "/" + basename + ".S"
 
     # print custom header part
     f = open(fname, "w")
@@ -184,11 +352,12 @@ def write_rtype_arith_vectors(test, storecmd, xlen):
 
     # print directed and random test vectors
     # Coverage for R-type arithmetic instructions
-    if (test not in rtests):
-      exit("Error: %s not implemented yet" % test)
-    else:
-      write_rtype_arith_vectors(test, storecmd, xlen)
-      
+    #if (test not in rtests):
+    #  exit("Error: %s not implemented yet" % test)
+    #else:
+    #  write_rtype_arith_vectors(test, storecmd, xlen)
+    write_tests(coverpoints[test], test, storecmd, xlen) 
+
     # print footer
     line = "\n.EQU NUMTESTS," + str(1) + "\n\n"
     f.write(line)
diff --git a/tests/testgen/covergen_footer.S b/tests/testgen/covergen_footer.S
index 108119436..2e4abbbfc 100644
--- a/tests/testgen/covergen_footer.S
+++ b/tests/testgen/covergen_footer.S
@@ -1,30 +1,5 @@
-RVTEST_CODE_END
-RVMODEL_HALT
 
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0x98765432
-RVTEST_DATA_END
+self_loop:
+    j self_loop
 
-RVMODEL_DATA_BEGIN
-
-
-wally_signature:
-    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*(XLEN/32),4,0xdeadbeef
-
-#endif
-
-RVMODEL_DATA_END
+.end
diff --git a/tests/testgen/covergen_header.S b/tests/testgen/covergen_header.S
index a9b8f39e5..90be86381 100644
--- a/tests/testgen/covergen_header.S
+++ b/tests/testgen/covergen_header.S
@@ -4,15 +4,9 @@
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 ///////////////////////////////////////////
 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64I")
-
 .section .text.init
 .globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
 
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",temp)
+rvtest_entry_point:
 
+    
\ No newline at end of file
diff --git a/tests/testgen/virtual_memory_util.py b/tests/testgen/virtual_memory_util.py
deleted file mode 100644
index 0aafb3a12..000000000
--- a/tests/testgen/virtual_memory_util.py
+++ /dev/null
@@ -1,292 +0,0 @@
-#!/usr/bin/python3
-##################################
-# virtual_memory_util.py
-#
-# Jessica Torrey <jtorrey@hmc.edu>  01 March 2021
-# Thomas Fleming <tfleming@hmc.edu> 01 March 2021
-#
-# Modified kmacsaigoren@hmc.edu 2 June 2021
-#             file now reflects actual use to generate assembly code pagetable.
-#             file now also includes small guide on how it can be used.
-#
-# Utility for generating the pagetable for any test assembly code where virtual memory is needed.
-##################################
-
-######################################################
-""" HOW TO USE THIS FILE
-    
-This is all assuming you are writing code very similar to the WALLY-VIRTUALMEMORY tests and would like your own virtual memory map.
-This guide is also stored in the WALLY-VIRTUALMEMORY.S file as well.
-
-Begin by copying an existing page directory over to your test and running make (it'll be wrong, but we'll fix it in a second).
-  Make may hang or give you an error because the reference outputs may be wrong, but all we're trying to do is get an elf file.
-Simulate the test code on your favorite riscv processor simulator with a debugger that will show you internal state/register values.
-  I used OVPsimPlus with the command 'riscvOVPsimPlus.exe --variant <Variant name, ex: RV64I> --program <path to elf file> --gdbconsole'
-Run through the simulation until it has written to satp and read the bottom 60 bits of it. 
-  Assuming you're a test with the same setup code, this should be the value of the base ppn.
-
-Near the top of the python file you're reading right now, edit the value of 'INITIAL_PPN' to be the base PPN you just found in hex.
-
-Now find the mappings at the very bottom of the python file.
-Each of these loops is adding a mapping from each virtual page in the loop to a physical page somewhere in RAM. 
-
-add or remove mappings as you see fit. the first loop maps VPNs of 0x80000 to 0x80014 onto PPNs of 0x80000 to 0x80014
-  you can map single pages or ranges of pages. you can also map multiple VPNs onto the same PPN.
-  Make sure NOT to include the final VPN that causes the page fault in your test or your program will hang on the j loop instruction (unless you change the end condition).
-
-double check that you're using the right architecture/svmode in the 'arch' variable
-
-then run this python file and paste its output at the bottom of your assembly code. Be sure not to delete the signature fills.
-
-email kmacsaigoren@hmc.edu if you have any questions and he might be able to remember the answers.
-
-*** Currently doesn't work: mapping something with nonzeros in the VPN[3] feild onto any physical aderss. 
-    It'll produce a page table, but writing to those virtual adresses will not correspond to the correctly mapped physical adresses.
-
-    additionally, the expected behaviour doesn't really work when we try to map to a ram afress that starts with something larger than 000000008
-    This could be ebcause of the 32 bit adress space for physical memory.
-
-    remember that these things are broken with this program that generates page tables for test code. it does not say whether the test or module
-    itself works or not.
-*/
-
-"""
-######################################################
-
-##################################
-# libraries
-##################################
-from datetime import datetime
-from random import randint, seed, getrandbits
-from textwrap import dedent
-
-##################################
-# global structures
-##################################
-PTE_D = 1 << 7
-PTE_A = 1 << 6
-PTE_G = 1 << 5
-PTE_U = 1 << 4
-PTE_X = 1 << 3
-PTE_W = 1 << 2
-PTE_R = 1 << 1
-PTE_V = 1 << 0
-
-PTE_PTR_MASK = ~(PTE_W | PTE_R | PTE_X)
-
-pgdir = []
-
-pages = {}
-
-
-testcase_num = 0
-signature_len = 2000
-signature = [0xff for _ in range(signature_len)]
-
-# Base PPN, comes after 2 pages of test code and 2 pages of filler signature output space.
-# depending on your test however, this value may be different. You can use OVPsimPlus or QEMU with your testcode to find it. 
-INITIAL_PPN = 0x80005
-
-
-##################################
-# classes
-##################################
-class Architecture:
-  def __init__(self, xlen, svMode):
-    if (xlen == 32):
-      self.PTESIZE = 4 # bytes
-      self.PTE_BITS = 32
-
-      self.VPN_BITS = 20
-      self.VPN_SEGMENT_BITS = 10
-
-      self.PPN_BITS = 22
-
-      self.LEVELS = 2
-    elif (xlen == 64):
-      if (svMode == 39): 
-        self.PTESIZE = 8
-        self.PTE_BITS = 54
-
-        self.VPN_BITS = 27
-        self.VPN_SEGMENT_BITS = 9
-
-        self.PPN_BITS = 44
-
-        self.LEVELS = 3
-      elif (svMode == 48):
-        self.PTESIZE = 8
-        self.PTE_BITS = 54
-
-        self.VPN_BITS = 36
-        self.VPN_SEGMENT_BITS = 9
-
-        self.PPN_BITS = 44
-
-        self.LEVELS = 4
-      else:
-        raise ValueError('Only Sv39 and Sv48 are implemented')
-    else:
-      raise ValueError('Only rv32 and rv64 are allowed.')
-
-    self.PGSIZE = 2**12
-    self.NPTENTRIES = self.PGSIZE // self.PTESIZE
-    self.OFFSET_BITS = 12
-    self.FLAG_BITS = 8
-    self.VA_BITS = self.VPN_BITS + self.OFFSET_BITS
-
-class PageTableEntry:
-  def __init__(self, ppn, flags, arch):
-    assert 0 <= ppn and ppn < 2**arch.PPN_BITS, "Invalid physical page number for PTE"
-    assert 0 <= flags and flags < 2**arch.FLAG_BITS, "Invalid flags for PTE"
-    self.ppn = ppn
-    self.flags = flags
-    self.arch = arch
-
-  def entry(self):
-    return (self.ppn << (self.arch.PTE_BITS - self.arch.PPN_BITS)) | self.flags
-
-  def __str__(self):
-    return "0x{0:0{1}x}".format(self.entry(), self.arch.PTESIZE*2)
-
-  def __repr__(self):
-    return f"<ppn: {hex(self.ppn)}, flags: {self.flags:08b}>"
-
-class PageTable:
-  """
-  Represents a single level of the page table, located at some physical page
-  number `ppn` with symbol `name`, using a specified architecture `arch`.
-  """
-  def __init__(self, name, ppn, arch):
-    self.table = {}
-    self.name = name
-    self.ppn = ppn
-    self.arch = arch
-
-    self.children = 0
-
-    pages[ppn] = self
-
-  def add_entry(self, vpn_segment, ppn, flags):
-    if not (0 <= vpn_segment < 2**self.arch.VPN_SEGMENT_BITS):
-      raise ValueError("Invalid virtual page segment number")
-    self.table[vpn_segment] = PageTableEntry(ppn, flags, self.arch)
-
-  def add_mapping(self, va, pa, flags):
-    """
-    Maps a virtual address `va` to a physical address `pa` with given `flags`,
-    creating missing page table levels as needed.
-    """
-    if not (0 <= va < 2**self.arch.VA_BITS):
-      raise ValueError("Invalid virtual page number")
-
-    vpn = virtual_to_vpn(va, self.arch)
-    ppn = pa >> self.arch.OFFSET_BITS
-    current_level = self
-
-    pathname = self.name
-
-    for level in range(self.arch.LEVELS - 1, -1, -1):
-      if level == 0:
-        current_level.add_entry(vpn[level], ppn, flags)
-      elif vpn[level] in current_level.table:
-        current_level = pages[current_level.table[vpn[level]].ppn]
-        pathname += f"_{current_level.name}"
-      else:
-        next_level_ppn = next_ppn()
-        current_level.add_entry(vpn[level], next_level_ppn, flags & PTE_PTR_MASK)
-        pathname += f"_t{current_level.children}"
-        current_level.children += 1
-        pages[next_level_ppn] = PageTable(pathname, next_level_ppn, self.arch)
-        current_level = pages[next_level_ppn]
-
-  def assembly(self):
-    # Sort the page table
-    entries = list(sorted(self.table.items(), key=lambda item: item[0]))
-    current_index = 0
-
-    # Align the table
-    asm = f".balign {self.arch.PGSIZE}\n{self.name}:\n"
-    for entry in entries:
-      vpn_index, pte = entry
-      if current_index < vpn_index:
-        asm += f"  .fill {vpn_index - current_index}, {self.arch.PTESIZE}, 0\n"
-      asm += f"  .{self.arch.PTESIZE}byte {str(pte)}\n"
-      current_index = vpn_index + 1
-    if current_index < self.arch.NPTENTRIES:
-      asm += f"  .fill {self.arch.NPTENTRIES - current_index}, {self.arch.PTESIZE}, 0\n"
-    return asm
-  
-  def __str__(self):
-    return self.assembly()
-
-  def __repr__(self):
-    return f"<table: {self.table}>"
-
-
-##################################
-# functions
-##################################
-
-def virtual_to_vpn(vaddr, arch):
-  if not (0 <= vaddr < 2**arch.VA_BITS):
-    raise ValueError("Invalid physical address")
-
-  page_number = [0 for _ in range(arch.LEVELS)]
-
-  vaddr = vaddr >> arch.OFFSET_BITS
-  mask = 2**arch.VPN_SEGMENT_BITS - 1
-  for level in range(arch.LEVELS):
-    page_number[level] = vaddr & mask
-    vaddr = vaddr >> arch.VPN_SEGMENT_BITS
-
-  return page_number
-
-next_free_ppn = INITIAL_PPN
-def next_ppn():
-  global next_free_ppn
-  ppn = next_free_ppn
-  next_free_ppn += 1
-  return ppn
-
-def print_pages():
-  for page in pages:
-    print(pages[page])
-
-##################################
-# helper variables
-##################################
-sv32 = Architecture(32, 32)
-sv39 = Architecture(64, 39)
-sv48 = Architecture(64, 48)
-
-if __name__ == "__main__":
-  arch = sv39
-  pgdir = PageTable("page_directory", next_ppn(), arch)
-
-  # Directly map the first 20 pages of RAM
-  for page in range(20):
-    vaddr = 0x80000000 + (arch.PGSIZE * page)
-    paddr = 0x80000000 + (arch.PGSIZE * page)
-    pgdir.add_mapping(vaddr, paddr, PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_X | PTE_V)
-
-  # Map Vpn of of the offset below and the 20 pages after it mapped onto the same 20 pages of ram.
-  # the first two of these are also the location of the output for each test.
-  for page in range(40):
-    vaddr = 0x00000000 + (arch.PGSIZE * page)
-    paddr = 0x80000000 + (arch.PGSIZE * page)
-    if page >= 20:
-      pgdir.add_mapping(vaddr, paddr, PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_X | 0) # gives me an invalid mapping where I can try to store/read to force a page fault.
-    else:
-      pgdir.add_mapping(vaddr, paddr, PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_X | PTE_V)
-
-
-  """
-  supervisor_pgdir = PageTable("sdir", next_ppn(), rv64)
-  supervisor_pgdir.add_mapping(0x80000000, 0x80000000, PTE_R | PTE_W | PTE_X)
-  supervisor_pgdir.add_mapping(0x80000001, 0x80000001, PTE_R | PTE_W | PTE_X)
-  supervisor_pgdir.add_mapping(0x80001000, 0x80000000, PTE_R | PTE_W | PTE_X)
-  supervisor_pgdir.add_mapping(0xffff0000, 0x80000000, PTE_R | PTE_W | PTE_X)
-  """
-
-  print_pages()
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S
deleted file mode 100644
index 218780782..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S
+++ /dev/null
@@ -1,320 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:53 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x8000000000000000; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x1; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x8000000000000001; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x2; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x8000000000000002; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0xfffffffffffff; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0x800fffffffffffff; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x10000000000000; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x8010000000000000; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x10000000000002; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x8010000000000002; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x7fefffffffffffff; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0xffefffffffffffff; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x7ff0000000000000; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0xfff0000000000000; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
-
-inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0x7ff8000000000000; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
-
-inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0xfff8000000000000; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
-
-inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0x7ff8000000000001; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
-
-inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0xfff8000000000001; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
-
-inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0x7ff0000000000001; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
-
-inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0xfff0000000000001; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
-
-inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0x3ff0000000000000; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
-
-inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0xbf80000000000000; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,
-/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
-
-inst_25:// rs1==f6, rd==x6,
-/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
-
-inst_26:// rs1==f5, rd==x5,
-/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,
-/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
-
-inst_28:// rs1==f3, rd==x3,
-/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
-
-inst_29:// rs1==f2, rd==x2,
-/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
-
-inst_30:// rs1==f1, rd==x1,
-/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
-
-inst_31:// rs1==f0, rd==x0,
-/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-test_dataset_1:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 10*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S
deleted file mode 100644
index c24128a5d..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S
+++ /dev/null
@@ -1,383 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:53 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b22 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b22)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08577924770d3 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08577924770d3; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fd and fm1 == 0x93fdc7b89296c and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x3fd93fdc7b89296c; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 1 and fe1 == 0x3fe and fm1 == 0x766ba34c2da80 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0xbfe766ba34c2da80; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xd2d6b7dc59a3a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x3ffd2d6b7dc59a3a; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x400 and fm1 == 0xcf84ba749f9c5 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x400cf84ba749f9c5; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x401 and fm1 == 0x854a908ceac39 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x401854a908ceac39; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x402 and fm1 == 0x137a953e8eb43 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x402137a953e8eb43; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x403 and fm1 == 0xf3ebcf3d06f86 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0xc03f3ebcf3d06f86; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x404 and fm1 == 0x5c74eff1e5bef and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x4045c74eff1e5bef; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x405 and fm1 == 0xdc3386b9f15c4 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x405dc3386b9f15c4; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x406 and fm1 == 0x5ae6a9a6ab329 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x4065ae6a9a6ab329; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x407 and fm1 == 0x489b36bd7f503 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0xc07489b36bd7f503; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x408 and fm1 == 0x43277acca7f0d and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x40843277acca7f0d; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x409 and fm1 == 0xaf9492cb7362c and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x409af9492cb7362c; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x40a and fm1 == 0x5cd28a96ec2b3 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x40a5cd28a96ec2b3; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x40b and fm1 == 0xc491074f942cb and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0xc0bc491074f942cb; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
-
-inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x40c and fm1 == 0x3d480fb7f6f5d and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0xc0c3d480fb7f6f5d; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
-
-inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x40d and fm1 == 0x9d02f708cc1b6 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0x40d9d02f708cc1b6; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
-
-inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x40e and fm1 == 0x953b00b54aa22 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0x40e953b00b54aa22; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
-
-inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x40f and fm1 == 0x224c03c53d0e3 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0x40f224c03c53d0e3; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
-
-inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x410 and fm1 == 0xe8dacf0e58650 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0x410e8dacf0e58650; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
-
-inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x411 and fm1 == 0x5dbbb894deab4 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0xc115dbbb894deab4; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
-
-inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x412 and fm1 == 0x3d7c9e5f0307e and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0x4123d7c9e5f0307e; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
-
-inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x413 and fm1 == 0x8c8a1aaac3142 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0x4138c8a1aaac3142; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x414 and fm1 == 0x785036f9fb997 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0x414785036f9fb997; valaddr_reg:x8;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
-
-inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x415 and fm1 == 0x95a4da7298c66 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x41595a4da7298c66; valaddr_reg:x8;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
-
-inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x416 and fm1 == 0x807dad814d575 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x416807dad814d575; valaddr_reg:x8;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x417 and fm1 == 0x396bad798c9cf and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0xc17396bad798c9cf; valaddr_reg:x8;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
-
-inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x418 and fm1 == 0x3d06169b1dcbf and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x4183d06169b1dcbf; valaddr_reg:x8;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
-
-inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x419 and fm1 == 0x7f21608208d09 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x4197f21608208d09; valaddr_reg:x8;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
-
-inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x41a and fm1 == 0x9b4f3d167533a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0xc1a9b4f3d167533a; valaddr_reg:x8;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
-
-inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x41b and fm1 == 0x889261270dee2 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0xc1b889261270dee2; valaddr_reg:x8;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
-
-inst_32:// fs1 == 0 and fe1 == 0x41c and fm1 == 0x14b91dae98554 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x41c14b91dae98554; valaddr_reg:x8;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
-
-inst_33:// fs1 == 1 and fe1 == 0x41d and fm1 == 0x9136562694646 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xc1d9136562694646; valaddr_reg:x8;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
-
-inst_34:// fs1 == 1 and fe1 == 0x41e and fm1 == 0xe9b7e5fc9eba4 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xc1ee9b7e5fc9eba4; valaddr_reg:x8;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
-
-inst_35:// fs1 == 1 and fe1 == 0x41f and fm1 == 0x1ce80265039f6 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xc1f1ce80265039f6; valaddr_reg:x8;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
-
-inst_36:// fs1 == 0 and fe1 == 0x420 and fm1 == 0xc5ec6c6880007 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x420c5ec6c6880007; valaddr_reg:x8;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
-
-inst_37:// fs1 == 1 and fe1 == 0x421 and fm1 == 0x2a96d71097999 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xc212a96d71097999; valaddr_reg:x8;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
-
-inst_38:// fs1 == 0 and fe1 == 0x3ca and fm1 == 0x30e08ceb506f6 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ca30e08ceb506f6; valaddr_reg:x8;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
-
-inst_39:// fs1 == 0 and fe1 == 0x5ca and fm1 == 0xf871c6ee84270 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x5caf871c6ee84270; valaddr_reg:x8;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
-
-inst_40:// fs1 == 1 and fe1 == 0x41b and fm1 == 0x889261270dee2 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xc1b889261270dee2; valaddr_reg:x8;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(4593818368519663827,64,FLEN)
-NAN_BOXED(4600778710533613932,64,FLEN)
-NAN_BOXED(13828134130799532672,64,FLEN)
-NAN_BOXED(4610891533192108602,64,FLEN)
-NAN_BOXED(4615336721960794565,64,FLEN)
-NAN_BOXED(4618534502842412089,64,FLEN)
-NAN_BOXED(4621035893055613763,64,FLEN)
-NAN_BOXED(13852859960080232326,64,FLEN)
-NAN_BOXED(4631326933921979375,64,FLEN)
-NAN_BOXED(4638077838352651716,64,FLEN)
-NAN_BOXED(4640306763955614505,64,FLEN)
-NAN_BOXED(13867860556282066179,64,FLEN)
-NAN_BOXED(4648896204934643469,64,FLEN)
-NAN_BOXED(4655307257518962220,64,FLEN)
-NAN_BOXED(4658354964109640371,64,FLEN)
-NAN_BOXED(13888055685934564043,64,FLEN)
-NAN_BOXED(13890179326181076829,64,FLEN)
-NAN_BOXED(4672994990543913398,64,FLEN)
-NAN_BOXED(4677361703570418210,64,FLEN)
-NAN_BOXED(4679843370855813347,64,FLEN)
-NAN_BOXED(4687840036054730320,64,FLEN)
-NAN_BOXED(13913268222339967668,64,FLEN)
-NAN_BOXED(4693832498796310654,64,FLEN)
-NAN_BOXED(4699726807839813954,64,FLEN)
-test_dataset_1:
-NAN_BOXED(4703874585615907223,64,FLEN)
-NAN_BOXED(4708894174956063846,64,FLEN)
-NAN_BOXED(4713025646552733045,64,FLEN)
-NAN_BOXED(13939651000867015119,64,FLEN)
-NAN_BOXED(4720845951218080959,64,FLEN)
-NAN_BOXED(4726512510388178185,64,FLEN)
-NAN_BOXED(13954883879667454778,64,FLEN)
-NAN_BOXED(13959057841646001890,64,FLEN)
-NAN_BOXED(4738151372785550676,64,FLEN)
-NAN_BOXED(13968217045429995078,64,FLEN)
-NAN_BOXED(13974277660852480932,64,FLEN)
-NAN_BOXED(13975178168501287414,64,FLEN)
-NAN_BOXED(4759283114051108871,64,FLEN)
-NAN_BOXED(13984426080451787161,64,FLEN)
-NAN_BOXED(4369351494470010614,64,FLEN)
-NAN_BOXED(6678705328603284080,64,FLEN)
-NAN_BOXED(13959057841646001890,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 28*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S
deleted file mode 100644
index ee8f30a80..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S
+++ /dev/null
@@ -1,418 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:53 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b23 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b23)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43dffffffffffffc; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x43dffffffffffffc; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x43dffffffffffffc; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x43dffffffffffffc; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x43dffffffffffffc; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x43dffffffffffffd; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x43dffffffffffffd; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0x43dffffffffffffd; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x43dffffffffffffd; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x43dffffffffffffd; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x43dffffffffffffe; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x43dffffffffffffe; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x43dffffffffffffe; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x43dffffffffffffe; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x43dffffffffffffe; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0x43dfffffffffffff; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
-
-inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0x43dfffffffffffff; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
-
-inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0x43dfffffffffffff; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
-
-inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0x43dfffffffffffff; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
-
-inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0x43dfffffffffffff; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
-
-inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0x43e0000000000000; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
-
-inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0x43e0000000000000; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
-
-inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0x43e0000000000000; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
-
-inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0x43e0000000000000; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0x43e0000000000000; valaddr_reg:x8;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
-
-inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x43e0000000000001; valaddr_reg:x8;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
-
-inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x43e0000000000001; valaddr_reg:x8;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0x43e0000000000001; valaddr_reg:x8;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
-
-inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x43e0000000000001; valaddr_reg:x8;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
-
-inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x43e0000000000001; valaddr_reg:x8;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
-
-inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x43e0000000000002; valaddr_reg:x8;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
-
-inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x43e0000000000002; valaddr_reg:x8;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
-
-inst_32:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x8;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
-
-inst_33:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x8;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
-
-inst_34:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x8;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
-
-inst_35:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x8;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
-
-inst_36:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x8;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
-
-inst_37:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x8;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
-
-inst_38:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x8;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
-
-inst_39:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x8;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
-
-inst_40:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x8;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
-
-inst_41:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x8;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
-
-inst_42:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x8;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
-
-inst_43:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x8;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
-
-inst_44:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x8;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
-
-inst_45:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x8;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(4890909195324358652,64,FLEN)
-NAN_BOXED(4890909195324358652,64,FLEN)
-NAN_BOXED(4890909195324358652,64,FLEN)
-NAN_BOXED(4890909195324358652,64,FLEN)
-NAN_BOXED(4890909195324358652,64,FLEN)
-NAN_BOXED(4890909195324358653,64,FLEN)
-NAN_BOXED(4890909195324358653,64,FLEN)
-NAN_BOXED(4890909195324358653,64,FLEN)
-NAN_BOXED(4890909195324358653,64,FLEN)
-NAN_BOXED(4890909195324358653,64,FLEN)
-NAN_BOXED(4890909195324358654,64,FLEN)
-NAN_BOXED(4890909195324358654,64,FLEN)
-NAN_BOXED(4890909195324358654,64,FLEN)
-NAN_BOXED(4890909195324358654,64,FLEN)
-NAN_BOXED(4890909195324358654,64,FLEN)
-NAN_BOXED(4890909195324358655,64,FLEN)
-NAN_BOXED(4890909195324358655,64,FLEN)
-NAN_BOXED(4890909195324358655,64,FLEN)
-NAN_BOXED(4890909195324358655,64,FLEN)
-NAN_BOXED(4890909195324358655,64,FLEN)
-NAN_BOXED(4890909195324358656,64,FLEN)
-NAN_BOXED(4890909195324358656,64,FLEN)
-NAN_BOXED(4890909195324358656,64,FLEN)
-NAN_BOXED(4890909195324358656,64,FLEN)
-test_dataset_1:
-NAN_BOXED(4890909195324358656,64,FLEN)
-NAN_BOXED(4890909195324358657,64,FLEN)
-NAN_BOXED(4890909195324358657,64,FLEN)
-NAN_BOXED(4890909195324358657,64,FLEN)
-NAN_BOXED(4890909195324358657,64,FLEN)
-NAN_BOXED(4890909195324358657,64,FLEN)
-NAN_BOXED(4890909195324358658,64,FLEN)
-NAN_BOXED(4890909195324358658,64,FLEN)
-NAN_BOXED(4890909195324358658,64,FLEN)
-NAN_BOXED(4890909195324358658,64,FLEN)
-NAN_BOXED(4890909195324358658,64,FLEN)
-NAN_BOXED(4890909195324358659,64,FLEN)
-NAN_BOXED(4890909195324358659,64,FLEN)
-NAN_BOXED(4890909195324358659,64,FLEN)
-NAN_BOXED(4890909195324358659,64,FLEN)
-NAN_BOXED(4890909195324358659,64,FLEN)
-NAN_BOXED(4890909195324358660,64,FLEN)
-NAN_BOXED(4890909195324358660,64,FLEN)
-NAN_BOXED(4890909195324358660,64,FLEN)
-NAN_BOXED(4890909195324358660,64,FLEN)
-NAN_BOXED(4890909195324358660,64,FLEN)
-NAN_BOXED(4890909195324358658,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 38*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S
deleted file mode 100644
index 24fee21c3..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S
+++ /dev/null
@@ -1,838 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:53 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b24 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b24)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
-
-inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
-
-inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
-
-inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
-
-inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
-
-inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0xbfb999999999999a; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
-
-inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0xbfb999999999999a; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
-
-inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0xbfb999999999999a; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
-
-inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0xbfb999999999999a; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0xbfb999999999999a; valaddr_reg:x8;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
-
-inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
-
-inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
-
-inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
-
-inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
-
-inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0xbff0000000000000; valaddr_reg:x8;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
-
-inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0xbff0000000000000; valaddr_reg:x8;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
-
-inst_32:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x8;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
-
-inst_33:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x8;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
-
-inst_34:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x8;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
-
-inst_35:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x8;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
-
-inst_36:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x8;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
-
-inst_37:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x8;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
-
-inst_38:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x8;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
-
-inst_39:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x8;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
-
-inst_40:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x8;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
-
-inst_41:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x8;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
-
-inst_42:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x8;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
-
-inst_43:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x8;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
-
-inst_44:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x8;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
-
-inst_45:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x8;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
-
-inst_46:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x8;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)
-
-inst_47:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x8;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)
-
-inst_48:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x8;
-val_offset:24*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)
-
-inst_49:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x8;
-val_offset:25*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)
-
-inst_50:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x8;
-val_offset:26*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)
-
-inst_51:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x8;
-val_offset:27*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)
-
-inst_52:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x8;
-val_offset:28*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)
-
-inst_53:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x8;
-val_offset:29*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)
-
-inst_54:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x8;
-val_offset:30*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)
-
-inst_55:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x8;
-val_offset:31*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)
-
-inst_56:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x8;
-val_offset:32*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)
-
-inst_57:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x8;
-val_offset:33*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)
-
-inst_58:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x8;
-val_offset:34*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)
-
-inst_59:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x8;
-val_offset:35*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)
-
-inst_60:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3feccccccccccccd; valaddr_reg:x8;
-val_offset:36*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)
-
-inst_61:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3feccccccccccccd; valaddr_reg:x8;
-val_offset:37*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)
-
-inst_62:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3feccccccccccccd; valaddr_reg:x8;
-val_offset:38*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)
-
-inst_63:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3feccccccccccccd; valaddr_reg:x8;
-val_offset:39*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)
-
-inst_64:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3feccccccccccccd; valaddr_reg:x8;
-val_offset:40*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)
-
-inst_65:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x8;
-val_offset:41*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)
-
-inst_66:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x8;
-val_offset:42*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)
-
-inst_67:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x8;
-val_offset:43*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)
-
-inst_68:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x8;
-val_offset:44*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)
-
-inst_69:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x8;
-val_offset:45*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)
-
-inst_70:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x8;
-val_offset:46*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)
-
-inst_71:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x8;
-val_offset:47*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)
-
-inst_72:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x8;
-val_offset:48*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)
-
-inst_73:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x8;
-val_offset:49*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)
-
-inst_74:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x8;
-val_offset:50*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)
-
-inst_75:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x8;
-val_offset:51*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)
-
-inst_76:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x8;
-val_offset:52*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)
-
-inst_77:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x8;
-val_offset:53*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)
-
-inst_78:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x8;
-val_offset:54*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)
-
-inst_79:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x8;
-val_offset:55*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)
-
-inst_80:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x8;
-val_offset:56*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)
-
-inst_81:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x8;
-val_offset:57*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 57*FLEN/8, x9, x5, x6,FLREG)
-
-inst_82:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x8;
-val_offset:58*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 58*FLEN/8, x9, x5, x6,FLREG)
-
-inst_83:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x8;
-val_offset:59*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 59*FLEN/8, x9, x5, x6,FLREG)
-
-inst_84:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x8;
-val_offset:60*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 60*FLEN/8, x9, x5, x6,FLREG)
-
-inst_85:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x8;
-val_offset:61*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 61*FLEN/8, x9, x5, x6,FLREG)
-
-inst_86:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x8;
-val_offset:62*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 62*FLEN/8, x9, x5, x6,FLREG)
-
-inst_87:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x8;
-val_offset:63*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 63*FLEN/8, x9, x5, x6,FLREG)
-
-inst_88:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x8;
-val_offset:64*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 64*FLEN/8, x9, x5, x6,FLREG)
-
-inst_89:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x8;
-val_offset:65*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 65*FLEN/8, x9, x5, x6,FLREG)
-
-inst_90:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x8;
-val_offset:66*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 66*FLEN/8, x9, x5, x6,FLREG)
-
-inst_91:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x8;
-val_offset:67*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 67*FLEN/8, x9, x5, x6,FLREG)
-
-inst_92:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x8;
-val_offset:68*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 68*FLEN/8, x9, x5, x6,FLREG)
-
-inst_93:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x8;
-val_offset:69*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 69*FLEN/8, x9, x5, x6,FLREG)
-
-inst_94:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x8;
-val_offset:70*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 70*FLEN/8, x9, x5, x6,FLREG)
-
-inst_95:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fb999999999999a; valaddr_reg:x8;
-val_offset:71*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 71*FLEN/8, x9, x5, x6,FLREG)
-
-inst_96:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fb999999999999a; valaddr_reg:x8;
-val_offset:72*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 72*FLEN/8, x9, x5, x6,FLREG)
-
-inst_97:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fb999999999999a; valaddr_reg:x8;
-val_offset:73*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 73*FLEN/8, x9, x5, x6,FLREG)
-
-inst_98:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fb999999999999a; valaddr_reg:x8;
-val_offset:74*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 74*FLEN/8, x9, x5, x6,FLREG)
-
-inst_99:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fb999999999999a; valaddr_reg:x8;
-val_offset:75*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 75*FLEN/8, x9, x5, x6,FLREG)
-
-inst_100:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x8;
-val_offset:76*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 76*FLEN/8, x9, x5, x6,FLREG)
-
-inst_101:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x8;
-val_offset:77*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 77*FLEN/8, x9, x5, x6,FLREG)
-
-inst_102:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x8;
-val_offset:78*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 78*FLEN/8, x9, x5, x6,FLREG)
-
-inst_103:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x8;
-val_offset:79*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 79*FLEN/8, x9, x5, x6,FLREG)
-
-inst_104:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x8;
-val_offset:80*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 80*FLEN/8, x9, x5, x6,FLREG)
-
-inst_105:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x8;
-val_offset:81*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 81*FLEN/8, x9, x5, x6,FLREG)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(4606191626881995899,64,FLEN)
-NAN_BOXED(4606191626881995899,64,FLEN)
-NAN_BOXED(4606191626881995899,64,FLEN)
-NAN_BOXED(4606191626881995899,64,FLEN)
-NAN_BOXED(4606191626881995899,64,FLEN)
-NAN_BOXED(4576918229304087675,64,FLEN)
-NAN_BOXED(4576918229304087675,64,FLEN)
-NAN_BOXED(4576918229304087675,64,FLEN)
-NAN_BOXED(4576918229304087675,64,FLEN)
-NAN_BOXED(4576918229304087675,64,FLEN)
-NAN_BOXED(4607677814759028163,64,FLEN)
-NAN_BOXED(4607677814759028163,64,FLEN)
-NAN_BOXED(4607677814759028163,64,FLEN)
-NAN_BOXED(4607677814759028163,64,FLEN)
-NAN_BOXED(4607677814759028163,64,FLEN)
-NAN_BOXED(13815962792862112809,64,FLEN)
-NAN_BOXED(13815962792862112809,64,FLEN)
-NAN_BOXED(13815962792862112809,64,FLEN)
-NAN_BOXED(13815962792862112809,64,FLEN)
-NAN_BOXED(13815962792862112809,64,FLEN)
-NAN_BOXED(13815242216921733530,64,FLEN)
-NAN_BOXED(13815242216921733530,64,FLEN)
-NAN_BOXED(13815242216921733530,64,FLEN)
-NAN_BOXED(13815242216921733530,64,FLEN)
-test_dataset_1:
-NAN_BOXED(13815242216921733530,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13830554455654793216,64,FLEN)
-NAN_BOXED(13830554455654793216,64,FLEN)
-NAN_BOXED(13830554455654793216,64,FLEN)
-NAN_BOXED(13830554455654793216,64,FLEN)
-NAN_BOXED(13830554455654793216,64,FLEN)
-NAN_BOXED(4607227454796291113,64,FLEN)
-NAN_BOXED(4607227454796291113,64,FLEN)
-NAN_BOXED(4607227454796291113,64,FLEN)
-NAN_BOXED(4607227454796291113,64,FLEN)
-NAN_BOXED(4607227454796291113,64,FLEN)
-NAN_BOXED(13829563663736771707,64,FLEN)
-NAN_BOXED(13829563663736771707,64,FLEN)
-NAN_BOXED(13829563663736771707,64,FLEN)
-NAN_BOXED(13829563663736771707,64,FLEN)
-NAN_BOXED(13829563663736771707,64,FLEN)
-NAN_BOXED(13831004815617530266,64,FLEN)
-NAN_BOXED(13831004815617530266,64,FLEN)
-NAN_BOXED(13831004815617530266,64,FLEN)
-NAN_BOXED(13831004815617530266,64,FLEN)
-NAN_BOXED(13831004815617530266,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13800290266158863483,64,FLEN)
-NAN_BOXED(13800290266158863483,64,FLEN)
-NAN_BOXED(13800290266158863483,64,FLEN)
-NAN_BOXED(13800290266158863483,64,FLEN)
-NAN_BOXED(13800290266158863483,64,FLEN)
-NAN_BOXED(4606281698874543309,64,FLEN)
-NAN_BOXED(4606281698874543309,64,FLEN)
-NAN_BOXED(4606281698874543309,64,FLEN)
-NAN_BOXED(4606281698874543309,64,FLEN)
-NAN_BOXED(4606281698874543309,64,FLEN)
-NAN_BOXED(13830464383662245806,64,FLEN)
-NAN_BOXED(13830464383662245806,64,FLEN)
-NAN_BOXED(13830464383662245806,64,FLEN)
-NAN_BOXED(13830464383662245806,64,FLEN)
-NAN_BOXED(13830464383662245806,64,FLEN)
-NAN_BOXED(4607632778762754458,64,FLEN)
-NAN_BOXED(4607632778762754458,64,FLEN)
-NAN_BOXED(4607632778762754458,64,FLEN)
-NAN_BOXED(4607632778762754458,64,FLEN)
-NAN_BOXED(4607632778762754458,64,FLEN)
-NAN_BOXED(13831049851613803971,64,FLEN)
-NAN_BOXED(13831049851613803971,64,FLEN)
-NAN_BOXED(13831049851613803971,64,FLEN)
-NAN_BOXED(13831049851613803971,64,FLEN)
-NAN_BOXED(13831049851613803971,64,FLEN)
-NAN_BOXED(4592590756007337001,64,FLEN)
-NAN_BOXED(4592590756007337001,64,FLEN)
-NAN_BOXED(4592590756007337001,64,FLEN)
-NAN_BOXED(4592590756007337001,64,FLEN)
-NAN_BOXED(4592590756007337001,64,FLEN)
-NAN_BOXED(4607092346807469998,64,FLEN)
-NAN_BOXED(4607092346807469998,64,FLEN)
-NAN_BOXED(4607092346807469998,64,FLEN)
-NAN_BOXED(4607092346807469998,64,FLEN)
-NAN_BOXED(4607092346807469998,64,FLEN)
-NAN_BOXED(13830599491651066921,64,FLEN)
-NAN_BOXED(13830599491651066921,64,FLEN)
-NAN_BOXED(13830599491651066921,64,FLEN)
-NAN_BOXED(13830599491651066921,64,FLEN)
-NAN_BOXED(13830599491651066921,64,FLEN)
-NAN_BOXED(4591870180066957722,64,FLEN)
-NAN_BOXED(4591870180066957722,64,FLEN)
-NAN_BOXED(4591870180066957722,64,FLEN)
-NAN_BOXED(4591870180066957722,64,FLEN)
-NAN_BOXED(4591870180066957722,64,FLEN)
-NAN_BOXED(13829653735729319117,64,FLEN)
-NAN_BOXED(13829653735729319117,64,FLEN)
-NAN_BOXED(13829653735729319117,64,FLEN)
-NAN_BOXED(13829653735729319117,64,FLEN)
-NAN_BOXED(13829653735729319117,64,FLEN)
-NAN_BOXED(13830554455654793216,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 158*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S
deleted file mode 100644
index 138dc1bfd..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S
+++ /dev/null
@@ -1,320 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:53 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b27 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b27)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x7ff0000000000001; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0xfff0000000000001; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x7ff4aaaaaaaaaaaa; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0xfff4aaaaaaaaaaaa; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x7ff8000000000001; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0xfff8000000000001; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x7ff and fm1 == 0xc000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x7ffc000000000001; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x7ff and fm1 == 0xc000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0xfffc000000000001; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
-
-inst_8:// rs1==f23, rd==x23,
-/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x0; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
-
-inst_9:// rs1==f22, rd==x22,
-/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
-
-inst_10:// rs1==f21, rd==x21,
-/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
-
-inst_11:// rs1==f20, rd==x20,
-/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
-
-inst_12:// rs1==f19, rd==x19,
-/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
-
-inst_13:// rs1==f18, rd==x18,
-/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
-
-inst_14:// rs1==f17, rd==x17,
-/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
-
-inst_15:// rs1==f16, rd==x16,
-/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
-
-inst_16:// rs1==f15, rd==x15,
-/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
-
-inst_17:// rs1==f14, rd==x14,
-/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
-
-inst_18:// rs1==f13, rd==x13,
-/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
-
-inst_19:// rs1==f12, rd==x12,
-/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
-
-inst_20:// rs1==f11, rd==x11,
-/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
-
-inst_21:// rs1==f10, rd==x10,
-/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
-
-inst_22:// rs1==f9, rd==x9,
-/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
-
-inst_23:// rs1==f8, rd==x8,
-/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,
-/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
-
-inst_25:// rs1==f6, rd==x6,
-/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
-
-inst_26:// rs1==f5, rd==x5,
-/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,
-/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
-
-inst_28:// rs1==f3, rd==x3,
-/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
-
-inst_29:// rs1==f2, rd==x2,
-/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
-
-inst_30:// rs1==f1, rd==x1,
-/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
-
-inst_31:// rs1==f0, rd==x0,
-/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9220181987118721706,64,FLEN)
-NAN_BOXED(18443554023973497514,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9222246136947933185,64,FLEN)
-NAN_BOXED(18445618173802708993,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-test_dataset_1:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 10*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b28-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b28-01.S
deleted file mode 100644
index 9b1915e68..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b28-01.S
+++ /dev/null
@@ -1,320 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:53 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b28 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b28)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fe and fm1 == 0x248ee18215dfa and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x3fe248ee18215dfa; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x3ff0000000000000; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x3ff4000000000000; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x3ff8000000000000; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xc000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x3ffc000000000000; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x400 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x4000000000000000; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x400 and fm1 == 0x2000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0x4002000000000000; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x400 and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x4004000000000000; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x400 and fm1 == 0x6000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x4006000000000000; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x43c and fm1 == 0xb72eb13dc494a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x43cb72eb13dc494a; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x43e0000000000000; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x7ff0000000000000; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x7ff0000000000001; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x7ff8000000000001; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0x8000000000000000; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
-
-inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x3fd and fm1 == 0xb008d57e19f88 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0xbfdb008d57e19f88; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
-
-inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0xbf80000000000000; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
-
-inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x400 and fm1 == 0x6000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0xc006000000000000; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
-
-inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x400 and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0xc004000000000000; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
-
-inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x400 and fm1 == 0x2000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0xc002000000000000; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
-
-inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x400 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0xc000000000000000; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
-
-inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x3ff and fm1 == 0xc000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0xbffc000000000000; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
-
-inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0xbff8000000000000; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0xbff4000000000000; valaddr_reg:x8;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
-
-inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x43d and fm1 == 0x967a4ae26514c and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0xc3d967a4ae26514c; valaddr_reg:x8;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
-
-inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0xc3e0000000000000; valaddr_reg:x8;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0xfff0000000000000; valaddr_reg:x8;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
-
-inst_28:// rs1==f3, rd==x3,
-/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
-
-inst_29:// rs1==f2, rd==x2,
-/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
-
-inst_30:// rs1==f1, rd==x1,
-/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
-
-inst_31:// rs1==f0, rd==x0,
-/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(4603321956570324474,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4608308318706860032,64,FLEN)
-NAN_BOXED(4609434218613702656,64,FLEN)
-NAN_BOXED(4610560118520545280,64,FLEN)
-NAN_BOXED(4611686018427387904,64,FLEN)
-NAN_BOXED(4612248968380809216,64,FLEN)
-NAN_BOXED(4612811918334230528,64,FLEN)
-NAN_BOXED(4613374868287651840,64,FLEN)
-NAN_BOXED(4885124574789519690,64,FLEN)
-NAN_BOXED(4890909195324358656,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(13824644088208662408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13836746905142427648,64,FLEN)
-NAN_BOXED(13836183955189006336,64,FLEN)
-NAN_BOXED(13835621005235585024,64,FLEN)
-NAN_BOXED(13835058055282163712,64,FLEN)
-NAN_BOXED(13833932155375321088,64,FLEN)
-NAN_BOXED(13832806255468478464,64,FLEN)
-test_dataset_1:
-NAN_BOXED(13831680355561635840,64,FLEN)
-NAN_BOXED(14112424864336204108,64,FLEN)
-NAN_BOXED(14114281232179134464,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 10*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b29-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b29-01.S
deleted file mode 100644
index 6ae0b5a07..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fcvtmod.w.d_b29-01.S
+++ /dev/null
@@ -1,663 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:53 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b29 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b29)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b8698; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x3fc08574923b8698; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x3fc08574923b8698; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x3fc08574923b8698; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x3fc08574923b8698; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x3fc08574923b8699; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x3fc08574923b8699; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0x3fc08574923b8699; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x3fc08574923b8699; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x3fc08574923b8699; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x3fc08574923b869a; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x3fc08574923b869a; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x3fc08574923b869a; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x3fc08574923b869a; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x3fc08574923b869a; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0x3fc08574923b869b; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
-
-inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0x3fc08574923b869b; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
-
-inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0x3fc08574923b869b; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
-
-inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0x3fc08574923b869b; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
-
-inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0x3fc08574923b869b; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
-
-inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0x3fc08574923b869c; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
-
-inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0x3fc08574923b869c; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
-
-inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0x3fc08574923b869c; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
-
-inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0x3fc08574923b869c; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0x3fc08574923b869c; valaddr_reg:x8;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
-
-inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x3fc08574923b869d; valaddr_reg:x8;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
-
-inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x3fc08574923b869d; valaddr_reg:x8;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0x3fc08574923b869d; valaddr_reg:x8;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
-
-inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x3fc08574923b869d; valaddr_reg:x8;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
-
-inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x3fc08574923b869d; valaddr_reg:x8;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
-
-inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x3fc08574923b869e; valaddr_reg:x8;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
-
-inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x3fc08574923b869e; valaddr_reg:x8;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
-
-inst_32:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x8;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
-
-inst_33:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x8;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
-
-inst_34:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x8;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
-
-inst_35:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x8;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
-
-inst_36:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x8;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
-
-inst_37:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x8;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
-
-inst_38:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x8;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
-
-inst_39:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x8;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
-
-inst_40:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x8;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
-
-inst_41:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x8;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
-
-inst_42:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x8;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
-
-inst_43:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x8;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
-
-inst_44:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x8;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
-
-inst_45:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x8;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
-
-inst_46:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x8;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)
-
-inst_47:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x8;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)
-
-inst_48:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x8;
-val_offset:24*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)
-
-inst_49:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x8;
-val_offset:25*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)
-
-inst_50:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x8;
-val_offset:26*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)
-
-inst_51:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x8;
-val_offset:27*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)
-
-inst_52:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x8;
-val_offset:28*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)
-
-inst_53:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x8;
-val_offset:29*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)
-
-inst_54:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x8;
-val_offset:30*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)
-
-inst_55:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x8;
-val_offset:31*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)
-
-inst_56:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x8;
-val_offset:32*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)
-
-inst_57:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x8;
-val_offset:33*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)
-
-inst_58:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x8;
-val_offset:34*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)
-
-inst_59:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x8;
-val_offset:35*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)
-
-inst_60:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x8;
-val_offset:36*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)
-
-inst_61:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x8;
-val_offset:37*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)
-
-inst_62:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x8;
-val_offset:38*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)
-
-inst_63:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x8;
-val_offset:39*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)
-
-inst_64:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x8;
-val_offset:40*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)
-
-inst_65:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x8;
-val_offset:41*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)
-
-inst_66:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x8;
-val_offset:42*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)
-
-inst_67:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x8;
-val_offset:43*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)
-
-inst_68:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x8;
-val_offset:44*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)
-
-inst_69:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x8;
-val_offset:45*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)
-
-inst_70:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x8;
-val_offset:46*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)
-
-inst_71:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x8;
-val_offset:47*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)
-
-inst_72:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x8;
-val_offset:48*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)
-
-inst_73:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x8;
-val_offset:49*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)
-
-inst_74:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x8;
-val_offset:50*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)
-
-inst_75:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x8;
-val_offset:51*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)
-
-inst_76:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x8;
-val_offset:52*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)
-
-inst_77:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x8;
-val_offset:53*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)
-
-inst_78:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x8;
-val_offset:54*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)
-
-inst_79:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x8;
-val_offset:55*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)
-
-inst_80:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x8;
-val_offset:56*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(4593818355633981080,64,FLEN)
-NAN_BOXED(4593818355633981080,64,FLEN)
-NAN_BOXED(4593818355633981080,64,FLEN)
-NAN_BOXED(4593818355633981080,64,FLEN)
-NAN_BOXED(4593818355633981080,64,FLEN)
-NAN_BOXED(4593818355633981081,64,FLEN)
-NAN_BOXED(4593818355633981081,64,FLEN)
-NAN_BOXED(4593818355633981081,64,FLEN)
-NAN_BOXED(4593818355633981081,64,FLEN)
-NAN_BOXED(4593818355633981081,64,FLEN)
-NAN_BOXED(4593818355633981082,64,FLEN)
-NAN_BOXED(4593818355633981082,64,FLEN)
-NAN_BOXED(4593818355633981082,64,FLEN)
-NAN_BOXED(4593818355633981082,64,FLEN)
-NAN_BOXED(4593818355633981082,64,FLEN)
-NAN_BOXED(4593818355633981083,64,FLEN)
-NAN_BOXED(4593818355633981083,64,FLEN)
-NAN_BOXED(4593818355633981083,64,FLEN)
-NAN_BOXED(4593818355633981083,64,FLEN)
-NAN_BOXED(4593818355633981083,64,FLEN)
-NAN_BOXED(4593818355633981084,64,FLEN)
-NAN_BOXED(4593818355633981084,64,FLEN)
-NAN_BOXED(4593818355633981084,64,FLEN)
-NAN_BOXED(4593818355633981084,64,FLEN)
-test_dataset_1:
-NAN_BOXED(4593818355633981084,64,FLEN)
-NAN_BOXED(4593818355633981085,64,FLEN)
-NAN_BOXED(4593818355633981085,64,FLEN)
-NAN_BOXED(4593818355633981085,64,FLEN)
-NAN_BOXED(4593818355633981085,64,FLEN)
-NAN_BOXED(4593818355633981085,64,FLEN)
-NAN_BOXED(4593818355633981086,64,FLEN)
-NAN_BOXED(4593818355633981086,64,FLEN)
-NAN_BOXED(4593818355633981086,64,FLEN)
-NAN_BOXED(4593818355633981086,64,FLEN)
-NAN_BOXED(4593818355633981086,64,FLEN)
-NAN_BOXED(4593818355633981087,64,FLEN)
-NAN_BOXED(4593818355633981087,64,FLEN)
-NAN_BOXED(4593818355633981087,64,FLEN)
-NAN_BOXED(4593818355633981087,64,FLEN)
-NAN_BOXED(4593818355633981087,64,FLEN)
-NAN_BOXED(13817190392488756888,64,FLEN)
-NAN_BOXED(13817190392488756888,64,FLEN)
-NAN_BOXED(13817190392488756888,64,FLEN)
-NAN_BOXED(13817190392488756888,64,FLEN)
-NAN_BOXED(13817190392488756888,64,FLEN)
-NAN_BOXED(13817190392488756889,64,FLEN)
-NAN_BOXED(13817190392488756889,64,FLEN)
-NAN_BOXED(13817190392488756889,64,FLEN)
-NAN_BOXED(13817190392488756889,64,FLEN)
-NAN_BOXED(13817190392488756889,64,FLEN)
-NAN_BOXED(13817190392488756890,64,FLEN)
-NAN_BOXED(13817190392488756890,64,FLEN)
-NAN_BOXED(13817190392488756890,64,FLEN)
-NAN_BOXED(13817190392488756890,64,FLEN)
-NAN_BOXED(13817190392488756890,64,FLEN)
-NAN_BOXED(13817190392488756891,64,FLEN)
-NAN_BOXED(13817190392488756891,64,FLEN)
-NAN_BOXED(13817190392488756891,64,FLEN)
-NAN_BOXED(13817190392488756891,64,FLEN)
-NAN_BOXED(13817190392488756891,64,FLEN)
-NAN_BOXED(13817190392488756892,64,FLEN)
-NAN_BOXED(13817190392488756892,64,FLEN)
-NAN_BOXED(13817190392488756892,64,FLEN)
-NAN_BOXED(13817190392488756892,64,FLEN)
-NAN_BOXED(13817190392488756892,64,FLEN)
-NAN_BOXED(13817190392488756893,64,FLEN)
-NAN_BOXED(13817190392488756893,64,FLEN)
-NAN_BOXED(13817190392488756893,64,FLEN)
-NAN_BOXED(13817190392488756893,64,FLEN)
-NAN_BOXED(13817190392488756893,64,FLEN)
-NAN_BOXED(13817190392488756894,64,FLEN)
-NAN_BOXED(13817190392488756894,64,FLEN)
-NAN_BOXED(13817190392488756894,64,FLEN)
-NAN_BOXED(13817190392488756894,64,FLEN)
-NAN_BOXED(13817190392488756894,64,FLEN)
-NAN_BOXED(13817190392488756895,64,FLEN)
-NAN_BOXED(13817190392488756895,64,FLEN)
-NAN_BOXED(13817190392488756895,64,FLEN)
-NAN_BOXED(13817190392488756895,64,FLEN)
-NAN_BOXED(13817190392488756895,64,FLEN)
-NAN_BOXED(4593818355633981086,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 108*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fleq.d_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fleq.d_b1-01.S
deleted file mode 100644
index c165c332e..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fleq.d_b1-01.S
+++ /dev/null
@@ -1,4740 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:14:28 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fleq.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fleq.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fleq.d_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fleq.d_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f29; op2:f29; dest:x30; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f30; op2:f31; dest:x29; op1val:0x0; op2val:0x1;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f28; op2:f27; dest:x28; op1val:0x0; op2val:0x8000000000000001;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f27; op2:f28; dest:x27; op1val:0x0; op2val:0x2;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f26; op2:f25; dest:x26; op1val:0x0; op2val:0x8000000000000002;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f25; op2:f26; dest:x25; op1val:0x0; op2val:0xfffffffffffff;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f24; op2:f23; dest:x24; op1val:0x0; op2val:0x800fffffffffffff;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f23; op2:f24; dest:x23; op1val:0x0; op2val:0x10000000000000;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f22; op2:f21; dest:x22; op1val:0x0; op2val:0x8010000000000000;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f21; op2:f22; dest:x21; op1val:0x0; op2val:0x10000000000002;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f20; op2:f19; dest:x20; op1val:0x0; op2val:0x8010000000000002;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f19; op2:f20; dest:x19; op1val:0x0; op2val:0x7fefffffffffffff;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f18; op2:f17; dest:x18; op1val:0x0; op2val:0xffefffffffffffff;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f17; op2:f18; dest:x17; op1val:0x0; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f16; op2:f15; dest:x16; op1val:0x0; op2val:0xfff0000000000000;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f15; op2:f16; dest:x15; op1val:0x0; op2val:0x7ff8000000000000;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f14; op2:f13; dest:x14; op1val:0x0; op2val:0xfff8000000000000;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f13; op2:f14; dest:x13; op1val:0x0; op2val:0x7ff8000000000001;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f12; op2:f11; dest:x12; op1val:0x0; op2val:0xfff8000000000001;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f11; op2:f12; dest:x11; op1val:0x0; op2val:0x7ff0000000000001;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f10; op2:f9; dest:x10; op1val:0x0; op2val:0xfff0000000000001;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f9; op2:f10; dest:x9; op1val:0x0; op2val:0x3ff0000000000000;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f8; op2:f7; dest:x8; op1val:0x0; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f7; op2:f8; dest:x7; op1val:0x8000000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f6; op2:f5; dest:x6; op1val:0x8000000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f5; op2:f6; dest:x5; op1val:0x8000000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f4; op2:f3; dest:x4; op1val:0x8000000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f3; op2:f4; dest:x3; op1val:0x8000000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f2; op2:f1; dest:x2; op1val:0x8000000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f1; op2:f2; dest:x1; op1val:0x8000000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f0; op2:f31; dest:x31; op1val:0x8000000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f0; dest:x31; op1val:0x8000000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x0; op1val:0x8000000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x0;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x1;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x2;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x0;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x1;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x2;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x0;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x1;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x2;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x0;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x1;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x2;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x0;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x1;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x2;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
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-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 80*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fleq.d_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fleq.d_b19-01.S
deleted file mode 100644
index a1e8af908..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fleq.d_b19-01.S
+++ /dev/null
@@ -1,8928 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:14:28 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fleq.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fleq.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fleq.d_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fleq.d_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x7fce759ff97b7507;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f29; op2:f29; dest:x30; op1val:0x7fce759ff97b7507; op2val:0x7fce759ff97b7507;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x004b878423be8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f30; op2:f31; dest:x29; op1val:0x7ff0000000000000; op2val:0x7fb004b878423be8;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x004b878423be8 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f28; op2:f27; dest:x28; op1val:0x7fb004b878423be8; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f27; op2:f28; dest:x27; op1val:0x7ff0000000000000; op2val:0x7fe405e69652cae2;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f26; op2:f25; dest:x26; op1val:0x7fce759ff97b7507; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f25; op2:f26; dest:x25; op1val:0x7fce759ff97b7507; op2val:0x7fd09941946801c5;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f24; op2:f23; dest:x24; op1val:0x7fd09941946801c5; op2val:0x7fce759ff97b7507;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f23; op2:f24; dest:x23; op1val:0x7fce759ff97b7507; op2val:0x7feac44ace32d282;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x569d571c24201 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f22; op2:f21; dest:x22; op1val:0x7ff0000000000000; op2val:0x7fb569d571c24201;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x569d571c24201 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f21; op2:f22; dest:x21; op1val:0x7fb569d571c24201; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f20; op2:f19; dest:x20; op1val:0x7ff0000000000000; op2val:0x7feac44ace32d282;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f19; op2:f20; dest:x19; op1val:0x7fce759ff97b7507; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x0409f707c3583 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f18; op2:f17; dest:x18; op1val:0x7ff0000000000000; op2val:0x7fb0409f707c3583;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x0409f707c3583 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f17; op2:f18; dest:x17; op1val:0x7fb0409f707c3583; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f16; op2:f15; dest:x16; op1val:0x7ff0000000000000; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f15; op2:f16; dest:x15; op1val:0x7fce759ff97b7507; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f14; op2:f13; dest:x14; op1val:0xffdd2b592ef4e4e6; op2val:0x7fce759ff97b7507;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f13; op2:f14; dest:x13; op1val:0x7fce759ff97b7507; op2val:0xffede7300593ddb7;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7ec266adcb15f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f12; op2:f11; dest:x12; op1val:0x7ff0000000000000; op2val:0xffb7ec266adcb15f;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7ec266adcb15f and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f11; op2:f12; dest:x11; op1val:0xffb7ec266adcb15f; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f10; op2:f9; dest:x10; op1val:0x7ff0000000000000; op2val:0xffede7300593ddb7;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f9; op2:f10; dest:x9; op1val:0x7fce759ff97b7507; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x399e37c2fb926 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f8; op2:f7; dest:x8; op1val:0x7ff0000000000000; op2val:0xffb399e37c2fb926;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x7fb and fm1 == 0x399e37c2fb926 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f7; op2:f8; dest:x7; op1val:0xffb399e37c2fb926; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f6; op2:f5; dest:x6; op1val:0x7ff0000000000000; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f5; op2:f6; dest:x5; op1val:0x7fce759ff97b7507; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f4; op2:f3; dest:x4; op1val:0xffe0c1b6ea69558e; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f3; op2:f4; dest:x3; op1val:0x7fce759ff97b7507; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f2; op2:f1; dest:x2; op1val:0xffc0e3e4312fc728; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f1; op2:f2; dest:x1; op1val:0x7fce759ff97b7507; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xd4e5c31a3975f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f0; op2:f31; dest:x31; op1val:0x3137cb6875068; op2val:0x7fdd4e5c31a3975f;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3137cb6875068 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f0; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0x3137cb6875068;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x0; op1val:0x3137cb6875068; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3137cb6875068 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x3137cb6875068;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x04ebfabda54d7 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x4dcb3b62b25ff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x4ebfabda54d7; op2val:0x7fc4dcb3b62b25ff;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x04ebfabda54d7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0x4ebfabda54d7;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x04ebfabda54d7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x4ebfabda54d7; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x04ebfabda54d7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x4ebfabda54d7;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xf8c50a18d0c04 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0x7fbf8c50a18d0c04;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xec2df2149240f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0x1ec2df2149240f;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xec2df2149240f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x1ec2df2149240f;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x43fe46d2b7ce6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0x7fb43fe46d2b7ce6;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xec2df2149240f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0x1ec2df2149240f;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x093dbe3aa0387 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0x7fb093dbe3aa0387;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xec2df2149240f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0x1ec2df2149240f;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xf6025caa2d205 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3137cb6875068; op2val:0xffdf6025caa2d205;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3137cb6875068 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0x3137cb6875068;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3137cb6875068; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x9bff6a8783cf3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3137cb6875068; op2val:0xffc9bff6a8783cf3;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3137cb6875068 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0x3137cb6875068;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3137cb6875068; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x0c90875ccb5d8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0xffb0c90875ccb5d8;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xec2df2149240f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0x1ec2df2149240f;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xae9e55abc765f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0xffbae9e55abc765f;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 0 and fe2 == 0x001 and fm2 == 0xec2df2149240f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0x1ec2df2149240f;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x47f2e5cadc271 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3137cb6875068; op2val:0xffd47f2e5cadc271;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3137cb6875068 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0x3137cb6875068;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3137cb6875068; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x0;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 0 and fe1 == 0x401 and fm1 == 0x11c8af0ae0986 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x40111c8af0ae0986; op2val:0x0;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x401 and fm2 == 0x11c8af0ae0986 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x40111c8af0ae0986;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x401 and fm2 == 0x11c8af0ae0986 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x40111c8af0ae0986;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x004b878423be8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb004b878423be8; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x004b878423be8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x7fb004b878423be8;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x004b878423be8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb004b878423be8; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x004b878423be8 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb004b878423be8; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x004b878423be8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fb004b878423be8;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x004b878423be8 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb004b878423be8; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x004b878423be8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb004b878423be8; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x004b878423be8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb004b878423be8; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0cf11346ee18e and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xcf11346ee18e; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0cf11346ee18e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xcf11346ee18e;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0cf11346ee18e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xcf11346ee18e; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0cf11346ee18e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xcf11346ee18e;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x014b4eba4b028 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x14b4eba4b028; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x014b4eba4b028 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x14b4eba4b028;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x014b4eba4b028 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x14b4eba4b028; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x014b4eba4b028 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x14b4eba4b028;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x816ac0c54cf8a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x816ac0c54cf8a;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x816ac0c54cf8a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x816ac0c54cf8a;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x94fdd88765c1f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0x7fe94fdd88765c1f;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x816ac0c54cf8a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0x816ac0c54cf8a;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x4b8d2dc948469 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0x7fe4b8d2dc948469;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x816ac0c54cf8a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0x816ac0c54cf8a;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0cf11346ee18e and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xcf11346ee18e; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0cf11346ee18e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xcf11346ee18e;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0cf11346ee18e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xcf11346ee18e; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0cf11346ee18e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xcf11346ee18e; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x4fb4a933fe34f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0xffe4fb4a933fe34f;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x816ac0c54cf8a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0x816ac0c54cf8a;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x816ac0c54cf8a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x816ac0c54cf8a;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0cf11346ee18e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xcf11346ee18e; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x0;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1ff65f57ff366 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff1ff65f57ff366; op2val:0x0;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x1ff65f57ff366 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff1ff65f57ff366;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x1ff65f57ff366 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x3ff1ff65f57ff366;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xd4e5c31a3975f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0x7fdd4e5c31a3975f;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x35a452e11324d and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0x35a452e11324d;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x35a452e11324d and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x35a452e11324d;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x055d3b7ce8508 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x4dcb3b62b25ff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x55d3b7ce8508; op2val:0x7fc4dcb3b62b25ff;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x055d3b7ce8508 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0x55d3b7ce8508;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x055d3b7ce8508 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x55d3b7ce8508; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x055d3b7ce8508 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x55d3b7ce8508;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xf8c50a18d0c04 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0x7fbf8c50a18d0c04;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x0c359e655fb81 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0x20c359e655fb81;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x0c359e655fb81 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x20c359e655fb81;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x43fe46d2b7ce6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0x7fb43fe46d2b7ce6;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x0c359e655fb81 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0x20c359e655fb81;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x093dbe3aa0387 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0x7fb093dbe3aa0387;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x0c359e655fb81 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0x20c359e655fb81;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xf6025caa2d205 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0xffdf6025caa2d205;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x35a452e11324d and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0x35a452e11324d;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x9bff6a8783cf3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0xffc9bff6a8783cf3;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x35a452e11324d and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0x35a452e11324d;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x0c90875ccb5d8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0xffb0c90875ccb5d8;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x0c359e655fb81 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0x20c359e655fb81;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xae9e55abc765f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0xffbae9e55abc765f;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 0 and fe2 == 0x002 and fm2 == 0x0c359e655fb81 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0x20c359e655fb81;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x47f2e5cadc271 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0xffd47f2e5cadc271;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x35a452e11324d and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0x35a452e11324d;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x0;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 0 and fe1 == 0x401 and fm1 == 0x2a6496228606e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x4012a6496228606e; op2val:0x0;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x401 and fm2 == 0x2a6496228606e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x4012a6496228606e;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x401 and fm2 == 0x2a6496228606e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x4012a6496228606e;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x569d571c24201 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb569d571c24201; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x569d571c24201 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x7fb569d571c24201;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x569d571c24201 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb569d571c24201; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x569d571c24201 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb569d571c24201; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x569d571c24201 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fb569d571c24201;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x569d571c24201 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb569d571c24201; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x569d571c24201 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb569d571c24201; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x569d571c24201 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb569d571c24201; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x114ce95016c16 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x114ce95016c16; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x114ce95016c16 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x114ce95016c16;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x114ce95016c16 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x114ce95016c16; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x114ce95016c16 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x114ce95016c16;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01bae4219be02 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1bae4219be02; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01bae4219be02 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x1bae4219be02;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01bae4219be02 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1bae4219be02; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01bae4219be02 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x1bae4219be02;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xad011d20e38de and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xad011d20e38de;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xad011d20e38de and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xad011d20e38de;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x94fdd88765c1f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0x7fe94fdd88765c1f;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xad011d20e38de and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0xad011d20e38de;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x4b8d2dc948469 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0x7fe4b8d2dc948469;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xad011d20e38de and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0xad011d20e38de;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x114ce95016c16 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x114ce95016c16; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x114ce95016c16 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x114ce95016c16;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x114ce95016c16 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x114ce95016c16; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x114ce95016c16 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x114ce95016c16; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x4fb4a933fe34f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0xffe4fb4a933fe34f;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xad011d20e38de and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0xad011d20e38de;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xad011d20e38de and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xad011d20e38de;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x114ce95016c16 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x114ce95016c16; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x0;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x80f28c9e9c76b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff80f28c9e9c76b; op2val:0x0;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x80f28c9e9c76b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff80f28c9e9c76b;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x80f28c9e9c76b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x3ff80f28c9e9c76b;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x0409f707c3583 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb0409f707c3583; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x0409f707c3583 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x7fb0409f707c3583;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x0409f707c3583 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb0409f707c3583; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x0409f707c3583 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb0409f707c3583; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x0409f707c3583 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fb0409f707c3583;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x0409f707c3583 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb0409f707c3583; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x0409f707c3583 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb0409f707c3583; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x0409f707c3583 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb0409f707c3583; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d2178c8e4bc2 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd2178c8e4bc2; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d2178c8e4bc2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xd2178c8e4bc2;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d2178c8e4bc2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd2178c8e4bc2; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d2178c8e4bc2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xd2178c8e4bc2;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x015025adb0793 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15025adb0793; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x015025adb0793 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x15025adb0793;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x015025adb0793 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15025adb0793; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x015025adb0793 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x15025adb0793;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x834eb7d8ef590 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x834eb7d8ef590;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x834eb7d8ef590 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x834eb7d8ef590;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x94fdd88765c1f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0x7fe94fdd88765c1f;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x834eb7d8ef590 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0x834eb7d8ef590;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x4b8d2dc948469 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0x7fe4b8d2dc948469;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x834eb7d8ef590 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0x834eb7d8ef590;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d2178c8e4bc2 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd2178c8e4bc2; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d2178c8e4bc2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xd2178c8e4bc2;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d2178c8e4bc2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd2178c8e4bc2; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d2178c8e4bc2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd2178c8e4bc2; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x4fb4a933fe34f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0xffe4fb4a933fe34f;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x834eb7d8ef590 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0x834eb7d8ef590;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x834eb7d8ef590 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x834eb7d8ef590;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d2178c8e4bc2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd2178c8e4bc2; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x0;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x242b3b0a4387a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff242b3b0a4387a; op2val:0x0;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x242b3b0a4387a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff242b3b0a4387a;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x242b3b0a4387a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x3ff242b3b0a4387a;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7ec266adcb15f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffb7ec266adcb15f;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7ec266adcb15f and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb7ec266adcb15f; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x399e37c2fb926 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffb399e37c2fb926;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x399e37c2fb926 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb399e37c2fb926; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xd4e5c31a3975f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0x7fdd4e5c31a3975f;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e443bf91c5dd and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0x8005e443bf91c5dd;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e443bf91c5dd and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x8005e443bf91c5dd;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x096d393282d63 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x4dcb3b62b25ff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800096d393282d63; op2val:0x7fc4dcb3b62b25ff;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x096d393282d63 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0x800096d393282d63;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x096d393282d63 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800096d393282d63; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x096d393282d63 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x800096d393282d63;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xf8c50a18d0c04 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0x7fbf8c50a18d0c04;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd7552bdd8dd50 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0x802d7552bdd8dd50;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd7552bdd8dd50 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x802d7552bdd8dd50;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x43fe46d2b7ce6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0x7fb43fe46d2b7ce6;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd7552bdd8dd50 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0x802d7552bdd8dd50;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x093dbe3aa0387 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0x7fb093dbe3aa0387;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd7552bdd8dd50 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0x802d7552bdd8dd50;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xf6025caa2d205 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0xffdf6025caa2d205;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e443bf91c5dd and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0x8005e443bf91c5dd;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x9bff6a8783cf3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0xffc9bff6a8783cf3;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e443bf91c5dd and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0x8005e443bf91c5dd;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x0c90875ccb5d8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0xffb0c90875ccb5d8;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd7552bdd8dd50 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0x802d7552bdd8dd50;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xae9e55abc765f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0xffbae9e55abc765f;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd7552bdd8dd50 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0x802d7552bdd8dd50;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x47f2e5cadc271 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0xffd47f2e5cadc271;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e443bf91c5dd and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0x8005e443bf91c5dd;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x0;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 1 and fe1 == 0x402 and fm1 == 0x06300128a7be9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc0206300128a7be9; op2val:0x0;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x06300128a7be9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc0206300128a7be9;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x06300128a7be9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xc0206300128a7be9;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7ec266adcb15f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb7ec266adcb15f; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7ec266adcb15f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xffb7ec266adcb15f;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7ec266adcb15f and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb7ec266adcb15f; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7ec266adcb15f and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb7ec266adcb15f; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7ec266adcb15f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb7ec266adcb15f; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7ec266adcb15f and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb7ec266adcb15f; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1353dad8f9fcc and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001353dad8f9fcc; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1353dad8f9fcc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8001353dad8f9fcc;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1353dad8f9fcc and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001353dad8f9fcc; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1353dad8f9fcc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x8001353dad8f9fcc;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01eec915b2994 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001eec915b2994; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01eec915b2994 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x80001eec915b2994;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01eec915b2994 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001eec915b2994; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01eec915b2994 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x80001eec915b2994;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc1468c79c3df8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x800c1468c79c3df8;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc1468c79c3df8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x800c1468c79c3df8;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x94fdd88765c1f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0x7fe94fdd88765c1f;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc1468c79c3df8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0x800c1468c79c3df8;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x4b8d2dc948469 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0x7fe4b8d2dc948469;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc1468c79c3df8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0x800c1468c79c3df8;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1353dad8f9fcc and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001353dad8f9fcc; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1353dad8f9fcc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8001353dad8f9fcc;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1353dad8f9fcc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001353dad8f9fcc; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1353dad8f9fcc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001353dad8f9fcc; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x4fb4a933fe34f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0xffe4fb4a933fe34f;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc1468c79c3df8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0x800c1468c79c3df8;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc1468c79c3df8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x800c1468c79c3df8;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1353dad8f9fcc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001353dad8f9fcc; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x0;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xae0d6ce341771 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbffae0d6ce341771; op2val:0x0;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xae0d6ce341771 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbffae0d6ce341771;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xae0d6ce341771 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xbffae0d6ce341771;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x399e37c2fb926 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb399e37c2fb926; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x399e37c2fb926 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xffb399e37c2fb926;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x399e37c2fb926 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb399e37c2fb926; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x399e37c2fb926 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb399e37c2fb926; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x399e37c2fb926 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb399e37c2fb926; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x399e37c2fb926 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb399e37c2fb926; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0fd6141352983 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000fd6141352983; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0fd6141352983 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000fd6141352983;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0fd6141352983 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000fd6141352983; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0fd6141352983 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x8000fd6141352983;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01956868550f3 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001956868550f3; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01956868550f3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x80001956868550f3;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01956868550f3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001956868550f3; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01956868550f3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x80001956868550f3;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x9e5cc8c139f1c and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8009e5cc8c139f1c;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x9e5cc8c139f1c and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x8009e5cc8c139f1c;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x94fdd88765c1f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0x7fe94fdd88765c1f;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x9e5cc8c139f1c and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0x8009e5cc8c139f1c;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x4b8d2dc948469 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0x7fe4b8d2dc948469;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x9e5cc8c139f1c and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0x8009e5cc8c139f1c;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0fd6141352983 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000fd6141352983; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0fd6141352983 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8000fd6141352983;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0fd6141352983 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000fd6141352983; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0fd6141352983 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000fd6141352983; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x4fb4a933fe34f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0xffe4fb4a933fe34f;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x9e5cc8c139f1c and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0x8009e5cc8c139f1c;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x9e5cc8c139f1c and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8009e5cc8c139f1c;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0fd6141352983 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000fd6141352983; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x0;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x605e3d372e471 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbff605e3d372e471; op2val:0x0;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x605e3d372e471 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbff605e3d372e471;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x605e3d372e471 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xbff605e3d372e471;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xd4e5c31a3975f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0x7fdd4e5c31a3975f;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6c4e25604ed00 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0x8006c4e25604ed00;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6c4e25604ed00 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x8006c4e25604ed00;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0ad49d566e480 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x4dcb3b62b25ff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000ad49d566e480; op2val:0x7fc4dcb3b62b25ff;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0ad49d566e480 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0x8000ad49d566e480;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0ad49d566e480 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000ad49d566e480; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0ad49d566e480 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x8000ad49d566e480;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xf8c50a18d0c04 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0x7fbf8c50a18d0c04;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0ec35d70c5080 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0x8030ec35d70c5080;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0ec35d70c5080 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x8030ec35d70c5080;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x43fe46d2b7ce6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0x7fb43fe46d2b7ce6;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0ec35d70c5080 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0x8030ec35d70c5080;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x093dbe3aa0387 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0x7fb093dbe3aa0387;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0ec35d70c5080 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0x8030ec35d70c5080;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xf6025caa2d205 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0xffdf6025caa2d205;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6c4e25604ed00 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0x8006c4e25604ed00;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x9bff6a8783cf3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0xffc9bff6a8783cf3;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6c4e25604ed00 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0x8006c4e25604ed00;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x0c90875ccb5d8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0xffb0c90875ccb5d8;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0ec35d70c5080 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0x8030ec35d70c5080;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xae9e55abc765f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0xffbae9e55abc765f;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0ec35d70c5080 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0x8030ec35d70c5080;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x47f2e5cadc271 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0xffd47f2e5cadc271;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6c4e25604ed00 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0x8006c4e25604ed00;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x0;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0x402 and fm1 == 0x2d3be740985a9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc022d3be740985a9; op2val:0x0;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x2d3be740985a9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc022d3be740985a9;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x402 and fm2 == 0x2d3be740985a9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xc022d3be740985a9;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xd4e5c31a3975f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0x7fdd4e5c31a3975f;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1b4ac2dd761b7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0x8001b4ac2dd761b7;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1b4ac2dd761b7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x8001b4ac2dd761b7;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x02baad1625692 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x4dcb3b62b25ff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80002baad1625692; op2val:0x7fc4dcb3b62b25ff;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x02baad1625692 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0x80002baad1625692;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x02baad1625692 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80002baad1625692; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x02baad1625692 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x80002baad1625692;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-
-inst_578:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1110*FLEN/8, x10, x6, x7)
-
-inst_579:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xf8c50a18d0c04 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0x7fbf8c50a18d0c04;
-valaddr_reg:x9; val_offset:1112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1112*FLEN/8, x10, x6, x7)
-
-inst_580:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x10eb9ca69d123 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0x80110eb9ca69d123;
-valaddr_reg:x9; val_offset:1114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1114*FLEN/8, x10, x6, x7)
-
-inst_581:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1116*FLEN/8, x10, x6, x7)
-
-inst_582:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x10eb9ca69d123 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x80110eb9ca69d123;
-valaddr_reg:x9; val_offset:1118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1118*FLEN/8, x10, x6, x7)
-
-inst_583:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1120*FLEN/8, x10, x6, x7)
-
-inst_584:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x43fe46d2b7ce6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0x7fb43fe46d2b7ce6;
-valaddr_reg:x9; val_offset:1122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1122*FLEN/8, x10, x6, x7)
-
-inst_585:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x10eb9ca69d123 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0x80110eb9ca69d123;
-valaddr_reg:x9; val_offset:1124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1124*FLEN/8, x10, x6, x7)
-
-inst_586:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1126*FLEN/8, x10, x6, x7)
-
-inst_587:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1128*FLEN/8, x10, x6, x7)
-
-inst_588:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x093dbe3aa0387 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0x7fb093dbe3aa0387;
-valaddr_reg:x9; val_offset:1130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1130*FLEN/8, x10, x6, x7)
-
-inst_589:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x10eb9ca69d123 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0x80110eb9ca69d123;
-valaddr_reg:x9; val_offset:1132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1132*FLEN/8, x10, x6, x7)
-
-inst_590:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1134*FLEN/8, x10, x6, x7)
-
-inst_591:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1136*FLEN/8, x10, x6, x7)
-
-inst_592:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xf6025caa2d205 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0xffdf6025caa2d205;
-valaddr_reg:x9; val_offset:1138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1138*FLEN/8, x10, x6, x7)
-
-inst_593:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1b4ac2dd761b7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0x8001b4ac2dd761b7;
-valaddr_reg:x9; val_offset:1140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1140*FLEN/8, x10, x6, x7)
-
-inst_594:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1142*FLEN/8, x10, x6, x7)
-
-inst_595:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1144*FLEN/8, x10, x6, x7)
-
-inst_596:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x9bff6a8783cf3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0xffc9bff6a8783cf3;
-valaddr_reg:x9; val_offset:1146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1146*FLEN/8, x10, x6, x7)
-
-inst_597:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1b4ac2dd761b7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0x8001b4ac2dd761b7;
-valaddr_reg:x9; val_offset:1148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1148*FLEN/8, x10, x6, x7)
-
-inst_598:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1150*FLEN/8, x10, x6, x7)
-
-inst_599:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1152*FLEN/8, x10, x6, x7)
-
-inst_600:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x0c90875ccb5d8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0xffb0c90875ccb5d8;
-valaddr_reg:x9; val_offset:1154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1154*FLEN/8, x10, x6, x7)
-
-inst_601:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x10eb9ca69d123 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0x80110eb9ca69d123;
-valaddr_reg:x9; val_offset:1156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1156*FLEN/8, x10, x6, x7)
-
-inst_602:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1158*FLEN/8, x10, x6, x7)
-
-inst_603:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1160*FLEN/8, x10, x6, x7)
-
-inst_604:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xae9e55abc765f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0xffbae9e55abc765f;
-valaddr_reg:x9; val_offset:1162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1162*FLEN/8, x10, x6, x7)
-
-inst_605:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 1 and fe2 == 0x001 and fm2 == 0x10eb9ca69d123 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0x80110eb9ca69d123;
-valaddr_reg:x9; val_offset:1164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1164*FLEN/8, x10, x6, x7)
-
-inst_606:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1166*FLEN/8, x10, x6, x7)
-
-inst_607:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1168*FLEN/8, x10, x6, x7)
-
-inst_608:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x47f2e5cadc271 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0xffd47f2e5cadc271;
-valaddr_reg:x9; val_offset:1170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1170*FLEN/8, x10, x6, x7)
-
-inst_609:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1b4ac2dd761b7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0x8001b4ac2dd761b7;
-valaddr_reg:x9; val_offset:1172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1172*FLEN/8, x10, x6, x7)
-
-inst_610:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1174*FLEN/8, x10, x6, x7)
-
-inst_611:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x0;
-valaddr_reg:x9; val_offset:1176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1176*FLEN/8, x10, x6, x7)
-
-inst_612:// fs1 == 1 and fe1 == 0x400 and fm1 == 0x2fa24c650ac14 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc002fa24c650ac14; op2val:0x0;
-valaddr_reg:x9; val_offset:1178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1178*FLEN/8, x10, x6, x7)
-
-inst_613:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x2fa24c650ac14 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc002fa24c650ac14;
-valaddr_reg:x9; val_offset:1180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1180*FLEN/8, x10, x6, x7)
-
-inst_614:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x2fa24c650ac14 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xc002fa24c650ac14;
-valaddr_reg:x9; val_offset:1182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1182*FLEN/8, x10, x6, x7)
-
-inst_615:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1184*FLEN/8, x10, x6, x7)
-
-inst_616:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1186*FLEN/8, x10, x6, x7)
-
-inst_617:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xd4e5c31a3975f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x7fdd4e5c31a3975f;
-valaddr_reg:x9; val_offset:1188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1188*FLEN/8, x10, x6, x7)
-
-inst_618:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1190*FLEN/8, x10, x6, x7)
-
-inst_619:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1192*FLEN/8, x10, x6, x7)
-
-inst_620:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1194*FLEN/8, x10, x6, x7)
-
-inst_621:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1196*FLEN/8, x10, x6, x7)
-
-inst_622:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1198*FLEN/8, x10, x6, x7)
-
-inst_623:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1200*FLEN/8, x10, x6, x7)
-
-inst_624:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1202*FLEN/8, x10, x6, x7)
-
-inst_625:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1204*FLEN/8, x10, x6, x7)
-
-inst_626:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1206*FLEN/8, x10, x6, x7)
-
-inst_627:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1208*FLEN/8, x10, x6, x7)
-
-inst_628:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1210*FLEN/8, x10, x6, x7)
-
-inst_629:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1212*FLEN/8, x10, x6, x7)
-
-inst_630:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1214*FLEN/8, x10, x6, x7)
-
-inst_631:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1216*FLEN/8, x10, x6, x7)
-
-inst_632:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1218*FLEN/8, x10, x6, x7)
-
-inst_633:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1220*FLEN/8, x10, x6, x7)
-
-inst_634:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x097889c6218ac and fs2 == 0 and fe2 == 0x000 and fm2 == 0x21b5c662d267b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x97889c6218ac; op2val:0x21b5c662d267b;
-valaddr_reg:x9; val_offset:1222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1222*FLEN/8, x10, x6, x7)
-
-inst_635:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x097889c6218ac and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x97889c6218ac;
-valaddr_reg:x9; val_offset:1224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1224*FLEN/8, x10, x6, x7)
-
-inst_636:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x097889c6218ac and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x97889c6218ac; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1226*FLEN/8, x10, x6, x7)
-
-inst_637:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x097889c6218ac and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x97889c6218ac;
-valaddr_reg:x9; val_offset:1228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1228*FLEN/8, x10, x6, x7)
-
-inst_638:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1230*FLEN/8, x10, x6, x7)
-
-inst_639:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x197d0ed8b1e34 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0x197d0ed8b1e34;
-valaddr_reg:x9; val_offset:1232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1232*FLEN/8, x10, x6, x7)
-
-inst_640:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xd98ae8b28d198 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x2d98ae8b28d198;
-valaddr_reg:x9; val_offset:1234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1234*FLEN/8, x10, x6, x7)
-
-inst_641:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1236*FLEN/8, x10, x6, x7)
-
-inst_642:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xd98ae8b28d198 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x2d98ae8b28d198;
-valaddr_reg:x9; val_offset:1238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1238*FLEN/8, x10, x6, x7)
-
-inst_643:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1240*FLEN/8, x10, x6, x7)
-
-inst_644:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x105c326c5af30 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0x105c326c5af30;
-valaddr_reg:x9; val_offset:1242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1242*FLEN/8, x10, x6, x7)
-
-inst_645:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xd98ae8b28d198 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x2d98ae8b28d198;
-valaddr_reg:x9; val_offset:1244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1244*FLEN/8, x10, x6, x7)
-
-inst_646:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1246*FLEN/8, x10, x6, x7)
-
-inst_647:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1248*FLEN/8, x10, x6, x7)
-
-inst_648:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d64b86ad9094 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0xd64b86ad9094;
-valaddr_reg:x9; val_offset:1250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1250*FLEN/8, x10, x6, x7)
-
-inst_649:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xd98ae8b28d198 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x2d98ae8b28d198;
-valaddr_reg:x9; val_offset:1252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1252*FLEN/8, x10, x6, x7)
-
-inst_650:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1254*FLEN/8, x10, x6, x7)
-
-inst_651:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1256*FLEN/8, x10, x6, x7)
-
-inst_652:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1258*FLEN/8, x10, x6, x7)
-
-inst_653:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1260*FLEN/8, x10, x6, x7)
-
-inst_654:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1262*FLEN/8, x10, x6, x7)
-
-inst_655:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1264*FLEN/8, x10, x6, x7)
-
-inst_656:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d8fae5b11a26 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0x8000d8fae5b11a26;
-valaddr_reg:x9; val_offset:1266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1266*FLEN/8, x10, x6, x7)
-
-inst_657:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xd98ae8b28d198 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x2d98ae8b28d198;
-valaddr_reg:x9; val_offset:1268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1268*FLEN/8, x10, x6, x7)
-
-inst_658:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1270*FLEN/8, x10, x6, x7)
-
-inst_659:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1272*FLEN/8, x10, x6, x7)
-
-inst_660:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x15be852c0ecf4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0x80015be852c0ecf4;
-valaddr_reg:x9; val_offset:1274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1274*FLEN/8, x10, x6, x7)
-
-inst_661:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xd98ae8b28d198 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x2d98ae8b28d198;
-valaddr_reg:x9; val_offset:1276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1276*FLEN/8, x10, x6, x7)
-
-inst_662:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1278*FLEN/8, x10, x6, x7)
-
-inst_663:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1280*FLEN/8, x10, x6, x7)
-
-inst_664:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1282*FLEN/8, x10, x6, x7)
-
-inst_665:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x0;
-valaddr_reg:x9; val_offset:1284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1284*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_5)
-
-inst_666:// fs1 == 0 and fe1 == 0x402 and fm1 == 0x076ab4deeec91 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x402076ab4deeec91; op2val:0x0;
-valaddr_reg:x9; val_offset:1286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1286*FLEN/8, x10, x6, x7)
-
-inst_667:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x076ab4deeec91 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x402076ab4deeec91;
-valaddr_reg:x9; val_offset:1288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1288*FLEN/8, x10, x6, x7)
-
-inst_668:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x076ab4deeec91 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x402076ab4deeec91;
-valaddr_reg:x9; val_offset:1290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1290*FLEN/8, x10, x6, x7)
-
-inst_669:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1292*FLEN/8, x10, x6, x7)
-
-inst_670:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1294*FLEN/8, x10, x6, x7)
-
-inst_671:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x4dcb3b62b25ff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x7fc4dcb3b62b25ff;
-valaddr_reg:x9; val_offset:1296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1296*FLEN/8, x10, x6, x7)
-
-inst_672:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1298*FLEN/8, x10, x6, x7)
-
-inst_673:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1300*FLEN/8, x10, x6, x7)
-
-inst_674:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1302*FLEN/8, x10, x6, x7)
-
-inst_675:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1304*FLEN/8, x10, x6, x7)
-
-inst_676:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1306*FLEN/8, x10, x6, x7)
-
-inst_677:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1308*FLEN/8, x10, x6, x7)
-
-inst_678:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1310*FLEN/8, x10, x6, x7)
-
-inst_679:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1312*FLEN/8, x10, x6, x7)
-
-inst_680:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1314*FLEN/8, x10, x6, x7)
-
-inst_681:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1316*FLEN/8, x10, x6, x7)
-
-inst_682:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1318*FLEN/8, x10, x6, x7)
-
-inst_683:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1320*FLEN/8, x10, x6, x7)
-
-inst_684:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1322*FLEN/8, x10, x6, x7)
-
-inst_685:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1324*FLEN/8, x10, x6, x7)
-
-inst_686:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1326*FLEN/8, x10, x6, x7)
-
-inst_687:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1328*FLEN/8, x10, x6, x7)
-
-inst_688:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1330*FLEN/8, x10, x6, x7)
-
-inst_689:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x21b5c662d267b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x21b5c662d267b;
-valaddr_reg:x9; val_offset:1332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1332*FLEN/8, x10, x6, x7)
-
-inst_690:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1334*FLEN/8, x10, x6, x7)
-
-inst_691:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x028c817c11c9f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x28c817c11c9f;
-valaddr_reg:x9; val_offset:1336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1336*FLEN/8, x10, x6, x7)
-
-inst_692:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x028c817c11c9f and fs2 == 0 and fe2 == 0x001 and fm2 == 0x5119bfdc380d2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x28c817c11c9f; op2val:0x15119bfdc380d2;
-valaddr_reg:x9; val_offset:1338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1338*FLEN/8, x10, x6, x7)
-
-inst_693:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1340*FLEN/8, x10, x6, x7)
-
-inst_694:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x5119bfdc380d2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x15119bfdc380d2;
-valaddr_reg:x9; val_offset:1342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1342*FLEN/8, x10, x6, x7)
-
-inst_695:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1344*FLEN/8, x10, x6, x7)
-
-inst_696:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01a2d1d7a2b1e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x1a2d1d7a2b1e;
-valaddr_reg:x9; val_offset:1346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1346*FLEN/8, x10, x6, x7)
-
-inst_697:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01a2d1d7a2b1e and fs2 == 0 and fe2 == 0x001 and fm2 == 0x5119bfdc380d2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1a2d1d7a2b1e; op2val:0x15119bfdc380d2;
-valaddr_reg:x9; val_offset:1348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1348*FLEN/8, x10, x6, x7)
-
-inst_698:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1350*FLEN/8, x10, x6, x7)
-
-inst_699:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1352*FLEN/8, x10, x6, x7)
-
-inst_700:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0156df3de280f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x156df3de280f;
-valaddr_reg:x9; val_offset:1354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1354*FLEN/8, x10, x6, x7)
-
-inst_701:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0156df3de280f and fs2 == 0 and fe2 == 0x001 and fm2 == 0x5119bfdc380d2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x156df3de280f; op2val:0x15119bfdc380d2;
-valaddr_reg:x9; val_offset:1356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1356*FLEN/8, x10, x6, x7)
-
-inst_702:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1358*FLEN/8, x10, x6, x7)
-
-inst_703:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1360*FLEN/8, x10, x6, x7)
-
-inst_704:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0a23bfe815416 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x8000a23bfe815416;
-valaddr_reg:x9; val_offset:1362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1362*FLEN/8, x10, x6, x7)
-
-inst_705:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0a23bfe815416 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x21b5c662d267b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000a23bfe815416; op2val:0x21b5c662d267b;
-valaddr_reg:x9; val_offset:1364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1364*FLEN/8, x10, x6, x7)
-
-inst_706:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1366*FLEN/8, x10, x6, x7)
-
-inst_707:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1368*FLEN/8, x10, x6, x7)
-
-inst_708:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x042929a1b2ce1 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x800042929a1b2ce1;
-valaddr_reg:x9; val_offset:1370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1370*FLEN/8, x10, x6, x7)
-
-inst_709:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x042929a1b2ce1 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x21b5c662d267b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800042929a1b2ce1; op2val:0x21b5c662d267b;
-valaddr_reg:x9; val_offset:1372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1372*FLEN/8, x10, x6, x7)
-
-inst_710:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1374*FLEN/8, x10, x6, x7)
-
-inst_711:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1376*FLEN/8, x10, x6, x7)
-
-inst_712:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x015b2b091b5d1 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x800015b2b091b5d1;
-valaddr_reg:x9; val_offset:1378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1378*FLEN/8, x10, x6, x7)
-
-inst_713:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x015b2b091b5d1 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x5119bfdc380d2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800015b2b091b5d1; op2val:0x15119bfdc380d2;
-valaddr_reg:x9; val_offset:1380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1380*FLEN/8, x10, x6, x7)
-
-inst_714:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1382*FLEN/8, x10, x6, x7)
-
-inst_715:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1384*FLEN/8, x10, x6, x7)
-
-inst_716:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x022ca6eace47f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x800022ca6eace47f;
-valaddr_reg:x9; val_offset:1386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1386*FLEN/8, x10, x6, x7)
-
-inst_717:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x022ca6eace47f and fs2 == 0 and fe2 == 0x001 and fm2 == 0x5119bfdc380d2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800022ca6eace47f; op2val:0x15119bfdc380d2;
-valaddr_reg:x9; val_offset:1388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1388*FLEN/8, x10, x6, x7)
-
-inst_718:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1390*FLEN/8, x10, x6, x7)
-
-inst_719:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1392*FLEN/8, x10, x6, x7)
-
-inst_720:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x069fbb598d312 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x800069fbb598d312;
-valaddr_reg:x9; val_offset:1394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1394*FLEN/8, x10, x6, x7)
-
-inst_721:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x069fbb598d312 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x21b5c662d267b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800069fbb598d312; op2val:0x21b5c662d267b;
-valaddr_reg:x9; val_offset:1396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1396*FLEN/8, x10, x6, x7)
-
-inst_722:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1398*FLEN/8, x10, x6, x7)
-
-inst_723:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x0;
-valaddr_reg:x9; val_offset:1400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1400*FLEN/8, x10, x6, x7)
-
-inst_724:// fs1 == 0 and fe1 == 0x400 and fm1 == 0x77096ee4d2f12 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x40077096ee4d2f12; op2val:0x0;
-valaddr_reg:x9; val_offset:1402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1402*FLEN/8, x10, x6, x7)
-
-inst_725:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x77096ee4d2f12 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x40077096ee4d2f12;
-valaddr_reg:x9; val_offset:1404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1404*FLEN/8, x10, x6, x7)
-
-inst_726:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x77096ee4d2f12 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x40077096ee4d2f12;
-valaddr_reg:x9; val_offset:1406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1406*FLEN/8, x10, x6, x7)
-
-inst_727:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1408*FLEN/8, x10, x6, x7)
-
-inst_728:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1410*FLEN/8, x10, x6, x7)
-
-inst_729:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xf8c50a18d0c04 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x7fbf8c50a18d0c04;
-valaddr_reg:x9; val_offset:1412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1412*FLEN/8, x10, x6, x7)
-
-inst_730:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1414*FLEN/8, x10, x6, x7)
-
-inst_731:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1416*FLEN/8, x10, x6, x7)
-
-inst_732:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1418*FLEN/8, x10, x6, x7)
-
-inst_733:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1420*FLEN/8, x10, x6, x7)
-
-inst_734:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1422*FLEN/8, x10, x6, x7)
-
-inst_735:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1424*FLEN/8, x10, x6, x7)
-
-inst_736:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1426*FLEN/8, x10, x6, x7)
-
-inst_737:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1428*FLEN/8, x10, x6, x7)
-
-inst_738:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1430*FLEN/8, x10, x6, x7)
-
-inst_739:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1432*FLEN/8, x10, x6, x7)
-
-inst_740:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1434*FLEN/8, x10, x6, x7)
-
-inst_741:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1436*FLEN/8, x10, x6, x7)
-
-inst_742:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1438*FLEN/8, x10, x6, x7)
-
-inst_743:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1440*FLEN/8, x10, x6, x7)
-
-inst_744:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1442*FLEN/8, x10, x6, x7)
-
-inst_745:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1444*FLEN/8, x10, x6, x7)
-
-inst_746:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1446*FLEN/8, x10, x6, x7)
-
-inst_747:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x197d0ed8b1e34 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x197d0ed8b1e34;
-valaddr_reg:x9; val_offset:1448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1448*FLEN/8, x10, x6, x7)
-
-inst_748:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1450*FLEN/8, x10, x6, x7)
-
-inst_749:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x028c817c11c9f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x28c817c11c9f; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1452*FLEN/8, x10, x6, x7)
-
-inst_750:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x028c817c11c9f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x28c817c11c9f;
-valaddr_reg:x9; val_offset:1454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1454*FLEN/8, x10, x6, x7)
-
-inst_751:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1456*FLEN/8, x10, x6, x7)
-
-inst_752:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1458*FLEN/8, x10, x6, x7)
-
-inst_753:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1460*FLEN/8, x10, x6, x7)
-
-inst_754:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1462*FLEN/8, x10, x6, x7)
-
-inst_755:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1464*FLEN/8, x10, x6, x7)
-
-inst_756:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xfafb7b5426c47 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x802fafb7b5426c47;
-valaddr_reg:x9; val_offset:1466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1466*FLEN/8, x10, x6, x7)
-
-inst_757:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x197d0ed8b1e34 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0x197d0ed8b1e34;
-valaddr_reg:x9; val_offset:1468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1468*FLEN/8, x10, x6, x7)
-
-inst_758:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1470*FLEN/8, x10, x6, x7)
-
-inst_759:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1472*FLEN/8, x10, x6, x7)
-
-inst_760:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xa0144329d87cc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x801a0144329d87cc;
-valaddr_reg:x9; val_offset:1474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1474*FLEN/8, x10, x6, x7)
-
-inst_761:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 0 and fe2 == 0x000 and fm2 == 0x197d0ed8b1e34 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0x197d0ed8b1e34;
-valaddr_reg:x9; val_offset:1476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1476*FLEN/8, x10, x6, x7)
-
-inst_762:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1478*FLEN/8, x10, x6, x7)
-
-inst_763:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1480*FLEN/8, x10, x6, x7)
-
-inst_764:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1482*FLEN/8, x10, x6, x7)
-
-inst_765:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1484*FLEN/8, x10, x6, x7)
-
-inst_766:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1486*FLEN/8, x10, x6, x7)
-
-inst_767:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1488*FLEN/8, x10, x6, x7)
-
-inst_768:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x4b32977d93970 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x8024b32977d93970;
-valaddr_reg:x9; val_offset:1490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1490*FLEN/8, x10, x6, x7)
-
-inst_769:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x197d0ed8b1e34 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0x197d0ed8b1e34;
-valaddr_reg:x9; val_offset:1492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1492*FLEN/8, x10, x6, x7)
-
-inst_770:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1494*FLEN/8, x10, x6, x7)
-
-inst_771:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x0;
-valaddr_reg:x9; val_offset:1496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1496*FLEN/8, x10, x6, x7)
-
-inst_772:// fs1 == 0 and fe1 == 0x400 and fm1 == 0x1b91ae09e503b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x4001b91ae09e503b; op2val:0x0;
-valaddr_reg:x9; val_offset:1498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1498*FLEN/8, x10, x6, x7)
-
-inst_773:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x1b91ae09e503b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x4001b91ae09e503b;
-valaddr_reg:x9; val_offset:1500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1500*FLEN/8, x10, x6, x7)
-
-inst_774:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x1b91ae09e503b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x4001b91ae09e503b;
-valaddr_reg:x9; val_offset:1502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1502*FLEN/8, x10, x6, x7)
-
-inst_775:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1504*FLEN/8, x10, x6, x7)
-
-inst_776:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1506*FLEN/8, x10, x6, x7)
-
-inst_777:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x43fe46d2b7ce6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x7fb43fe46d2b7ce6;
-valaddr_reg:x9; val_offset:1508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1508*FLEN/8, x10, x6, x7)
-
-inst_778:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1510*FLEN/8, x10, x6, x7)
-
-inst_779:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1512*FLEN/8, x10, x6, x7)
-
-inst_780:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1514*FLEN/8, x10, x6, x7)
-
-inst_781:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x94fdd88765c1f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x7fe94fdd88765c1f;
-valaddr_reg:x9; val_offset:1516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1516*FLEN/8, x10, x6, x7)
-
-inst_782:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1518*FLEN/8, x10, x6, x7)
-
-inst_783:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1520*FLEN/8, x10, x6, x7)
-
-inst_784:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1522*FLEN/8, x10, x6, x7)
-
-inst_785:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1524*FLEN/8, x10, x6, x7)
-
-inst_786:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1526*FLEN/8, x10, x6, x7)
-
-inst_787:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1528*FLEN/8, x10, x6, x7)
-
-inst_788:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1530*FLEN/8, x10, x6, x7)
-
-inst_789:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1532*FLEN/8, x10, x6, x7)
-
-inst_790:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1534*FLEN/8, x10, x6, x7)
-
-inst_791:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1536*FLEN/8, x10, x6, x7)
-
-inst_792:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1538*FLEN/8, x10, x6, x7)
-
-inst_793:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1540*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_6)
-
-inst_794:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1542*FLEN/8, x10, x6, x7)
-
-inst_795:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1544*FLEN/8, x10, x6, x7)
-
-inst_796:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1546*FLEN/8, x10, x6, x7)
-
-inst_797:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1548*FLEN/8, x10, x6, x7)
-
-inst_798:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1550*FLEN/8, x10, x6, x7)
-
-inst_799:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1552*FLEN/8, x10, x6, x7)
-
-inst_800:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x105c326c5af30 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x105c326c5af30;
-valaddr_reg:x9; val_offset:1554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1554*FLEN/8, x10, x6, x7)
-
-inst_801:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1556*FLEN/8, x10, x6, x7)
-
-inst_802:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01a2d1d7a2b1e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1a2d1d7a2b1e; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1558*FLEN/8, x10, x6, x7)
-
-inst_803:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01a2d1d7a2b1e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x1a2d1d7a2b1e;
-valaddr_reg:x9; val_offset:1560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1560*FLEN/8, x10, x6, x7)
-
-inst_804:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1562*FLEN/8, x10, x6, x7)
-
-inst_805:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1564*FLEN/8, x10, x6, x7)
-
-inst_806:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1566*FLEN/8, x10, x6, x7)
-
-inst_807:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xfafb7b5426c47 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x802fafb7b5426c47;
-valaddr_reg:x9; val_offset:1568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1568*FLEN/8, x10, x6, x7)
-
-inst_808:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x105c326c5af30 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0x105c326c5af30;
-valaddr_reg:x9; val_offset:1570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1570*FLEN/8, x10, x6, x7)
-
-inst_809:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1572*FLEN/8, x10, x6, x7)
-
-inst_810:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1574*FLEN/8, x10, x6, x7)
-
-inst_811:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xa0144329d87cc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x801a0144329d87cc;
-valaddr_reg:x9; val_offset:1576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1576*FLEN/8, x10, x6, x7)
-
-inst_812:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 0 and fe2 == 0x000 and fm2 == 0x105c326c5af30 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0x105c326c5af30;
-valaddr_reg:x9; val_offset:1578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1578*FLEN/8, x10, x6, x7)
-
-inst_813:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1580*FLEN/8, x10, x6, x7)
-
-inst_814:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1582*FLEN/8, x10, x6, x7)
-
-inst_815:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1584*FLEN/8, x10, x6, x7)
-
-inst_816:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1586*FLEN/8, x10, x6, x7)
-
-inst_817:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1588*FLEN/8, x10, x6, x7)
-
-inst_818:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1590*FLEN/8, x10, x6, x7)
-
-inst_819:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x4b32977d93970 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x8024b32977d93970;
-valaddr_reg:x9; val_offset:1592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1592*FLEN/8, x10, x6, x7)
-
-inst_820:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x105c326c5af30 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0x105c326c5af30;
-valaddr_reg:x9; val_offset:1594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1594*FLEN/8, x10, x6, x7)
-
-inst_821:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1596*FLEN/8, x10, x6, x7)
-
-inst_822:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x0;
-valaddr_reg:x9; val_offset:1598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1598*FLEN/8, x10, x6, x7)
-
-inst_823:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x6c0679d004e5b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff6c0679d004e5b; op2val:0x0;
-valaddr_reg:x9; val_offset:1600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1600*FLEN/8, x10, x6, x7)
-
-inst_824:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x6c0679d004e5b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff6c0679d004e5b;
-valaddr_reg:x9; val_offset:1602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1602*FLEN/8, x10, x6, x7)
-
-inst_825:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x6c0679d004e5b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x3ff6c0679d004e5b;
-valaddr_reg:x9; val_offset:1604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1604*FLEN/8, x10, x6, x7)
-
-inst_826:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1606*FLEN/8, x10, x6, x7)
-
-inst_827:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1608*FLEN/8, x10, x6, x7)
-
-inst_828:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x093dbe3aa0387 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x7fb093dbe3aa0387;
-valaddr_reg:x9; val_offset:1610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1610*FLEN/8, x10, x6, x7)
-
-inst_829:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1612*FLEN/8, x10, x6, x7)
-
-inst_830:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1614*FLEN/8, x10, x6, x7)
-
-inst_831:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1616*FLEN/8, x10, x6, x7)
-
-inst_832:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x4b8d2dc948469 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x7fe4b8d2dc948469;
-valaddr_reg:x9; val_offset:1618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1618*FLEN/8, x10, x6, x7)
-
-inst_833:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1620*FLEN/8, x10, x6, x7)
-
-inst_834:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1622*FLEN/8, x10, x6, x7)
-
-inst_835:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1624*FLEN/8, x10, x6, x7)
-
-inst_836:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1626*FLEN/8, x10, x6, x7)
-
-inst_837:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1628*FLEN/8, x10, x6, x7)
-
-inst_838:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1630*FLEN/8, x10, x6, x7)
-
-inst_839:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1632*FLEN/8, x10, x6, x7)
-
-inst_840:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1634*FLEN/8, x10, x6, x7)
-
-inst_841:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1636*FLEN/8, x10, x6, x7)
-
-inst_842:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1638*FLEN/8, x10, x6, x7)
-
-inst_843:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1640*FLEN/8, x10, x6, x7)
-
-inst_844:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1642*FLEN/8, x10, x6, x7)
-
-inst_845:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1644*FLEN/8, x10, x6, x7)
-
-inst_846:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1646*FLEN/8, x10, x6, x7)
-
-inst_847:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1648*FLEN/8, x10, x6, x7)
-
-inst_848:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1650*FLEN/8, x10, x6, x7)
-
-inst_849:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1652*FLEN/8, x10, x6, x7)
-
-inst_850:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1654*FLEN/8, x10, x6, x7)
-
-inst_851:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d64b86ad9094 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xd64b86ad9094;
-valaddr_reg:x9; val_offset:1656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1656*FLEN/8, x10, x6, x7)
-
-inst_852:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1658*FLEN/8, x10, x6, x7)
-
-inst_853:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0156df3de280f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x156df3de280f; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1660*FLEN/8, x10, x6, x7)
-
-inst_854:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0156df3de280f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x156df3de280f;
-valaddr_reg:x9; val_offset:1662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1662*FLEN/8, x10, x6, x7)
-
-inst_855:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1664*FLEN/8, x10, x6, x7)
-
-inst_856:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xfafb7b5426c47 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x802fafb7b5426c47;
-valaddr_reg:x9; val_offset:1666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1666*FLEN/8, x10, x6, x7)
-
-inst_857:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d64b86ad9094 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0xd64b86ad9094;
-valaddr_reg:x9; val_offset:1668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1668*FLEN/8, x10, x6, x7)
-
-inst_858:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1670*FLEN/8, x10, x6, x7)
-
-inst_859:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1672*FLEN/8, x10, x6, x7)
-
-inst_860:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xa0144329d87cc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x801a0144329d87cc;
-valaddr_reg:x9; val_offset:1674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1674*FLEN/8, x10, x6, x7)
-
-inst_861:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d64b86ad9094 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0xd64b86ad9094;
-valaddr_reg:x9; val_offset:1676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1676*FLEN/8, x10, x6, x7)
-
-inst_862:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1678*FLEN/8, x10, x6, x7)
-
-inst_863:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1680*FLEN/8, x10, x6, x7)
-
-inst_864:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1682*FLEN/8, x10, x6, x7)
-
-inst_865:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1684*FLEN/8, x10, x6, x7)
-
-inst_866:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1686*FLEN/8, x10, x6, x7)
-
-inst_867:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1688*FLEN/8, x10, x6, x7)
-
-inst_868:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x4b32977d93970 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x8024b32977d93970;
-valaddr_reg:x9; val_offset:1690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1690*FLEN/8, x10, x6, x7)
-
-inst_869:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d64b86ad9094 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0xd64b86ad9094;
-valaddr_reg:x9; val_offset:1692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1692*FLEN/8, x10, x6, x7)
-
-inst_870:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1694*FLEN/8, x10, x6, x7)
-
-inst_871:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x0;
-valaddr_reg:x9; val_offset:1696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1696*FLEN/8, x10, x6, x7)
-
-inst_872:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x2a038f94d730b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff2a038f94d730b; op2val:0x0;
-valaddr_reg:x9; val_offset:1698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1698*FLEN/8, x10, x6, x7)
-
-inst_873:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x2a038f94d730b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff2a038f94d730b;
-valaddr_reg:x9; val_offset:1700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1700*FLEN/8, x10, x6, x7)
-
-inst_874:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x2a038f94d730b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x3ff2a038f94d730b;
-valaddr_reg:x9; val_offset:1702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1702*FLEN/8, x10, x6, x7)
-
-inst_875:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1704*FLEN/8, x10, x6, x7)
-
-inst_876:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1706*FLEN/8, x10, x6, x7)
-
-inst_877:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xf6025caa2d205 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xffdf6025caa2d205;
-valaddr_reg:x9; val_offset:1708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1708*FLEN/8, x10, x6, x7)
-
-inst_878:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1710*FLEN/8, x10, x6, x7)
-
-inst_879:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1712*FLEN/8, x10, x6, x7)
-
-inst_880:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1714*FLEN/8, x10, x6, x7)
-
-inst_881:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1716*FLEN/8, x10, x6, x7)
-
-inst_882:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1718*FLEN/8, x10, x6, x7)
-
-inst_883:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1720*FLEN/8, x10, x6, x7)
-
-inst_884:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1722*FLEN/8, x10, x6, x7)
-
-inst_885:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1724*FLEN/8, x10, x6, x7)
-
-inst_886:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1726*FLEN/8, x10, x6, x7)
-
-inst_887:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1728*FLEN/8, x10, x6, x7)
-
-inst_888:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1730*FLEN/8, x10, x6, x7)
-
-inst_889:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1732*FLEN/8, x10, x6, x7)
-
-inst_890:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1734*FLEN/8, x10, x6, x7)
-
-inst_891:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1736*FLEN/8, x10, x6, x7)
-
-inst_892:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1738*FLEN/8, x10, x6, x7)
-
-inst_893:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1740*FLEN/8, x10, x6, x7)
-
-inst_894:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0a23bfe815416 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000a23bfe815416; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1742*FLEN/8, x10, x6, x7)
-
-inst_895:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0a23bfe815416 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x8000a23bfe815416;
-valaddr_reg:x9; val_offset:1744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1744*FLEN/8, x10, x6, x7)
-
-inst_896:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1746*FLEN/8, x10, x6, x7)
-
-inst_897:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1748*FLEN/8, x10, x6, x7)
-
-inst_898:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x002 and fm2 == 0xfafb7b5426c47 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x802fafb7b5426c47;
-valaddr_reg:x9; val_offset:1750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1750*FLEN/8, x10, x6, x7)
-
-inst_899:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1752*FLEN/8, x10, x6, x7)
-
-inst_900:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1754*FLEN/8, x10, x6, x7)
-
-inst_901:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1756*FLEN/8, x10, x6, x7)
-
-inst_902:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1758*FLEN/8, x10, x6, x7)
-
-inst_903:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1760*FLEN/8, x10, x6, x7)
-
-inst_904:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1762*FLEN/8, x10, x6, x7)
-
-inst_905:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1764*FLEN/8, x10, x6, x7)
-
-inst_906:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d8fae5b11a26 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0x8000d8fae5b11a26;
-valaddr_reg:x9; val_offset:1766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1766*FLEN/8, x10, x6, x7)
-
-inst_907:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xfafb7b5426c47 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x802fafb7b5426c47;
-valaddr_reg:x9; val_offset:1768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1768*FLEN/8, x10, x6, x7)
-
-inst_908:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1770*FLEN/8, x10, x6, x7)
-
-inst_909:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1772*FLEN/8, x10, x6, x7)
-
-inst_910:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x15be852c0ecf4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0x80015be852c0ecf4;
-valaddr_reg:x9; val_offset:1774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1774*FLEN/8, x10, x6, x7)
-
-inst_911:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xfafb7b5426c47 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x802fafb7b5426c47;
-valaddr_reg:x9; val_offset:1776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1776*FLEN/8, x10, x6, x7)
-
-inst_912:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1778*FLEN/8, x10, x6, x7)
-
-inst_913:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1780*FLEN/8, x10, x6, x7)
-
-inst_914:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1782*FLEN/8, x10, x6, x7)
-
-inst_915:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x0;
-valaddr_reg:x9; val_offset:1784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1784*FLEN/8, x10, x6, x7)
-
-inst_916:// fs1 == 1 and fe1 == 0x402 and fm1 == 0x1a04aee65a608 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc021a04aee65a608; op2val:0x0;
-valaddr_reg:x9; val_offset:1786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1786*FLEN/8, x10, x6, x7)
-
-inst_917:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x1a04aee65a608 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc021a04aee65a608;
-valaddr_reg:x9; val_offset:1788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1788*FLEN/8, x10, x6, x7)
-
-inst_918:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x402 and fm2 == 0x1a04aee65a608 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xc021a04aee65a608;
-valaddr_reg:x9; val_offset:1790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1790*FLEN/8, x10, x6, x7)
-
-inst_919:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1792*FLEN/8, x10, x6, x7)
-
-inst_920:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1794*FLEN/8, x10, x6, x7)
-
-inst_921:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x9bff6a8783cf3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xffc9bff6a8783cf3;
-valaddr_reg:x9; val_offset:1796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1796*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_7)
-
-inst_922:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1798*FLEN/8, x10, x6, x7)
-
-inst_923:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1800*FLEN/8, x10, x6, x7)
-
-inst_924:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1802*FLEN/8, x10, x6, x7)
-
-inst_925:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1804*FLEN/8, x10, x6, x7)
-
-inst_926:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1806*FLEN/8, x10, x6, x7)
-
-inst_927:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1808*FLEN/8, x10, x6, x7)
-
-inst_928:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1810*FLEN/8, x10, x6, x7)
-
-inst_929:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1812*FLEN/8, x10, x6, x7)
-
-inst_930:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1814*FLEN/8, x10, x6, x7)
-
-inst_931:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1816*FLEN/8, x10, x6, x7)
-
-inst_932:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1818*FLEN/8, x10, x6, x7)
-
-inst_933:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1820*FLEN/8, x10, x6, x7)
-
-inst_934:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1822*FLEN/8, x10, x6, x7)
-
-inst_935:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1824*FLEN/8, x10, x6, x7)
-
-inst_936:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1826*FLEN/8, x10, x6, x7)
-
-inst_937:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1828*FLEN/8, x10, x6, x7)
-
-inst_938:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x042929a1b2ce1 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800042929a1b2ce1; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1830*FLEN/8, x10, x6, x7)
-
-inst_939:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x042929a1b2ce1 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x800042929a1b2ce1;
-valaddr_reg:x9; val_offset:1832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1832*FLEN/8, x10, x6, x7)
-
-inst_940:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1834*FLEN/8, x10, x6, x7)
-
-inst_941:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1836*FLEN/8, x10, x6, x7)
-
-inst_942:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xa0144329d87cc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x801a0144329d87cc;
-valaddr_reg:x9; val_offset:1838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1838*FLEN/8, x10, x6, x7)
-
-inst_943:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1840*FLEN/8, x10, x6, x7)
-
-inst_944:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1842*FLEN/8, x10, x6, x7)
-
-inst_945:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1844*FLEN/8, x10, x6, x7)
-
-inst_946:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1846*FLEN/8, x10, x6, x7)
-
-inst_947:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1848*FLEN/8, x10, x6, x7)
-
-inst_948:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d8fae5b11a26 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0x8000d8fae5b11a26;
-valaddr_reg:x9; val_offset:1850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1850*FLEN/8, x10, x6, x7)
-
-inst_949:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xa0144329d87cc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x801a0144329d87cc;
-valaddr_reg:x9; val_offset:1852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1852*FLEN/8, x10, x6, x7)
-
-inst_950:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1854*FLEN/8, x10, x6, x7)
-
-inst_951:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1856*FLEN/8, x10, x6, x7)
-
-inst_952:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x15be852c0ecf4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0x80015be852c0ecf4;
-valaddr_reg:x9; val_offset:1858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1858*FLEN/8, x10, x6, x7)
-
-inst_953:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xa0144329d87cc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x801a0144329d87cc;
-valaddr_reg:x9; val_offset:1860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1860*FLEN/8, x10, x6, x7)
-
-inst_954:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1862*FLEN/8, x10, x6, x7)
-
-inst_955:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1864*FLEN/8, x10, x6, x7)
-
-inst_956:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1866*FLEN/8, x10, x6, x7)
-
-inst_957:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x0;
-valaddr_reg:x9; val_offset:1868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1868*FLEN/8, x10, x6, x7)
-
-inst_958:// fs1 == 1 and fe1 == 0x400 and fm1 == 0xcee7468323917 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc00cee7468323917; op2val:0x0;
-valaddr_reg:x9; val_offset:1870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1870*FLEN/8, x10, x6, x7)
-
-inst_959:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x400 and fm2 == 0xcee7468323917 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc00cee7468323917;
-valaddr_reg:x9; val_offset:1872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1872*FLEN/8, x10, x6, x7)
-
-inst_960:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x400 and fm2 == 0xcee7468323917 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xc00cee7468323917;
-valaddr_reg:x9; val_offset:1874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1874*FLEN/8, x10, x6, x7)
-
-inst_961:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1876*FLEN/8, x10, x6, x7)
-
-inst_962:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1878*FLEN/8, x10, x6, x7)
-
-inst_963:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x0c90875ccb5d8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xffb0c90875ccb5d8;
-valaddr_reg:x9; val_offset:1880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1880*FLEN/8, x10, x6, x7)
-
-inst_964:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1882*FLEN/8, x10, x6, x7)
-
-inst_965:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1884*FLEN/8, x10, x6, x7)
-
-inst_966:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1886*FLEN/8, x10, x6, x7)
-
-inst_967:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x4fb4a933fe34f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xffe4fb4a933fe34f;
-valaddr_reg:x9; val_offset:1888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1888*FLEN/8, x10, x6, x7)
-
-inst_968:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1890*FLEN/8, x10, x6, x7)
-
-inst_969:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1892*FLEN/8, x10, x6, x7)
-
-inst_970:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1894*FLEN/8, x10, x6, x7)
-
-inst_971:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1896*FLEN/8, x10, x6, x7)
-
-inst_972:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1898*FLEN/8, x10, x6, x7)
-
-inst_973:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1900*FLEN/8, x10, x6, x7)
-
-inst_974:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1902*FLEN/8, x10, x6, x7)
-
-inst_975:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1904*FLEN/8, x10, x6, x7)
-
-inst_976:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1906*FLEN/8, x10, x6, x7)
-
-inst_977:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1908*FLEN/8, x10, x6, x7)
-
-inst_978:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1910*FLEN/8, x10, x6, x7)
-
-inst_979:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1912*FLEN/8, x10, x6, x7)
-
-inst_980:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1914*FLEN/8, x10, x6, x7)
-
-inst_981:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1916*FLEN/8, x10, x6, x7)
-
-inst_982:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1918*FLEN/8, x10, x6, x7)
-
-inst_983:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1920*FLEN/8, x10, x6, x7)
-
-inst_984:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1922*FLEN/8, x10, x6, x7)
-
-inst_985:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1924*FLEN/8, x10, x6, x7)
-
-inst_986:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d8fae5b11a26 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x8000d8fae5b11a26;
-valaddr_reg:x9; val_offset:1926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1926*FLEN/8, x10, x6, x7)
-
-inst_987:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1928*FLEN/8, x10, x6, x7)
-
-inst_988:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x015b2b091b5d1 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800015b2b091b5d1; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1930*FLEN/8, x10, x6, x7)
-
-inst_989:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x015b2b091b5d1 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x800015b2b091b5d1;
-valaddr_reg:x9; val_offset:1932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1932*FLEN/8, x10, x6, x7)
-
-inst_990:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1934*FLEN/8, x10, x6, x7)
-
-inst_991:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1936*FLEN/8, x10, x6, x7)
-
-inst_992:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1938*FLEN/8, x10, x6, x7)
-
-inst_993:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1940*FLEN/8, x10, x6, x7)
-
-inst_994:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1942*FLEN/8, x10, x6, x7)
-
-inst_995:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1944*FLEN/8, x10, x6, x7)
-
-inst_996:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1946*FLEN/8, x10, x6, x7)
-
-inst_997:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x4b32977d93970 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x8024b32977d93970;
-valaddr_reg:x9; val_offset:1948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1948*FLEN/8, x10, x6, x7)
-
-inst_998:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d8fae5b11a26 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0x8000d8fae5b11a26;
-valaddr_reg:x9; val_offset:1950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1950*FLEN/8, x10, x6, x7)
-
-inst_999:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1952*FLEN/8, x10, x6, x7)
-
-inst_1000:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x0;
-valaddr_reg:x9; val_offset:1954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1954*FLEN/8, x10, x6, x7)
-
-inst_1001:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x2dbf77d539bae and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbff2dbf77d539bae; op2val:0x0;
-valaddr_reg:x9; val_offset:1956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1956*FLEN/8, x10, x6, x7)
-
-inst_1002:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x2dbf77d539bae and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbff2dbf77d539bae;
-valaddr_reg:x9; val_offset:1958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1958*FLEN/8, x10, x6, x7)
-
-inst_1003:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x2dbf77d539bae and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xbff2dbf77d539bae;
-valaddr_reg:x9; val_offset:1960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1960*FLEN/8, x10, x6, x7)
-
-inst_1004:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1962*FLEN/8, x10, x6, x7)
-
-inst_1005:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1964*FLEN/8, x10, x6, x7)
-
-inst_1006:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xae9e55abc765f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xffbae9e55abc765f;
-valaddr_reg:x9; val_offset:1966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1966*FLEN/8, x10, x6, x7)
-
-inst_1007:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1968*FLEN/8, x10, x6, x7)
-
-inst_1008:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1970*FLEN/8, x10, x6, x7)
-
-inst_1009:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1972*FLEN/8, x10, x6, x7)
-
-inst_1010:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1974*FLEN/8, x10, x6, x7)
-
-inst_1011:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1976*FLEN/8, x10, x6, x7)
-
-inst_1012:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1978*FLEN/8, x10, x6, x7)
-
-inst_1013:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1980*FLEN/8, x10, x6, x7)
-
-inst_1014:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1982*FLEN/8, x10, x6, x7)
-
-inst_1015:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1984*FLEN/8, x10, x6, x7)
-
-inst_1016:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1986*FLEN/8, x10, x6, x7)
-
-inst_1017:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1988*FLEN/8, x10, x6, x7)
-
-inst_1018:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1990*FLEN/8, x10, x6, x7)
-
-inst_1019:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1992*FLEN/8, x10, x6, x7)
-
-inst_1020:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1994*FLEN/8, x10, x6, x7)
-
-inst_1021:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1996*FLEN/8, x10, x6, x7)
-
-inst_1022:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1998*FLEN/8, x10, x6, x7)
-
-inst_1023:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:2000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2000*FLEN/8, x10, x6, x7)
-
-inst_1024:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x15be852c0ecf4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x80015be852c0ecf4;
-valaddr_reg:x9; val_offset:2002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2002*FLEN/8, x10, x6, x7)
-
-inst_1025:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:2004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2004*FLEN/8, x10, x6, x7)
-
-inst_1026:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x022ca6eace47f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800022ca6eace47f; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:2006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2006*FLEN/8, x10, x6, x7)
-
-inst_1027:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x022ca6eace47f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x800022ca6eace47f;
-valaddr_reg:x9; val_offset:2008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2008*FLEN/8, x10, x6, x7)
-
-inst_1028:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:2010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2010*FLEN/8, x10, x6, x7)
-
-inst_1029:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:2012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2012*FLEN/8, x10, x6, x7)
-
-inst_1030:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:2014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2014*FLEN/8, x10, x6, x7)
-
-inst_1031:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:2016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2016*FLEN/8, x10, x6, x7)
-
-inst_1032:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:2018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2018*FLEN/8, x10, x6, x7)
-
-inst_1033:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x4b32977d93970 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x8024b32977d93970;
-valaddr_reg:x9; val_offset:2020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2020*FLEN/8, x10, x6, x7)
-
-inst_1034:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x15be852c0ecf4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0x80015be852c0ecf4;
-valaddr_reg:x9; val_offset:2022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2022*FLEN/8, x10, x6, x7)
-
-inst_1035:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:2024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2024*FLEN/8, x10, x6, x7)
-
-inst_1036:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x0;
-valaddr_reg:x9; val_offset:2026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2026*FLEN/8, x10, x6, x7)
-
-inst_1037:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xe3d32f95a320d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbffe3d32f95a320d; op2val:0x0;
-valaddr_reg:x9; val_offset:2028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2028*FLEN/8, x10, x6, x7)
-
-inst_1038:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xe3d32f95a320d and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbffe3d32f95a320d;
-valaddr_reg:x9; val_offset:2030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2030*FLEN/8, x10, x6, x7)
-
-inst_1039:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xe3d32f95a320d and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xbffe3d32f95a320d;
-valaddr_reg:x9; val_offset:2032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2032*FLEN/8, x10, x6, x7)
-
-inst_1040:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:2034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2034*FLEN/8, x10, x6, x7)
-
-inst_1041:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:2036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2036*FLEN/8, x10, x6, x7)
-
-inst_1042:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x47f2e5cadc271 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xffd47f2e5cadc271;
-valaddr_reg:x9; val_offset:2038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2038*FLEN/8, x10, x6, x7)
-
-inst_1043:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:2040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2040*FLEN/8, x10, x6, x7)
-
-inst_1044:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:2042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2042*FLEN/8, x10, x6, x7)
-
-inst_1045:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:2044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2044*FLEN/8, x10, x6, x7)
-
-inst_1046:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:2046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2046*FLEN/8, x10, x6, x7)
-
-inst_1047:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:2048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2048*FLEN/8, x10, x6, x7)
-
-inst_1048:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:2050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2050*FLEN/8, x10, x6, x7)
-
-inst_1049:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:2052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2052*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_8)
-
-inst_1050:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:2054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2054*FLEN/8, x10, x6, x7)
-
-inst_1051:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:2056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2056*FLEN/8, x10, x6, x7)
-
-inst_1052:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:2058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2058*FLEN/8, x10, x6, x7)
-
-inst_1053:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:2060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2060*FLEN/8, x10, x6, x7)
-
-inst_1054:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:2062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2062*FLEN/8, x10, x6, x7)
-
-inst_1055:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:2064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2064*FLEN/8, x10, x6, x7)
-
-inst_1056:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:2066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2066*FLEN/8, x10, x6, x7)
-
-inst_1057:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:2068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2068*FLEN/8, x10, x6, x7)
-
-inst_1058:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:2070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2070*FLEN/8, x10, x6, x7)
-
-inst_1059:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x069fbb598d312 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800069fbb598d312; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:2072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2072*FLEN/8, x10, x6, x7)
-
-inst_1060:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x069fbb598d312 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x800069fbb598d312;
-valaddr_reg:x9; val_offset:2074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2074*FLEN/8, x10, x6, x7)
-
-inst_1061:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:2076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2076*FLEN/8, x10, x6, x7)
-
-inst_1062:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:2078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2078*FLEN/8, x10, x6, x7)
-
-inst_1063:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x4b32977d93970 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x8024b32977d93970;
-valaddr_reg:x9; val_offset:2080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2080*FLEN/8, x10, x6, x7)
-
-inst_1064:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:2082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2082*FLEN/8, x10, x6, x7)
-
-inst_1065:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:2084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2084*FLEN/8, x10, x6, x7)
-
-inst_1066:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:2086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2086*FLEN/8, x10, x6, x7)
-
-inst_1067:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:2088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2088*FLEN/8, x10, x6, x7)
-
-inst_1068:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:2090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2090*FLEN/8, x10, x6, x7)
-
-inst_1069:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:2092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2092*FLEN/8, x10, x6, x7)
-
-inst_1070:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:2094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2094*FLEN/8, x10, x6, x7)
-
-inst_1071:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:2096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2096*FLEN/8, x10, x6, x7)
-
-inst_1072:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x0;
-valaddr_reg:x9; val_offset:2098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2098*FLEN/8, x10, x6, x7)
-
-inst_1073:// fs1 == 1 and fe1 == 0x401 and fm1 == 0x707836e56fe8b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc01707836e56fe8b; op2val:0x0;
-valaddr_reg:x9; val_offset:2100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2100*FLEN/8, x10, x6, x7)
-
-inst_1074:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x707836e56fe8b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc01707836e56fe8b;
-valaddr_reg:x9; val_offset:2102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2102*FLEN/8, x10, x6, x7)
-
-inst_1075:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x707836e56fe8b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xc01707836e56fe8b;
-valaddr_reg:x9; val_offset:2104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2104*FLEN/8, x10, x6, x7)
-
-inst_1076:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:2106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2106*FLEN/8, x10, x6, x7)
-
-inst_1077:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x9; val_offset:2108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2108*FLEN/8, x10, x6, x7)
-
-inst_1078:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:2110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2110*FLEN/8, x10, x6, x7)
-
-inst_1079:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:2112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2112*FLEN/8, x10, x6, x7)
-
-inst_1080:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:2114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2114*FLEN/8, x10, x6, x7)
-
-inst_1081:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:2116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2116*FLEN/8, x10, x6, x7)
-
-inst_1082:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:2118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2118*FLEN/8, x10, x6, x7)
-
-inst_1083:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:2120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2120*FLEN/8, x10, x6, x7)
-
-inst_1084:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:2122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2122*FLEN/8, x10, x6, x7)
-
-inst_1085:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:2124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2124*FLEN/8, x10, x6, x7)
-
-inst_1086:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:2126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2126*FLEN/8, x10, x6, x7)
-
-inst_1087:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:2128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2128*FLEN/8, x10, x6, x7)
-
-inst_1088:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:2130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2130*FLEN/8, x10, x6, x7)
-
-inst_1089:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:2132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2132*FLEN/8, x10, x6, x7)
-
-inst_1090:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:2134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2134*FLEN/8, x10, x6, x7)
-
-inst_1091:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:2136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2136*FLEN/8, x10, x6, x7)
-
-inst_1092:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:2138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2138*FLEN/8, x10, x6, x7)
-
-inst_1093:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:2140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2140*FLEN/8, x10, x6, x7)
-
-inst_1094:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:2142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2142*FLEN/8, x10, x6, x7)
-
-inst_1095:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:2144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2144*FLEN/8, x10, x6, x7)
-
-inst_1096:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:2146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2146*FLEN/8, x10, x6, x7)
-
-inst_1097:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:2148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2148*FLEN/8, x10, x6, x7)
-
-inst_1098:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3137cb6875068; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:2150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2150*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
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-NAN_BOXED(18440129808424478575,64,FLEN)
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-NAN_BOXED(18437949865815790990,64,FLEN)
-NAN_BOXED(18427297996618888799,64,FLEN)
-NAN_BOXED(18437949865815790990,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(18428980244417333032,64,FLEN)
-NAN_BOXED(18427297996618888799,64,FLEN)
-NAN_BOXED(18428980244417333032,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(1666129950209720,64,FLEN)
-NAN_BOXED(9223754565210402036,64,FLEN)
-NAN_BOXED(1666129950209720,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9223754565210402036,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(59303361859750,64,FLEN)
-NAN_BOXED(9223410289690338431,64,FLEN)
-NAN_BOXED(59303361859750,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9223410289690338431,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9225155822421362907,64,FLEN)
-NAN_BOXED(9223754565210402036,64,FLEN)
-NAN_BOXED(9225155822421362907,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9224104011036082376,64,FLEN)
-NAN_BOXED(9223754565210402036,64,FLEN)
-NAN_BOXED(9224104011036082376,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9223754565210402036,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(9223754565210402036,64,FLEN)
-NAN_BOXED(9223754565210402036,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13834562394469839373,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13834562394469839373,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(13834562394469839373,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9209427617965110535,64,FLEN)
-NAN_BOXED(18434499011834397297,64,FLEN)
-NAN_BOXED(9209427617965110535,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(18434499011834397297,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9215497225429502690,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9210029744914432453,64,FLEN)
-NAN_BOXED(18434499011834397297,64,FLEN)
-NAN_BOXED(9210029744914432453,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9217395412933202562,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9215579554420835044,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(18436940111564563686,64,FLEN)
-NAN_BOXED(18434499011834397297,64,FLEN)
-NAN_BOXED(18436940111564563686,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(18441650242590072247,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(18440129808424478575,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(18437949865815790990,64,FLEN)
-NAN_BOXED(18434499011834397297,64,FLEN)
-NAN_BOXED(18437949865815790990,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(18428980244417333032,64,FLEN)
-NAN_BOXED(18434499011834397297,64,FLEN)
-NAN_BOXED(18428980244417333032,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(59303361859750,64,FLEN)
-NAN_BOXED(9223488566659175186,64,FLEN)
-NAN_BOXED(59303361859750,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9223488566659175186,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(4483985710198278,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(4483985710198278,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(2878107039619043,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(2878107039619043,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(2356198704129481,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(2356198704129481,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9225757757924902265,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(9225757757924902265,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13841540240819814027,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13841540240819814027,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(13841540240819814027,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9209427617965110535,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9215497225429502690,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9210029744914432453,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9217395412933202562,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9215579554420835044,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18436940111564563686,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18441650242590072247,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18440129808424478575,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18437949865815790990,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18428980244417333032,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(1666129950209720,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(59303361859750,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(4483985710198278,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2878107039619043,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2356198704129481,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9225155822421362907,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9224104011036082376,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9225757757924902265,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9209427617965110535,64,FLEN)
-NAN_BOXED(9215497225429502690,64,FLEN)
-NAN_BOXED(865851289325672,64,FLEN)
-NAN_BOXED(1666129950209720,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_7:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_8:
-    .fill 98*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fleq_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fleq_b1-01.S
deleted file mode 100644
index 9f8a65aa9..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fleq_b1-01.S
+++ /dev/null
@@ -1,368 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:12:39 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fleq.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fleq.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fleq_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f29; op2:f29; dest:x30; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f30; op2:f31; dest:x29; op1val:0x0; op2val:0x1;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f28; op2:f27; dest:x28; op1val:0x0; op2val:0x80000001;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f27; op2:f28; dest:x27; op1val:0x0; op2val:0x2;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f26; op2:f25; dest:x26; op1val:0x0; op2val:0x807ffffe;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f25; op2:f26; dest:x25; op1val:0x0; op2val:0x7fffff;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f24; op2:f23; dest:x24; op1val:0x0; op2val:0x807fffff;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f23; op2:f24; dest:x23; op1val:0x0; op2val:0x800000;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f22; op2:f21; dest:x22; op1val:0x0; op2val:0x80800000;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f21; op2:f22; dest:x21; op1val:0x0; op2val:0x800001;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f20; op2:f19; dest:x20; op1val:0x0; op2val:0x80855555;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f19; op2:f20; dest:x19; op1val:0x0; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f18; op2:f17; dest:x18; op1val:0x0; op2val:0xff7fffff;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f17; op2:f18; dest:x17; op1val:0x0; op2val:0x7f800000;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f16; op2:f15; dest:x16; op1val:0x0; op2val:0xff800000;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f15; op2:f16; dest:x15; op1val:0x0; op2val:0x7fc00000;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f14; op2:f13; dest:x14; op1val:0x0; op2val:0xffc00000;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f13; op2:f14; dest:x13; op1val:0x0; op2val:0x7fc00001;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f12; op2:f11; dest:x12; op1val:0x0; op2val:0xffc55555;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f11; op2:f12; dest:x11; op1val:0x0; op2val:0x7f800001;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f10; op2:f9; dest:x10; op1val:0x0; op2val:0xffaaaaaa;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f9; op2:f10; dest:x9; op1val:0x0; op2val:0x3f800000;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f8; op2:f7; dest:x8; op1val:0x0; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f7; op2:f8; dest:x7; op1val:0x80000000; op2val:0x0;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f6; op2:f5; dest:x6; op1val:0x80000000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f5; op2:f6; dest:x5; op1val:0x80000000; op2val:0x1;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f4; op2:f3; dest:x4; op1val:0x80000000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f3; op2:f4; dest:x3; op1val:0x80000000; op2val:0x2;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f2; op2:f1; dest:x2; op1val:0x80000000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f1; op2:f2; dest:x1; op1val:0x80000000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f0; op2:f31; dest:x31; op1val:0x80000000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f31; op2:f0; dest:x31; op1val:0x80000000; op2val:0x800000;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x0; op1val:0x80000000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-test_dataset_1:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 16*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fleq_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fleq_b19-01.S
deleted file mode 100644
index b28cdf85b..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fleq_b19-01.S
+++ /dev/null
@@ -1,368 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:12:39 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fleq.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fleq.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fleq_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x7e36c1bf;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f29; op2:f29; dest:x30; op1val:0x7e36c1bf; op2val:0x7e36c1bf;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x4038a5 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f30; op2:f31; dest:x29; op1val:0x7f7fffff; op2val:0x7d4038a5;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0xfa and fm1 == 0x4038a5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f28; op2:f27; dest:x28; op1val:0x7d4038a5; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f27; op2:f28; dest:x27; op1val:0x7f7fffff; op2val:0x7ef046ce;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f26; op2:f25; dest:x26; op1val:0x7e36c1bf; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f25; op2:f26; dest:x25; op1val:0x7e36c1bf; op2val:0x7e472f12;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f24; op2:f23; dest:x24; op1val:0x7e472f12; op2val:0x7e36c1bf;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f23; op2:f24; dest:x23; op1val:0x7e36c1bf; op2val:0x7f2099c0;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x007b00 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f22; op2:f21; dest:x22; op1val:0x7f7fffff; op2val:0x7d807b00;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0xfb and fm1 == 0x007b00 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f21; op2:f22; dest:x21; op1val:0x7d807b00; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f20; op2:f19; dest:x20; op1val:0x7f7fffff; op2val:0x7f2099c0;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f19; op2:f20; dest:x19; op1val:0x7e36c1bf; op2val:0x7ef3c956;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x430778 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f18; op2:f17; dest:x18; op1val:0x7f7fffff; op2val:0x7d430778;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0xfa and fm1 == 0x430778 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f17; op2:f18; dest:x17; op1val:0x7d430778; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f16; op2:f15; dest:x16; op1val:0x7f7fffff; op2val:0x7ef3c956;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f15; op2:f16; dest:x15; op1val:0x7e36c1bf; op2val:0xfeaf0416;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x0c0345 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f14; op2:f13; dest:x14; op1val:0x7f7fffff; op2val:0xfd0c0345;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c0345 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f13; op2:f14; dest:x13; op1val:0xfd0c0345; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f12; op2:f11; dest:x12; op1val:0x7f7fffff; op2val:0xfeaf0416;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f11; op2:f12; dest:x11; op1val:0x7e36c1bf; op2val:0xff336b1f;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0f88e6 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f10; op2:f9; dest:x10; op1val:0x7f7fffff; op2val:0xfd8f88e6;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 1 and fe1 == 0xfb and fm1 == 0x0f88e6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f9; op2:f10; dest:x9; op1val:0xfd8f88e6; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f8; op2:f7; dest:x8; op1val:0x7f7fffff; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f7; op2:f8; dest:x7; op1val:0x7e36c1bf; op2val:0xff130229;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x6b36a9 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f6; op2:f5; dest:x6; op1val:0x7f7fffff; op2val:0xfd6b36a9;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0xfa and fm1 == 0x6b36a9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f5; op2:f6; dest:x5; op1val:0xfd6b36a9; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f4; op2:f3; dest:x4; op1val:0x7f7fffff; op2val:0xff130229;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f3; op2:f4; dest:x3; op1val:0x7e36c1bf; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x20dd41 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f2; op2:f1; dest:x2; op1val:0x7f7fffff; op2val:0xfd20dd41;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0xfa and fm1 == 0x20dd41 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f1; op2:f2; dest:x1; op1val:0xfd20dd41; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f0; op2:f31; dest:x31; op1val:0x7f7fffff; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f31; op2:f0; dest:x31; op1val:0x7e36c1bf; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x0; op1val:0xfdcaaeb1; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2101360805,32,FLEN)
-NAN_BOXED(2101360805,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2105572096,32,FLEN)
-NAN_BOXED(2105572096,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2101544824,32,FLEN)
-NAN_BOXED(2101544824,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4245422917,32,FLEN)
-NAN_BOXED(4245422917,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4254042342,32,FLEN)
-NAN_BOXED(4254042342,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-test_dataset_1:
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4251661993,32,FLEN)
-NAN_BOXED(4251661993,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4246789441,32,FLEN)
-NAN_BOXED(4246789441,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 16*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fli.d-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fli.d-01.S
deleted file mode 100644
index b670ebc23..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fli.d-01.S
+++ /dev/null
@@ -1,204 +0,0 @@
-// Copyright (c) 2023. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fli.d instruction
-// for the following ISA configurations:
-// * RV32ID_Zfa
-// * RV64ID_Zfa
-
-#include "model_test.h"
-#include "arch_test.h"
-
-RVTEST_ISA("RV32ID_Zfa,RV64ID_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-
-RVMODEL_BOOT
-
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fli.d)
-
-// Registers with a special purpose
-#define SIG_BASEREG x1
-#define FCSR_REG x2
-#define DATA_BASEREG x3
-
-// Initialize the FPU
-RVTEST_FP_ENABLE()
-// Prepare the DATA_BASEREG register
-RVTEST_VALBASEUPD(DATA_BASEREG, dataset_tc1)
-// Prepare the SIG_BASEREG register
-RVTEST_SIGBASE(SIG_BASEREG, signature_tc1)
-
-// FLI.D loads a pre-defined constant into a FP register.
-// FLI.D has the following inputs and outputs:
-// - input rs1: 5-bit immediate holding the constants ID
-// - output fld: FP register
-
-// TEST_CASE_FLI_D executes a FLI.D insn and stores the result in the sig
-// 1) the FCSR_OLD value will be store into FCSR using FCSR_REG
-// 2) fli.d is executed using FLD as dest register and FLI_CONST as constant
-// 3) The constents of FLD and FCSR are stored in the signature
-#define TEST_CASE_FLI_D(fld, fli_const, fcsr_old, fcsr_reg) \
-    li fcsr_reg, fcsr_old ;\
-    csrw fcsr, fcsr_reg   ;\
-    fli.d fld, fli_const  ;\
-    csrr fcsr_reg, fcsr   ;\
-    RVTEST_SIGUPD_F(SIG_BASEREG, fld, fcsr_reg) ;\
-
-// Below we have one instruction test per constant
-
-inst_0:
-TEST_CASE_FLI_D(f16, -0x1p+0, 0, FCSR_REG)
-
-inst_1:
-TEST_CASE_FLI_D(f17, min, 0, FCSR_REG)
-
-inst_2:
-TEST_CASE_FLI_D(f18, 0x1p-16, 0, FCSR_REG)
-
-inst_3:
-TEST_CASE_FLI_D(f19, 0x1p-15, 0, FCSR_REG)
-
-inst_4:
-TEST_CASE_FLI_D(f20, 0x1p-8, 0, FCSR_REG)
-
-inst_5:
-TEST_CASE_FLI_D(f21, 0x1p-7, 0, FCSR_REG)
-
-inst_6:
-TEST_CASE_FLI_D(f22, 0x1p-4, 0, FCSR_REG)
-
-inst_7:
-TEST_CASE_FLI_D(f23, 0x1p-3, 0, FCSR_REG)
-
-inst_8:
-TEST_CASE_FLI_D(f24, 0x1p-2, 0, FCSR_REG)
-
-inst_9:
-TEST_CASE_FLI_D(f25, 0x1.4p-2, 0, FCSR_REG)
-
-inst_10:
-TEST_CASE_FLI_D(f26, 0x1.8p-2, 0, FCSR_REG)
-
-inst_11:
-TEST_CASE_FLI_D(f27, 0x1.cp-2, 0, FCSR_REG)
-
-inst_12:
-TEST_CASE_FLI_D(f28, 0x1p-1, 0, FCSR_REG)
-
-inst_13:
-TEST_CASE_FLI_D(f29, 0x1.4p-1, 0, FCSR_REG)
-
-inst_14:
-TEST_CASE_FLI_D(f30, 0x1.8p-1, 0, FCSR_REG)
-
-inst_15:
-TEST_CASE_FLI_D(f31, 0x1.cp-1, 0, FCSR_REG)
-
-inst_16:
-TEST_CASE_FLI_D(f0, 0x1p0, 0, FCSR_REG)
-
-inst_17:
-TEST_CASE_FLI_D(f1, 0x1.4p+0, 0, FCSR_REG)
-
-inst_18:
-TEST_CASE_FLI_D(f2, 0x1.8p+0, 0, FCSR_REG)
-
-inst_19:
-TEST_CASE_FLI_D(f3, 0x1.cp+0, 0, FCSR_REG)
-
-inst_20:
-TEST_CASE_FLI_D(f4, 0x1p+1, 0, FCSR_REG)
-
-inst_21:
-TEST_CASE_FLI_D(f5, 0x1.4p+1, 0, FCSR_REG)
-
-inst_22:
-TEST_CASE_FLI_D(f6, 0x1.8p+1, 0, FCSR_REG)
-
-inst_23:
-TEST_CASE_FLI_D(f7, 0x1p+2, 0, FCSR_REG)
-
-inst_24:
-TEST_CASE_FLI_D(f8, 0x1p+3, 0, FCSR_REG)
-
-inst_25:
-TEST_CASE_FLI_D(f9, 0x1p+4, 0, FCSR_REG)
-
-inst_26:
-TEST_CASE_FLI_D(f10, 0x1p+7, 0, FCSR_REG)
-
-inst_27:
-TEST_CASE_FLI_D(f11, 0x1p+8, 0, FCSR_REG)
-
-inst_28:
-TEST_CASE_FLI_D(f12, 0x1p+15, 0, FCSR_REG)
-
-inst_29:
-TEST_CASE_FLI_D(f13, 0x1p+16, 0, FCSR_REG)
-
-inst_30:
-TEST_CASE_FLI_D(f14, inf, 0, FCSR_REG)
-
-inst_31:
-TEST_CASE_FLI_D(f15, nan, 0, FCSR_REG)
-
-#endif // TEST_CASE_1
-
-RVTEST_CODE_END
-
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.word 0xbabecafe // trapreg_sv
-.word 0xabecafeb // tramptbl_sv
-.word 0xbecafeba // mtvec_save
-.word 0xecafebab // mscratch_save
-dataset_tc1:
-/* empty */
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-signature_tc1:
-// We have 32 test cases and store for each test case:
-// - 32-bit FP register (fld)
-// - 32-bit FCSR content after the instruction
-    .fill 64*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-
-tsig_begin_canary:
-CANARY;
-tsig_begin_canary:
-CANARY;
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-tsig_end_canary:
-CANARY;
-tsig_end_canary:
-CANARY;
-
-#endif // rvtest_mtrap_routine
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif // rvtest_gpr_save
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fltq.d_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fltq.d_b1-01.S
deleted file mode 100644
index 674477dee..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fltq.d_b1-01.S
+++ /dev/null
@@ -1,4740 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:17:37 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fltq.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fltq.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fltq.d_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fltq.d_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 == rs2, rs1==f31, rs2==f31, rd==x31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f31; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 != rs2, rs1==f30, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f30; op2:f29; dest:x30; op1val:0x0; op2val:0x8000000000000000;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x30, f30, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f29, rs2==f30, rd==x29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f29; op2:f30; dest:x29; op1val:0x0; op2val:0x1;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x29, f29, f30, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f28; op2:f27; dest:x28; op1val:0x0; op2val:0x8000000000000001;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f27; op2:f28; dest:x27; op1val:0x0; op2val:0x2;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f26; op2:f25; dest:x26; op1val:0x0; op2val:0x8000000000000002;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f25; op2:f26; dest:x25; op1val:0x0; op2val:0xfffffffffffff;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f24; op2:f23; dest:x24; op1val:0x0; op2val:0x800fffffffffffff;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f23; op2:f24; dest:x23; op1val:0x0; op2val:0x10000000000000;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f22; op2:f21; dest:x22; op1val:0x0; op2val:0x8010000000000000;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f21; op2:f22; dest:x21; op1val:0x0; op2val:0x10000000000002;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f20; op2:f19; dest:x20; op1val:0x0; op2val:0x8010000000000002;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f19; op2:f20; dest:x19; op1val:0x0; op2val:0x7fefffffffffffff;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f18; op2:f17; dest:x18; op1val:0x0; op2val:0xffefffffffffffff;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f17; op2:f18; dest:x17; op1val:0x0; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f16; op2:f15; dest:x16; op1val:0x0; op2val:0xfff0000000000000;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f15; op2:f16; dest:x15; op1val:0x0; op2val:0x7ff8000000000000;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f14; op2:f13; dest:x14; op1val:0x0; op2val:0xfff8000000000000;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f13; op2:f14; dest:x13; op1val:0x0; op2val:0x7ff8000000000001;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f12; op2:f11; dest:x12; op1val:0x0; op2val:0xfff8000000000001;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f11; op2:f12; dest:x11; op1val:0x0; op2val:0x7ff0000000000001;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f10; op2:f9; dest:x10; op1val:0x0; op2val:0xfff0000000000001;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f9; op2:f10; dest:x9; op1val:0x0; op2val:0x3ff0000000000000;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f8; op2:f7; dest:x8; op1val:0x0; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f7; op2:f8; dest:x7; op1val:0x8000000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f6; op2:f5; dest:x6; op1val:0x8000000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f5; op2:f6; dest:x5; op1val:0x8000000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f4; op2:f3; dest:x4; op1val:0x8000000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f3; op2:f4; dest:x3; op1val:0x8000000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f2; op2:f1; dest:x2; op1val:0x8000000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f1; op2:f2; dest:x1; op1val:0x8000000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f0; op2:f31; dest:x31; op1val:0x8000000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f0; dest:x31; op1val:0x8000000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x0; op1val:0x8000000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x0;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x1;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x2;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x0;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x1;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x2;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x0;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x1;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x2;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x0;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x1;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x2;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x0;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x1;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x2;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
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-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 80*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fltq.d_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fltq.d_b19-01.S
deleted file mode 100644
index 4aa3786cb..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fltq.d_b19-01.S
+++ /dev/null
@@ -1,9344 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:17:37 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fltq.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fltq.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fltq.d_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fltq.d_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 == rs2, rs1==f31, rs2==f31, rd==x31,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f31; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 != rs2, rs1==f30, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f30; op2:f29; dest:x30; op1val:0x7fee97d52f73d2ed; op2val:0x7feabc6824ad2440;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x30, f30, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f29, rs2==f30, rd==x29,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f29; op2:f30; dest:x29; op1val:0x7feabc6824ad2440; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x29, f29, f30, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f28; op2:f27; dest:x28; op1val:0x7fee97d52f73d2ed; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f27; op2:f28; dest:x27; op1val:0x7fe363e504d94fe2; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f26; op2:f25; dest:x26; op1val:0x7fee97d52f73d2ed; op2val:0x7fdb9017651b96db;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x879775929758a and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f25; op2:f26; dest:x25; op1val:0x7fb879775929758a; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x879775929758a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f24; op2:f23; dest:x24; op1val:0x7ff0000000000000; op2val:0x7fb879775929758a;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x879775929758a and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f23; op2:f24; dest:x23; op1val:0x7fb879775929758a; op2val:0x7fdb9017651b96db;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x879775929758a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f22; op2:f21; dest:x22; op1val:0x7fee97d52f73d2ed; op2val:0x7fb879775929758a;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f21; op2:f22; dest:x21; op1val:0x7fee97d52f73d2ed; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f20; op2:f19; dest:x20; op1val:0x7fee61729d7cfd5e; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f19; op2:f20; dest:x19; op1val:0x7fee97d52f73d2ed; op2val:0xffaab65b09a91410;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x3945f7a87913c and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f18; op2:f17; dest:x18; op1val:0x7f83945f7a87913c; op2val:0xfff0000000000000;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x3945f7a87913c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f17; op2:f18; dest:x17; op1val:0xfff0000000000000; op2val:0x7f83945f7a87913c;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x3945f7a87913c and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f16; op2:f15; dest:x16; op1val:0x7f83945f7a87913c; op2val:0xffaab65b09a91410;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x3945f7a87913c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f15; op2:f16; dest:x15; op1val:0x7fee97d52f73d2ed; op2val:0x7f83945f7a87913c;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f14; op2:f13; dest:x14; op1val:0x7fee97d52f73d2ed; op2val:0xffd0e5de21873eea;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x879775929758a and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f13; op2:f14; dest:x13; op1val:0x7fb879775929758a; op2val:0xfff0000000000000;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x879775929758a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f12; op2:f11; dest:x12; op1val:0xfff0000000000000; op2val:0x7fb879775929758a;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x879775929758a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f11; op2:f12; dest:x11; op1val:0x7fb879775929758a; op2val:0xffd0e5de21873eea;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f10; op2:f9; dest:x10; op1val:0x7fee97d52f73d2ed; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x879775929758a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f9; op2:f10; dest:x9; op1val:0x7fb879775929758a; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f8; op2:f7; dest:x8; op1val:0x7fee97d52f73d2ed; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f7; op2:f8; dest:x7; op1val:0xffe3682ff4c90ae0; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f6; op2:f5; dest:x6; op1val:0x7fee97d52f73d2ed; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x879775929758a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f5; op2:f6; dest:x5; op1val:0x7fb879775929758a; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f4; op2:f3; dest:x4; op1val:0x7fee97d52f73d2ed; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 0 and fe1 == 0x000 and fm1 == 0x13c6071994562 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x6660e5465cd6d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f3; op2:f4; dest:x3; op1val:0x13c6071994562; op2val:0x7fe6660e5465cd6d;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x13c6071994562 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f2; op2:f1; dest:x2; op1val:0x7fe6660e5465cd6d; op2val:0x13c6071994562;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 0 and fe1 == 0x000 and fm1 == 0x13c6071994562 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f1; op2:f2; dest:x1; op1val:0x13c6071994562; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0x13c6071994562 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f0; op2:f31; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x13c6071994562;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f0; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xa86c4594097a9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x0; op1val:0xc5bc46ffcb5d2; op2val:0x7fea86c4594097a9;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc5bc46ffcb5d2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0xc5bc46ffcb5d2;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc5bc46ffcb5d2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0xc5bc46ffcb5d2;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x705262580c704 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x7fe705262580c704;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc5bc46ffcb5d2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0xc5bc46ffcb5d2;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xca304f80cbc99 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x7feca304f80cbc99;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc5bc46ffcb5d2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0xc5bc46ffcb5d2;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x13c6071994562 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x13c6071994562; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x13c6071994562 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x13c6071994562;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x13c6071994562 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x13c6071994562; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc5bc46ffcb5d2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xc5bc46ffcb5d2;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb672fe8c6e870 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0xffeb672fe8c6e870;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc5bc46ffcb5d2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0xc5bc46ffcb5d2;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01fa33e8f53bd and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x484bb4eb5b9d5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1fa33e8f53bd; op2val:0xffe484bb4eb5b9d5;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01fa33e8f53bd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x1fa33e8f53bd;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01fa33e8f53bd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1fa33e8f53bd; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01fa33e8f53bd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x1fa33e8f53bd;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xcfbb63d922c8f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0xffecfbb63d922c8f;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc5bc46ffcb5d2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0xc5bc46ffcb5d2;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x0;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xb7f9db1715774 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ffb7f9db1715774; op2val:0x0;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xb7f9db1715774 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ffb7f9db1715774;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xb7f9db1715774 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x3ffb7f9db1715774;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5638683bdb69a and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5638683bdb69a; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5638683bdb69a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7fb5638683bdb69a;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5638683bdb69a and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5638683bdb69a; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5638683bdb69a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x7fb5638683bdb69a;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x11c6b9c97c548 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f811c6b9c97c548; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x11c6b9c97c548 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7f811c6b9c97c548;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x11c6b9c97c548 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f811c6b9c97c548; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x11c6b9c97c548 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x7f811c6b9c97c548;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5638683bdb69a and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5638683bdb69a; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5638683bdb69a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fb5638683bdb69a;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5638683bdb69a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5638683bdb69a; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5638683bdb69a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5638683bdb69a; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5638683bdb69a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5638683bdb69a; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1147d0920addb and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x6660e5465cd6d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1147d0920addb; op2val:0x7fe6660e5465cd6d;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1147d0920addb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0x1147d0920addb;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1147d0920addb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1147d0920addb; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1147d0920addb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x1147d0920addb;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xa86c4594097a9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x7fea86c4594097a9;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xacce25b46ca92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0xacce25b46ca92;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xacce25b46ca92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xacce25b46ca92;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x705262580c704 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x7fe705262580c704;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xacce25b46ca92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0xacce25b46ca92;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xca304f80cbc99 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x7feca304f80cbc99;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xacce25b46ca92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0xacce25b46ca92;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1147d0920addb and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1147d0920addb; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1147d0920addb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x1147d0920addb;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1147d0920addb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1147d0920addb; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xacce25b46ca92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xacce25b46ca92;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb672fe8c6e870 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0xffeb672fe8c6e870;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xacce25b46ca92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0xacce25b46ca92;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01ba61a834496 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x484bb4eb5b9d5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ba61a834496; op2val:0xffe484bb4eb5b9d5;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01ba61a834496 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x1ba61a834496;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01ba61a834496 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ba61a834496; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01ba61a834496 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x1ba61a834496;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xcfbb63d922c8f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0xffecfbb63d922c8f;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xacce25b46ca92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0xacce25b46ca92;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x0;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x80812523614ab and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff80812523614ab; op2val:0x0;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x80812523614ab and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff80812523614ab;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x80812523614ab and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x3ff80812523614ab;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xf063b3af54c9d and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7faf063b3af54c9d; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xf063b3af54c9d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7faf063b3af54c9d;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xf063b3af54c9d and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7faf063b3af54c9d; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xf063b3af54c9d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x7faf063b3af54c9d;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0x8d1c8fbf7707e and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f78d1c8fbf7707e; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0x8d1c8fbf7707e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7f78d1c8fbf7707e;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0x8d1c8fbf7707e and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f78d1c8fbf7707e; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0x8d1c8fbf7707e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x7f78d1c8fbf7707e;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xf063b3af54c9d and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7faf063b3af54c9d; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xf063b3af54c9d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7faf063b3af54c9d;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xf063b3af54c9d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7faf063b3af54c9d; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xf063b3af54c9d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7faf063b3af54c9d; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xf063b3af54c9d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7faf063b3af54c9d; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0c885d3ef4f92 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x6660e5465cd6d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc885d3ef4f92; op2val:0x7fe6660e5465cd6d;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0c885d3ef4f92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0xc885d3ef4f92;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0c885d3ef4f92 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc885d3ef4f92; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0c885d3ef4f92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xc885d3ef4f92;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xa86c4594097a9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x7fea86c4594097a9;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7d53a47591bb8 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0x7d53a47591bb8;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7d53a47591bb8 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x7d53a47591bb8;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x705262580c704 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x7fe705262580c704;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7d53a47591bb8 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0x7d53a47591bb8;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xca304f80cbc99 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x7feca304f80cbc99;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7d53a47591bb8 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0x7d53a47591bb8;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0c885d3ef4f92 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc885d3ef4f92; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0c885d3ef4f92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xc885d3ef4f92;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0c885d3ef4f92 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc885d3ef4f92; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7d53a47591bb8 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7d53a47591bb8;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb672fe8c6e870 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0xffeb672fe8c6e870;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7d53a47591bb8 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0x7d53a47591bb8;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0140d61fe54c2 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x484bb4eb5b9d5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x140d61fe54c2; op2val:0xffe484bb4eb5b9d5;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0140d61fe54c2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x140d61fe54c2;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0140d61fe54c2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x140d61fe54c2; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0140d61fe54c2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x140d61fe54c2;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xcfbb63d922c8f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0xffecfbb63d922c8f;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7d53a47591bb8 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0x7d53a47591bb8;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x0;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x16dc795a2b73d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff16dc795a2b73d; op2val:0x0;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x16dc795a2b73d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff16dc795a2b73d;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x16dc795a2b73d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x3ff16dc795a2b73d;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x84df54aca644b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7fb84df54aca644b;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x84df54aca644b and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb84df54aca644b; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0x60cdf84161249 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0b1f8e609ac8a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fa60cdf84161249; op2val:0xffe0b1f8e609ac8a;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 0 and fe2 == 0x7fa and fm2 == 0x60cdf84161249 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0x7fa60cdf84161249;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0x60cdf84161249 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fa60cdf84161249; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x7fa and fm2 == 0x60cdf84161249 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x7fa60cdf84161249;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf0d1987a81166 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xffaf0d1987a81166;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf0d1987a81166 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaf0d1987a81166; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x59132cc0dc780 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x1eb3ea9eb0abd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x59132cc0dc780; op2val:0x7fb1eb3ea9eb0abd;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 0 and fe2 == 0x000 and fm2 == 0x59132cc0dc780 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0x59132cc0dc780;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x59132cc0dc780 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x59132cc0dc780; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x59132cc0dc780 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x59132cc0dc780;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5389d1433ac87 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x7fb5389d1433ac87;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x26a84eacd6c03 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x7fb26a84eacd6c03;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x6e8d0c67096e1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x7fb6e8d0c67096e1;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x59132cc0dc780 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x19e9f6802bcef and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x59132cc0dc780; op2val:0x7fe19e9f6802bcef;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 0 and fe2 == 0x000 and fm2 == 0x59132cc0dc780 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0x59132cc0dc780;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x59132cc0dc780 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x59132cc0dc780; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xcff30f3beb065 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0xffbcff30f3beb065;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x5ec2653d2538d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0xffb5ec2653d2538d;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xaaae5b42b9d01 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0xffbaaae5b42b9d01;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x08e851467c726 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x06a2f722afb11 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8e851467c726; op2val:0xffb06a2f722afb11;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x08e851467c726 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0x8e851467c726;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x08e851467c726 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8e851467c726; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x08e851467c726 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x8e851467c726;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x72fc4fe0e8a0c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0xffb72fc4fe0e8a0c;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x0;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 0 and fe1 == 0x401 and fm1 == 0xef7eded580ce9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x401ef7eded580ce9; op2val:0x0;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x401 and fm2 == 0xef7eded580ce9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x401ef7eded580ce9;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x401 and fm2 == 0xef7eded580ce9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x401ef7eded580ce9;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x84df54aca644b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb84df54aca644b; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x84df54aca644b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x7fb84df54aca644b;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x3719108a1e9d6 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f83719108a1e9d6; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x3719108a1e9d6 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7f83719108a1e9d6;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x3719108a1e9d6 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f83719108a1e9d6; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x3719108a1e9d6 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x7f83719108a1e9d6;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x84df54aca644b and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb84df54aca644b; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x84df54aca644b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fb84df54aca644b;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x84df54aca644b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb84df54aca644b; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x84df54aca644b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb84df54aca644b; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x84df54aca644b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb84df54aca644b; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x13a2e0625c7c9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x6660e5465cd6d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x13a2e0625c7c9; op2val:0x7fe6660e5465cd6d;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x13a2e0625c7c9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0x13a2e0625c7c9;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x13a2e0625c7c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x13a2e0625c7c9; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x13a2e0625c7c9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x13a2e0625c7c9;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xa86c4594097a9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x7fea86c4594097a9;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc45cc3d79cddb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0xc45cc3d79cddb;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc45cc3d79cddb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xc45cc3d79cddb;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x705262580c704 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x7fe705262580c704;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc45cc3d79cddb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0xc45cc3d79cddb;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xca304f80cbc99 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x7feca304f80cbc99;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc45cc3d79cddb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0xc45cc3d79cddb;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x13a2e0625c7c9 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x13a2e0625c7c9; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x13a2e0625c7c9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x13a2e0625c7c9;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x13a2e0625c7c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x13a2e0625c7c9; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc45cc3d79cddb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xc45cc3d79cddb;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb672fe8c6e870 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0xffeb672fe8c6e870;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc45cc3d79cddb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0xc45cc3d79cddb;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01f6b009d60c7 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x484bb4eb5b9d5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1f6b009d60c7; op2val:0xffe484bb4eb5b9d5;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01f6b009d60c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x1f6b009d60c7;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01f6b009d60c7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1f6b009d60c7; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01f6b009d60c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x1f6b009d60c7;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xcfbb63d922c8f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0xffecfbb63d922c8f;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc45cc3d79cddb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0xc45cc3d79cddb;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x0;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xb4ebb70505c5a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ffb4ebb70505c5a; op2val:0x0;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xb4ebb70505c5a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ffb4ebb70505c5a;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xb4ebb70505c5a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x3ffb4ebb70505c5a;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0b1f8e609ac8a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xffe0b1f8e609ac8a;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0xb096368d864aa and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0xff9b096368d864aa;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0xb096368d864aa and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0b1f8e609ac8a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff9b096368d864aa; op2val:0xffe0b1f8e609ac8a;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x421ba72f8a718 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0xffa421ba72f8a718;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x421ba72f8a718 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0b1f8e609ac8a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffa421ba72f8a718; op2val:0xffe0b1f8e609ac8a;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0x8d7479fb9a785 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xff78d7479fb9a785;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0x8d7479fb9a785 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff78d7479fb9a785; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x7569006cfbae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0xffa7569006cfbae0;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x7569006cfbae0 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0b1f8e609ac8a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffa7569006cfbae0; op2val:0xffe0b1f8e609ac8a;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6be865c2463a7 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xcab977644ddfc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006be865c2463a7; op2val:0x7f7cab977644ddfc;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xcab977644ddfc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6be865c2463a7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f7cab977644ddfc; op2val:0x8006be865c2463a7;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6be865c2463a7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006be865c2463a7; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6be865c2463a7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x8006be865c2463a7;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x0fa17435c8a06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x7f80fa17435c8a06;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x0fa17435c8a06 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f80fa17435c8a06; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xd773b1148acd1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x7f7d773b1148acd1;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xd773b1148acd1 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f7d773b1148acd1; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x253da385a124e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x7f8253da385a124e;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x253da385a124e and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f8253da385a124e; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6be865c2463a7 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xc30ff0cd12e4b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006be865c2463a7; op2val:0x7fac30ff0cd12e4b;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xc30ff0cd12e4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6be865c2463a7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fac30ff0cd12e4b; op2val:0x8006be865c2463a7;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6be865c2463a7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006be865c2463a7; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x7328d8fcbc051 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0xff87328d8fcbc051;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x7328d8fcbc051 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff87328d8fcbc051; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x189b8430ea93d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0xff8189b8430ea93d;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x189b8430ea93d and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff8189b8430ea93d; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x555849022e400 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0xff8555849022e400;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x555849022e400 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff8555849022e400; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0aca70936d6c4 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0xa437f1d1191b5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000aca70936d6c4; op2val:0xff7a437f1d1191b5;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0xa437f1d1191b5 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0aca70936d6c4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff7a437f1d1191b5; op2val:0x8000aca70936d6c4;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0aca70936d6c4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000aca70936d6c4; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0aca70936d6c4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x8000aca70936d6c4;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x28c9d980ba1a3 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0xff828c9d980ba1a3;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x28c9d980ba1a3 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff828c9d980ba1a3; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x0;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 1 and fe1 == 0x402 and fm1 == 0x2c20e7e96fa8e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc022c20e7e96fa8e; op2val:0x0;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x2c20e7e96fa8e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc022c20e7e96fa8e;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x2c20e7e96fa8e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xc022c20e7e96fa8e;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0xb096368d864aa and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff9b096368d864aa; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0xb096368d864aa and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xff9b096368d864aa;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf0d1987a81166 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffaf0d1987a81166;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf0d1987a81166 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaf0d1987a81166; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x369be8c5e3b80 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x1eb3ea9eb0abd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800369be8c5e3b80; op2val:0x7fb1eb3ea9eb0abd;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x369be8c5e3b80 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0x800369be8c5e3b80;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x369be8c5e3b80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800369be8c5e3b80; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x000 and fm2 == 0x369be8c5e3b80 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x800369be8c5e3b80;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5389d1433ac87 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x7fb5389d1433ac87;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x26a84eacd6c03 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x7fb26a84eacd6c03;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x6e8d0c67096e1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x7fb6e8d0c67096e1;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x369be8c5e3b80 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x19e9f6802bcef and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800369be8c5e3b80; op2val:0x7fe19e9f6802bcef;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 1 and fe2 == 0x000 and fm2 == 0x369be8c5e3b80 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0x800369be8c5e3b80;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x369be8c5e3b80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800369be8c5e3b80; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xcff30f3beb065 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0xffbcff30f3beb065;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x5ec2653d2538d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0xffb5ec2653d2538d;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xaaae5b42b9d01 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0xffbaaae5b42b9d01;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0575fdad63926 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x06a2f722afb11 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000575fdad63926; op2val:0xffb06a2f722afb11;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0575fdad63926 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0x8000575fdad63926;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0575fdad63926 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000575fdad63926; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0575fdad63926 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x8000575fdad63926;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x72fc4fe0e8a0c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0xffb72fc4fe0e8a0c;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x0;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 1 and fe1 == 0x401 and fm1 == 0x2fc5d39f551da and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc012fc5d39f551da; op2val:0x0;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x2fc5d39f551da and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc012fc5d39f551da;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x401 and fm2 == 0x2fc5d39f551da and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xc012fc5d39f551da;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x421ba72f8a718 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffa421ba72f8a718; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x421ba72f8a718 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xffa421ba72f8a718;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x51532237be62c and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x1eb3ea9eb0abd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80051532237be62c; op2val:0x7fb1eb3ea9eb0abd;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x51532237be62c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0x80051532237be62c;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x51532237be62c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80051532237be62c; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x000 and fm2 == 0x51532237be62c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x80051532237be62c;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5389d1433ac87 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x7fb5389d1433ac87;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x26a84eacd6c03 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x7fb26a84eacd6c03;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x6e8d0c67096e1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x7fb6e8d0c67096e1;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x51532237be62c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x19e9f6802bcef and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80051532237be62c; op2val:0x7fe19e9f6802bcef;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 1 and fe2 == 0x000 and fm2 == 0x51532237be62c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0x80051532237be62c;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x51532237be62c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80051532237be62c; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xcff30f3beb065 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0xffbcff30f3beb065;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x5ec2653d2538d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0xffb5ec2653d2538d;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xaaae5b42b9d01 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0xffbaaae5b42b9d01;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0821e9d25fd6b and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x06a2f722afb11 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000821e9d25fd6b; op2val:0xffb06a2f722afb11;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0821e9d25fd6b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0x8000821e9d25fd6b;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0821e9d25fd6b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000821e9d25fd6b; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0821e9d25fd6b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x8000821e9d25fd6b;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x72fc4fe0e8a0c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0xffb72fc4fe0e8a0c;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x0;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 1 and fe1 == 0x401 and fm1 == 0xc4624671f2f0c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc01c4624671f2f0c; op2val:0x0;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0xc4624671f2f0c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc01c4624671f2f0c;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x401 and fm2 == 0xc4624671f2f0c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xc01c4624671f2f0c;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf0d1987a81166 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaf0d1987a81166; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf0d1987a81166 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xffaf0d1987a81166;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0x8d7479fb9a785 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff78d7479fb9a785; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0x8d7479fb9a785 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xff78d7479fb9a785;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf0d1987a81166 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaf0d1987a81166; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf0d1987a81166 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaf0d1987a81166; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf0d1987a81166 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaf0d1987a81166; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c8b23887d51e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x6660e5465cd6d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000c8b23887d51e; op2val:0x7fe6660e5465cd6d;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0c8b23887d51e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0x8000c8b23887d51e;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c8b23887d51e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000c8b23887d51e; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0c8b23887d51e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x8000c8b23887d51e;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xa86c4594097a9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x7fea86c4594097a9;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7d6f6354e532b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0x8007d6f6354e532b;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7d6f6354e532b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x8007d6f6354e532b;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x705262580c704 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x7fe705262580c704;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7d6f6354e532b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0x8007d6f6354e532b;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xca304f80cbc99 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x7feca304f80cbc99;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7d6f6354e532b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0x8007d6f6354e532b;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-
-inst_578:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c8b23887d51e and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000c8b23887d51e; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1110*FLEN/8, x10, x6, x7)
-
-inst_579:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0c8b23887d51e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000c8b23887d51e;
-valaddr_reg:x9; val_offset:1112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1112*FLEN/8, x10, x6, x7)
-
-inst_580:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c8b23887d51e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000c8b23887d51e; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1114*FLEN/8, x10, x6, x7)
-
-inst_581:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1116*FLEN/8, x10, x6, x7)
-
-inst_582:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1118*FLEN/8, x10, x6, x7)
-
-inst_583:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7d6f6354e532b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8007d6f6354e532b;
-valaddr_reg:x9; val_offset:1120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1120*FLEN/8, x10, x6, x7)
-
-inst_584:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1122*FLEN/8, x10, x6, x7)
-
-inst_585:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1124*FLEN/8, x10, x6, x7)
-
-inst_586:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb672fe8c6e870 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0xffeb672fe8c6e870;
-valaddr_reg:x9; val_offset:1126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1126*FLEN/8, x10, x6, x7)
-
-inst_587:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7d6f6354e532b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0x8007d6f6354e532b;
-valaddr_reg:x9; val_offset:1128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1128*FLEN/8, x10, x6, x7)
-
-inst_588:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1130*FLEN/8, x10, x6, x7)
-
-inst_589:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1132*FLEN/8, x10, x6, x7)
-
-inst_590:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1134*FLEN/8, x10, x6, x7)
-
-inst_591:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1136*FLEN/8, x10, x6, x7)
-
-inst_592:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01411d273fbb6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x484bb4eb5b9d5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001411d273fbb6; op2val:0xffe484bb4eb5b9d5;
-valaddr_reg:x9; val_offset:1138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1138*FLEN/8, x10, x6, x7)
-
-inst_593:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01411d273fbb6 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x80001411d273fbb6;
-valaddr_reg:x9; val_offset:1140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1140*FLEN/8, x10, x6, x7)
-
-inst_594:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01411d273fbb6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001411d273fbb6; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1142*FLEN/8, x10, x6, x7)
-
-inst_595:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01411d273fbb6 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x80001411d273fbb6;
-valaddr_reg:x9; val_offset:1144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1144*FLEN/8, x10, x6, x7)
-
-inst_596:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1146*FLEN/8, x10, x6, x7)
-
-inst_597:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xcfbb63d922c8f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0xffecfbb63d922c8f;
-valaddr_reg:x9; val_offset:1148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1148*FLEN/8, x10, x6, x7)
-
-inst_598:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7d6f6354e532b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0x8007d6f6354e532b;
-valaddr_reg:x9; val_offset:1150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1150*FLEN/8, x10, x6, x7)
-
-inst_599:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1152*FLEN/8, x10, x6, x7)
-
-inst_600:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x0;
-valaddr_reg:x9; val_offset:1154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1154*FLEN/8, x10, x6, x7)
-
-inst_601:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x171a35c491d80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbff171a35c491d80; op2val:0x0;
-valaddr_reg:x9; val_offset:1156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1156*FLEN/8, x10, x6, x7)
-
-inst_602:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x171a35c491d80 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbff171a35c491d80;
-valaddr_reg:x9; val_offset:1158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1158*FLEN/8, x10, x6, x7)
-
-inst_603:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x171a35c491d80 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xbff171a35c491d80;
-valaddr_reg:x9; val_offset:1160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1160*FLEN/8, x10, x6, x7)
-
-inst_604:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1162*FLEN/8, x10, x6, x7)
-
-inst_605:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1164*FLEN/8, x10, x6, x7)
-
-inst_606:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1166*FLEN/8, x10, x6, x7)
-
-inst_607:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1168*FLEN/8, x10, x6, x7)
-
-inst_608:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1170*FLEN/8, x10, x6, x7)
-
-inst_609:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1172*FLEN/8, x10, x6, x7)
-
-inst_610:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1174*FLEN/8, x10, x6, x7)
-
-inst_611:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x7569006cfbae0 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffa7569006cfbae0; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1176*FLEN/8, x10, x6, x7)
-
-inst_612:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x7569006cfbae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xffa7569006cfbae0;
-valaddr_reg:x9; val_offset:1178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1178*FLEN/8, x10, x6, x7)
-
-inst_613:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1180*FLEN/8, x10, x6, x7)
-
-inst_614:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1182*FLEN/8, x10, x6, x7)
-
-inst_615:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e46ff3af089e and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x1eb3ea9eb0abd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e46ff3af089e; op2val:0x7fb1eb3ea9eb0abd;
-valaddr_reg:x9; val_offset:1184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1184*FLEN/8, x10, x6, x7)
-
-inst_616:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e46ff3af089e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0x8005e46ff3af089e;
-valaddr_reg:x9; val_offset:1186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1186*FLEN/8, x10, x6, x7)
-
-inst_617:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e46ff3af089e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e46ff3af089e; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1188*FLEN/8, x10, x6, x7)
-
-inst_618:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e46ff3af089e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x8005e46ff3af089e;
-valaddr_reg:x9; val_offset:1190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1190*FLEN/8, x10, x6, x7)
-
-inst_619:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1192*FLEN/8, x10, x6, x7)
-
-inst_620:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5389d1433ac87 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x7fb5389d1433ac87;
-valaddr_reg:x9; val_offset:1194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1194*FLEN/8, x10, x6, x7)
-
-inst_621:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1196*FLEN/8, x10, x6, x7)
-
-inst_622:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1198*FLEN/8, x10, x6, x7)
-
-inst_623:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1200*FLEN/8, x10, x6, x7)
-
-inst_624:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1202*FLEN/8, x10, x6, x7)
-
-inst_625:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x26a84eacd6c03 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x7fb26a84eacd6c03;
-valaddr_reg:x9; val_offset:1204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1204*FLEN/8, x10, x6, x7)
-
-inst_626:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1206*FLEN/8, x10, x6, x7)
-
-inst_627:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1208*FLEN/8, x10, x6, x7)
-
-inst_628:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1210*FLEN/8, x10, x6, x7)
-
-inst_629:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x6e8d0c67096e1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x7fb6e8d0c67096e1;
-valaddr_reg:x9; val_offset:1212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1212*FLEN/8, x10, x6, x7)
-
-inst_630:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1214*FLEN/8, x10, x6, x7)
-
-inst_631:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1216*FLEN/8, x10, x6, x7)
-
-inst_632:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1218*FLEN/8, x10, x6, x7)
-
-inst_633:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e46ff3af089e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x19e9f6802bcef and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e46ff3af089e; op2val:0x7fe19e9f6802bcef;
-valaddr_reg:x9; val_offset:1220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1220*FLEN/8, x10, x6, x7)
-
-inst_634:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e46ff3af089e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0x8005e46ff3af089e;
-valaddr_reg:x9; val_offset:1222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1222*FLEN/8, x10, x6, x7)
-
-inst_635:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e46ff3af089e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e46ff3af089e; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1224*FLEN/8, x10, x6, x7)
-
-inst_636:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1226*FLEN/8, x10, x6, x7)
-
-inst_637:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xcff30f3beb065 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0xffbcff30f3beb065;
-valaddr_reg:x9; val_offset:1228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1228*FLEN/8, x10, x6, x7)
-
-inst_638:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1230*FLEN/8, x10, x6, x7)
-
-inst_639:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1232*FLEN/8, x10, x6, x7)
-
-inst_640:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1234*FLEN/8, x10, x6, x7)
-
-inst_641:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x5ec2653d2538d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0xffb5ec2653d2538d;
-valaddr_reg:x9; val_offset:1236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1236*FLEN/8, x10, x6, x7)
-
-inst_642:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1238*FLEN/8, x10, x6, x7)
-
-inst_643:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1240*FLEN/8, x10, x6, x7)
-
-inst_644:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1242*FLEN/8, x10, x6, x7)
-
-inst_645:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xaaae5b42b9d01 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0xffbaaae5b42b9d01;
-valaddr_reg:x9; val_offset:1244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1244*FLEN/8, x10, x6, x7)
-
-inst_646:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1246*FLEN/8, x10, x6, x7)
-
-inst_647:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1248*FLEN/8, x10, x6, x7)
-
-inst_648:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1250*FLEN/8, x10, x6, x7)
-
-inst_649:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x096d7fec4b410 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x06a2f722afb11 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800096d7fec4b410; op2val:0xffb06a2f722afb11;
-valaddr_reg:x9; val_offset:1252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1252*FLEN/8, x10, x6, x7)
-
-inst_650:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x096d7fec4b410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0x800096d7fec4b410;
-valaddr_reg:x9; val_offset:1254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1254*FLEN/8, x10, x6, x7)
-
-inst_651:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x096d7fec4b410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800096d7fec4b410; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1256*FLEN/8, x10, x6, x7)
-
-inst_652:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x096d7fec4b410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x800096d7fec4b410;
-valaddr_reg:x9; val_offset:1258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1258*FLEN/8, x10, x6, x7)
-
-inst_653:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1260*FLEN/8, x10, x6, x7)
-
-inst_654:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x72fc4fe0e8a0c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0xffb72fc4fe0e8a0c;
-valaddr_reg:x9; val_offset:1262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1262*FLEN/8, x10, x6, x7)
-
-inst_655:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1264*FLEN/8, x10, x6, x7)
-
-inst_656:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1266*FLEN/8, x10, x6, x7)
-
-inst_657:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x0;
-valaddr_reg:x9; val_offset:1268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1268*FLEN/8, x10, x6, x7)
-
-inst_658:// fs1 == 1 and fe1 == 0x402 and fm1 == 0x0637b0487519a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc020637b0487519a; op2val:0x0;
-valaddr_reg:x9; val_offset:1270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1270*FLEN/8, x10, x6, x7)
-
-inst_659:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x0637b0487519a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc020637b0487519a;
-valaddr_reg:x9; val_offset:1272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1272*FLEN/8, x10, x6, x7)
-
-inst_660:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x0637b0487519a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xc020637b0487519a;
-valaddr_reg:x9; val_offset:1274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1274*FLEN/8, x10, x6, x7)
-
-inst_661:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1276*FLEN/8, x10, x6, x7)
-
-inst_662:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1278*FLEN/8, x10, x6, x7)
-
-inst_663:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x6660e5465cd6d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7fe6660e5465cd6d;
-valaddr_reg:x9; val_offset:1280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1280*FLEN/8, x10, x6, x7)
-
-inst_664:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1282*FLEN/8, x10, x6, x7)
-
-inst_665:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1284*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_5)
-
-inst_666:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1286*FLEN/8, x10, x6, x7)
-
-inst_667:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1288*FLEN/8, x10, x6, x7)
-
-inst_668:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1290*FLEN/8, x10, x6, x7)
-
-inst_669:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1292*FLEN/8, x10, x6, x7)
-
-inst_670:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1294*FLEN/8, x10, x6, x7)
-
-inst_671:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x1eb3ea9eb0abd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7fb1eb3ea9eb0abd;
-valaddr_reg:x9; val_offset:1296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1296*FLEN/8, x10, x6, x7)
-
-inst_672:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1298*FLEN/8, x10, x6, x7)
-
-inst_673:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1300*FLEN/8, x10, x6, x7)
-
-inst_674:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1302*FLEN/8, x10, x6, x7)
-
-inst_675:// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xcab977644ddfc and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f7cab977644ddfc; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1304*FLEN/8, x10, x6, x7)
-
-inst_676:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xcab977644ddfc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7f7cab977644ddfc;
-valaddr_reg:x9; val_offset:1306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1306*FLEN/8, x10, x6, x7)
-
-inst_677:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1308*FLEN/8, x10, x6, x7)
-
-inst_678:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1310*FLEN/8, x10, x6, x7)
-
-inst_679:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1312*FLEN/8, x10, x6, x7)
-
-inst_680:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1314*FLEN/8, x10, x6, x7)
-
-inst_681:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1316*FLEN/8, x10, x6, x7)
-
-inst_682:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1318*FLEN/8, x10, x6, x7)
-
-inst_683:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1320*FLEN/8, x10, x6, x7)
-
-inst_684:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1322*FLEN/8, x10, x6, x7)
-
-inst_685:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1324*FLEN/8, x10, x6, x7)
-
-inst_686:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1125252921dc7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x1125252921dc7;
-valaddr_reg:x9; val_offset:1326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1326*FLEN/8, x10, x6, x7)
-
-inst_687:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1125252921dc7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1125252921dc7; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1328*FLEN/8, x10, x6, x7)
-
-inst_688:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1330*FLEN/8, x10, x6, x7)
-
-inst_689:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1332*FLEN/8, x10, x6, x7)
-
-inst_690:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1334*FLEN/8, x10, x6, x7)
-
-inst_691:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0ee0fa88947a1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0xee0fa88947a1;
-valaddr_reg:x9; val_offset:1336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1336*FLEN/8, x10, x6, x7)
-
-inst_692:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0ee0fa88947a1 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xee0fa88947a1; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1338*FLEN/8, x10, x6, x7)
-
-inst_693:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1340*FLEN/8, x10, x6, x7)
-
-inst_694:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1342*FLEN/8, x10, x6, x7)
-
-inst_695:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x128254fc5a4fe and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x128254fc5a4fe;
-valaddr_reg:x9; val_offset:1344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1344*FLEN/8, x10, x6, x7)
-
-inst_696:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x128254fc5a4fe and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x128254fc5a4fe; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1346*FLEN/8, x10, x6, x7)
-
-inst_697:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1348*FLEN/8, x10, x6, x7)
-
-inst_698:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1350*FLEN/8, x10, x6, x7)
-
-inst_699:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1352*FLEN/8, x10, x6, x7)
-
-inst_700:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1354*FLEN/8, x10, x6, x7)
-
-inst_701:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x176d62053e9f2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x800176d62053e9f2;
-valaddr_reg:x9; val_offset:1356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1356*FLEN/8, x10, x6, x7)
-
-inst_702:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x176d62053e9f2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800176d62053e9f2; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1358*FLEN/8, x10, x6, x7)
-
-inst_703:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1360*FLEN/8, x10, x6, x7)
-
-inst_704:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1362*FLEN/8, x10, x6, x7)
-
-inst_705:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x11b63268cb80c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x80011b63268cb80c;
-valaddr_reg:x9; val_offset:1364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1364*FLEN/8, x10, x6, x7)
-
-inst_706:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11b63268cb80c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80011b63268cb80c; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1366*FLEN/8, x10, x6, x7)
-
-inst_707:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1368*FLEN/8, x10, x6, x7)
-
-inst_708:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1370*FLEN/8, x10, x6, x7)
-
-inst_709:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x158b9f3ccd07c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x800158b9f3ccd07c;
-valaddr_reg:x9; val_offset:1372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1372*FLEN/8, x10, x6, x7)
-
-inst_710:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x158b9f3ccd07c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800158b9f3ccd07c; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1374*FLEN/8, x10, x6, x7)
-
-inst_711:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1376*FLEN/8, x10, x6, x7)
-
-inst_712:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1378*FLEN/8, x10, x6, x7)
-
-inst_713:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01729d737e39f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d430d1d19325 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1729d737e39f; op2val:0x8000d430d1d19325;
-valaddr_reg:x9; val_offset:1380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1380*FLEN/8, x10, x6, x7)
-
-inst_714:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d430d1d19325 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01729d737e39f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d430d1d19325; op2val:0x1729d737e39f;
-valaddr_reg:x9; val_offset:1382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1382*FLEN/8, x10, x6, x7)
-
-inst_715:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01729d737e39f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1729d737e39f; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1384*FLEN/8, x10, x6, x7)
-
-inst_716:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01729d737e39f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x1729d737e39f;
-valaddr_reg:x9; val_offset:1386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1386*FLEN/8, x10, x6, x7)
-
-inst_717:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1388*FLEN/8, x10, x6, x7)
-
-inst_718:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x12bba85050ee4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x80012bba85050ee4;
-valaddr_reg:x9; val_offset:1390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1390*FLEN/8, x10, x6, x7)
-
-inst_719:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12bba85050ee4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80012bba85050ee4; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1392*FLEN/8, x10, x6, x7)
-
-inst_720:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1394*FLEN/8, x10, x6, x7)
-
-inst_721:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x0;
-valaddr_reg:x9; val_offset:1396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1396*FLEN/8, x10, x6, x7)
-
-inst_722:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x422095a1629ee and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff422095a1629ee; op2val:0x0;
-valaddr_reg:x9; val_offset:1398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1398*FLEN/8, x10, x6, x7)
-
-inst_723:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x422095a1629ee and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff422095a1629ee;
-valaddr_reg:x9; val_offset:1400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1400*FLEN/8, x10, x6, x7)
-
-inst_724:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x422095a1629ee and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x3ff422095a1629ee;
-valaddr_reg:x9; val_offset:1402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1402*FLEN/8, x10, x6, x7)
-
-inst_725:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1404*FLEN/8, x10, x6, x7)
-
-inst_726:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1406*FLEN/8, x10, x6, x7)
-
-inst_727:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xa86c4594097a9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7fea86c4594097a9;
-valaddr_reg:x9; val_offset:1408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1408*FLEN/8, x10, x6, x7)
-
-inst_728:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1410*FLEN/8, x10, x6, x7)
-
-inst_729:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1412*FLEN/8, x10, x6, x7)
-
-inst_730:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1414*FLEN/8, x10, x6, x7)
-
-inst_731:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1416*FLEN/8, x10, x6, x7)
-
-inst_732:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1418*FLEN/8, x10, x6, x7)
-
-inst_733:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1420*FLEN/8, x10, x6, x7)
-
-inst_734:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1422*FLEN/8, x10, x6, x7)
-
-inst_735:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5389d1433ac87 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7fb5389d1433ac87;
-valaddr_reg:x9; val_offset:1424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1424*FLEN/8, x10, x6, x7)
-
-inst_736:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1426*FLEN/8, x10, x6, x7)
-
-inst_737:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1428*FLEN/8, x10, x6, x7)
-
-inst_738:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1430*FLEN/8, x10, x6, x7)
-
-inst_739:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x0fa17435c8a06 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f80fa17435c8a06; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1432*FLEN/8, x10, x6, x7)
-
-inst_740:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x0fa17435c8a06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7f80fa17435c8a06;
-valaddr_reg:x9; val_offset:1434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1434*FLEN/8, x10, x6, x7)
-
-inst_741:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1436*FLEN/8, x10, x6, x7)
-
-inst_742:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1438*FLEN/8, x10, x6, x7)
-
-inst_743:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1440*FLEN/8, x10, x6, x7)
-
-inst_744:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1442*FLEN/8, x10, x6, x7)
-
-inst_745:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1444*FLEN/8, x10, x6, x7)
-
-inst_746:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1446*FLEN/8, x10, x6, x7)
-
-inst_747:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1448*FLEN/8, x10, x6, x7)
-
-inst_748:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1450*FLEN/8, x10, x6, x7)
-
-inst_749:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1452*FLEN/8, x10, x6, x7)
-
-inst_750:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1125252921dc7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1125252921dc7; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1454*FLEN/8, x10, x6, x7)
-
-inst_751:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1125252921dc7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x1125252921dc7;
-valaddr_reg:x9; val_offset:1456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1456*FLEN/8, x10, x6, x7)
-
-inst_752:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1458*FLEN/8, x10, x6, x7)
-
-inst_753:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1460*FLEN/8, x10, x6, x7)
-
-inst_754:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1462*FLEN/8, x10, x6, x7)
-
-inst_755:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1464*FLEN/8, x10, x6, x7)
-
-inst_756:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1466*FLEN/8, x10, x6, x7)
-
-inst_757:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1125252921dc7 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1125252921dc7; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1468*FLEN/8, x10, x6, x7)
-
-inst_758:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1125252921dc7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x1125252921dc7;
-valaddr_reg:x9; val_offset:1470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1470*FLEN/8, x10, x6, x7)
-
-inst_759:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1125252921dc7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1125252921dc7; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1472*FLEN/8, x10, x6, x7)
-
-inst_760:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1474*FLEN/8, x10, x6, x7)
-
-inst_761:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1476*FLEN/8, x10, x6, x7)
-
-inst_762:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1478*FLEN/8, x10, x6, x7)
-
-inst_763:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1480*FLEN/8, x10, x6, x7)
-
-inst_764:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1482*FLEN/8, x10, x6, x7)
-
-inst_765:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1484*FLEN/8, x10, x6, x7)
-
-inst_766:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1486*FLEN/8, x10, x6, x7)
-
-inst_767:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01b6ea1db6961 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1b6ea1db6961; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:1488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1488*FLEN/8, x10, x6, x7)
-
-inst_768:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01b6ea1db6961 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x1b6ea1db6961;
-valaddr_reg:x9; val_offset:1490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1490*FLEN/8, x10, x6, x7)
-
-inst_769:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01b6ea1db6961 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1b6ea1db6961; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1492*FLEN/8, x10, x6, x7)
-
-inst_770:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01b6ea1db6961 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x1b6ea1db6961;
-valaddr_reg:x9; val_offset:1494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1494*FLEN/8, x10, x6, x7)
-
-inst_771:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1496*FLEN/8, x10, x6, x7)
-
-inst_772:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1498*FLEN/8, x10, x6, x7)
-
-inst_773:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x0;
-valaddr_reg:x9; val_offset:1500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1500*FLEN/8, x10, x6, x7)
-
-inst_774:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x7d7db8b6fc61f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff7d7db8b6fc61f; op2val:0x0;
-valaddr_reg:x9; val_offset:1502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1502*FLEN/8, x10, x6, x7)
-
-inst_775:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x7d7db8b6fc61f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff7d7db8b6fc61f;
-valaddr_reg:x9; val_offset:1504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1504*FLEN/8, x10, x6, x7)
-
-inst_776:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x7d7db8b6fc61f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x3ff7d7db8b6fc61f;
-valaddr_reg:x9; val_offset:1506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1506*FLEN/8, x10, x6, x7)
-
-inst_777:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1508*FLEN/8, x10, x6, x7)
-
-inst_778:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1510*FLEN/8, x10, x6, x7)
-
-inst_779:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x705262580c704 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7fe705262580c704;
-valaddr_reg:x9; val_offset:1512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1512*FLEN/8, x10, x6, x7)
-
-inst_780:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1514*FLEN/8, x10, x6, x7)
-
-inst_781:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1516*FLEN/8, x10, x6, x7)
-
-inst_782:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1518*FLEN/8, x10, x6, x7)
-
-inst_783:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1520*FLEN/8, x10, x6, x7)
-
-inst_784:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1522*FLEN/8, x10, x6, x7)
-
-inst_785:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1524*FLEN/8, x10, x6, x7)
-
-inst_786:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1526*FLEN/8, x10, x6, x7)
-
-inst_787:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x26a84eacd6c03 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7fb26a84eacd6c03;
-valaddr_reg:x9; val_offset:1528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1528*FLEN/8, x10, x6, x7)
-
-inst_788:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1530*FLEN/8, x10, x6, x7)
-
-inst_789:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1532*FLEN/8, x10, x6, x7)
-
-inst_790:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1534*FLEN/8, x10, x6, x7)
-
-inst_791:// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xd773b1148acd1 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f7d773b1148acd1; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1536*FLEN/8, x10, x6, x7)
-
-inst_792:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xd773b1148acd1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7f7d773b1148acd1;
-valaddr_reg:x9; val_offset:1538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1538*FLEN/8, x10, x6, x7)
-
-inst_793:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1540*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_6)
-
-inst_794:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1542*FLEN/8, x10, x6, x7)
-
-inst_795:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1544*FLEN/8, x10, x6, x7)
-
-inst_796:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1546*FLEN/8, x10, x6, x7)
-
-inst_797:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1548*FLEN/8, x10, x6, x7)
-
-inst_798:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1550*FLEN/8, x10, x6, x7)
-
-inst_799:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1552*FLEN/8, x10, x6, x7)
-
-inst_800:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1554*FLEN/8, x10, x6, x7)
-
-inst_801:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1556*FLEN/8, x10, x6, x7)
-
-inst_802:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0ee0fa88947a1 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xee0fa88947a1; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1558*FLEN/8, x10, x6, x7)
-
-inst_803:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0ee0fa88947a1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xee0fa88947a1;
-valaddr_reg:x9; val_offset:1560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1560*FLEN/8, x10, x6, x7)
-
-inst_804:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1562*FLEN/8, x10, x6, x7)
-
-inst_805:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1564*FLEN/8, x10, x6, x7)
-
-inst_806:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1566*FLEN/8, x10, x6, x7)
-
-inst_807:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0ee0fa88947a1 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xee0fa88947a1; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1568*FLEN/8, x10, x6, x7)
-
-inst_808:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0ee0fa88947a1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0xee0fa88947a1;
-valaddr_reg:x9; val_offset:1570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1570*FLEN/8, x10, x6, x7)
-
-inst_809:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0ee0fa88947a1 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xee0fa88947a1; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1572*FLEN/8, x10, x6, x7)
-
-inst_810:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1574*FLEN/8, x10, x6, x7)
-
-inst_811:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1576*FLEN/8, x10, x6, x7)
-
-inst_812:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1578*FLEN/8, x10, x6, x7)
-
-inst_813:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1580*FLEN/8, x10, x6, x7)
-
-inst_814:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1582*FLEN/8, x10, x6, x7)
-
-inst_815:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1584*FLEN/8, x10, x6, x7)
-
-inst_816:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1586*FLEN/8, x10, x6, x7)
-
-inst_817:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x017ce5da753f7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x17ce5da753f7; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:1588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1588*FLEN/8, x10, x6, x7)
-
-inst_818:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x017ce5da753f7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x17ce5da753f7;
-valaddr_reg:x9; val_offset:1590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1590*FLEN/8, x10, x6, x7)
-
-inst_819:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x017ce5da753f7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x17ce5da753f7; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1592*FLEN/8, x10, x6, x7)
-
-inst_820:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x017ce5da753f7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x17ce5da753f7;
-valaddr_reg:x9; val_offset:1594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1594*FLEN/8, x10, x6, x7)
-
-inst_821:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1596*FLEN/8, x10, x6, x7)
-
-inst_822:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1598*FLEN/8, x10, x6, x7)
-
-inst_823:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x0;
-valaddr_reg:x9; val_offset:1600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1600*FLEN/8, x10, x6, x7)
-
-inst_824:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x4b1096905e83e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff4b1096905e83e; op2val:0x0;
-valaddr_reg:x9; val_offset:1602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1602*FLEN/8, x10, x6, x7)
-
-inst_825:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x4b1096905e83e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff4b1096905e83e;
-valaddr_reg:x9; val_offset:1604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1604*FLEN/8, x10, x6, x7)
-
-inst_826:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x4b1096905e83e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x3ff4b1096905e83e;
-valaddr_reg:x9; val_offset:1606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1606*FLEN/8, x10, x6, x7)
-
-inst_827:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1608*FLEN/8, x10, x6, x7)
-
-inst_828:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1610*FLEN/8, x10, x6, x7)
-
-inst_829:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xca304f80cbc99 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7feca304f80cbc99;
-valaddr_reg:x9; val_offset:1612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1612*FLEN/8, x10, x6, x7)
-
-inst_830:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1614*FLEN/8, x10, x6, x7)
-
-inst_831:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1616*FLEN/8, x10, x6, x7)
-
-inst_832:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1618*FLEN/8, x10, x6, x7)
-
-inst_833:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1620*FLEN/8, x10, x6, x7)
-
-inst_834:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1622*FLEN/8, x10, x6, x7)
-
-inst_835:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1624*FLEN/8, x10, x6, x7)
-
-inst_836:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1626*FLEN/8, x10, x6, x7)
-
-inst_837:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x6e8d0c67096e1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7fb6e8d0c67096e1;
-valaddr_reg:x9; val_offset:1628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1628*FLEN/8, x10, x6, x7)
-
-inst_838:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1630*FLEN/8, x10, x6, x7)
-
-inst_839:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1632*FLEN/8, x10, x6, x7)
-
-inst_840:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1634*FLEN/8, x10, x6, x7)
-
-inst_841:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x253da385a124e and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f8253da385a124e; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1636*FLEN/8, x10, x6, x7)
-
-inst_842:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x253da385a124e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7f8253da385a124e;
-valaddr_reg:x9; val_offset:1638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1638*FLEN/8, x10, x6, x7)
-
-inst_843:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1640*FLEN/8, x10, x6, x7)
-
-inst_844:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1642*FLEN/8, x10, x6, x7)
-
-inst_845:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1644*FLEN/8, x10, x6, x7)
-
-inst_846:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1646*FLEN/8, x10, x6, x7)
-
-inst_847:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1648*FLEN/8, x10, x6, x7)
-
-inst_848:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1650*FLEN/8, x10, x6, x7)
-
-inst_849:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1652*FLEN/8, x10, x6, x7)
-
-inst_850:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1654*FLEN/8, x10, x6, x7)
-
-inst_851:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1656*FLEN/8, x10, x6, x7)
-
-inst_852:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x128254fc5a4fe and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x128254fc5a4fe; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1658*FLEN/8, x10, x6, x7)
-
-inst_853:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x128254fc5a4fe and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x128254fc5a4fe;
-valaddr_reg:x9; val_offset:1660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1660*FLEN/8, x10, x6, x7)
-
-inst_854:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1662*FLEN/8, x10, x6, x7)
-
-inst_855:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x128254fc5a4fe and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x128254fc5a4fe; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1664*FLEN/8, x10, x6, x7)
-
-inst_856:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x128254fc5a4fe and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x128254fc5a4fe;
-valaddr_reg:x9; val_offset:1666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1666*FLEN/8, x10, x6, x7)
-
-inst_857:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x128254fc5a4fe and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x128254fc5a4fe; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1668*FLEN/8, x10, x6, x7)
-
-inst_858:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1670*FLEN/8, x10, x6, x7)
-
-inst_859:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1672*FLEN/8, x10, x6, x7)
-
-inst_860:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1674*FLEN/8, x10, x6, x7)
-
-inst_861:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1676*FLEN/8, x10, x6, x7)
-
-inst_862:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1678*FLEN/8, x10, x6, x7)
-
-inst_863:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1680*FLEN/8, x10, x6, x7)
-
-inst_864:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1682*FLEN/8, x10, x6, x7)
-
-inst_865:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01d9d54c6f6e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1d9d54c6f6e6; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:1684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1684*FLEN/8, x10, x6, x7)
-
-inst_866:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01d9d54c6f6e6 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x1d9d54c6f6e6;
-valaddr_reg:x9; val_offset:1686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1686*FLEN/8, x10, x6, x7)
-
-inst_867:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01d9d54c6f6e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1d9d54c6f6e6; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1688*FLEN/8, x10, x6, x7)
-
-inst_868:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01d9d54c6f6e6 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x1d9d54c6f6e6;
-valaddr_reg:x9; val_offset:1690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1690*FLEN/8, x10, x6, x7)
-
-inst_869:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1692*FLEN/8, x10, x6, x7)
-
-inst_870:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1694*FLEN/8, x10, x6, x7)
-
-inst_871:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x0;
-valaddr_reg:x9; val_offset:1696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1696*FLEN/8, x10, x6, x7)
-
-inst_872:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x9bd762d8a6627 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff9bd762d8a6627; op2val:0x0;
-valaddr_reg:x9; val_offset:1698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1698*FLEN/8, x10, x6, x7)
-
-inst_873:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x9bd762d8a6627 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff9bd762d8a6627;
-valaddr_reg:x9; val_offset:1700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1700*FLEN/8, x10, x6, x7)
-
-inst_874:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x9bd762d8a6627 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x3ff9bd762d8a6627;
-valaddr_reg:x9; val_offset:1702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1702*FLEN/8, x10, x6, x7)
-
-inst_875:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1704*FLEN/8, x10, x6, x7)
-
-inst_876:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1706*FLEN/8, x10, x6, x7)
-
-inst_877:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1708*FLEN/8, x10, x6, x7)
-
-inst_878:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1710*FLEN/8, x10, x6, x7)
-
-inst_879:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1712*FLEN/8, x10, x6, x7)
-
-inst_880:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1714*FLEN/8, x10, x6, x7)
-
-inst_881:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1716*FLEN/8, x10, x6, x7)
-
-inst_882:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x19e9f6802bcef and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7fe19e9f6802bcef;
-valaddr_reg:x9; val_offset:1718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1718*FLEN/8, x10, x6, x7)
-
-inst_883:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1720*FLEN/8, x10, x6, x7)
-
-inst_884:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1722*FLEN/8, x10, x6, x7)
-
-inst_885:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xc30ff0cd12e4b and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fac30ff0cd12e4b; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1724*FLEN/8, x10, x6, x7)
-
-inst_886:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xc30ff0cd12e4b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7fac30ff0cd12e4b;
-valaddr_reg:x9; val_offset:1726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1726*FLEN/8, x10, x6, x7)
-
-inst_887:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1728*FLEN/8, x10, x6, x7)
-
-inst_888:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1730*FLEN/8, x10, x6, x7)
-
-inst_889:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1732*FLEN/8, x10, x6, x7)
-
-inst_890:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1734*FLEN/8, x10, x6, x7)
-
-inst_891:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1736*FLEN/8, x10, x6, x7)
-
-inst_892:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1738*FLEN/8, x10, x6, x7)
-
-inst_893:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1740*FLEN/8, x10, x6, x7)
-
-inst_894:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1742*FLEN/8, x10, x6, x7)
-
-inst_895:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1744*FLEN/8, x10, x6, x7)
-
-inst_896:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1746*FLEN/8, x10, x6, x7)
-
-inst_897:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1748*FLEN/8, x10, x6, x7)
-
-inst_898:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1750*FLEN/8, x10, x6, x7)
-
-inst_899:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1752*FLEN/8, x10, x6, x7)
-
-inst_900:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1754*FLEN/8, x10, x6, x7)
-
-inst_901:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1756*FLEN/8, x10, x6, x7)
-
-inst_902:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x176d62053e9f2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x800176d62053e9f2;
-valaddr_reg:x9; val_offset:1758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1758*FLEN/8, x10, x6, x7)
-
-inst_903:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x176d62053e9f2 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800176d62053e9f2; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1760*FLEN/8, x10, x6, x7)
-
-inst_904:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1762*FLEN/8, x10, x6, x7)
-
-inst_905:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1764*FLEN/8, x10, x6, x7)
-
-inst_906:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x11b63268cb80c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x80011b63268cb80c;
-valaddr_reg:x9; val_offset:1766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1766*FLEN/8, x10, x6, x7)
-
-inst_907:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11b63268cb80c and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80011b63268cb80c; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1768*FLEN/8, x10, x6, x7)
-
-inst_908:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1770*FLEN/8, x10, x6, x7)
-
-inst_909:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1772*FLEN/8, x10, x6, x7)
-
-inst_910:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x158b9f3ccd07c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x800158b9f3ccd07c;
-valaddr_reg:x9; val_offset:1774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1774*FLEN/8, x10, x6, x7)
-
-inst_911:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x158b9f3ccd07c and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800158b9f3ccd07c; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1776*FLEN/8, x10, x6, x7)
-
-inst_912:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1778*FLEN/8, x10, x6, x7)
-
-inst_913:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1780*FLEN/8, x10, x6, x7)
-
-inst_914:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0b63657b34e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d430d1d19325 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb63657b34e4c; op2val:0x8000d430d1d19325;
-valaddr_reg:x9; val_offset:1782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1782*FLEN/8, x10, x6, x7)
-
-inst_915:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d430d1d19325 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0b63657b34e4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d430d1d19325; op2val:0xb63657b34e4c;
-valaddr_reg:x9; val_offset:1784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1784*FLEN/8, x10, x6, x7)
-
-inst_916:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0b63657b34e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb63657b34e4c; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1786*FLEN/8, x10, x6, x7)
-
-inst_917:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0b63657b34e4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xb63657b34e4c;
-valaddr_reg:x9; val_offset:1788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1788*FLEN/8, x10, x6, x7)
-
-inst_918:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1790*FLEN/8, x10, x6, x7)
-
-inst_919:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x12bba85050ee4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x80012bba85050ee4;
-valaddr_reg:x9; val_offset:1792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1792*FLEN/8, x10, x6, x7)
-
-inst_920:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12bba85050ee4 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80012bba85050ee4; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1794*FLEN/8, x10, x6, x7)
-
-inst_921:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1796*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_7)
-
-inst_922:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x0;
-valaddr_reg:x9; val_offset:1798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1798*FLEN/8, x10, x6, x7)
-
-inst_923:// fs1 == 0 and fe1 == 0x402 and fm1 == 0x3cbf277e6ba7f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x4023cbf277e6ba7f; op2val:0x0;
-valaddr_reg:x9; val_offset:1800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1800*FLEN/8, x10, x6, x7)
-
-inst_924:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x3cbf277e6ba7f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x4023cbf277e6ba7f;
-valaddr_reg:x9; val_offset:1802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1802*FLEN/8, x10, x6, x7)
-
-inst_925:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x3cbf277e6ba7f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x4023cbf277e6ba7f;
-valaddr_reg:x9; val_offset:1804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1804*FLEN/8, x10, x6, x7)
-
-inst_926:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1806*FLEN/8, x10, x6, x7)
-
-inst_927:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1808*FLEN/8, x10, x6, x7)
-
-inst_928:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1810*FLEN/8, x10, x6, x7)
-
-inst_929:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1812*FLEN/8, x10, x6, x7)
-
-inst_930:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1814*FLEN/8, x10, x6, x7)
-
-inst_931:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1816*FLEN/8, x10, x6, x7)
-
-inst_932:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1818*FLEN/8, x10, x6, x7)
-
-inst_933:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xcff30f3beb065 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xffbcff30f3beb065;
-valaddr_reg:x9; val_offset:1820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1820*FLEN/8, x10, x6, x7)
-
-inst_934:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1822*FLEN/8, x10, x6, x7)
-
-inst_935:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1824*FLEN/8, x10, x6, x7)
-
-inst_936:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x7328d8fcbc051 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff87328d8fcbc051; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1826*FLEN/8, x10, x6, x7)
-
-inst_937:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x7328d8fcbc051 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xff87328d8fcbc051;
-valaddr_reg:x9; val_offset:1828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1828*FLEN/8, x10, x6, x7)
-
-inst_938:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1830*FLEN/8, x10, x6, x7)
-
-inst_939:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1832*FLEN/8, x10, x6, x7)
-
-inst_940:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1834*FLEN/8, x10, x6, x7)
-
-inst_941:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1836*FLEN/8, x10, x6, x7)
-
-inst_942:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1838*FLEN/8, x10, x6, x7)
-
-inst_943:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1840*FLEN/8, x10, x6, x7)
-
-inst_944:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1842*FLEN/8, x10, x6, x7)
-
-inst_945:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1844*FLEN/8, x10, x6, x7)
-
-inst_946:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x176d62053e9f2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800176d62053e9f2; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1846*FLEN/8, x10, x6, x7)
-
-inst_947:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x176d62053e9f2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x800176d62053e9f2;
-valaddr_reg:x9; val_offset:1848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1848*FLEN/8, x10, x6, x7)
-
-inst_948:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1850*FLEN/8, x10, x6, x7)
-
-inst_949:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x176d62053e9f2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800176d62053e9f2; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1852*FLEN/8, x10, x6, x7)
-
-inst_950:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1854*FLEN/8, x10, x6, x7)
-
-inst_951:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1856*FLEN/8, x10, x6, x7)
-
-inst_952:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1858*FLEN/8, x10, x6, x7)
-
-inst_953:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1860*FLEN/8, x10, x6, x7)
-
-inst_954:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1862*FLEN/8, x10, x6, x7)
-
-inst_955:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0257bd0086432 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000257bd0086432; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:1864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1864*FLEN/8, x10, x6, x7)
-
-inst_956:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0257bd0086432 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x8000257bd0086432;
-valaddr_reg:x9; val_offset:1866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1866*FLEN/8, x10, x6, x7)
-
-inst_957:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0257bd0086432 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000257bd0086432; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1868*FLEN/8, x10, x6, x7)
-
-inst_958:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0257bd0086432 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x8000257bd0086432;
-valaddr_reg:x9; val_offset:1870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1870*FLEN/8, x10, x6, x7)
-
-inst_959:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1872*FLEN/8, x10, x6, x7)
-
-inst_960:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1874*FLEN/8, x10, x6, x7)
-
-inst_961:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x0;
-valaddr_reg:x9; val_offset:1876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1876*FLEN/8, x10, x6, x7)
-
-inst_962:// fs1 == 1 and fe1 == 0x400 and fm1 == 0x04a31976bdb6f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc0004a31976bdb6f; op2val:0x0;
-valaddr_reg:x9; val_offset:1878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1878*FLEN/8, x10, x6, x7)
-
-inst_963:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x04a31976bdb6f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc0004a31976bdb6f;
-valaddr_reg:x9; val_offset:1880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1880*FLEN/8, x10, x6, x7)
-
-inst_964:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x04a31976bdb6f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xc0004a31976bdb6f;
-valaddr_reg:x9; val_offset:1882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1882*FLEN/8, x10, x6, x7)
-
-inst_965:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1884*FLEN/8, x10, x6, x7)
-
-inst_966:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1886*FLEN/8, x10, x6, x7)
-
-inst_967:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb672fe8c6e870 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xffeb672fe8c6e870;
-valaddr_reg:x9; val_offset:1888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1888*FLEN/8, x10, x6, x7)
-
-inst_968:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1890*FLEN/8, x10, x6, x7)
-
-inst_969:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1892*FLEN/8, x10, x6, x7)
-
-inst_970:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1894*FLEN/8, x10, x6, x7)
-
-inst_971:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1896*FLEN/8, x10, x6, x7)
-
-inst_972:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1898*FLEN/8, x10, x6, x7)
-
-inst_973:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1900*FLEN/8, x10, x6, x7)
-
-inst_974:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1902*FLEN/8, x10, x6, x7)
-
-inst_975:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x5ec2653d2538d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xffb5ec2653d2538d;
-valaddr_reg:x9; val_offset:1904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1904*FLEN/8, x10, x6, x7)
-
-inst_976:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1906*FLEN/8, x10, x6, x7)
-
-inst_977:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1908*FLEN/8, x10, x6, x7)
-
-inst_978:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1910*FLEN/8, x10, x6, x7)
-
-inst_979:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x189b8430ea93d and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff8189b8430ea93d; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1912*FLEN/8, x10, x6, x7)
-
-inst_980:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x189b8430ea93d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xff8189b8430ea93d;
-valaddr_reg:x9; val_offset:1914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1914*FLEN/8, x10, x6, x7)
-
-inst_981:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1916*FLEN/8, x10, x6, x7)
-
-inst_982:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1918*FLEN/8, x10, x6, x7)
-
-inst_983:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1920*FLEN/8, x10, x6, x7)
-
-inst_984:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1922*FLEN/8, x10, x6, x7)
-
-inst_985:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1924*FLEN/8, x10, x6, x7)
-
-inst_986:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1926*FLEN/8, x10, x6, x7)
-
-inst_987:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1928*FLEN/8, x10, x6, x7)
-
-inst_988:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1930*FLEN/8, x10, x6, x7)
-
-inst_989:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1932*FLEN/8, x10, x6, x7)
-
-inst_990:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11b63268cb80c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80011b63268cb80c; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1934*FLEN/8, x10, x6, x7)
-
-inst_991:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x11b63268cb80c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x80011b63268cb80c;
-valaddr_reg:x9; val_offset:1936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1936*FLEN/8, x10, x6, x7)
-
-inst_992:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1938*FLEN/8, x10, x6, x7)
-
-inst_993:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11b63268cb80c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80011b63268cb80c; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1940*FLEN/8, x10, x6, x7)
-
-inst_994:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1942*FLEN/8, x10, x6, x7)
-
-inst_995:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1944*FLEN/8, x10, x6, x7)
-
-inst_996:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1946*FLEN/8, x10, x6, x7)
-
-inst_997:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01c56b70e1268 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001c56b70e1268; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:1948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1948*FLEN/8, x10, x6, x7)
-
-inst_998:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01c56b70e1268 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x80001c56b70e1268;
-valaddr_reg:x9; val_offset:1950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1950*FLEN/8, x10, x6, x7)
-
-inst_999:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01c56b70e1268 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001c56b70e1268; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1952*FLEN/8, x10, x6, x7)
-
-inst_1000:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01c56b70e1268 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x80001c56b70e1268;
-valaddr_reg:x9; val_offset:1954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1954*FLEN/8, x10, x6, x7)
-
-inst_1001:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1956*FLEN/8, x10, x6, x7)
-
-inst_1002:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1958*FLEN/8, x10, x6, x7)
-
-inst_1003:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x0;
-valaddr_reg:x9; val_offset:1960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1960*FLEN/8, x10, x6, x7)
-
-inst_1004:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8a193aec8d637 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbff8a193aec8d637; op2val:0x0;
-valaddr_reg:x9; val_offset:1962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1962*FLEN/8, x10, x6, x7)
-
-inst_1005:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x8a193aec8d637 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbff8a193aec8d637;
-valaddr_reg:x9; val_offset:1964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1964*FLEN/8, x10, x6, x7)
-
-inst_1006:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x8a193aec8d637 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xbff8a193aec8d637;
-valaddr_reg:x9; val_offset:1966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1966*FLEN/8, x10, x6, x7)
-
-inst_1007:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1968*FLEN/8, x10, x6, x7)
-
-inst_1008:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1970*FLEN/8, x10, x6, x7)
-
-inst_1009:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1972*FLEN/8, x10, x6, x7)
-
-inst_1010:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1974*FLEN/8, x10, x6, x7)
-
-inst_1011:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1976*FLEN/8, x10, x6, x7)
-
-inst_1012:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1978*FLEN/8, x10, x6, x7)
-
-inst_1013:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1980*FLEN/8, x10, x6, x7)
-
-inst_1014:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xaaae5b42b9d01 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xffbaaae5b42b9d01;
-valaddr_reg:x9; val_offset:1982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1982*FLEN/8, x10, x6, x7)
-
-inst_1015:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1984*FLEN/8, x10, x6, x7)
-
-inst_1016:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1986*FLEN/8, x10, x6, x7)
-
-inst_1017:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x555849022e400 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff8555849022e400; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1988*FLEN/8, x10, x6, x7)
-
-inst_1018:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x555849022e400 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xff8555849022e400;
-valaddr_reg:x9; val_offset:1990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1990*FLEN/8, x10, x6, x7)
-
-inst_1019:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1992*FLEN/8, x10, x6, x7)
-
-inst_1020:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1994*FLEN/8, x10, x6, x7)
-
-inst_1021:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1996*FLEN/8, x10, x6, x7)
-
-inst_1022:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1998*FLEN/8, x10, x6, x7)
-
-inst_1023:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:2000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2000*FLEN/8, x10, x6, x7)
-
-inst_1024:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:2002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2002*FLEN/8, x10, x6, x7)
-
-inst_1025:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:2004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2004*FLEN/8, x10, x6, x7)
-
-inst_1026:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:2006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2006*FLEN/8, x10, x6, x7)
-
-inst_1027:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x158b9f3ccd07c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800158b9f3ccd07c; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:2008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2008*FLEN/8, x10, x6, x7)
-
-inst_1028:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x158b9f3ccd07c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x800158b9f3ccd07c;
-valaddr_reg:x9; val_offset:2010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2010*FLEN/8, x10, x6, x7)
-
-inst_1029:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:2012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2012*FLEN/8, x10, x6, x7)
-
-inst_1030:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x158b9f3ccd07c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800158b9f3ccd07c; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:2014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2014*FLEN/8, x10, x6, x7)
-
-inst_1031:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:2016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2016*FLEN/8, x10, x6, x7)
-
-inst_1032:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x02278fec7ae73 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80002278fec7ae73; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:2018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2018*FLEN/8, x10, x6, x7)
-
-inst_1033:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x02278fec7ae73 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x80002278fec7ae73;
-valaddr_reg:x9; val_offset:2020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2020*FLEN/8, x10, x6, x7)
-
-inst_1034:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x02278fec7ae73 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80002278fec7ae73; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:2022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2022*FLEN/8, x10, x6, x7)
-
-inst_1035:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x02278fec7ae73 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x80002278fec7ae73;
-valaddr_reg:x9; val_offset:2024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2024*FLEN/8, x10, x6, x7)
-
-inst_1036:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:2026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2026*FLEN/8, x10, x6, x7)
-
-inst_1037:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:2028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2028*FLEN/8, x10, x6, x7)
-
-inst_1038:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x0;
-valaddr_reg:x9; val_offset:2030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2030*FLEN/8, x10, x6, x7)
-
-inst_1039:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xdf66a9ea7fbe7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbffdf66a9ea7fbe7; op2val:0x0;
-valaddr_reg:x9; val_offset:2032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2032*FLEN/8, x10, x6, x7)
-
-inst_1040:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xdf66a9ea7fbe7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbffdf66a9ea7fbe7;
-valaddr_reg:x9; val_offset:2034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2034*FLEN/8, x10, x6, x7)
-
-inst_1041:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xdf66a9ea7fbe7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xbffdf66a9ea7fbe7;
-valaddr_reg:x9; val_offset:2036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2036*FLEN/8, x10, x6, x7)
-
-inst_1042:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:2038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2038*FLEN/8, x10, x6, x7)
-
-inst_1043:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:2040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2040*FLEN/8, x10, x6, x7)
-
-inst_1044:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x484bb4eb5b9d5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xffe484bb4eb5b9d5;
-valaddr_reg:x9; val_offset:2042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2042*FLEN/8, x10, x6, x7)
-
-inst_1045:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:2044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2044*FLEN/8, x10, x6, x7)
-
-inst_1046:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:2046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2046*FLEN/8, x10, x6, x7)
-
-inst_1047:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:2048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2048*FLEN/8, x10, x6, x7)
-
-inst_1048:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:2050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2050*FLEN/8, x10, x6, x7)
-
-inst_1049:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:2052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2052*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_8)
-
-inst_1050:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:2054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2054*FLEN/8, x10, x6, x7)
-
-inst_1051:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:2056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2056*FLEN/8, x10, x6, x7)
-
-inst_1052:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x06a2f722afb11 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xffb06a2f722afb11;
-valaddr_reg:x9; val_offset:2058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2058*FLEN/8, x10, x6, x7)
-
-inst_1053:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:2060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2060*FLEN/8, x10, x6, x7)
-
-inst_1054:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:2062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2062*FLEN/8, x10, x6, x7)
-
-inst_1055:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:2064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2064*FLEN/8, x10, x6, x7)
-
-inst_1056:// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0xa437f1d1191b5 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff7a437f1d1191b5; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:2066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2066*FLEN/8, x10, x6, x7)
-
-inst_1057:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0xa437f1d1191b5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xff7a437f1d1191b5;
-valaddr_reg:x9; val_offset:2068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2068*FLEN/8, x10, x6, x7)
-
-inst_1058:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:2070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2070*FLEN/8, x10, x6, x7)
-
-inst_1059:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:2072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2072*FLEN/8, x10, x6, x7)
-
-inst_1060:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:2074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2074*FLEN/8, x10, x6, x7)
-
-inst_1061:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:2076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2076*FLEN/8, x10, x6, x7)
-
-inst_1062:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:2078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2078*FLEN/8, x10, x6, x7)
-
-inst_1063:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:2080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2080*FLEN/8, x10, x6, x7)
-
-inst_1064:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:2082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2082*FLEN/8, x10, x6, x7)
-
-inst_1065:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:2084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2084*FLEN/8, x10, x6, x7)
-
-inst_1066:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:2086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2086*FLEN/8, x10, x6, x7)
-
-inst_1067:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d430d1d19325 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d430d1d19325; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:2088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2088*FLEN/8, x10, x6, x7)
-
-inst_1068:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d430d1d19325 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x8000d430d1d19325;
-valaddr_reg:x9; val_offset:2090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2090*FLEN/8, x10, x6, x7)
-
-inst_1069:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:2092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2092*FLEN/8, x10, x6, x7)
-
-inst_1070:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:2094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2094*FLEN/8, x10, x6, x7)
-
-inst_1071:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:2096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2096*FLEN/8, x10, x6, x7)
-
-inst_1072:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:2098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2098*FLEN/8, x10, x6, x7)
-
-inst_1073:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:2100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2100*FLEN/8, x10, x6, x7)
-
-inst_1074:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:2102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2102*FLEN/8, x10, x6, x7)
-
-inst_1075:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:2104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2104*FLEN/8, x10, x6, x7)
-
-inst_1076:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:2106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2106*FLEN/8, x10, x6, x7)
-
-inst_1077:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d430d1d19325 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d430d1d19325; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:2108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2108*FLEN/8, x10, x6, x7)
-
-inst_1078:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:2110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2110*FLEN/8, x10, x6, x7)
-
-inst_1079:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:2112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2112*FLEN/8, x10, x6, x7)
-
-inst_1080:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:2114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2114*FLEN/8, x10, x6, x7)
-
-inst_1081:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:2116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2116*FLEN/8, x10, x6, x7)
-
-inst_1082:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:2118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2118*FLEN/8, x10, x6, x7)
-
-inst_1083:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:2120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2120*FLEN/8, x10, x6, x7)
-
-inst_1084:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:2122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2122*FLEN/8, x10, x6, x7)
-
-inst_1085:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01df90d4d4e4a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x80001df90d4d4e4a;
-valaddr_reg:x9; val_offset:2124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2124*FLEN/8, x10, x6, x7)
-
-inst_1086:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01df90d4d4e4a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001df90d4d4e4a; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:2126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2126*FLEN/8, x10, x6, x7)
-
-inst_1087:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:2128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2128*FLEN/8, x10, x6, x7)
-
-inst_1088:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x0;
-valaddr_reg:x9; val_offset:2130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2130*FLEN/8, x10, x6, x7)
-
-inst_1089:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x271665b532bfd and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbff271665b532bfd; op2val:0x0;
-valaddr_reg:x9; val_offset:2132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2132*FLEN/8, x10, x6, x7)
-
-inst_1090:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x271665b532bfd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbff271665b532bfd;
-valaddr_reg:x9; val_offset:2134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2134*FLEN/8, x10, x6, x7)
-
-inst_1091:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x271665b532bfd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xbff271665b532bfd;
-valaddr_reg:x9; val_offset:2136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2136*FLEN/8, x10, x6, x7)
-
-inst_1092:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:2138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2138*FLEN/8, x10, x6, x7)
-
-inst_1093:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:2140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2140*FLEN/8, x10, x6, x7)
-
-inst_1094:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xcfbb63d922c8f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xffecfbb63d922c8f;
-valaddr_reg:x9; val_offset:2142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2142*FLEN/8, x10, x6, x7)
-
-inst_1095:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:2144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2144*FLEN/8, x10, x6, x7)
-
-inst_1096:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:2146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2146*FLEN/8, x10, x6, x7)
-
-inst_1097:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:2148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2148*FLEN/8, x10, x6, x7)
-
-inst_1098:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:2150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2150*FLEN/8, x10, x6, x7)
-
-inst_1099:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:2152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2152*FLEN/8, x10, x6, x7)
-
-inst_1100:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:2154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2154*FLEN/8, x10, x6, x7)
-
-inst_1101:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:2156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2156*FLEN/8, x10, x6, x7)
-
-inst_1102:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x72fc4fe0e8a0c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xffb72fc4fe0e8a0c;
-valaddr_reg:x9; val_offset:2158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2158*FLEN/8, x10, x6, x7)
-
-inst_1103:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:2160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2160*FLEN/8, x10, x6, x7)
-
-inst_1104:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:2162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2162*FLEN/8, x10, x6, x7)
-
-inst_1105:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:2164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2164*FLEN/8, x10, x6, x7)
-
-inst_1106:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x28c9d980ba1a3 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff828c9d980ba1a3; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:2166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2166*FLEN/8, x10, x6, x7)
-
-inst_1107:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x28c9d980ba1a3 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xff828c9d980ba1a3;
-valaddr_reg:x9; val_offset:2168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2168*FLEN/8, x10, x6, x7)
-
-inst_1108:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:2170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2170*FLEN/8, x10, x6, x7)
-
-inst_1109:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:2172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2172*FLEN/8, x10, x6, x7)
-
-inst_1110:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:2174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2174*FLEN/8, x10, x6, x7)
-
-inst_1111:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:2176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2176*FLEN/8, x10, x6, x7)
-
-inst_1112:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:2178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2178*FLEN/8, x10, x6, x7)
-
-inst_1113:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:2180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2180*FLEN/8, x10, x6, x7)
-
-inst_1114:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:2182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2182*FLEN/8, x10, x6, x7)
-
-inst_1115:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:2184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2184*FLEN/8, x10, x6, x7)
-
-inst_1116:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:2186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2186*FLEN/8, x10, x6, x7)
-
-inst_1117:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12bba85050ee4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80012bba85050ee4; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:2188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2188*FLEN/8, x10, x6, x7)
-
-inst_1118:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x12bba85050ee4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x80012bba85050ee4;
-valaddr_reg:x9; val_offset:2190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2190*FLEN/8, x10, x6, x7)
-
-inst_1119:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:2192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2192*FLEN/8, x10, x6, x7)
-
-inst_1120:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12bba85050ee4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80012bba85050ee4; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:2194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2194*FLEN/8, x10, x6, x7)
-
-inst_1121:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:2196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2196*FLEN/8, x10, x6, x7)
-
-inst_1122:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01df90d4d4e4a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001df90d4d4e4a; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:2198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2198*FLEN/8, x10, x6, x7)
-
-inst_1123:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01df90d4d4e4a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x80001df90d4d4e4a;
-valaddr_reg:x9; val_offset:2200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2200*FLEN/8, x10, x6, x7)
-
-inst_1124:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x0;
-valaddr_reg:x9; val_offset:2202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2202*FLEN/8, x10, x6, x7)
-
-inst_1125:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xa0d2ebbb9cec0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbffa0d2ebbb9cec0; op2val:0x0;
-valaddr_reg:x9; val_offset:2204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2204*FLEN/8, x10, x6, x7)
-
-inst_1126:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xa0d2ebbb9cec0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbffa0d2ebbb9cec0;
-valaddr_reg:x9; val_offset:2206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2206*FLEN/8, x10, x6, x7)
-
-inst_1127:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xa0d2ebbb9cec0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xbffa0d2ebbb9cec0;
-valaddr_reg:x9; val_offset:2208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2208*FLEN/8, x10, x6, x7)
-
-inst_1128:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:2210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2210*FLEN/8, x10, x6, x7)
-
-inst_1129:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x9; val_offset:2212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2212*FLEN/8, x10, x6, x7)
-
-inst_1130:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:2214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2214*FLEN/8, x10, x6, x7)
-
-inst_1131:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:2216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2216*FLEN/8, x10, x6, x7)
-
-inst_1132:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:2218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2218*FLEN/8, x10, x6, x7)
-
-inst_1133:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:2220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2220*FLEN/8, x10, x6, x7)
-
-inst_1134:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:2222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2222*FLEN/8, x10, x6, x7)
-
-inst_1135:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:2224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2224*FLEN/8, x10, x6, x7)
-
-inst_1136:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:2226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2226*FLEN/8, x10, x6, x7)
-
-inst_1137:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:2228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2228*FLEN/8, x10, x6, x7)
-
-inst_1138:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:2230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2230*FLEN/8, x10, x6, x7)
-
-inst_1139:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:2232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2232*FLEN/8, x10, x6, x7)
-
-inst_1140:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:2234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2234*FLEN/8, x10, x6, x7)
-
-inst_1141:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:2236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2236*FLEN/8, x10, x6, x7)
-
-inst_1142:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:2238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2238*FLEN/8, x10, x6, x7)
-
-inst_1143:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:2240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2240*FLEN/8, x10, x6, x7)
-
-inst_1144:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:2242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2242*FLEN/8, x10, x6, x7)
-
-inst_1145:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:2244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2244*FLEN/8, x10, x6, x7)
-
-inst_1146:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:2246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2246*FLEN/8, x10, x6, x7)
-
-inst_1147:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:2248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2248*FLEN/8, x10, x6, x7)
-
-inst_1148:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:2250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2250*FLEN/8, x10, x6, x7)
-
-inst_1149:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:2252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2252*FLEN/8, x10, x6, x7)
-
-inst_1150:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xa86c4594097a9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x7fea86c4594097a9;
-valaddr_reg:x9; val_offset:2254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2254*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(9217386742845088832,64,FLEN)
-NAN_BOXED(9217386742845088832,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(9215319097810178018,64,FLEN)
-NAN_BOXED(9215319097810178018,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
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-NAN_BOXED(2003445158579959,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(9227493406996374393,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(9227493406996374393,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(9226487913246568569,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(9226487913246568569,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(9227162343446684891,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(9227162343446684891,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(9223404992362008138,64,FLEN)
-NAN_BOXED(9223404992362008138,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13831242090040994813,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13831242090040994813,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(13831242090040994813,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(18441391334310947983,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18441391334310947983,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9217386742845088832,64,FLEN)
-NAN_BOXED(18441391334310947983,64,FLEN)
-NAN_BOXED(9217386742845088832,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9215319097810178018,64,FLEN)
-NAN_BOXED(18441391334310947983,64,FLEN)
-NAN_BOXED(9215319097810178018,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9213115892871435995,64,FLEN)
-NAN_BOXED(18426248923532134924,64,FLEN)
-NAN_BOXED(9213115892871435995,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18426248923532134924,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9218412632170364254,64,FLEN)
-NAN_BOXED(18441391334310947983,64,FLEN)
-NAN_BOXED(9218412632170364254,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18422737727832790032,64,FLEN)
-NAN_BOXED(18411432835132662179,64,FLEN)
-NAN_BOXED(18422737727832790032,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18411432835132662179,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18433486017035452138,64,FLEN)
-NAN_BOXED(18426248923532134924,64,FLEN)
-NAN_BOXED(18433486017035452138,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18435812905463501022,64,FLEN)
-NAN_BOXED(18426248923532134924,64,FLEN)
-NAN_BOXED(18435812905463501022,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18438695854564510432,64,FLEN)
-NAN_BOXED(18441391334310947983,64,FLEN)
-NAN_BOXED(18438695854564510432,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18436941051517446552,64,FLEN)
-NAN_BOXED(18426248923532134924,64,FLEN)
-NAN_BOXED(18436941051517446552,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(254684718621748,64,FLEN)
-NAN_BOXED(9223701591927099108,64,FLEN)
-NAN_BOXED(254684718621748,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9223701591927099108,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(2003445158579959,64,FLEN)
-NAN_BOXED(9223701591927099108,64,FLEN)
-NAN_BOXED(2003445158579959,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(9223404992362008138,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9223404992362008138,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13833383699791072960,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13833383699791072960,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(13833383699791072960,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9217386742845088832,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9215319097810178018,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9213115892871435995,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9218412632170364254,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18422737727832790032,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18433486017035452138,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18435812905463501022,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18438695854564510432,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18436941051517446552,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(254684718621748,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(3016197586364871,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2617510194891852,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(3256156939645418,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2003445158579959,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9227493406996374393,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9226487913246568569,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9227162343446684891,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(3478598971078098,64,FLEN)
-NAN_BOXED(9217327765236258729,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_7:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_8:
-    .fill 202*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fltq_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fltq_b1-01.S
deleted file mode 100644
index 1188a705f..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fltq_b1-01.S
+++ /dev/null
@@ -1,368 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:16:00 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fltq.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fltq.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fltq_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f29; op2:f29; dest:x30; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f30; op2:f31; dest:x29; op1val:0x0; op2val:0x1;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f28; op2:f27; dest:x28; op1val:0x0; op2val:0x80000001;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f27; op2:f28; dest:x27; op1val:0x0; op2val:0x2;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f26; op2:f25; dest:x26; op1val:0x0; op2val:0x807ffffe;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f25; op2:f26; dest:x25; op1val:0x0; op2val:0x7fffff;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f24; op2:f23; dest:x24; op1val:0x0; op2val:0x807fffff;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f23; op2:f24; dest:x23; op1val:0x0; op2val:0x800000;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f22; op2:f21; dest:x22; op1val:0x0; op2val:0x80800000;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f21; op2:f22; dest:x21; op1val:0x0; op2val:0x800001;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f20; op2:f19; dest:x20; op1val:0x0; op2val:0x80855555;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f19; op2:f20; dest:x19; op1val:0x0; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f18; op2:f17; dest:x18; op1val:0x0; op2val:0xff7fffff;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f17; op2:f18; dest:x17; op1val:0x0; op2val:0x7f800000;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f16; op2:f15; dest:x16; op1val:0x0; op2val:0xff800000;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f15; op2:f16; dest:x15; op1val:0x0; op2val:0x7fc00000;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f14; op2:f13; dest:x14; op1val:0x0; op2val:0xffc00000;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f13; op2:f14; dest:x13; op1val:0x0; op2val:0x7fc00001;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f12; op2:f11; dest:x12; op1val:0x0; op2val:0xffc55555;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f11; op2:f12; dest:x11; op1val:0x0; op2val:0x7f800001;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f10; op2:f9; dest:x10; op1val:0x0; op2val:0xffaaaaaa;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f9; op2:f10; dest:x9; op1val:0x0; op2val:0x3f800000;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f8; op2:f7; dest:x8; op1val:0x0; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f7; op2:f8; dest:x7; op1val:0x80000000; op2val:0x0;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f6; op2:f5; dest:x6; op1val:0x80000000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f5; op2:f6; dest:x5; op1val:0x80000000; op2val:0x1;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f4; op2:f3; dest:x4; op1val:0x80000000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f3; op2:f4; dest:x3; op1val:0x80000000; op2val:0x2;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f2; op2:f1; dest:x2; op1val:0x80000000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f1; op2:f2; dest:x1; op1val:0x80000000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f0; op2:f31; dest:x31; op1val:0x80000000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f31; op2:f0; dest:x31; op1val:0x80000000; op2val:0x800000;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x0; op1val:0x80000000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-test_dataset_1:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 16*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fltq_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fltq_b19-01.S
deleted file mode 100644
index e96daa841..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fltq_b19-01.S
+++ /dev/null
@@ -1,368 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:16:00 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fltq.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fltq.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fltq_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f29; op2:f29; dest:x30; op1val:0x7f378efe; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f30; op2:f31; dest:x29; op1val:0x7f206a70; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f28; op2:f27; dest:x28; op1val:0x7f378efe; op2val:0x7ee8aebb;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f27; op2:f28; dest:x27; op1val:0x7ee8aebb; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f26; op2:f25; dest:x26; op1val:0x7f378efe; op2val:0x7ea5608b;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f25; op2:f26; dest:x25; op1val:0x7ea5608b; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f24; op2:f23; dest:x24; op1val:0x7f378efe; op2val:0x7f3648af;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f23; op2:f24; dest:x23; op1val:0x7f3648af; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f22; op2:f21; dest:x22; op1val:0x7f378efe; op2val:0xfd204621;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f21; op2:f22; dest:x21; op1val:0x7d92d8cb; op2val:0xfec857aa;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfb and fm2 == 0x12d8cb and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f20; op2:f19; dest:x20; op1val:0xfec857aa; op2val:0x7d92d8cb;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f19; op2:f20; dest:x19; op1val:0x7d92d8cb; op2val:0xfd204621;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfb and fm2 == 0x12d8cb and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f18; op2:f17; dest:x18; op1val:0x7f378efe; op2val:0x7d92d8cb;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f17; op2:f18; dest:x17; op1val:0x7f378efe; op2val:0xfe4ac669;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f16; op2:f15; dest:x16; op1val:0x7d92d8cb; op2val:0xff7fffff;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x12d8cb and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f15; op2:f16; dest:x15; op1val:0xff7fffff; op2val:0x7d92d8cb;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f14; op2:f13; dest:x14; op1val:0x7d92d8cb; op2val:0xfe4ac669;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f13; op2:f14; dest:x13; op1val:0x7f378efe; op2val:0xfe96fcf5;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f12; op2:f11; dest:x12; op1val:0xfe96fcf5; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f11; op2:f12; dest:x11; op1val:0x7f378efe; op2val:0xfee8e23e;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f10; op2:f9; dest:x10; op1val:0xfee8e23e; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f9; op2:f10; dest:x9; op1val:0x7f378efe; op2val:0xfeaf0937;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f8; op2:f7; dest:x8; op1val:0xfeaf0937; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f7; op2:f8; dest:x7; op1val:0x7f378efe; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a825 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f6; op2:f5; dest:x6; op1val:0x2a825; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a825 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f5; op2:f6; dest:x5; op1val:0x7f7a0dff; op2val:0x2a825;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a825 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f4; op2:f3; dest:x4; op1val:0x2a825; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a825 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f3; op2:f4; dest:x3; op1val:0x7f378efe; op2val:0x2a825;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f2; op2:f1; dest:x2; op1val:0x7f378efe; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f1; op2:f2; dest:x1; op1val:0x1a917b; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f0; op2:f31; dest:x31; op1val:0x7f7fffff; op2val:0x1a917b;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f31; op2:f0; dest:x31; op1val:0x1a917b; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x0; op1val:0x7f378efe; op2val:0x1a917b;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-test_dataset_1:
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(2138705407,32,FLEN)
-NAN_BOXED(2138705407,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 16*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmaxm.d_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmaxm.d_b1-01.S
deleted file mode 100644
index 42eb06f8c..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmaxm.d_b1-01.S
+++ /dev/null
@@ -1,5889 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:07:25 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmaxm.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmaxm.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fmaxm.d_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmaxm.d_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rd != rs2, rs1==f31, rs2==f30, rd==f31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f31; op2:f30; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:0*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rs2 == rd, rs1==f29, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f29; op2:f29; dest:f29; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:2*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f29, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs2 == rd != rs1, rs1==f30, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f28; dest:f28; op1val:0x0; op2val:0x1;
-   valaddr_reg:x3; val_offset:4*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f28, f30, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f28, rs2==f31, rd==f30,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f28; op2:f31; dest:f30; op1val:0x0; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:6*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f30, f28, f31, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f26; op2:f26; dest:f27; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:8*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f27, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f27; op2:f25; dest:f26; op1val:0x0; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:10*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f26, f27, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f24; op2:f27; dest:f25; op1val:0x0; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f25, f24, f27, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f25; op2:f23; dest:f24; op1val:0x0; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:14*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f24, f25, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f22; op2:f24; dest:f23; op1val:0x0; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:16*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f23, f22, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f23; op2:f21; dest:f22; op1val:0x0; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:18*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f22, f23, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:20*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f21; op2:f19; dest:f20; op1val:0x0; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:22*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f20, f21, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f18; op2:f20; dest:f19; op1val:0x0; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:24*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f19; op2:f17; dest:f18; op1val:0x0; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f18, f19, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f16; op2:f18; dest:f17; op1val:0x0; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:28*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f17, f16, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f17; op2:f15; dest:f16; op1val:0x0; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:30*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f16, f17, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:32*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f15; op2:f13; dest:f14; op1val:0x0; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:34*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f14, f15, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f12; op2:f14; dest:f13; op1val:0x0; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:36*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f13; op2:f11; dest:f12; op1val:0x0; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:38*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f12, f13, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f10; op2:f12; dest:f11; op1val:0x0; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:40*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f11, f10, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f11; op2:f9; dest:f10; op1val:0x0; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:42*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f10, f11, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:44*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f9; op2:f7; dest:f8; op1val:0x0; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:46*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f8, f9, f7, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f6; op2:f8; dest:f7; op1val:0x8000000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:48*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f7, rs2==f5, rd==f6,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f7; op2:f5; dest:f6; op1val:0x8000000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:50*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f6, f7, f5, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f4; op2:f6; dest:f5; op1val:0x8000000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:52*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f5, f4, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f5, rs2==f3, rd==f4,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f5; op2:f3; dest:f4; op1val:0x8000000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:54*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f4, f5, f3, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f2; op2:f4; dest:f3; op1val:0x8000000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:56*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f3, rs2==f1, rd==f2,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f3; op2:f1; dest:f2; op1val:0x8000000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:58*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f2, f3, f1, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f0; op2:f2; dest:f1; op1val:0x8000000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:60*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f1,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f1; op2:f30; dest:f31; op1val:0x8000000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:62*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f1, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f0; dest:f31; op1val:0x8000000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:64*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f0, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rd==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f31; op2:f30; dest:f0; op1val:0x8000000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:66*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:68*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:70*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:72*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:74*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:76*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:78*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:80*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:82*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:84*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:86*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:88*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:90*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:92*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:94*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x0;
-   valaddr_reg:x3; val_offset:96*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:98*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x1;
-   valaddr_reg:x3; val_offset:100*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:102*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x2;
-   valaddr_reg:x3; val_offset:104*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:106*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:108*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:110*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:112*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:114*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:116*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:118*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:120*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:122*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:124*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:126*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:128*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:130*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:132*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:134*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:136*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:138*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:140*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:142*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:144*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:146*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:148*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:150*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:152*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:154*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:156*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:158*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:160*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:162*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:164*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:166*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:168*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:170*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:172*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:174*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:176*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:178*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:180*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:182*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:184*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:186*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:188*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:190*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x0;
-   valaddr_reg:x3; val_offset:192*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:194*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x1;
-   valaddr_reg:x3; val_offset:196*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:198*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x2;
-   valaddr_reg:x3; val_offset:200*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:202*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:204*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:206*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:208*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:210*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:212*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:214*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:216*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:218*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:220*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:222*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:224*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:226*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:228*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:230*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:232*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:234*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:236*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:238*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x0;
-   valaddr_reg:x3; val_offset:240*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:242*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x1;
-   valaddr_reg:x3; val_offset:244*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:246*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x2;
-   valaddr_reg:x3; val_offset:248*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:250*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:252*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:254*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:256*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:258*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:260*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:262*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:264*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:266*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:268*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:270*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:272*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:274*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:276*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:278*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:280*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:282*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:284*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:286*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:288*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:290*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:292*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:294*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:296*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:298*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:300*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:302*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:304*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:306*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:308*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:310*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:312*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:314*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:316*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:318*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:320*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:322*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:324*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:326*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:328*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:330*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:332*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:334*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:336*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:338*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:340*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:342*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:344*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:346*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:348*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:350*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:352*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:354*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:356*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:358*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:360*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:362*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:364*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:366*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:368*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:370*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:372*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:374*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:376*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:378*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:380*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:382*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:384*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:386*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:388*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:390*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:392*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:394*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:396*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:398*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:400*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:402*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:404*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:406*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:408*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:410*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:412*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:414*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:416*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:418*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:420*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:422*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:424*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:426*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:428*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:430*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:432*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:434*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:436*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:438*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:440*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:442*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:444*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:446*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:448*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:450*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:452*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:454*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:456*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:458*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:460*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:462*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:464*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:466*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:468*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:470*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:472*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:474*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:476*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:478*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x0;
-   valaddr_reg:x3; val_offset:480*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:482*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x1;
-   valaddr_reg:x3; val_offset:484*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:486*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x2;
-   valaddr_reg:x3; val_offset:488*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:490*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:492*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:494*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:496*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:498*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:500*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:502*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:504*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:506*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:508*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:510*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:512*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:514*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:516*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:518*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:520*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:522*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:524*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:526*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x0;
-   valaddr_reg:x3; val_offset:528*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:530*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x1;
-   valaddr_reg:x3; val_offset:532*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:534*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x2;
-   valaddr_reg:x3; val_offset:536*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:538*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:540*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:542*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:544*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:546*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:548*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:550*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:552*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:554*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:556*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:558*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:560*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:562*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:564*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:566*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:568*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:570*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:572*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:574*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:576*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:578*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:580*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:582*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:584*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:586*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:588*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:590*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:592*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:594*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:596*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:598*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:600*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:602*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:604*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:606*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:608*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:610*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:612*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:614*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:616*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:618*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:620*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:622*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:624*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:626*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:628*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:630*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:632*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:634*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:636*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:638*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:640*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:642*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:644*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:646*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:648*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:650*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:652*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:654*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:656*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:658*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:660*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:662*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:664*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:666*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:668*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:670*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:672*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:674*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:676*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:678*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:680*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:682*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:684*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:686*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:688*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:690*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:692*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:694*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:696*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:698*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:700*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:702*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:704*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:706*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:708*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:710*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:712*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:714*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:716*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:718*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:720*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:722*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:724*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:726*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:728*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:730*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:732*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:734*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:736*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:738*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:740*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:742*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:744*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:746*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:748*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:750*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:752*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:754*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:756*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:758*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:760*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:762*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:764*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:766*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:768*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:770*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:772*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:774*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:776*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:778*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:780*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:782*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:784*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:786*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:788*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:790*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:792*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:794*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:796*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:798*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:800*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:802*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:804*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:806*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:808*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:810*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:812*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:814*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:816*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:818*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:820*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:822*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:824*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:826*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:828*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:830*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:832*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:834*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:836*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:838*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:840*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:842*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:844*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:846*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:848*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:850*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:852*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:854*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:856*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:858*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:860*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:862*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:864*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:866*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:868*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:870*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:872*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:874*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:876*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:878*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:880*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:882*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:884*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:886*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:888*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:890*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:892*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:894*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:896*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:898*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:900*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:902*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:904*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:906*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:908*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:910*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:912*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:914*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:916*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:918*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:920*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:922*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:924*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:926*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:928*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:930*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:932*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:934*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:936*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:938*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:940*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:942*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:944*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:946*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:948*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:950*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:952*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:954*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:956*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:958*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:960*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:962*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:964*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:966*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:968*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:970*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:972*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:974*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:976*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:978*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:980*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:982*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:984*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:986*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:988*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:990*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:992*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:994*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:996*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:998*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1000*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1002*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1004*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1006*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:1008*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:1010*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:1012*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:1014*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:1016*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:1018*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:1020*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:1022*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:1024*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:1026*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:1028*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:1030*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:1032*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:1034*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1036*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1038*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:1040*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:1042*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:1044*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:1046*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1048*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1050*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1052*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1054*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1056*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:1058*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1060*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:1062*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1064*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:1066*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:1068*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:1070*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:1072*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:1074*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:1076*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:1078*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:1080*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:1082*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1084*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1086*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:1088*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:1090*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:1092*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:1094*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1096*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1098*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1100*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1102*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1104*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:1106*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1108*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:1110*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1112*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:1114*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:1116*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:1118*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:1120*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:1122*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:1124*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:1126*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:1128*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:1130*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1132*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1134*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:1136*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:1138*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:1140*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:1142*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1144*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1146*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1148*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1150*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:1152*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x2;
-   valaddr_reg:x3; val_offset:1154*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
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-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 132*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmaxm.d_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmaxm.d_b19-01.S
deleted file mode 100644
index 507622676..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmaxm.d_b19-01.S
+++ /dev/null
@@ -1,11279 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:07:25 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmaxm.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmaxm.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fmaxm.d_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmaxm.d_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rd != rs2, rs1==f31, rs2==f30, rd==f31,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f31; op2:f30; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:0*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rs2 == rd, rs1==f29, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f29; op2:f29; dest:f29; op1val:0x7fc132d8f91b7583; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:2*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f29, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs2 == rd != rs1, rs1==f30, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f28; dest:f28; op1val:0x7fdfb5355e167379; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:4*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f28, f30, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f28, rs2==f31, rd==f30,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f28; op2:f31; dest:f30; op1val:0x7fc132d8f91b7583; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:6*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f30, f28, f31, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f26; op2:f26; dest:f27; op1val:0x7fb8072e8f9c858f; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:8*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f27, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f27; op2:f25; dest:f26; op1val:0x7fc132d8f91b7583; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:10*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f26, f27, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x383adc274749d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f24; op2:f27; dest:f25; op1val:0x7ff0000000000000; op2val:0x7fb383adc274749d;
-   valaddr_reg:x3; val_offset:12*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f25, f24, f27, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f25; op2:f23; dest:f24; op1val:0x7fb383adc274749d; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:14*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f24, f25, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f22; op2:f24; dest:f23; op1val:0x7ff0000000000000; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:16*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f23, f22, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f23; op2:f21; dest:f22; op1val:0x7fc132d8f91b7583; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:18*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f22, f23, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f20; op2:f22; dest:f21; op1val:0x7fc132d8f91b7583; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:20*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f21; op2:f19; dest:f20; op1val:0x7fcd481499755d4b; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:22*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f20, f21, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f18; op2:f20; dest:f19; op1val:0x7fc132d8f91b7583; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:24*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f19, rs2==f17, rd==f18,fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f19; op2:f17; dest:f18; op1val:0xffc3874a9329ec20; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:26*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f18, f19, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f16; op2:f18; dest:f17; op1val:0x7fc132d8f91b7583; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:28*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f17, f16, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f17, rs2==f15, rd==f16,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f17; op2:f15; dest:f16; op1val:0xffe19dc4ea1c6bbe; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:30*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f16, f17, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f14; op2:f16; dest:f15; op1val:0x7fc132d8f91b7583; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:32*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x8dfd26d2431d6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f15; op2:f13; dest:f14; op1val:0x7ff0000000000000; op2val:0xffb8dfd26d2431d6;
-   valaddr_reg:x3; val_offset:34*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f14, f15, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f12; op2:f14; dest:f13; op1val:0xffb8dfd26d2431d6; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:36*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f13; op2:f11; dest:f12; op1val:0x7ff0000000000000; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:38*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f12, f13, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f10; op2:f12; dest:f11; op1val:0x7fc132d8f91b7583; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:40*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f11, f10, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x98bcc3a92c611 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f11; op2:f9; dest:f10; op1val:0x7ff0000000000000; op2val:0xffb98bcc3a92c611;
-   valaddr_reg:x3; val_offset:42*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f10, f11, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f8; op2:f10; dest:f9; op1val:0xffb98bcc3a92c611; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:44*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f9; op2:f7; dest:f8; op1val:0x7ff0000000000000; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:46*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f8, f9, f7, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f6; op2:f8; dest:f7; op1val:0x7fc132d8f91b7583; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:48*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f7, rs2==f5, rd==f6,fs1 == 0 and fe1 == 0x7f8 and fm1 == 0xb848e5b5f226b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x1836cb3e931a8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f7; op2:f5; dest:f6; op1val:0x7f8b848e5b5f226b; op2val:0xffe1836cb3e931a8;
-   valaddr_reg:x3; val_offset:50*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f6, f7, f5, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0xb848e5b5f226b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f4; op2:f6; dest:f5; op1val:0xffe1836cb3e931a8; op2val:0x7f8b848e5b5f226b;
-   valaddr_reg:x3; val_offset:52*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f5, f4, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f5, rs2==f3, rd==f4,fs1 == 0 and fe1 == 0x7f8 and fm1 == 0xb848e5b5f226b and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f5; op2:f3; dest:f4; op1val:0x7f8b848e5b5f226b; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:54*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f4, f5, f3, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0xb848e5b5f226b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f2; op2:f4; dest:f3; op1val:0x7fc132d8f91b7583; op2val:0x7f8b848e5b5f226b;
-   valaddr_reg:x3; val_offset:56*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f3, rs2==f1, rd==f2,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f3; op2:f1; dest:f2; op1val:0x7fc132d8f91b7583; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:58*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f2, f3, f1, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x833777722304f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f0; op2:f2; dest:f1; op1val:0x115e76ceed9d88; op2val:0x7fb833777722304f;
-   valaddr_reg:x3; val_offset:60*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f1,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f1; op2:f30; dest:f31; op1val:0x7fb833777722304f; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:62*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f1, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f0,fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f0; dest:f31; op1val:0x115e76ceed9d88; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:64*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f0, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rd==f0,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f31; op2:f30; dest:f0; op1val:0x7fc132d8f91b7583; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:66*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:68*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x4a57d3f9bbb84 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0x7fb4a57d3f9bbb84;
-   valaddr_reg:x3; val_offset:70*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:72*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:74*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:76*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xa7b6d804df453 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0x7fba7b6d804df453;
-   valaddr_reg:x3; val_offset:78*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:80*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:82*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:84*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1bca57b17c2f4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x1a406f11e5bc4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1bca57b17c2f4; op2val:0x7fe1a406f11e5bc4;
-   valaddr_reg:x3; val_offset:86*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1bca57b17c2f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x1bca57b17c2f4;
-   valaddr_reg:x3; val_offset:88*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1bca57b17c2f4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1bca57b17c2f4; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:90*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1bca57b17c2f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x1bca57b17c2f4;
-   valaddr_reg:x3; val_offset:92*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:94*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xc900ea9c600e8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0x7fbc900ea9c600e8;
-   valaddr_reg:x3; val_offset:96*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:98*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:100*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:102*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x79a9d1edd4c29 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0xffb79a9d1edd4c29;
-   valaddr_reg:x3; val_offset:104*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:106*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:108*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:110*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1bca57b17c2f4 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0bc8069a0dddf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1bca57b17c2f4; op2val:0xffd0bc8069a0dddf;
-   valaddr_reg:x3; val_offset:112*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1bca57b17c2f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x1bca57b17c2f4;
-   valaddr_reg:x3; val_offset:114*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1bca57b17c2f4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1bca57b17c2f4; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:116*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:118*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x1f930d5b2a8f5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0xffb1f930d5b2a8f5;
-   valaddr_reg:x3; val_offset:120*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:122*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:124*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:126*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1bca57b17c2f4 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x60eeb556ce9ce and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1bca57b17c2f4; op2val:0xffd60eeb556ce9ce;
-   valaddr_reg:x3; val_offset:128*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1bca57b17c2f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x1bca57b17c2f4;
-   valaddr_reg:x3; val_offset:130*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1bca57b17c2f4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1bca57b17c2f4; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:132*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:134*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xeb781eb40c69d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0xffbeb781eb40c69d;
-   valaddr_reg:x3; val_offset:136*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:138*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:140*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x0;
-   valaddr_reg:x3; val_offset:142*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 0 and fe1 == 0x400 and fm1 == 0x352db02b86485 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x400352db02b86485; op2val:0x0;
-   valaddr_reg:x3; val_offset:144*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x352db02b86485 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x400352db02b86485;
-   valaddr_reg:x3; val_offset:146*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x352db02b86485 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x400352db02b86485;
-   valaddr_reg:x3; val_offset:148*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:150*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:152*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:154*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:156*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:158*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:160*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:162*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:164*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:166*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:168*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:170*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:172*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:174*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:176*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0x95dc44b45292d and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x1836cb3e931a8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fa95dc44b45292d; op2val:0xffe1836cb3e931a8;
-   valaddr_reg:x3; val_offset:178*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0x95dc44b45292d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0x7fa95dc44b45292d;
-   valaddr_reg:x3; val_offset:180*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0x95dc44b45292d and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fa95dc44b45292d; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:182*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0x95dc44b45292d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x7fa95dc44b45292d;
-   valaddr_reg:x3; val_offset:184*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:186*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x833777722304f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0x7fb833777722304f;
-   valaddr_reg:x3; val_offset:188*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:190*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:192*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:194*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:196*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x4a57d3f9bbb84 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0x7fb4a57d3f9bbb84;
-   valaddr_reg:x3; val_offset:198*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:200*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:202*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:204*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xa7b6d804df453 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0x7fba7b6d804df453;
-   valaddr_reg:x3; val_offset:206*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:208*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:210*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:212*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6678633536e0f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x1a406f11e5bc4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6678633536e0f; op2val:0x7fe1a406f11e5bc4;
-   valaddr_reg:x3; val_offset:214*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6678633536e0f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x6678633536e0f;
-   valaddr_reg:x3; val_offset:216*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6678633536e0f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6678633536e0f; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:218*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6678633536e0f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x6678633536e0f;
-   valaddr_reg:x3; val_offset:220*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:222*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xc900ea9c600e8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0x7fbc900ea9c600e8;
-   valaddr_reg:x3; val_offset:224*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:226*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:228*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:230*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x79a9d1edd4c29 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0xffb79a9d1edd4c29;
-   valaddr_reg:x3; val_offset:232*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:234*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:236*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:238*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6678633536e0f and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0bc8069a0dddf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6678633536e0f; op2val:0xffd0bc8069a0dddf;
-   valaddr_reg:x3; val_offset:240*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6678633536e0f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x6678633536e0f;
-   valaddr_reg:x3; val_offset:242*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6678633536e0f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6678633536e0f; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:244*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:246*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x1f930d5b2a8f5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0xffb1f930d5b2a8f5;
-   valaddr_reg:x3; val_offset:248*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:250*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:252*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:254*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6678633536e0f and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x60eeb556ce9ce and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6678633536e0f; op2val:0xffd60eeb556ce9ce;
-   valaddr_reg:x3; val_offset:256*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6678633536e0f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x6678633536e0f;
-   valaddr_reg:x3; val_offset:258*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6678633536e0f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6678633536e0f; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:260*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:262*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xeb781eb40c69d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0xffbeb781eb40c69d;
-   valaddr_reg:x3; val_offset:264*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:266*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:268*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x0;
-   valaddr_reg:x3; val_offset:270*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 0 and fe1 == 0x402 and fm1 == 0x1d013feac5b5a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x4021d013feac5b5a; op2val:0x0;
-   valaddr_reg:x3; val_offset:272*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x1d013feac5b5a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x4021d013feac5b5a;
-   valaddr_reg:x3; val_offset:274*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x1d013feac5b5a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x4021d013feac5b5a;
-   valaddr_reg:x3; val_offset:276*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:278*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:280*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe08fa3383a6f3 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x383adc274749d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee08fa3383a6f3; op2val:0x7fb383adc274749d;
-   valaddr_reg:x3; val_offset:282*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe08fa3383a6f3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0x7fee08fa3383a6f3;
-   valaddr_reg:x3; val_offset:284*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe08fa3383a6f3 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee08fa3383a6f3; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:286*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe08fa3383a6f3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7fee08fa3383a6f3;
-   valaddr_reg:x3; val_offset:288*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:290*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:292*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:294*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:296*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:298*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:300*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:302*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe08fa3383a6f3 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x8dfd26d2431d6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee08fa3383a6f3; op2val:0xffb8dfd26d2431d6;
-   valaddr_reg:x3; val_offset:304*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe08fa3383a6f3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0x7fee08fa3383a6f3;
-   valaddr_reg:x3; val_offset:306*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe08fa3383a6f3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee08fa3383a6f3; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:308*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:310*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe08fa3383a6f3 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x98bcc3a92c611 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee08fa3383a6f3; op2val:0xffb98bcc3a92c611;
-   valaddr_reg:x3; val_offset:312*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe08fa3383a6f3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0x7fee08fa3383a6f3;
-   valaddr_reg:x3; val_offset:314*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe08fa3383a6f3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee08fa3383a6f3; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:316*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:318*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x338f20c7d37a6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x1836cb3e931a8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f8338f20c7d37a6; op2val:0xffe1836cb3e931a8;
-   valaddr_reg:x3; val_offset:320*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x338f20c7d37a6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0x7f8338f20c7d37a6;
-   valaddr_reg:x3; val_offset:322*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x338f20c7d37a6 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f8338f20c7d37a6; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:324*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x338f20c7d37a6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7f8338f20c7d37a6;
-   valaddr_reg:x3; val_offset:326*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:328*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x833777722304f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0x7fb833777722304f;
-   valaddr_reg:x3; val_offset:330*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:332*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:334*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:336*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:338*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x4a57d3f9bbb84 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0x7fb4a57d3f9bbb84;
-   valaddr_reg:x3; val_offset:340*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:342*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:344*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:346*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xa7b6d804df453 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0x7fba7b6d804df453;
-   valaddr_reg:x3; val_offset:348*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:350*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:352*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:354*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1369b1ce3b6b7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x1a406f11e5bc4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1369b1ce3b6b7; op2val:0x7fe1a406f11e5bc4;
-   valaddr_reg:x3; val_offset:356*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1369b1ce3b6b7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x1369b1ce3b6b7;
-   valaddr_reg:x3; val_offset:358*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1369b1ce3b6b7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1369b1ce3b6b7; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:360*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1369b1ce3b6b7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x1369b1ce3b6b7;
-   valaddr_reg:x3; val_offset:362*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:364*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xc900ea9c600e8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0x7fbc900ea9c600e8;
-   valaddr_reg:x3; val_offset:366*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:368*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:370*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:372*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x79a9d1edd4c29 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0xffb79a9d1edd4c29;
-   valaddr_reg:x3; val_offset:374*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:376*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:378*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:380*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1369b1ce3b6b7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0bc8069a0dddf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1369b1ce3b6b7; op2val:0xffd0bc8069a0dddf;
-   valaddr_reg:x3; val_offset:382*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1369b1ce3b6b7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x1369b1ce3b6b7;
-   valaddr_reg:x3; val_offset:384*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1369b1ce3b6b7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1369b1ce3b6b7; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:386*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:388*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x1f930d5b2a8f5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0xffb1f930d5b2a8f5;
-   valaddr_reg:x3; val_offset:390*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:392*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:394*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:396*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1369b1ce3b6b7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x60eeb556ce9ce and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1369b1ce3b6b7; op2val:0xffd60eeb556ce9ce;
-   valaddr_reg:x3; val_offset:398*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1369b1ce3b6b7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x1369b1ce3b6b7;
-   valaddr_reg:x3; val_offset:400*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1369b1ce3b6b7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1369b1ce3b6b7; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:402*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:404*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xeb781eb40c69d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0xffbeb781eb40c69d;
-   valaddr_reg:x3; val_offset:406*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:408*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:410*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x0;
-   valaddr_reg:x3; val_offset:412*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xaff35fd55192c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ffaff35fd55192c; op2val:0x0;
-   valaddr_reg:x3; val_offset:414*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xaff35fd55192c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ffaff35fd55192c;
-   valaddr_reg:x3; val_offset:416*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xaff35fd55192c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x3ffaff35fd55192c;
-   valaddr_reg:x3; val_offset:418*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:420*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:422*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x383adc274749d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7fb383adc274749d;
-   valaddr_reg:x3; val_offset:424*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:426*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:428*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:430*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:432*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:434*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:436*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:438*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:440*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:442*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x383adc274749d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7fb383adc274749d;
-   valaddr_reg:x3; val_offset:444*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:446*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:448*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:450*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:452*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:454*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:456*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:458*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:460*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xf391603ed8761 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f7f391603ed8761; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:462*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xf391603ed8761 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7f7f391603ed8761;
-   valaddr_reg:x3; val_offset:464*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xf391603ed8761 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f7f391603ed8761; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:466*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xf391603ed8761 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7f7f391603ed8761;
-   valaddr_reg:x3; val_offset:468*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:470*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe405554eabc62 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0x7fee405554eabc62;
-   valaddr_reg:x3; val_offset:472*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe405554eabc62 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9da958592a6de and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee405554eabc62; op2val:0x9da958592a6de;
-   valaddr_reg:x3; val_offset:474*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:476*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9da958592a6de and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x9da958592a6de;
-   valaddr_reg:x3; val_offset:478*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:480*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x9cedc8f82aa65 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0x7fe9cedc8f82aa65;
-   valaddr_reg:x3; val_offset:482*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x9cedc8f82aa65 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9da958592a6de and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe9cedc8f82aa65; op2val:0x9da958592a6de;
-   valaddr_reg:x3; val_offset:484*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:486*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:488*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:490*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9da958592a6de and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x9da958592a6de;
-   valaddr_reg:x3; val_offset:492*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:494*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:496*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fc4226f510b0 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfc4226f510b0; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:498*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0fc4226f510b0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfc4226f510b0;
-   valaddr_reg:x3; val_offset:500*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fc4226f510b0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfc4226f510b0; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:502*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0fc4226f510b0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xfc4226f510b0;
-   valaddr_reg:x3; val_offset:504*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:506*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:508*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:510*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd814466949f33 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0xffed814466949f33;
-   valaddr_reg:x3; val_offset:512*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd814466949f33 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9da958592a6de and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed814466949f33; op2val:0x9da958592a6de;
-   valaddr_reg:x3; val_offset:514*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:516*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:518*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fc4226f510b0 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfc4226f510b0; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:520*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0fc4226f510b0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfc4226f510b0;
-   valaddr_reg:x3; val_offset:522*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fc4226f510b0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfc4226f510b0; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:524*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:526*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x6777d0b1f5332 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0xffe6777d0b1f5332;
-   valaddr_reg:x3; val_offset:528*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x6777d0b1f5332 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9da958592a6de and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe6777d0b1f5332; op2val:0x9da958592a6de;
-   valaddr_reg:x3; val_offset:530*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:532*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:534*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fc4226f510b0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfc4226f510b0; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:536*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:538*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:540*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9da958592a6de and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x9da958592a6de;
-   valaddr_reg:x3; val_offset:542*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:544*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x0;
-   valaddr_reg:x3; val_offset:546*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x5ecef9517d94f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff5ecef9517d94f; op2val:0x0;
-   valaddr_reg:x3; val_offset:548*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x5ecef9517d94f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ff5ecef9517d94f;
-   valaddr_reg:x3; val_offset:550*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x5ecef9517d94f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x3ff5ecef9517d94f;
-   valaddr_reg:x3; val_offset:552*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:554*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:556*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:558*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:560*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:562*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:564*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:566*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:568*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:570*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:572*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 0 and fe1 == 0x7f9 and fm1 == 0x76cdd4791176f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x1836cb3e931a8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f976cdd4791176f; op2val:0xffe1836cb3e931a8;
-   valaddr_reg:x3; val_offset:574*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7f9 and fm2 == 0x76cdd4791176f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0x7f976cdd4791176f;
-   valaddr_reg:x3; val_offset:576*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0x7f9 and fm1 == 0x76cdd4791176f and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f976cdd4791176f; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:578*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x7f9 and fm2 == 0x76cdd4791176f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x7f976cdd4791176f;
-   valaddr_reg:x3; val_offset:580*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:582*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x833777722304f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0x7fb833777722304f;
-   valaddr_reg:x3; val_offset:584*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:586*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:588*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:590*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:592*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x4a57d3f9bbb84 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0x7fb4a57d3f9bbb84;
-   valaddr_reg:x3; val_offset:594*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:596*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:598*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:600*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xa7b6d804df453 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0x7fba7b6d804df453;
-   valaddr_reg:x3; val_offset:602*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:604*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:606*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:608*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x2f508b3cddb2a and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x1a406f11e5bc4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2f508b3cddb2a; op2val:0x7fe1a406f11e5bc4;
-   valaddr_reg:x3; val_offset:610*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x2f508b3cddb2a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x2f508b3cddb2a;
-   valaddr_reg:x3; val_offset:612*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x2f508b3cddb2a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2f508b3cddb2a; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:614*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x2f508b3cddb2a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x2f508b3cddb2a;
-   valaddr_reg:x3; val_offset:616*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:618*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xc900ea9c600e8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0x7fbc900ea9c600e8;
-   valaddr_reg:x3; val_offset:620*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:622*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:624*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:626*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x79a9d1edd4c29 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0xffb79a9d1edd4c29;
-   valaddr_reg:x3; val_offset:628*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:630*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:632*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:634*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x2f508b3cddb2a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0bc8069a0dddf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2f508b3cddb2a; op2val:0xffd0bc8069a0dddf;
-   valaddr_reg:x3; val_offset:636*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x000 and fm2 == 0x2f508b3cddb2a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x2f508b3cddb2a;
-   valaddr_reg:x3; val_offset:638*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x2f508b3cddb2a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2f508b3cddb2a; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:640*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:642*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x1f930d5b2a8f5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0xffb1f930d5b2a8f5;
-   valaddr_reg:x3; val_offset:644*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:646*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:648*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:650*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x2f508b3cddb2a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x60eeb556ce9ce and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2f508b3cddb2a; op2val:0xffd60eeb556ce9ce;
-   valaddr_reg:x3; val_offset:652*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x000 and fm2 == 0x2f508b3cddb2a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x2f508b3cddb2a;
-   valaddr_reg:x3; val_offset:654*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x2f508b3cddb2a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2f508b3cddb2a; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:656*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:658*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xeb781eb40c69d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0xffbeb781eb40c69d;
-   valaddr_reg:x3; val_offset:660*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:662*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:664*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x0;
-   valaddr_reg:x3; val_offset:666*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 0 and fe1 == 0x401 and fm1 == 0x0732431031347 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x4010732431031347; op2val:0x0;
-   valaddr_reg:x3; val_offset:668*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x401 and fm2 == 0x0732431031347 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x4010732431031347;
-   valaddr_reg:x3; val_offset:670*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x401 and fm2 == 0x0732431031347 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x4010732431031347;
-   valaddr_reg:x3; val_offset:672*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:674*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:676*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:678*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:680*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:682*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:684*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:686*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x8dfd26d2431d6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffb8dfd26d2431d6;
-   valaddr_reg:x3; val_offset:688*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:690*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:692*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:694*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x98bcc3a92c611 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffb98bcc3a92c611;
-   valaddr_reg:x3; val_offset:696*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:698*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:700*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:702*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0xf3eddb8431366 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x1836cb3e931a8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff8f3eddb8431366; op2val:0xffe1836cb3e931a8;
-   valaddr_reg:x3; val_offset:704*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0xf3eddb8431366 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0xff8f3eddb8431366;
-   valaddr_reg:x3; val_offset:706*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0xf3eddb8431366 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff8f3eddb8431366; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:708*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0xf3eddb8431366 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xff8f3eddb8431366;
-   valaddr_reg:x3; val_offset:710*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:712*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x833777722304f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0x7fb833777722304f;
-   valaddr_reg:x3; val_offset:714*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:716*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:718*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:720*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:722*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x4a57d3f9bbb84 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0x7fb4a57d3f9bbb84;
-   valaddr_reg:x3; val_offset:724*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:726*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:728*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:730*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xa7b6d804df453 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0x7fba7b6d804df453;
-   valaddr_reg:x3; val_offset:732*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:734*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:736*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:738*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1f8e1b3b91d2b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x1a406f11e5bc4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001f8e1b3b91d2b; op2val:0x7fe1a406f11e5bc4;
-   valaddr_reg:x3; val_offset:740*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1f8e1b3b91d2b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x8001f8e1b3b91d2b;
-   valaddr_reg:x3; val_offset:742*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1f8e1b3b91d2b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001f8e1b3b91d2b; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:744*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1f8e1b3b91d2b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x8001f8e1b3b91d2b;
-   valaddr_reg:x3; val_offset:746*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:748*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xc900ea9c600e8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0x7fbc900ea9c600e8;
-   valaddr_reg:x3; val_offset:750*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:752*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:754*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:756*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x79a9d1edd4c29 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0xffb79a9d1edd4c29;
-   valaddr_reg:x3; val_offset:758*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:760*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:762*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:764*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1f8e1b3b91d2b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0bc8069a0dddf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001f8e1b3b91d2b; op2val:0xffd0bc8069a0dddf;
-   valaddr_reg:x3; val_offset:766*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1f8e1b3b91d2b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x8001f8e1b3b91d2b;
-   valaddr_reg:x3; val_offset:768*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1f8e1b3b91d2b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001f8e1b3b91d2b; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:770*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:772*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x1f930d5b2a8f5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0xffb1f930d5b2a8f5;
-   valaddr_reg:x3; val_offset:774*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:776*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:778*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:780*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1f8e1b3b91d2b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x60eeb556ce9ce and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001f8e1b3b91d2b; op2val:0xffd60eeb556ce9ce;
-   valaddr_reg:x3; val_offset:782*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1f8e1b3b91d2b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x8001f8e1b3b91d2b;
-   valaddr_reg:x3; val_offset:784*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1f8e1b3b91d2b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001f8e1b3b91d2b; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:786*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:788*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xeb781eb40c69d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0xffbeb781eb40c69d;
-   valaddr_reg:x3; val_offset:790*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:792*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:794*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x0;
-   valaddr_reg:x3; val_offset:796*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 1 and fe1 == 0x400 and fm1 == 0x5f0feaa8af2a4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc005f0feaa8af2a4; op2val:0x0;
-   valaddr_reg:x3; val_offset:798*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x5f0feaa8af2a4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc005f0feaa8af2a4;
-   valaddr_reg:x3; val_offset:800*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x5f0feaa8af2a4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xc005f0feaa8af2a4;
-   valaddr_reg:x3; val_offset:802*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:804*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:806*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:808*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:810*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:812*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:814*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc2fa17693df96 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x1836cb3e931a8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac2fa17693df96; op2val:0xffe1836cb3e931a8;
-   valaddr_reg:x3; val_offset:816*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc2fa17693df96 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0xffac2fa17693df96;
-   valaddr_reg:x3; val_offset:818*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc2fa17693df96 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac2fa17693df96; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:820*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc2fa17693df96 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xffac2fa17693df96;
-   valaddr_reg:x3; val_offset:822*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:824*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x833777722304f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0x7fb833777722304f;
-   valaddr_reg:x3; val_offset:826*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:828*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:830*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:832*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:834*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x4a57d3f9bbb84 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0x7fb4a57d3f9bbb84;
-   valaddr_reg:x3; val_offset:836*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:838*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:840*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:842*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xa7b6d804df453 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0x7fba7b6d804df453;
-   valaddr_reg:x3; val_offset:844*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:846*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:848*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:850*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71dc729cd4c0d and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x1a406f11e5bc4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071dc729cd4c0d; op2val:0x7fe1a406f11e5bc4;
-   valaddr_reg:x3; val_offset:852*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71dc729cd4c0d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x80071dc729cd4c0d;
-   valaddr_reg:x3; val_offset:854*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71dc729cd4c0d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071dc729cd4c0d; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:856*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71dc729cd4c0d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x80071dc729cd4c0d;
-   valaddr_reg:x3; val_offset:858*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:860*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xc900ea9c600e8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0x7fbc900ea9c600e8;
-   valaddr_reg:x3; val_offset:862*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:864*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:866*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:868*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x79a9d1edd4c29 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0xffb79a9d1edd4c29;
-   valaddr_reg:x3; val_offset:870*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:872*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:874*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:876*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71dc729cd4c0d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0bc8069a0dddf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071dc729cd4c0d; op2val:0xffd0bc8069a0dddf;
-   valaddr_reg:x3; val_offset:878*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71dc729cd4c0d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x80071dc729cd4c0d;
-   valaddr_reg:x3; val_offset:880*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71dc729cd4c0d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071dc729cd4c0d; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:882*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:884*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x1f930d5b2a8f5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0xffb1f930d5b2a8f5;
-   valaddr_reg:x3; val_offset:886*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:888*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:890*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:892*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71dc729cd4c0d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x60eeb556ce9ce and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071dc729cd4c0d; op2val:0xffd60eeb556ce9ce;
-   valaddr_reg:x3; val_offset:894*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71dc729cd4c0d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x80071dc729cd4c0d;
-   valaddr_reg:x3; val_offset:896*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71dc729cd4c0d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071dc729cd4c0d; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:898*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:900*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xeb781eb40c69d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0xffbeb781eb40c69d;
-   valaddr_reg:x3; val_offset:902*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:904*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:906*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x0;
-   valaddr_reg:x3; val_offset:908*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 1 and fe1 == 0x402 and fm1 == 0x3cafcfae8bc5f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc023cafcfae8bc5f; op2val:0x0;
-   valaddr_reg:x3; val_offset:910*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x3cafcfae8bc5f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc023cafcfae8bc5f;
-   valaddr_reg:x3; val_offset:912*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x402 and fm2 == 0x3cafcfae8bc5f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xc023cafcfae8bc5f;
-   valaddr_reg:x3; val_offset:914*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:916*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:918*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x8dfd26d2431d6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xffb8dfd26d2431d6;
-   valaddr_reg:x3; val_offset:920*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:922*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:924*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:926*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:928*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:930*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:932*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:934*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:936*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:938*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:940*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:942*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:944*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:946*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:948*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x3e641f0e9c178 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff83e641f0e9c178; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:950*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x3e641f0e9c178 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xff83e641f0e9c178;
-   valaddr_reg:x3; val_offset:952*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x3e641f0e9c178 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff83e641f0e9c178; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:954*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x3e641f0e9c178 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xff83e641f0e9c178;
-   valaddr_reg:x3; val_offset:956*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:958*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe405554eabc62 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0x7fee405554eabc62;
-   valaddr_reg:x3; val_offset:960*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe405554eabc62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc8f73c41dbdb6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee405554eabc62; op2val:0x800c8f73c41dbdb6;
-   valaddr_reg:x3; val_offset:962*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:964*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc8f73c41dbdb6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x800c8f73c41dbdb6;
-   valaddr_reg:x3; val_offset:966*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:968*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x9cedc8f82aa65 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0x7fe9cedc8f82aa65;
-   valaddr_reg:x3; val_offset:970*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x9cedc8f82aa65 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc8f73c41dbdb6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe9cedc8f82aa65; op2val:0x800c8f73c41dbdb6;
-   valaddr_reg:x3; val_offset:972*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:974*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:976*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:978*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc8f73c41dbdb6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x800c8f73c41dbdb6;
-   valaddr_reg:x3; val_offset:980*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:982*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:984*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1418b939c92f9 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001418b939c92f9; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:986*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1418b939c92f9 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8001418b939c92f9;
-   valaddr_reg:x3; val_offset:988*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1418b939c92f9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001418b939c92f9; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:990*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1418b939c92f9 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x8001418b939c92f9;
-   valaddr_reg:x3; val_offset:992*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:994*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:996*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:998*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd814466949f33 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0xffed814466949f33;
-   valaddr_reg:x3; val_offset:1000*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd814466949f33 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc8f73c41dbdb6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed814466949f33; op2val:0x800c8f73c41dbdb6;
-   valaddr_reg:x3; val_offset:1002*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1004*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1006*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1418b939c92f9 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001418b939c92f9; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1008*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1418b939c92f9 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8001418b939c92f9;
-   valaddr_reg:x3; val_offset:1010*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1418b939c92f9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001418b939c92f9; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1012*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1014*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x6777d0b1f5332 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0xffe6777d0b1f5332;
-   valaddr_reg:x3; val_offset:1016*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x6777d0b1f5332 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc8f73c41dbdb6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe6777d0b1f5332; op2val:0x800c8f73c41dbdb6;
-   valaddr_reg:x3; val_offset:1018*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1020*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1022*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1418b939c92f9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001418b939c92f9; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1024*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1026*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1028*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc8f73c41dbdb6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x800c8f73c41dbdb6;
-   valaddr_reg:x3; val_offset:1030*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1032*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x0;
-   valaddr_reg:x3; val_offset:1034*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xbf29e6067a411 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbffbf29e6067a411; op2val:0x0;
-   valaddr_reg:x3; val_offset:1036*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xbf29e6067a411 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbffbf29e6067a411;
-   valaddr_reg:x3; val_offset:1038*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xbf29e6067a411 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xbffbf29e6067a411;
-   valaddr_reg:x3; val_offset:1040*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1042*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1044*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x98bcc3a92c611 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xffb98bcc3a92c611;
-   valaddr_reg:x3; val_offset:1046*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1048*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1050*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1052*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1054*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1056*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1058*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1060*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1062*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1064*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1066*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1068*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1070*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x46fd69542380e and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff846fd69542380e; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1072*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x46fd69542380e and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xff846fd69542380e;
-   valaddr_reg:x3; val_offset:1074*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x46fd69542380e and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff846fd69542380e; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1076*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x46fd69542380e and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xff846fd69542380e;
-   valaddr_reg:x3; val_offset:1078*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1080*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe405554eabc62 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0x7fee405554eabc62;
-   valaddr_reg:x3; val_offset:1082*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe405554eabc62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xce64abc9e6d7c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee405554eabc62; op2val:0x800ce64abc9e6d7c;
-   valaddr_reg:x3; val_offset:1084*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1086*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xce64abc9e6d7c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x800ce64abc9e6d7c;
-   valaddr_reg:x3; val_offset:1088*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1090*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x9cedc8f82aa65 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0x7fe9cedc8f82aa65;
-   valaddr_reg:x3; val_offset:1092*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x9cedc8f82aa65 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xce64abc9e6d7c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe9cedc8f82aa65; op2val:0x800ce64abc9e6d7c;
-   valaddr_reg:x3; val_offset:1094*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1096*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1098*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1100*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xce64abc9e6d7c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x800ce64abc9e6d7c;
-   valaddr_reg:x3; val_offset:1102*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1104*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1106*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x14a3aac763e26 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80014a3aac763e26; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1108*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x14a3aac763e26 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x80014a3aac763e26;
-   valaddr_reg:x3; val_offset:1110*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x14a3aac763e26 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80014a3aac763e26; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1112*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x14a3aac763e26 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x80014a3aac763e26;
-   valaddr_reg:x3; val_offset:1114*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1116*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1118*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1120*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd814466949f33 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0xffed814466949f33;
-   valaddr_reg:x3; val_offset:1122*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd814466949f33 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xce64abc9e6d7c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed814466949f33; op2val:0x800ce64abc9e6d7c;
-   valaddr_reg:x3; val_offset:1124*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1126*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1128*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x14a3aac763e26 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80014a3aac763e26; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1130*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x14a3aac763e26 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x80014a3aac763e26;
-   valaddr_reg:x3; val_offset:1132*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x14a3aac763e26 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80014a3aac763e26; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1134*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1136*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x6777d0b1f5332 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0xffe6777d0b1f5332;
-   valaddr_reg:x3; val_offset:1138*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x6777d0b1f5332 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xce64abc9e6d7c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe6777d0b1f5332; op2val:0x800ce64abc9e6d7c;
-   valaddr_reg:x3; val_offset:1140*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1142*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1144*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x14a3aac763e26 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80014a3aac763e26; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1146*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1148*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1150*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xce64abc9e6d7c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x800ce64abc9e6d7c;
-   valaddr_reg:x3; val_offset:1152*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1154*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-
-inst_578:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x0;
-   valaddr_reg:x3; val_offset:1156*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1156*FLEN/8, x4, x1, x2)
-
-inst_579:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xcb3d7eda95caf and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbffcb3d7eda95caf; op2val:0x0;
-   valaddr_reg:x3; val_offset:1158*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1158*FLEN/8, x4, x1, x2)
-
-inst_580:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xcb3d7eda95caf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbffcb3d7eda95caf;
-   valaddr_reg:x3; val_offset:1160*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1160*FLEN/8, x4, x1, x2)
-
-inst_581:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xcb3d7eda95caf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xbffcb3d7eda95caf;
-   valaddr_reg:x3; val_offset:1162*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1162*FLEN/8, x4, x1, x2)
-
-inst_582:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1164*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1164*FLEN/8, x4, x1, x2)
-
-inst_583:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1166*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1166*FLEN/8, x4, x1, x2)
-
-inst_584:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x1836cb3e931a8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xffe1836cb3e931a8;
-   valaddr_reg:x3; val_offset:1168*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1168*FLEN/8, x4, x1, x2)
-
-inst_585:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1170*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1170*FLEN/8, x4, x1, x2)
-
-inst_586:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1172*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1172*FLEN/8, x4, x1, x2)
-
-inst_587:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1174*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1174*FLEN/8, x4, x1, x2)
-
-inst_588:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1176*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1176*FLEN/8, x4, x1, x2)
-
-inst_589:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1178*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1178*FLEN/8, x4, x1, x2)
-
-inst_590:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1180*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1180*FLEN/8, x4, x1, x2)
-
-inst_591:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1182*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1182*FLEN/8, x4, x1, x2)
-
-inst_592:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1184*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1184*FLEN/8, x4, x1, x2)
-
-inst_593:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1186*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1186*FLEN/8, x4, x1, x2)
-
-inst_594:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1188*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1188*FLEN/8, x4, x1, x2)
-
-inst_595:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1190*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1190*FLEN/8, x4, x1, x2)
-
-inst_596:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1192*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1192*FLEN/8, x4, x1, x2)
-
-inst_597:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1194*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1194*FLEN/8, x4, x1, x2)
-
-inst_598:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1196*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1196*FLEN/8, x4, x1, x2)
-
-inst_599:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1198*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1198*FLEN/8, x4, x1, x2)
-
-inst_600:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1200*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1200*FLEN/8, x4, x1, x2)
-
-inst_601:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x35c5f9281c03f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0x7f835c5f9281c03f;
-   valaddr_reg:x3; val_offset:1202*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1202*FLEN/8, x4, x1, x2)
-
-inst_602:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x35c5f9281c03f and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f835c5f9281c03f; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1204*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1204*FLEN/8, x4, x1, x2)
-
-inst_603:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1206*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1206*FLEN/8, x4, x1, x2)
-
-inst_604:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1208*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1208*FLEN/8, x4, x1, x2)
-
-inst_605:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1210*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1210*FLEN/8, x4, x1, x2)
-
-inst_606:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x0846432e2fc69 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0x7f80846432e2fc69;
-   valaddr_reg:x3; val_offset:1212*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1212*FLEN/8, x4, x1, x2)
-
-inst_607:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x0846432e2fc69 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f80846432e2fc69; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1214*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1214*FLEN/8, x4, x1, x2)
-
-inst_608:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1216*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1216*FLEN/8, x4, x1, x2)
-
-inst_609:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1218*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1218*FLEN/8, x4, x1, x2)
-
-inst_610:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x52f8acd0b29dc and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0x7f852f8acd0b29dc;
-   valaddr_reg:x3; val_offset:1220*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1220*FLEN/8, x4, x1, x2)
-
-inst_611:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x52f8acd0b29dc and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f852f8acd0b29dc; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1222*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1222*FLEN/8, x4, x1, x2)
-
-inst_612:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1224*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1224*FLEN/8, x4, x1, x2)
-
-inst_613:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1226*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1226*FLEN/8, x4, x1, x2)
-
-inst_614:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71322c1100041 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xc39a4b4fd5fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071322c1100041; op2val:0x7fac39a4b4fd5fa0;
-   valaddr_reg:x3; val_offset:1228*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1228*FLEN/8, x4, x1, x2)
-
-inst_615:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xc39a4b4fd5fa0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71322c1100041 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fac39a4b4fd5fa0; op2val:0x80071322c1100041;
-   valaddr_reg:x3; val_offset:1230*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1230*FLEN/8, x4, x1, x2)
-
-inst_616:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71322c1100041 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071322c1100041; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1232*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1232*FLEN/8, x4, x1, x2)
-
-inst_617:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71322c1100041 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x80071322c1100041;
-   valaddr_reg:x3; val_offset:1234*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1234*FLEN/8, x4, x1, x2)
-
-inst_618:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1236*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1236*FLEN/8, x4, x1, x2)
-
-inst_619:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x6d9a5549e6720 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0x7f86d9a5549e6720;
-   valaddr_reg:x3; val_offset:1238*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1238*FLEN/8, x4, x1, x2)
-
-inst_620:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x6d9a5549e6720 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f86d9a5549e6720; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1240*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1240*FLEN/8, x4, x1, x2)
-
-inst_621:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1242*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1242*FLEN/8, x4, x1, x2)
-
-inst_622:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1244*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1244*FLEN/8, x4, x1, x2)
-
-inst_623:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x2e2174be43ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0xff82e2174be43ced;
-   valaddr_reg:x3; val_offset:1246*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1246*FLEN/8, x4, x1, x2)
-
-inst_624:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x2e2174be43ced and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff82e2174be43ced; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1248*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1248*FLEN/8, x4, x1, x2)
-
-inst_625:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1250*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1250*FLEN/8, x4, x1, x2)
-
-inst_626:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1252*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1252*FLEN/8, x4, x1, x2)
-
-inst_627:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71322c1100041 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0xac733dc349632 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071322c1100041; op2val:0xff9ac733dc349632;
-   valaddr_reg:x3; val_offset:1254*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1254*FLEN/8, x4, x1, x2)
-
-inst_628:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0xac733dc349632 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71322c1100041 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff9ac733dc349632; op2val:0x80071322c1100041;
-   valaddr_reg:x3; val_offset:1256*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1256*FLEN/8, x4, x1, x2)
-
-inst_629:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71322c1100041 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071322c1100041; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1258*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1258*FLEN/8, x4, x1, x2)
-
-inst_630:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1260*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1260*FLEN/8, x4, x1, x2)
-
-inst_631:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0xcc1e7bc510e55 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0xff7cc1e7bc510e55;
-   valaddr_reg:x3; val_offset:1262*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1262*FLEN/8, x4, x1, x2)
-
-inst_632:
-// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0xcc1e7bc510e55 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff7cc1e7bc510e55; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1264*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1264*FLEN/8, x4, x1, x2)
-
-inst_633:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1266*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1266*FLEN/8, x4, x1, x2)
-
-inst_634:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1268*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1268*FLEN/8, x4, x1, x2)
-
-inst_635:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71322c1100041 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x1a5891123ee3f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071322c1100041; op2val:0xffa1a5891123ee3f;
-   valaddr_reg:x3; val_offset:1270*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1270*FLEN/8, x4, x1, x2)
-
-inst_636:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x1a5891123ee3f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71322c1100041 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffa1a5891123ee3f; op2val:0x80071322c1100041;
-   valaddr_reg:x3; val_offset:1272*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1272*FLEN/8, x4, x1, x2)
-
-inst_637:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71322c1100041 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071322c1100041; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1274*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1274*FLEN/8, x4, x1, x2)
-
-inst_638:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1276*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1276*FLEN/8, x4, x1, x2)
-
-inst_639:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x892ce55cd6bb0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0xff8892ce55cd6bb0;
-   valaddr_reg:x3; val_offset:1278*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1278*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_6)
-
-inst_640:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x892ce55cd6bb0 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff8892ce55cd6bb0; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1280*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1280*FLEN/8, x4, x1, x2)
-
-inst_641:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1282*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1282*FLEN/8, x4, x1, x2)
-
-inst_642:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x0;
-   valaddr_reg:x3; val_offset:1284*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1284*FLEN/8, x4, x1, x2)
-
-inst_643:
-// fs1 == 1 and fe1 == 0x402 and fm1 == 0x3ad6377363fb3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc023ad6377363fb3; op2val:0x0;
-   valaddr_reg:x3; val_offset:1286*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1286*FLEN/8, x4, x1, x2)
-
-inst_644:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x3ad6377363fb3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc023ad6377363fb3;
-   valaddr_reg:x3; val_offset:1288*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1288*FLEN/8, x4, x1, x2)
-
-inst_645:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x3ad6377363fb3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xc023ad6377363fb3;
-   valaddr_reg:x3; val_offset:1290*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1290*FLEN/8, x4, x1, x2)
-
-inst_646:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1292*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1292*FLEN/8, x4, x1, x2)
-
-inst_647:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1294*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1294*FLEN/8, x4, x1, x2)
-
-inst_648:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x833777722304f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7fb833777722304f;
-   valaddr_reg:x3; val_offset:1296*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1296*FLEN/8, x4, x1, x2)
-
-inst_649:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1298*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1298*FLEN/8, x4, x1, x2)
-
-inst_650:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1300*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1300*FLEN/8, x4, x1, x2)
-
-inst_651:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1302*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1302*FLEN/8, x4, x1, x2)
-
-inst_652:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1304*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1304*FLEN/8, x4, x1, x2)
-
-inst_653:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1306*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1306*FLEN/8, x4, x1, x2)
-
-inst_654:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1308*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1308*FLEN/8, x4, x1, x2)
-
-inst_655:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe405554eabc62 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee405554eabc62; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1310*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1310*FLEN/8, x4, x1, x2)
-
-inst_656:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe405554eabc62 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7fee405554eabc62;
-   valaddr_reg:x3; val_offset:1312*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1312*FLEN/8, x4, x1, x2)
-
-inst_657:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1314*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1314*FLEN/8, x4, x1, x2)
-
-inst_658:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1316*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1316*FLEN/8, x4, x1, x2)
-
-inst_659:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1318*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1318*FLEN/8, x4, x1, x2)
-
-inst_660:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1320*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1320*FLEN/8, x4, x1, x2)
-
-inst_661:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1322*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1322*FLEN/8, x4, x1, x2)
-
-inst_662:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1324*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1324*FLEN/8, x4, x1, x2)
-
-inst_663:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1326*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1326*FLEN/8, x4, x1, x2)
-
-inst_664:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe405554eabc62 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee405554eabc62; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1328*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1328*FLEN/8, x4, x1, x2)
-
-inst_665:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1330*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1330*FLEN/8, x4, x1, x2)
-
-inst_666:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe405554eabc62 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee405554eabc62; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1332*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1332*FLEN/8, x4, x1, x2)
-
-inst_667:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1334*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1334*FLEN/8, x4, x1, x2)
-
-inst_668:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x35c5f9281c03f and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f835c5f9281c03f; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1336*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1336*FLEN/8, x4, x1, x2)
-
-inst_669:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x35c5f9281c03f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7f835c5f9281c03f;
-   valaddr_reg:x3; val_offset:1338*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1338*FLEN/8, x4, x1, x2)
-
-inst_670:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1340*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1340*FLEN/8, x4, x1, x2)
-
-inst_671:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1342*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1342*FLEN/8, x4, x1, x2)
-
-inst_672:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1344*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1344*FLEN/8, x4, x1, x2)
-
-inst_673:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1346*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1346*FLEN/8, x4, x1, x2)
-
-inst_674:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1348*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1348*FLEN/8, x4, x1, x2)
-
-inst_675:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x138d792d007f4 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x138d792d007f4; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1350*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1350*FLEN/8, x4, x1, x2)
-
-inst_676:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x138d792d007f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x138d792d007f4;
-   valaddr_reg:x3; val_offset:1352*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1352*FLEN/8, x4, x1, x2)
-
-inst_677:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x138d792d007f4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x138d792d007f4; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1354*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1354*FLEN/8, x4, x1, x2)
-
-inst_678:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x138d792d007f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x138d792d007f4;
-   valaddr_reg:x3; val_offset:1356*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1356*FLEN/8, x4, x1, x2)
-
-inst_679:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1358*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1358*FLEN/8, x4, x1, x2)
-
-inst_680:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1360*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1360*FLEN/8, x4, x1, x2)
-
-inst_681:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1362*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1362*FLEN/8, x4, x1, x2)
-
-inst_682:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1364*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1364*FLEN/8, x4, x1, x2)
-
-inst_683:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1366*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1366*FLEN/8, x4, x1, x2)
-
-inst_684:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x138d792d007f4 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x138d792d007f4; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1368*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1368*FLEN/8, x4, x1, x2)
-
-inst_685:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x138d792d007f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x138d792d007f4;
-   valaddr_reg:x3; val_offset:1370*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1370*FLEN/8, x4, x1, x2)
-
-inst_686:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x138d792d007f4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x138d792d007f4; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1372*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1372*FLEN/8, x4, x1, x2)
-
-inst_687:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1374*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1374*FLEN/8, x4, x1, x2)
-
-inst_688:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1376*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1376*FLEN/8, x4, x1, x2)
-
-inst_689:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1378*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1378*FLEN/8, x4, x1, x2)
-
-inst_690:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x138d792d007f4 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x138d792d007f4; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:1380*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1380*FLEN/8, x4, x1, x2)
-
-inst_691:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x138d792d007f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x138d792d007f4;
-   valaddr_reg:x3; val_offset:1382*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1382*FLEN/8, x4, x1, x2)
-
-inst_692:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x138d792d007f4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x138d792d007f4; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1384*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1384*FLEN/8, x4, x1, x2)
-
-inst_693:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1386*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1386*FLEN/8, x4, x1, x2)
-
-inst_694:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1388*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1388*FLEN/8, x4, x1, x2)
-
-inst_695:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x0;
-   valaddr_reg:x3; val_offset:1390*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1390*FLEN/8, x4, x1, x2)
-
-inst_696:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xb30f7a95c7e30 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ffb30f7a95c7e30; op2val:0x0;
-   valaddr_reg:x3; val_offset:1392*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1392*FLEN/8, x4, x1, x2)
-
-inst_697:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xb30f7a95c7e30 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ffb30f7a95c7e30;
-   valaddr_reg:x3; val_offset:1394*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1394*FLEN/8, x4, x1, x2)
-
-inst_698:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xb30f7a95c7e30 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x3ffb30f7a95c7e30;
-   valaddr_reg:x3; val_offset:1396*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1396*FLEN/8, x4, x1, x2)
-
-inst_699:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1398*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1398*FLEN/8, x4, x1, x2)
-
-inst_700:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1400*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1400*FLEN/8, x4, x1, x2)
-
-inst_701:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x4a57d3f9bbb84 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7fb4a57d3f9bbb84;
-   valaddr_reg:x3; val_offset:1402*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1402*FLEN/8, x4, x1, x2)
-
-inst_702:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1404*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1404*FLEN/8, x4, x1, x2)
-
-inst_703:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1406*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1406*FLEN/8, x4, x1, x2)
-
-inst_704:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1408*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1408*FLEN/8, x4, x1, x2)
-
-inst_705:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1410*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1410*FLEN/8, x4, x1, x2)
-
-inst_706:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1412*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1412*FLEN/8, x4, x1, x2)
-
-inst_707:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1414*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1414*FLEN/8, x4, x1, x2)
-
-inst_708:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x9cedc8f82aa65 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe9cedc8f82aa65; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1416*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1416*FLEN/8, x4, x1, x2)
-
-inst_709:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x9cedc8f82aa65 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7fe9cedc8f82aa65;
-   valaddr_reg:x3; val_offset:1418*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1418*FLEN/8, x4, x1, x2)
-
-inst_710:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1420*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1420*FLEN/8, x4, x1, x2)
-
-inst_711:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1422*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1422*FLEN/8, x4, x1, x2)
-
-inst_712:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1424*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1424*FLEN/8, x4, x1, x2)
-
-inst_713:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1426*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1426*FLEN/8, x4, x1, x2)
-
-inst_714:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1428*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1428*FLEN/8, x4, x1, x2)
-
-inst_715:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1430*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1430*FLEN/8, x4, x1, x2)
-
-inst_716:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1432*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1432*FLEN/8, x4, x1, x2)
-
-inst_717:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x9cedc8f82aa65 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe9cedc8f82aa65; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1434*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1434*FLEN/8, x4, x1, x2)
-
-inst_718:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1436*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1436*FLEN/8, x4, x1, x2)
-
-inst_719:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x9cedc8f82aa65 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe9cedc8f82aa65; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1438*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1438*FLEN/8, x4, x1, x2)
-
-inst_720:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1440*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1440*FLEN/8, x4, x1, x2)
-
-inst_721:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x0846432e2fc69 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f80846432e2fc69; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1442*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1442*FLEN/8, x4, x1, x2)
-
-inst_722:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x0846432e2fc69 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7f80846432e2fc69;
-   valaddr_reg:x3; val_offset:1444*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1444*FLEN/8, x4, x1, x2)
-
-inst_723:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1446*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1446*FLEN/8, x4, x1, x2)
-
-inst_724:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1448*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1448*FLEN/8, x4, x1, x2)
-
-inst_725:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1450*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1450*FLEN/8, x4, x1, x2)
-
-inst_726:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x10ae479ad094b and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10ae479ad094b; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1452*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1452*FLEN/8, x4, x1, x2)
-
-inst_727:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x10ae479ad094b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x10ae479ad094b;
-   valaddr_reg:x3; val_offset:1454*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1454*FLEN/8, x4, x1, x2)
-
-inst_728:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x10ae479ad094b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10ae479ad094b; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1456*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1456*FLEN/8, x4, x1, x2)
-
-inst_729:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x000 and fm2 == 0x10ae479ad094b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x10ae479ad094b;
-   valaddr_reg:x3; val_offset:1458*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1458*FLEN/8, x4, x1, x2)
-
-inst_730:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1460*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1460*FLEN/8, x4, x1, x2)
-
-inst_731:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1462*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1462*FLEN/8, x4, x1, x2)
-
-inst_732:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1464*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1464*FLEN/8, x4, x1, x2)
-
-inst_733:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1466*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1466*FLEN/8, x4, x1, x2)
-
-inst_734:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1468*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1468*FLEN/8, x4, x1, x2)
-
-inst_735:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x10ae479ad094b and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10ae479ad094b; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1470*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1470*FLEN/8, x4, x1, x2)
-
-inst_736:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x10ae479ad094b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x10ae479ad094b;
-   valaddr_reg:x3; val_offset:1472*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1472*FLEN/8, x4, x1, x2)
-
-inst_737:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x10ae479ad094b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10ae479ad094b; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1474*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1474*FLEN/8, x4, x1, x2)
-
-inst_738:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1476*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1476*FLEN/8, x4, x1, x2)
-
-inst_739:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1478*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1478*FLEN/8, x4, x1, x2)
-
-inst_740:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1480*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1480*FLEN/8, x4, x1, x2)
-
-inst_741:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x10ae479ad094b and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10ae479ad094b; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:1482*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1482*FLEN/8, x4, x1, x2)
-
-inst_742:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x10ae479ad094b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x10ae479ad094b;
-   valaddr_reg:x3; val_offset:1484*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1484*FLEN/8, x4, x1, x2)
-
-inst_743:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x10ae479ad094b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10ae479ad094b; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1486*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1486*FLEN/8, x4, x1, x2)
-
-inst_744:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1488*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1488*FLEN/8, x4, x1, x2)
-
-inst_745:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1490*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1490*FLEN/8, x4, x1, x2)
-
-inst_746:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x0;
-   valaddr_reg:x3; val_offset:1492*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1492*FLEN/8, x4, x1, x2)
-
-inst_747:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x7328e09ede5ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff7328e09ede5ed; op2val:0x0;
-   valaddr_reg:x3; val_offset:1494*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1494*FLEN/8, x4, x1, x2)
-
-inst_748:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x7328e09ede5ed and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ff7328e09ede5ed;
-   valaddr_reg:x3; val_offset:1496*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1496*FLEN/8, x4, x1, x2)
-
-inst_749:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x7328e09ede5ed and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x3ff7328e09ede5ed;
-   valaddr_reg:x3; val_offset:1498*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1498*FLEN/8, x4, x1, x2)
-
-inst_750:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1500*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1500*FLEN/8, x4, x1, x2)
-
-inst_751:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1502*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1502*FLEN/8, x4, x1, x2)
-
-inst_752:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xa7b6d804df453 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7fba7b6d804df453;
-   valaddr_reg:x3; val_offset:1504*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1504*FLEN/8, x4, x1, x2)
-
-inst_753:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1506*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1506*FLEN/8, x4, x1, x2)
-
-inst_754:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1508*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1508*FLEN/8, x4, x1, x2)
-
-inst_755:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1510*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1510*FLEN/8, x4, x1, x2)
-
-inst_756:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1512*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1512*FLEN/8, x4, x1, x2)
-
-inst_757:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1514*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1514*FLEN/8, x4, x1, x2)
-
-inst_758:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1516*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1516*FLEN/8, x4, x1, x2)
-
-inst_759:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1518*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1518*FLEN/8, x4, x1, x2)
-
-inst_760:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1520*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1520*FLEN/8, x4, x1, x2)
-
-inst_761:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1522*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1522*FLEN/8, x4, x1, x2)
-
-inst_762:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1524*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1524*FLEN/8, x4, x1, x2)
-
-inst_763:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1526*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1526*FLEN/8, x4, x1, x2)
-
-inst_764:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1528*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1528*FLEN/8, x4, x1, x2)
-
-inst_765:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1530*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1530*FLEN/8, x4, x1, x2)
-
-inst_766:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1532*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1532*FLEN/8, x4, x1, x2)
-
-inst_767:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1534*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1534*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_7)
-
-inst_768:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1536*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1536*FLEN/8, x4, x1, x2)
-
-inst_769:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x52f8acd0b29dc and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f852f8acd0b29dc; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1538*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1538*FLEN/8, x4, x1, x2)
-
-inst_770:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x52f8acd0b29dc and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7f852f8acd0b29dc;
-   valaddr_reg:x3; val_offset:1540*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1540*FLEN/8, x4, x1, x2)
-
-inst_771:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1542*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1542*FLEN/8, x4, x1, x2)
-
-inst_772:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1565452ad8ee7 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1565452ad8ee7; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1544*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1544*FLEN/8, x4, x1, x2)
-
-inst_773:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1565452ad8ee7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x1565452ad8ee7;
-   valaddr_reg:x3; val_offset:1546*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1546*FLEN/8, x4, x1, x2)
-
-inst_774:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1565452ad8ee7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1565452ad8ee7; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1548*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1548*FLEN/8, x4, x1, x2)
-
-inst_775:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1565452ad8ee7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x1565452ad8ee7;
-   valaddr_reg:x3; val_offset:1550*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1550*FLEN/8, x4, x1, x2)
-
-inst_776:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1552*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1552*FLEN/8, x4, x1, x2)
-
-inst_777:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1554*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1554*FLEN/8, x4, x1, x2)
-
-inst_778:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1556*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1556*FLEN/8, x4, x1, x2)
-
-inst_779:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1558*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1558*FLEN/8, x4, x1, x2)
-
-inst_780:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1560*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1560*FLEN/8, x4, x1, x2)
-
-inst_781:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1565452ad8ee7 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1565452ad8ee7; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1562*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1562*FLEN/8, x4, x1, x2)
-
-inst_782:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1565452ad8ee7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x1565452ad8ee7;
-   valaddr_reg:x3; val_offset:1564*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1564*FLEN/8, x4, x1, x2)
-
-inst_783:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1565452ad8ee7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1565452ad8ee7; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1566*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1566*FLEN/8, x4, x1, x2)
-
-inst_784:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1568*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1568*FLEN/8, x4, x1, x2)
-
-inst_785:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1570*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1570*FLEN/8, x4, x1, x2)
-
-inst_786:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1572*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1572*FLEN/8, x4, x1, x2)
-
-inst_787:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1565452ad8ee7 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1565452ad8ee7; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:1574*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1574*FLEN/8, x4, x1, x2)
-
-inst_788:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1565452ad8ee7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x1565452ad8ee7;
-   valaddr_reg:x3; val_offset:1576*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1576*FLEN/8, x4, x1, x2)
-
-inst_789:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1565452ad8ee7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1565452ad8ee7; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1578*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1578*FLEN/8, x4, x1, x2)
-
-inst_790:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1580*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1580*FLEN/8, x4, x1, x2)
-
-inst_791:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1582*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1582*FLEN/8, x4, x1, x2)
-
-inst_792:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x0;
-   valaddr_reg:x3; val_offset:1584*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1584*FLEN/8, x4, x1, x2)
-
-inst_793:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xdc114e9aa78bb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ffdc114e9aa78bb; op2val:0x0;
-   valaddr_reg:x3; val_offset:1586*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1586*FLEN/8, x4, x1, x2)
-
-inst_794:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xdc114e9aa78bb and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ffdc114e9aa78bb;
-   valaddr_reg:x3; val_offset:1588*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1588*FLEN/8, x4, x1, x2)
-
-inst_795:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xdc114e9aa78bb and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x3ffdc114e9aa78bb;
-   valaddr_reg:x3; val_offset:1590*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1590*FLEN/8, x4, x1, x2)
-
-inst_796:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1592*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1592*FLEN/8, x4, x1, x2)
-
-inst_797:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1594*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1594*FLEN/8, x4, x1, x2)
-
-inst_798:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x1a406f11e5bc4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7fe1a406f11e5bc4;
-   valaddr_reg:x3; val_offset:1596*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1596*FLEN/8, x4, x1, x2)
-
-inst_799:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1598*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1598*FLEN/8, x4, x1, x2)
-
-inst_800:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1600*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1600*FLEN/8, x4, x1, x2)
-
-inst_801:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1602*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1602*FLEN/8, x4, x1, x2)
-
-inst_802:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1604*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1604*FLEN/8, x4, x1, x2)
-
-inst_803:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1606*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1606*FLEN/8, x4, x1, x2)
-
-inst_804:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1608*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1608*FLEN/8, x4, x1, x2)
-
-inst_805:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1610*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1610*FLEN/8, x4, x1, x2)
-
-inst_806:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1612*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1612*FLEN/8, x4, x1, x2)
-
-inst_807:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1614*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1614*FLEN/8, x4, x1, x2)
-
-inst_808:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1616*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1616*FLEN/8, x4, x1, x2)
-
-inst_809:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1618*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1618*FLEN/8, x4, x1, x2)
-
-inst_810:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1620*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1620*FLEN/8, x4, x1, x2)
-
-inst_811:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1622*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1622*FLEN/8, x4, x1, x2)
-
-inst_812:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1624*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1624*FLEN/8, x4, x1, x2)
-
-inst_813:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1626*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1626*FLEN/8, x4, x1, x2)
-
-inst_814:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1628*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1628*FLEN/8, x4, x1, x2)
-
-inst_815:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xc39a4b4fd5fa0 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fac39a4b4fd5fa0; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1630*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1630*FLEN/8, x4, x1, x2)
-
-inst_816:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xc39a4b4fd5fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7fac39a4b4fd5fa0;
-   valaddr_reg:x3; val_offset:1632*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1632*FLEN/8, x4, x1, x2)
-
-inst_817:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1634*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1634*FLEN/8, x4, x1, x2)
-
-inst_818:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1636*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1636*FLEN/8, x4, x1, x2)
-
-inst_819:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1638*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1638*FLEN/8, x4, x1, x2)
-
-inst_820:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1640*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1640*FLEN/8, x4, x1, x2)
-
-inst_821:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1642*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1642*FLEN/8, x4, x1, x2)
-
-inst_822:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1644*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1644*FLEN/8, x4, x1, x2)
-
-inst_823:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1646*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1646*FLEN/8, x4, x1, x2)
-
-inst_824:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1648*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1648*FLEN/8, x4, x1, x2)
-
-inst_825:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x171398510409d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x171398510409d;
-   valaddr_reg:x3; val_offset:1650*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1650*FLEN/8, x4, x1, x2)
-
-inst_826:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x171398510409d and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x171398510409d; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1652*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1652*FLEN/8, x4, x1, x2)
-
-inst_827:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1654*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1654*FLEN/8, x4, x1, x2)
-
-inst_828:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1656*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1656*FLEN/8, x4, x1, x2)
-
-inst_829:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1311fac939004 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x8001311fac939004;
-   valaddr_reg:x3; val_offset:1658*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1658*FLEN/8, x4, x1, x2)
-
-inst_830:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1311fac939004 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001311fac939004; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1660*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1660*FLEN/8, x4, x1, x2)
-
-inst_831:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1662*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1662*FLEN/8, x4, x1, x2)
-
-inst_832:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1664*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1664*FLEN/8, x4, x1, x2)
-
-inst_833:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1666*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1666*FLEN/8, x4, x1, x2)
-
-inst_834:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1668*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1668*FLEN/8, x4, x1, x2)
-
-inst_835:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0e856af141964 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x8000e856af141964;
-   valaddr_reg:x3; val_offset:1670*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1670*FLEN/8, x4, x1, x2)
-
-inst_836:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0e856af141964 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000e856af141964; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1672*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1672*FLEN/8, x4, x1, x2)
-
-inst_837:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1674*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1674*FLEN/8, x4, x1, x2)
-
-inst_838:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1676*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1676*FLEN/8, x4, x1, x2)
-
-inst_839:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1678*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1678*FLEN/8, x4, x1, x2)
-
-inst_840:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1680*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1680*FLEN/8, x4, x1, x2)
-
-inst_841:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x18d1201fedb6b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x80018d1201fedb6b;
-   valaddr_reg:x3; val_offset:1682*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1682*FLEN/8, x4, x1, x2)
-
-inst_842:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x18d1201fedb6b and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80018d1201fedb6b; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1684*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1684*FLEN/8, x4, x1, x2)
-
-inst_843:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1686*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1686*FLEN/8, x4, x1, x2)
-
-inst_844:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x0;
-   valaddr_reg:x3; val_offset:1688*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1688*FLEN/8, x4, x1, x2)
-
-inst_845:
-// fs1 == 0 and fe1 == 0x402 and fm1 == 0x3d204f37ca317 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x4023d204f37ca317; op2val:0x0;
-   valaddr_reg:x3; val_offset:1690*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1690*FLEN/8, x4, x1, x2)
-
-inst_846:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x3d204f37ca317 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x4023d204f37ca317;
-   valaddr_reg:x3; val_offset:1692*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1692*FLEN/8, x4, x1, x2)
-
-inst_847:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x402 and fm2 == 0x3d204f37ca317 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x4023d204f37ca317;
-   valaddr_reg:x3; val_offset:1694*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1694*FLEN/8, x4, x1, x2)
-
-inst_848:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1696*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1696*FLEN/8, x4, x1, x2)
-
-inst_849:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1698*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1698*FLEN/8, x4, x1, x2)
-
-inst_850:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xc900ea9c600e8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7fbc900ea9c600e8;
-   valaddr_reg:x3; val_offset:1700*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1700*FLEN/8, x4, x1, x2)
-
-inst_851:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1702*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1702*FLEN/8, x4, x1, x2)
-
-inst_852:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1704*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1704*FLEN/8, x4, x1, x2)
-
-inst_853:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1706*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1706*FLEN/8, x4, x1, x2)
-
-inst_854:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1708*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1708*FLEN/8, x4, x1, x2)
-
-inst_855:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1710*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1710*FLEN/8, x4, x1, x2)
-
-inst_856:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1712*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1712*FLEN/8, x4, x1, x2)
-
-inst_857:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1714*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1714*FLEN/8, x4, x1, x2)
-
-inst_858:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1716*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1716*FLEN/8, x4, x1, x2)
-
-inst_859:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1718*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1718*FLEN/8, x4, x1, x2)
-
-inst_860:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1720*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1720*FLEN/8, x4, x1, x2)
-
-inst_861:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1722*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1722*FLEN/8, x4, x1, x2)
-
-inst_862:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1724*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1724*FLEN/8, x4, x1, x2)
-
-inst_863:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1726*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1726*FLEN/8, x4, x1, x2)
-
-inst_864:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1728*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1728*FLEN/8, x4, x1, x2)
-
-inst_865:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1730*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1730*FLEN/8, x4, x1, x2)
-
-inst_866:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1732*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1732*FLEN/8, x4, x1, x2)
-
-inst_867:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x6d9a5549e6720 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f86d9a5549e6720; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1734*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1734*FLEN/8, x4, x1, x2)
-
-inst_868:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x6d9a5549e6720 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7f86d9a5549e6720;
-   valaddr_reg:x3; val_offset:1736*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1736*FLEN/8, x4, x1, x2)
-
-inst_869:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1738*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1738*FLEN/8, x4, x1, x2)
-
-inst_870:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x171398510409d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x171398510409d; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1740*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1740*FLEN/8, x4, x1, x2)
-
-inst_871:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x171398510409d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x171398510409d;
-   valaddr_reg:x3; val_offset:1742*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1742*FLEN/8, x4, x1, x2)
-
-inst_872:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1744*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1744*FLEN/8, x4, x1, x2)
-
-inst_873:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1746*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1746*FLEN/8, x4, x1, x2)
-
-inst_874:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1748*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1748*FLEN/8, x4, x1, x2)
-
-inst_875:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x171398510409d and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x171398510409d; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1750*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1750*FLEN/8, x4, x1, x2)
-
-inst_876:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x171398510409d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x171398510409d;
-   valaddr_reg:x3; val_offset:1752*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1752*FLEN/8, x4, x1, x2)
-
-inst_877:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x171398510409d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x171398510409d; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1754*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1754*FLEN/8, x4, x1, x2)
-
-inst_878:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1756*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1756*FLEN/8, x4, x1, x2)
-
-inst_879:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1758*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1758*FLEN/8, x4, x1, x2)
-
-inst_880:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1760*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1760*FLEN/8, x4, x1, x2)
-
-inst_881:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x171398510409d and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x171398510409d; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:1762*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1762*FLEN/8, x4, x1, x2)
-
-inst_882:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x171398510409d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x171398510409d;
-   valaddr_reg:x3; val_offset:1764*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1764*FLEN/8, x4, x1, x2)
-
-inst_883:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x171398510409d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x171398510409d; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1766*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1766*FLEN/8, x4, x1, x2)
-
-inst_884:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1768*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1768*FLEN/8, x4, x1, x2)
-
-inst_885:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1770*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1770*FLEN/8, x4, x1, x2)
-
-inst_886:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x0;
-   valaddr_reg:x3; val_offset:1772*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1772*FLEN/8, x4, x1, x2)
-
-inst_887:
-// fs1 == 0 and fe1 == 0x400 and fm1 == 0x00bc2d04a6fc5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x40000bc2d04a6fc5; op2val:0x0;
-   valaddr_reg:x3; val_offset:1774*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1774*FLEN/8, x4, x1, x2)
-
-inst_888:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x00bc2d04a6fc5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x40000bc2d04a6fc5;
-   valaddr_reg:x3; val_offset:1776*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1776*FLEN/8, x4, x1, x2)
-
-inst_889:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x00bc2d04a6fc5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x40000bc2d04a6fc5;
-   valaddr_reg:x3; val_offset:1778*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1778*FLEN/8, x4, x1, x2)
-
-inst_890:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1780*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1780*FLEN/8, x4, x1, x2)
-
-inst_891:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1782*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1782*FLEN/8, x4, x1, x2)
-
-inst_892:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x79a9d1edd4c29 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xffb79a9d1edd4c29;
-   valaddr_reg:x3; val_offset:1784*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1784*FLEN/8, x4, x1, x2)
-
-inst_893:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1786*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1786*FLEN/8, x4, x1, x2)
-
-inst_894:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1788*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1788*FLEN/8, x4, x1, x2)
-
-inst_895:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1790*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1790*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_8)
-
-inst_896:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1792*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1792*FLEN/8, x4, x1, x2)
-
-inst_897:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1794*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1794*FLEN/8, x4, x1, x2)
-
-inst_898:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1796*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1796*FLEN/8, x4, x1, x2)
-
-inst_899:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd814466949f33 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed814466949f33; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1798*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1798*FLEN/8, x4, x1, x2)
-
-inst_900:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd814466949f33 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xffed814466949f33;
-   valaddr_reg:x3; val_offset:1800*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1800*FLEN/8, x4, x1, x2)
-
-inst_901:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1802*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1802*FLEN/8, x4, x1, x2)
-
-inst_902:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1804*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1804*FLEN/8, x4, x1, x2)
-
-inst_903:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1806*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1806*FLEN/8, x4, x1, x2)
-
-inst_904:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1808*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1808*FLEN/8, x4, x1, x2)
-
-inst_905:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1810*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1810*FLEN/8, x4, x1, x2)
-
-inst_906:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1812*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1812*FLEN/8, x4, x1, x2)
-
-inst_907:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1814*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1814*FLEN/8, x4, x1, x2)
-
-inst_908:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd814466949f33 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed814466949f33; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1816*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1816*FLEN/8, x4, x1, x2)
-
-inst_909:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1818*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1818*FLEN/8, x4, x1, x2)
-
-inst_910:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd814466949f33 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed814466949f33; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1820*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1820*FLEN/8, x4, x1, x2)
-
-inst_911:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1822*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1822*FLEN/8, x4, x1, x2)
-
-inst_912:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x2e2174be43ced and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff82e2174be43ced; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1824*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1824*FLEN/8, x4, x1, x2)
-
-inst_913:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x2e2174be43ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xff82e2174be43ced;
-   valaddr_reg:x3; val_offset:1826*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1826*FLEN/8, x4, x1, x2)
-
-inst_914:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1828*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1828*FLEN/8, x4, x1, x2)
-
-inst_915:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1311fac939004 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001311fac939004; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1830*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1830*FLEN/8, x4, x1, x2)
-
-inst_916:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1311fac939004 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x8001311fac939004;
-   valaddr_reg:x3; val_offset:1832*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1832*FLEN/8, x4, x1, x2)
-
-inst_917:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1834*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1834*FLEN/8, x4, x1, x2)
-
-inst_918:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1311fac939004 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001311fac939004; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1836*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1836*FLEN/8, x4, x1, x2)
-
-inst_919:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1311fac939004 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x8001311fac939004;
-   valaddr_reg:x3; val_offset:1838*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1838*FLEN/8, x4, x1, x2)
-
-inst_920:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1311fac939004 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001311fac939004; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1840*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1840*FLEN/8, x4, x1, x2)
-
-inst_921:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1842*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1842*FLEN/8, x4, x1, x2)
-
-inst_922:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1844*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1844*FLEN/8, x4, x1, x2)
-
-inst_923:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1846*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1846*FLEN/8, x4, x1, x2)
-
-inst_924:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1311fac939004 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001311fac939004; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:1848*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1848*FLEN/8, x4, x1, x2)
-
-inst_925:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1311fac939004 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x8001311fac939004;
-   valaddr_reg:x3; val_offset:1850*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1850*FLEN/8, x4, x1, x2)
-
-inst_926:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1311fac939004 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001311fac939004; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1852*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1852*FLEN/8, x4, x1, x2)
-
-inst_927:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1854*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1854*FLEN/8, x4, x1, x2)
-
-inst_928:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1856*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1856*FLEN/8, x4, x1, x2)
-
-inst_929:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x0;
-   valaddr_reg:x3; val_offset:1858*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1858*FLEN/8, x4, x1, x2)
-
-inst_930:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xa853a7101cfb4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbffa853a7101cfb4; op2val:0x0;
-   valaddr_reg:x3; val_offset:1860*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1860*FLEN/8, x4, x1, x2)
-
-inst_931:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xa853a7101cfb4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbffa853a7101cfb4;
-   valaddr_reg:x3; val_offset:1862*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1862*FLEN/8, x4, x1, x2)
-
-inst_932:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xa853a7101cfb4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xbffa853a7101cfb4;
-   valaddr_reg:x3; val_offset:1864*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1864*FLEN/8, x4, x1, x2)
-
-inst_933:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1866*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1866*FLEN/8, x4, x1, x2)
-
-inst_934:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1868*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1868*FLEN/8, x4, x1, x2)
-
-inst_935:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0bc8069a0dddf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xffd0bc8069a0dddf;
-   valaddr_reg:x3; val_offset:1870*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1870*FLEN/8, x4, x1, x2)
-
-inst_936:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1872*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1872*FLEN/8, x4, x1, x2)
-
-inst_937:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1874*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1874*FLEN/8, x4, x1, x2)
-
-inst_938:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1876*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1876*FLEN/8, x4, x1, x2)
-
-inst_939:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1878*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1878*FLEN/8, x4, x1, x2)
-
-inst_940:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1880*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1880*FLEN/8, x4, x1, x2)
-
-inst_941:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1882*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1882*FLEN/8, x4, x1, x2)
-
-inst_942:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1884*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1884*FLEN/8, x4, x1, x2)
-
-inst_943:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1886*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1886*FLEN/8, x4, x1, x2)
-
-inst_944:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1888*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1888*FLEN/8, x4, x1, x2)
-
-inst_945:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1890*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1890*FLEN/8, x4, x1, x2)
-
-inst_946:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1892*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1892*FLEN/8, x4, x1, x2)
-
-inst_947:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1894*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1894*FLEN/8, x4, x1, x2)
-
-inst_948:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1896*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1896*FLEN/8, x4, x1, x2)
-
-inst_949:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1898*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1898*FLEN/8, x4, x1, x2)
-
-inst_950:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1900*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1900*FLEN/8, x4, x1, x2)
-
-inst_951:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1902*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1902*FLEN/8, x4, x1, x2)
-
-inst_952:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0xac733dc349632 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff9ac733dc349632; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1904*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1904*FLEN/8, x4, x1, x2)
-
-inst_953:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0xac733dc349632 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xff9ac733dc349632;
-   valaddr_reg:x3; val_offset:1906*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1906*FLEN/8, x4, x1, x2)
-
-inst_954:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1908*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1908*FLEN/8, x4, x1, x2)
-
-inst_955:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1910*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1910*FLEN/8, x4, x1, x2)
-
-inst_956:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1912*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1912*FLEN/8, x4, x1, x2)
-
-inst_957:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1914*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1914*FLEN/8, x4, x1, x2)
-
-inst_958:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1916*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1916*FLEN/8, x4, x1, x2)
-
-inst_959:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1918*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1918*FLEN/8, x4, x1, x2)
-
-inst_960:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1920*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1920*FLEN/8, x4, x1, x2)
-
-inst_961:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1922*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1922*FLEN/8, x4, x1, x2)
-
-inst_962:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1924*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1924*FLEN/8, x4, x1, x2)
-
-inst_963:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1926*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1926*FLEN/8, x4, x1, x2)
-
-inst_964:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1928*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1928*FLEN/8, x4, x1, x2)
-
-inst_965:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1930*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1930*FLEN/8, x4, x1, x2)
-
-inst_966:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0e856af141964 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x8000e856af141964;
-   valaddr_reg:x3; val_offset:1932*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1932*FLEN/8, x4, x1, x2)
-
-inst_967:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0e856af141964 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000e856af141964; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1934*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1934*FLEN/8, x4, x1, x2)
-
-inst_968:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1936*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1936*FLEN/8, x4, x1, x2)
-
-inst_969:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1938*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1938*FLEN/8, x4, x1, x2)
-
-inst_970:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1940*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1940*FLEN/8, x4, x1, x2)
-
-inst_971:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1942*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1942*FLEN/8, x4, x1, x2)
-
-inst_972:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x18d1201fedb6b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x80018d1201fedb6b;
-   valaddr_reg:x3; val_offset:1944*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1944*FLEN/8, x4, x1, x2)
-
-inst_973:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x18d1201fedb6b and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80018d1201fedb6b; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1946*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1946*FLEN/8, x4, x1, x2)
-
-inst_974:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1948*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1948*FLEN/8, x4, x1, x2)
-
-inst_975:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x0;
-   valaddr_reg:x3; val_offset:1950*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1950*FLEN/8, x4, x1, x2)
-
-inst_976:
-// fs1 == 1 and fe1 == 0x401 and fm1 == 0x2cde30fb81e08 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc012cde30fb81e08; op2val:0x0;
-   valaddr_reg:x3; val_offset:1952*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1952*FLEN/8, x4, x1, x2)
-
-inst_977:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x2cde30fb81e08 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc012cde30fb81e08;
-   valaddr_reg:x3; val_offset:1954*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1954*FLEN/8, x4, x1, x2)
-
-inst_978:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x401 and fm2 == 0x2cde30fb81e08 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xc012cde30fb81e08;
-   valaddr_reg:x3; val_offset:1956*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1956*FLEN/8, x4, x1, x2)
-
-inst_979:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1958*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1958*FLEN/8, x4, x1, x2)
-
-inst_980:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1960*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1960*FLEN/8, x4, x1, x2)
-
-inst_981:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x1f930d5b2a8f5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xffb1f930d5b2a8f5;
-   valaddr_reg:x3; val_offset:1962*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1962*FLEN/8, x4, x1, x2)
-
-inst_982:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1964*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1964*FLEN/8, x4, x1, x2)
-
-inst_983:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1966*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1966*FLEN/8, x4, x1, x2)
-
-inst_984:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1968*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1968*FLEN/8, x4, x1, x2)
-
-inst_985:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1970*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1970*FLEN/8, x4, x1, x2)
-
-inst_986:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1972*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1972*FLEN/8, x4, x1, x2)
-
-inst_987:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1974*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1974*FLEN/8, x4, x1, x2)
-
-inst_988:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x6777d0b1f5332 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe6777d0b1f5332; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1976*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1976*FLEN/8, x4, x1, x2)
-
-inst_989:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x6777d0b1f5332 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xffe6777d0b1f5332;
-   valaddr_reg:x3; val_offset:1978*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1978*FLEN/8, x4, x1, x2)
-
-inst_990:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1980*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1980*FLEN/8, x4, x1, x2)
-
-inst_991:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1982*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1982*FLEN/8, x4, x1, x2)
-
-inst_992:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1984*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1984*FLEN/8, x4, x1, x2)
-
-inst_993:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1986*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1986*FLEN/8, x4, x1, x2)
-
-inst_994:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1988*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1988*FLEN/8, x4, x1, x2)
-
-inst_995:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1990*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1990*FLEN/8, x4, x1, x2)
-
-inst_996:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1992*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1992*FLEN/8, x4, x1, x2)
-
-inst_997:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x6777d0b1f5332 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe6777d0b1f5332; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1994*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1994*FLEN/8, x4, x1, x2)
-
-inst_998:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1996*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1996*FLEN/8, x4, x1, x2)
-
-inst_999:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x6777d0b1f5332 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe6777d0b1f5332; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1998*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1998*FLEN/8, x4, x1, x2)
-
-inst_1000:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:2000*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2000*FLEN/8, x4, x1, x2)
-
-inst_1001:
-// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0xcc1e7bc510e55 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff7cc1e7bc510e55; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:2002*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2002*FLEN/8, x4, x1, x2)
-
-inst_1002:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0xcc1e7bc510e55 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xff7cc1e7bc510e55;
-   valaddr_reg:x3; val_offset:2004*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2004*FLEN/8, x4, x1, x2)
-
-inst_1003:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:2006*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2006*FLEN/8, x4, x1, x2)
-
-inst_1004:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0e856af141964 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000e856af141964; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:2008*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2008*FLEN/8, x4, x1, x2)
-
-inst_1005:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0e856af141964 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x8000e856af141964;
-   valaddr_reg:x3; val_offset:2010*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2010*FLEN/8, x4, x1, x2)
-
-inst_1006:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:2012*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2012*FLEN/8, x4, x1, x2)
-
-inst_1007:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0e856af141964 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000e856af141964; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:2014*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2014*FLEN/8, x4, x1, x2)
-
-inst_1008:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:2016*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2016*FLEN/8, x4, x1, x2)
-
-inst_1009:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0e856af141964 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000e856af141964; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:2018*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2018*FLEN/8, x4, x1, x2)
-
-inst_1010:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0e856af141964 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x8000e856af141964;
-   valaddr_reg:x3; val_offset:2020*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2020*FLEN/8, x4, x1, x2)
-
-inst_1011:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0e856af141964 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000e856af141964; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:2022*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2022*FLEN/8, x4, x1, x2)
-
-inst_1012:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:2024*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2024*FLEN/8, x4, x1, x2)
-
-inst_1013:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:2026*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2026*FLEN/8, x4, x1, x2)
-
-inst_1014:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x0;
-   valaddr_reg:x3; val_offset:2028*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2028*FLEN/8, x4, x1, x2)
-
-inst_1015:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x431b4a598252a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbff431b4a598252a; op2val:0x0;
-   valaddr_reg:x3; val_offset:2030*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2030*FLEN/8, x4, x1, x2)
-
-inst_1016:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x431b4a598252a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbff431b4a598252a;
-   valaddr_reg:x3; val_offset:2032*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2032*FLEN/8, x4, x1, x2)
-
-inst_1017:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x431b4a598252a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xbff431b4a598252a;
-   valaddr_reg:x3; val_offset:2034*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2034*FLEN/8, x4, x1, x2)
-
-inst_1018:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:2036*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2036*FLEN/8, x4, x1, x2)
-
-inst_1019:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:2038*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2038*FLEN/8, x4, x1, x2)
-
-inst_1020:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x60eeb556ce9ce and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xffd60eeb556ce9ce;
-   valaddr_reg:x3; val_offset:2040*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2040*FLEN/8, x4, x1, x2)
-
-inst_1021:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:2042*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2042*FLEN/8, x4, x1, x2)
-
-inst_1022:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:2044*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2044*FLEN/8, x4, x1, x2)
-
-inst_1023:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:2046*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2046*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_9)
-
-inst_1024:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:2048*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2048*FLEN/8, x4, x1, x2)
-
-inst_1025:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:2050*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2050*FLEN/8, x4, x1, x2)
-
-inst_1026:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:2052*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2052*FLEN/8, x4, x1, x2)
-
-inst_1027:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:2054*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2054*FLEN/8, x4, x1, x2)
-
-inst_1028:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:2056*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2056*FLEN/8, x4, x1, x2)
-
-inst_1029:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:2058*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2058*FLEN/8, x4, x1, x2)
-
-inst_1030:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:2060*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2060*FLEN/8, x4, x1, x2)
-
-inst_1031:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:2062*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2062*FLEN/8, x4, x1, x2)
-
-inst_1032:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:2064*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2064*FLEN/8, x4, x1, x2)
-
-inst_1033:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:2066*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2066*FLEN/8, x4, x1, x2)
-
-inst_1034:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:2068*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2068*FLEN/8, x4, x1, x2)
-
-inst_1035:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:2070*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2070*FLEN/8, x4, x1, x2)
-
-inst_1036:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:2072*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2072*FLEN/8, x4, x1, x2)
-
-inst_1037:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x1a5891123ee3f and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffa1a5891123ee3f; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:2074*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2074*FLEN/8, x4, x1, x2)
-
-inst_1038:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x1a5891123ee3f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xffa1a5891123ee3f;
-   valaddr_reg:x3; val_offset:2076*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2076*FLEN/8, x4, x1, x2)
-
-inst_1039:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:2078*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2078*FLEN/8, x4, x1, x2)
-
-inst_1040:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:2080*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2080*FLEN/8, x4, x1, x2)
-
-inst_1041:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:2082*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2082*FLEN/8, x4, x1, x2)
-
-inst_1042:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:2084*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2084*FLEN/8, x4, x1, x2)
-
-inst_1043:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:2086*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2086*FLEN/8, x4, x1, x2)
-
-inst_1044:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:2088*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2088*FLEN/8, x4, x1, x2)
-
-inst_1045:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:2090*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2090*FLEN/8, x4, x1, x2)
-
-inst_1046:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:2092*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2092*FLEN/8, x4, x1, x2)
-
-inst_1047:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:2094*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2094*FLEN/8, x4, x1, x2)
-
-inst_1048:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:2096*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2096*FLEN/8, x4, x1, x2)
-
-inst_1049:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:2098*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2098*FLEN/8, x4, x1, x2)
-
-inst_1050:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:2100*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2100*FLEN/8, x4, x1, x2)
-
-inst_1051:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:2102*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2102*FLEN/8, x4, x1, x2)
-
-inst_1052:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:2104*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2104*FLEN/8, x4, x1, x2)
-
-inst_1053:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x18d1201fedb6b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x80018d1201fedb6b;
-   valaddr_reg:x3; val_offset:2106*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2106*FLEN/8, x4, x1, x2)
-
-inst_1054:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x18d1201fedb6b and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80018d1201fedb6b; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:2108*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2108*FLEN/8, x4, x1, x2)
-
-inst_1055:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:2110*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2110*FLEN/8, x4, x1, x2)
-
-inst_1056:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x0;
-   valaddr_reg:x3; val_offset:2112*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2112*FLEN/8, x4, x1, x2)
-
-inst_1057:
-// fs1 == 1 and fe1 == 0x401 and fm1 == 0x8c8a47b3dd237 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc018c8a47b3dd237; op2val:0x0;
-   valaddr_reg:x3; val_offset:2114*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2114*FLEN/8, x4, x1, x2)
-
-inst_1058:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x8c8a47b3dd237 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc018c8a47b3dd237;
-   valaddr_reg:x3; val_offset:2116*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2116*FLEN/8, x4, x1, x2)
-
-inst_1059:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x8c8a47b3dd237 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xc018c8a47b3dd237;
-   valaddr_reg:x3; val_offset:2118*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2118*FLEN/8, x4, x1, x2)
-
-inst_1060:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:2120*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2120*FLEN/8, x4, x1, x2)
-
-inst_1061:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:2122*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2122*FLEN/8, x4, x1, x2)
-
-inst_1062:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xeb781eb40c69d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xffbeb781eb40c69d;
-   valaddr_reg:x3; val_offset:2124*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2124*FLEN/8, x4, x1, x2)
-
-inst_1063:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:2126*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2126*FLEN/8, x4, x1, x2)
-
-inst_1064:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:2128*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2128*FLEN/8, x4, x1, x2)
-
-inst_1065:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:2130*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2130*FLEN/8, x4, x1, x2)
-
-inst_1066:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:2132*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2132*FLEN/8, x4, x1, x2)
-
-inst_1067:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:2134*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2134*FLEN/8, x4, x1, x2)
-
-inst_1068:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:2136*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2136*FLEN/8, x4, x1, x2)
-
-inst_1069:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:2138*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2138*FLEN/8, x4, x1, x2)
-
-inst_1070:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:2140*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2140*FLEN/8, x4, x1, x2)
-
-inst_1071:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:2142*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2142*FLEN/8, x4, x1, x2)
-
-inst_1072:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:2144*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2144*FLEN/8, x4, x1, x2)
-
-inst_1073:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:2146*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2146*FLEN/8, x4, x1, x2)
-
-inst_1074:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:2148*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2148*FLEN/8, x4, x1, x2)
-
-inst_1075:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:2150*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2150*FLEN/8, x4, x1, x2)
-
-inst_1076:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:2152*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2152*FLEN/8, x4, x1, x2)
-
-inst_1077:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:2154*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2154*FLEN/8, x4, x1, x2)
-
-inst_1078:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:2156*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2156*FLEN/8, x4, x1, x2)
-
-inst_1079:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x892ce55cd6bb0 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff8892ce55cd6bb0; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:2158*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2158*FLEN/8, x4, x1, x2)
-
-inst_1080:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x892ce55cd6bb0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xff8892ce55cd6bb0;
-   valaddr_reg:x3; val_offset:2160*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2160*FLEN/8, x4, x1, x2)
-
-inst_1081:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:2162*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2162*FLEN/8, x4, x1, x2)
-
-inst_1082:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x18d1201fedb6b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80018d1201fedb6b; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:2164*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2164*FLEN/8, x4, x1, x2)
-
-inst_1083:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x18d1201fedb6b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x80018d1201fedb6b;
-   valaddr_reg:x3; val_offset:2166*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2166*FLEN/8, x4, x1, x2)
-
-inst_1084:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:2168*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2168*FLEN/8, x4, x1, x2)
-
-inst_1085:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x18d1201fedb6b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80018d1201fedb6b; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:2170*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2170*FLEN/8, x4, x1, x2)
-
-inst_1086:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:2172*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2172*FLEN/8, x4, x1, x2)
-
-inst_1087:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x18d1201fedb6b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80018d1201fedb6b; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:2174*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2174*FLEN/8, x4, x1, x2)
-
-inst_1088:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x0;
-   valaddr_reg:x3; val_offset:2176*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2176*FLEN/8, x4, x1, x2)
-
-inst_1089:
-// fs1 == 1 and fe1 == 0x400 and fm1 == 0x1418de01443c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc001418de01443c7; op2val:0x0;
-   valaddr_reg:x3; val_offset:2178*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2178*FLEN/8, x4, x1, x2)
-
-inst_1090:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x1418de01443c7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc001418de01443c7;
-   valaddr_reg:x3; val_offset:2180*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2180*FLEN/8, x4, x1, x2)
-
-inst_1091:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x1418de01443c7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xc001418de01443c7;
-   valaddr_reg:x3; val_offset:2182*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2182*FLEN/8, x4, x1, x2)
-
-inst_1092:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:2184*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2184*FLEN/8, x4, x1, x2)
-
-inst_1093:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:2186*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2186*FLEN/8, x4, x1, x2)
-
-inst_1094:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:2188*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2188*FLEN/8, x4, x1, x2)
-
-inst_1095:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:2190*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2190*FLEN/8, x4, x1, x2)
-
-inst_1096:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:2192*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2192*FLEN/8, x4, x1, x2)
-
-inst_1097:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:2194*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2194*FLEN/8, x4, x1, x2)
-
-inst_1098:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:2196*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2196*FLEN/8, x4, x1, x2)
-
-inst_1099:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:2198*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2198*FLEN/8, x4, x1, x2)
-
-inst_1100:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:2200*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2200*FLEN/8, x4, x1, x2)
-
-inst_1101:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:2202*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2202*FLEN/8, x4, x1, x2)
-
-inst_1102:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:2204*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2204*FLEN/8, x4, x1, x2)
-
-inst_1103:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:2206*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2206*FLEN/8, x4, x1, x2)
-
-inst_1104:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:2208*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2208*FLEN/8, x4, x1, x2)
-
-inst_1105:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:2210*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2210*FLEN/8, x4, x1, x2)
-
-inst_1106:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:2212*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2212*FLEN/8, x4, x1, x2)
-
-inst_1107:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:2214*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2214*FLEN/8, x4, x1, x2)
-
-inst_1108:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:2216*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2216*FLEN/8, x4, x1, x2)
-
-inst_1109:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:2218*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2218*FLEN/8, x4, x1, x2)
-
-inst_1110:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:2220*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2220*FLEN/8, x4, x1, x2)
-
-inst_1111:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:2222*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2222*FLEN/8, x4, x1, x2)
-
-inst_1112:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:2224*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2224*FLEN/8, x4, x1, x2)
-
-inst_1113:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:2226*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2226*FLEN/8, x4, x1, x2)
-
-inst_1114:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:2228*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2228*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
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-NAN_BOXED(9226726907712872489,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(9225926626876390883,64,FLEN)
-NAN_BOXED(9234145997515084564,64,FLEN)
-NAN_BOXED(9225926626876390883,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9234145997515084564,64,FLEN)
-NAN_BOXED(9223808620313893739,64,FLEN)
-NAN_BOXED(9223808620313893739,64,FLEN)
-NAN_BOXED(9234145997515084564,64,FLEN)
-NAN_BOXED(9234145997515084564,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13842034063491060279,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13842034063491060279,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(13842034063491060279,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9205695020795655555,64,FLEN)
-NAN_BOXED(18428368493872203421,64,FLEN)
-NAN_BOXED(9205695020795655555,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18428368493872203421,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9214282603439747961,64,FLEN)
-NAN_BOXED(18428368493872203421,64,FLEN)
-NAN_BOXED(9214282603439747961,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9203113735090898319,64,FLEN)
-NAN_BOXED(18428368493872203421,64,FLEN)
-NAN_BOXED(9203113735090898319,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9216727246563283396,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9209096066353683787,64,FLEN)
-NAN_BOXED(18428368493872203421,64,FLEN)
-NAN_BOXED(9209096066353683787,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18429722854496529440,64,FLEN)
-NAN_BOXED(18428368493872203421,64,FLEN)
-NAN_BOXED(18429722854496529440,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18438191818498403262,64,FLEN)
-NAN_BOXED(18428368493872203421,64,FLEN)
-NAN_BOXED(18438191818498403262,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18441985142712778316,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18442221504440006550,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18423106200321465408,64,FLEN)
-NAN_BOXED(18413128491404716976,64,FLEN)
-NAN_BOXED(18423106200321465408,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18413128491404716976,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(2005845601180795,64,FLEN)
-NAN_BOXED(9223808620313893739,64,FLEN)
-NAN_BOXED(2005845601180795,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9223808620313893739,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9224323542291873999,64,FLEN)
-NAN_BOXED(9223808620313893739,64,FLEN)
-NAN_BOXED(9224323542291873999,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(9223808620313893739,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13835411607864492999,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13835411607864492999,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(13835411607864492999,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9205695020795655555,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9214282603439747961,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9203113735090898319,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9216727246563283396,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9209096066353683787,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18429722854496529440,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18438191818498403262,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18441985142712778316,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18442221504440006550,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18423106200321465408,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(3439735089418121,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2934513869151469,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(3763951410582788,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2005845601180795,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(4059668362200610,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9226726907712872489,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9224323542291873999,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9225926626876390883,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9205695020795655555,64,FLEN)
-NAN_BOXED(9214282603439747961,64,FLEN)
-NAN_BOXED(9203113735090898319,64,FLEN)
-NAN_BOXED(9205695020795655555,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_7:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_8:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_9:
-    .fill 182*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmaxm_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmaxm_b1-01.S
deleted file mode 100644
index cabd93e68..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmaxm_b1-01.S
+++ /dev/null
@@ -1,449 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:05:51 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmaxm.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmaxm.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fmaxm_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rs2 == rd, rs1==f31, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f31; op2:f31; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rs2 != rd, rs1==f29, rs2==f29, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f29; op2:f29; dest:f30; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f30, rs2==f28, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f30; op2:f28; dest:f29; op1val:0x0; op2val:0x1;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f29, f30, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs2 == rd != rs1, rs1==f28, rs2==f27, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f28; op2:f27; dest:f27; op1val:0x0; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f27, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rd != rs2, rs1==f26, rs2==f30, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f26; op2:f30; dest:f26; op1val:0x0; op2val:0x2;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f26, f26, f30, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f27, rs2==f26, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f27; op2:f26; dest:f28; op1val:0x0; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f28, f27, f26, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f23, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f24; op2:f23; dest:f25; op1val:0x0; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f25, f24, f23, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f23, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f23; op2:f25; dest:f24; op1val:0x0; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f24, f23, f25, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f25, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f25; op2:f24; dest:f23; op1val:0x0; op2val:0x800000;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f23, f25, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rs2==f20, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f21; op2:f20; dest:f22; op1val:0x0; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f22, f21, f20, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x800001;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f22, rs2==f21, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f22; op2:f21; dest:f20; op1val:0x0; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f20, f22, f21, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f17, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f18; op2:f17; dest:f19; op1val:0x0; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f19, f18, f17, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f17, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f17; op2:f19; dest:f18; op1val:0x0; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f18, f17, f19, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f19, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f19; op2:f18; dest:f17; op1val:0x0; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f17, f19, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rs2==f14, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f15; op2:f14; dest:f16; op1val:0x0; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f16, f15, f14, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f16, rs2==f15, rd==f14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f16; op2:f15; dest:f14; op1val:0x0; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f14, f16, f15, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f11, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f12; op2:f11; dest:f13; op1val:0x0; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f13, f12, f11, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f11, rs2==f13, rd==f12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f11; op2:f13; dest:f12; op1val:0x0; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f12, f11, f13, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f13, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f13; op2:f12; dest:f11; op1val:0x0; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f11, f13, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rs2==f8, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f9; op2:f8; dest:f10; op1val:0x0; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f10, f9, f8, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f10, rs2==f9, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f10; op2:f9; dest:f8; op1val:0x0; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f8, f10, f9, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f5, rd==f7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f6; op2:f5; dest:f7; op1val:0x80000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f7, f6, f5, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f5, rs2==f7, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f5; op2:f7; dest:f6; op1val:0x80000000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f6, f5, f7, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f7, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f7; op2:f6; dest:f5; op1val:0x80000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f5, f7, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rs2==f2, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f3; op2:f2; dest:f4; op1val:0x80000000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f4, f3, f2, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f2; op2:f4; dest:f3; op1val:0x80000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f4, rs2==f3, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f4; op2:f3; dest:f2; op1val:0x80000000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f2, f4, f3, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f1; op2:f30; dest:f31; op1val:0x80000000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f1, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f0; op2:f30; dest:f31; op1val:0x80000000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f0, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f30; op2:f1; dest:f31; op1val:0x80000000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f1, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f30; op2:f0; dest:f31; op1val:0x80000000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f0, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// rd==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f1; op1val:0x80000000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f1, f31, f30, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// rd==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f0; op1val:0x80000000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f0, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 72*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmaxm_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmaxm_b19-01.S
deleted file mode 100644
index ffb48fa3a..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmaxm_b19-01.S
+++ /dev/null
@@ -1,449 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:05:51 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmaxm.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmaxm.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fmaxm_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rs2 == rd, rs1==f31, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f31; op2:f31; dest:f31; op1val:0x7dce622b; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rs2 != rd, rs1==f29, rs2==f29, rd==f30,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f29; op2:f29; dest:f30; op1val:0x7dce622b; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f30, rs2==f28, rd==f29,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x183299 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f30; op2:f28; dest:f29; op1val:0x7f7fffff; op2val:0x7d183299;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f29, f30, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs2 == rd != rs1, rs1==f28, rs2==f27, rd==f27,fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f28; op2:f27; dest:f27; op1val:0x7d183299; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f27, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rd != rs2, rs1==f26, rs2==f30, rd==f26,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f26; op2:f30; dest:f26; op1val:0x7f7fffff; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f26, f26, f30, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f27, rs2==f26, rd==f28,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f27; op2:f26; dest:f28; op1val:0x7dce622b; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f28, f27, f26, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f23, rd==f25,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f24; op2:f23; dest:f25; op1val:0x7dce622b; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f25, f24, f23, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f23, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f23; op2:f25; dest:f24; op1val:0x7d902b16; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f24, f23, f25, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f25, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f25; op2:f24; dest:f23; op1val:0x7dce622b; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f23, f25, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rs2==f20, rd==f22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x6a2c24 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f21; op2:f20; dest:f22; op1val:0x7f7fffff; op2val:0x7d6a2c24;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f22, f21, f20, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f20; op2:f22; dest:f21; op1val:0x7d6a2c24; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f22, rs2==f21, rd==f20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f22; op2:f21; dest:f20; op1val:0x7f7fffff; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f20, f22, f21, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f17, rd==f19,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f18; op2:f17; dest:f19; op1val:0x7dce622b; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f19, f18, f17, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f17, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f17; op2:f19; dest:f18; op1val:0x7e2fb07b; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f18, f17, f19, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f19, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f19; op2:f18; dest:f17; op1val:0x7dce622b; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f17, f19, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rs2==f14, rd==f16,fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f15; op2:f14; dest:f16; op1val:0xfdea577e; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f16, f15, f14, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f14; op2:f16; dest:f15; op1val:0x7dce622b; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f16, rs2==f15, rd==f14,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x291dc8 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f16; op2:f15; dest:f14; op1val:0x7f7fffff; op2val:0xfd291dc8;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f14, f16, f15, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f11, rd==f13,fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f12; op2:f11; dest:f13; op1val:0xfd291dc8; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f13, f12, f11, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f11, rs2==f13, rd==f12,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f11; op2:f13; dest:f12; op1val:0x7f7fffff; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f12, f11, f13, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f13, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f13; op2:f12; dest:f11; op1val:0x7dce622b; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f11, f13, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rs2==f8, rd==f10,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x153eee and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f9; op2:f8; dest:f10; op1val:0x7f7fffff; op2val:0xfd953eee;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f10, f9, f8, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f8; op2:f10; dest:f9; op1val:0xfd953eee; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f10, rs2==f9, rd==f8,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f10; op2:f9; dest:f8; op1val:0x7f7fffff; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f8, f10, f9, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f5, rd==f7,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f6; op2:f5; dest:f7; op1val:0x7dce622b; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f7, f6, f5, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f5, rs2==f7, rd==f6,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x1946c8 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f5; op2:f7; dest:f6; op1val:0x7f7fffff; op2val:0xfd9946c8;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f6, f5, f7, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f7, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f7; op2:f6; dest:f5; op1val:0xfd9946c8; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f5, f7, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rs2==f2, rd==f4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f3; op2:f2; dest:f4; op1val:0x7f7fffff; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f4, f3, f2, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f2; op2:f4; dest:f3; op1val:0x7dce622b; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f4, rs2==f3, rd==f2,fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f4; op2:f3; dest:f2; op1val:0xfd2820df; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f2, f4, f3, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f1,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f1; op2:f30; dest:f31; op1val:0x7dce622b; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f1, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x07167c and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f0; op2:f30; dest:f31; op1val:0x255707; op2val:0x7e07167c;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f0, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f1,fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f30; op2:f1; dest:f31; op1val:0x7e07167c; op2val:0x255707;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f1, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rs2==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f30; op2:f0; dest:f31; op1val:0x255707; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f0, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// rd==f1,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f1; op1val:0x7dce622b; op2val:0x255707;
-   valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f1, f31, f30, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// rd==f0,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f0; op1val:0x7dce622b; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f0, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2104110116,32,FLEN)
-NAN_BOXED(2104110116,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4247330248,32,FLEN)
-NAN_BOXED(4247330248,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4254416622,32,FLEN)
-NAN_BOXED(4254416622,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4254680776,32,FLEN)
-NAN_BOXED(4254680776,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(3203502,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2114393724,32,FLEN)
-NAN_BOXED(2114393724,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(3203502,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2732978,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 72*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fminm.d_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fminm.d_b1-01.S
deleted file mode 100644
index 7ab6d67b5..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fminm.d_b1-01.S
+++ /dev/null
@@ -1,5889 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:10:38 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fminm.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fminm.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fminm.d_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fminm.d_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs2 == rd != rs1, rs1==f30, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f31; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rs2 != rd, rs1==f29, rs2==f29, rd==f30,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f29; op2:f29; dest:f30; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f31, rs2==f30, rd==f29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f31; op2:f30; dest:f29; op1val:0x0; op2val:0x1;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f29, f31, f30, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 == rd != rs2, rs1==f28, rs2==f27, rd==f28,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f28; op2:f27; dest:f28; op1val:0x0; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rs2 == rd, rs1==f26, rs2==f26, rd==f26,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f26; op2:f26; dest:f26; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f26, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f25, rs2==f28, rd==f27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f25; op2:f28; dest:f27; op1val:0x0; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f27, f25, f28, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f27, rs2==f24, rd==f25,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f27; op2:f24; dest:f25; op1val:0x0; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f25, f27, f24, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f23, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f23; op2:f25; dest:f24; op1val:0x0; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f24, f23, f25, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f24, rs2==f22, rd==f23,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f24; op2:f22; dest:f23; op1val:0x0; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f23, f24, f22, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rs2==f23, rd==f22,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f21; op2:f23; dest:f22; op1val:0x0; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f22, f21, f23, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f22, rs2==f20, rd==f21,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f22; op2:f20; dest:f21; op1val:0x0; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f21, f22, f20, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f19, rs2==f21, rd==f20,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f19; op2:f21; dest:f20; op1val:0x0; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f20, f19, f21, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f20, rs2==f18, rd==f19,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f20; op2:f18; dest:f19; op1val:0x0; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f19, f20, f18, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f17, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f17; op2:f19; dest:f18; op1val:0x0; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f18, f17, f19, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f18, rs2==f16, rd==f17,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f18; op2:f16; dest:f17; op1val:0x0; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f17, f18, f16, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rs2==f17, rd==f16,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f15; op2:f17; dest:f16; op1val:0x0; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f16, f15, f17, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f16, rs2==f14, rd==f15,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f16; op2:f14; dest:f15; op1val:0x0; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f15, f16, f14, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f13, rs2==f15, rd==f14,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f13; op2:f15; dest:f14; op1val:0x0; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f14, f13, f15, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f14, rs2==f12, rd==f13,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f14; op2:f12; dest:f13; op1val:0x0; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f13, f14, f12, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f11, rs2==f13, rd==f12,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f11; op2:f13; dest:f12; op1val:0x0; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f12, f11, f13, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f12, rs2==f10, rd==f11,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f12; op2:f10; dest:f11; op1val:0x0; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f11, f12, f10, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rs2==f11, rd==f10,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f9; op2:f11; dest:f10; op1val:0x0; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f10, f9, f11, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f10, rs2==f8, rd==f9,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f10; op2:f8; dest:f9; op1val:0x0; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f9, f10, f8, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f7, rs2==f9, rd==f8,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f7; op2:f9; dest:f8; op1val:0x0; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f8, f7, f9, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f8, rs2==f6, rd==f7,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f8; op2:f6; dest:f7; op1val:0x8000000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f7, f8, f6, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f5, rs2==f7, rd==f6,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f5; op2:f7; dest:f6; op1val:0x8000000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f6, f5, f7, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f6, rs2==f4, rd==f5,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f6; op2:f4; dest:f5; op1val:0x8000000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f5, f6, f4, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rs2==f5, rd==f4,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f3; op2:f5; dest:f4; op1val:0x8000000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f4, f3, f5, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f4, rs2==f2, rd==f3,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f4; op2:f2; dest:f3; op1val:0x8000000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f3, f4, f2, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f1, rs2==f3, rd==f2,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f1; op2:f3; dest:f2; op1val:0x8000000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f2, f1, f3, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f2, rs2==f0, rd==f1,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f2; op2:f0; dest:f1; op1val:0x8000000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f1, f2, f0, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f0; op2:f30; dest:f31; op1val:0x8000000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f0, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f1,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f1; dest:f31; op1val:0x8000000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f1, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rd==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f31; op2:f30; dest:f0; op1val:0x8000000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:72*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:74*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:76*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:78*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:80*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:82*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:84*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:86*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:88*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:90*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:92*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:94*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x0;
-   valaddr_reg:x3; val_offset:96*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:98*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x1;
-   valaddr_reg:x3; val_offset:100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x2;
-   valaddr_reg:x3; val_offset:104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x0;
-   valaddr_reg:x3; val_offset:192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x1;
-   valaddr_reg:x3; val_offset:196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x2;
-   valaddr_reg:x3; val_offset:200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x0;
-   valaddr_reg:x3; val_offset:240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x1;
-   valaddr_reg:x3; val_offset:244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x2;
-   valaddr_reg:x3; val_offset:248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x0;
-   valaddr_reg:x3; val_offset:480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x1;
-   valaddr_reg:x3; val_offset:484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x2;
-   valaddr_reg:x3; val_offset:488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x0;
-   valaddr_reg:x3; val_offset:528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x1;
-   valaddr_reg:x3; val_offset:532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x2;
-   valaddr_reg:x3; val_offset:536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:990*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:992*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:994*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:996*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:998*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1000*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1002*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1004*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1006*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:1008*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:1010*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:1012*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:1014*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:1016*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:1018*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:1020*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:1022*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:1024*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:1026*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:1028*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:1030*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:1032*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:1034*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1036*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1038*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:1040*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:1042*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:1044*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:1046*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1048*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1050*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1052*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1054*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1056*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:1058*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1060*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:1062*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1064*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:1066*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:1068*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:1070*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:1072*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:1074*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:1076*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:1078*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:1080*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:1082*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1084*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1086*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:1088*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:1090*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:1092*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:1094*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1096*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1098*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:1106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:1110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:1114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:1116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:1118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:1120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:1122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:1124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:1126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:1128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:1130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:1136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:1138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:1140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:1142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:1152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x2;
-   valaddr_reg:x3; val_offset:1154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
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-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(2,64,FLEN)
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-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
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-NAN_BOXED(18444492273895866369,64,FLEN)
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-NAN_BOXED(18444492273895866369,64,FLEN)
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-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(1,64,FLEN)
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-NAN_BOXED(9218868437227405313,64,FLEN)
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-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
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-NAN_BOXED(9227875636482146304,64,FLEN)
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-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
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-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
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-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
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-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(2,64,FLEN)
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-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
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-NAN_BOXED(2,64,FLEN)
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-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
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-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
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-NAN_BOXED(18442240474082181119,64,FLEN)
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-NAN_BOXED(9221120237041090560,64,FLEN)
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-NAN_BOXED(18444492273895866368,64,FLEN)
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-NAN_BOXED(13799029258263199744,64,FLEN)
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-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 132*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fminm.d_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fminm.d_b19-01.S
deleted file mode 100644
index 0fb7ae049..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fminm.d_b19-01.S
+++ /dev/null
@@ -1,11109 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:10:38 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fminm.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fminm.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fminm.d_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fminm.d_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs2 == rd != rs1, rs1==f30, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f31; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rs2 != rd, rs1==f29, rs2==f29, rd==f30,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f29; op2:f29; dest:f30; op1val:0x7feb0580f98a7dbd; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f31, rs2==f30, rd==f29,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f31; op2:f30; dest:f29; op1val:0x7fb59e00c7a1fe31; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f29, f31, f30, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 == rd != rs2, rs1==f28, rs2==f27, rd==f28,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x59e00c7a1fe31 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f28; op2:f27; dest:f28; op1val:0x7ff0000000000000; op2val:0x7fb59e00c7a1fe31;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rs2 == rd, rs1==f26, rs2==f26, rd==f26,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f26; op2:f26; dest:f26; op1val:0x7fb59e00c7a1fe31; op2val:0x7fb59e00c7a1fe31;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f26, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f25, rs2==f28, rd==f27,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x59e00c7a1fe31 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f25; op2:f28; dest:f27; op1val:0x7feb0580f98a7dbd; op2val:0x7fb59e00c7a1fe31;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f27, f25, f28, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f27, rs2==f24, rd==f25,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f27; op2:f24; dest:f25; op1val:0x7feb0580f98a7dbd; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f25, f27, f24, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f23, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f23; op2:f25; dest:f24; op1val:0x7fb59e00c7a1fe31; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f24, f23, f25, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f24, rs2==f22, rd==f23,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f24; op2:f22; dest:f23; op1val:0x7feb0580f98a7dbd; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f23, f24, f22, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rs2==f23, rd==f22,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f21; op2:f23; dest:f22; op1val:0x7fb59e00c7a1fe31; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f22, f21, f23, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f22, rs2==f20, rd==f21,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f22; op2:f20; dest:f21; op1val:0x7feb0580f98a7dbd; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f21, f22, f20, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f19, rs2==f21, rd==f20,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f19; op2:f21; dest:f20; op1val:0x7fed1ca42e21585b; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f20, f19, f21, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f20, rs2==f18, rd==f19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f20; op2:f18; dest:f19; op1val:0x7feb0580f98a7dbd; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f19, f20, f18, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f17, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f17; op2:f19; dest:f18; op1val:0x7fb59e00c7a1fe31; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f18, f17, f19, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f18, rs2==f16, rd==f17,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x59e00c7a1fe31 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f18; op2:f16; dest:f17; op1val:0xfff0000000000000; op2val:0x7fb59e00c7a1fe31;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f17, f18, f16, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rs2==f17, rd==f16,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f15; op2:f17; dest:f16; op1val:0x7fb59e00c7a1fe31; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f16, f15, f17, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f16, rs2==f14, rd==f15,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f16; op2:f14; dest:f15; op1val:0x7feb0580f98a7dbd; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f15, f16, f14, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f13, rs2==f15, rd==f14,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f13; op2:f15; dest:f14; op1val:0xffe30ac79053ba62; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f14, f13, f15, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f14, rs2==f12, rd==f13,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f14; op2:f12; dest:f13; op1val:0x7feb0580f98a7dbd; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f13, f14, f12, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f11, rs2==f13, rd==f12,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f11; op2:f13; dest:f12; op1val:0x7fb59e00c7a1fe31; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f12, f11, f13, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f12, rs2==f10, rd==f11,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f12; op2:f10; dest:f11; op1val:0x7feb0580f98a7dbd; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f11, f12, f10, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rs2==f11, rd==f10,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f9; op2:f11; dest:f10; op1val:0x7fb59e00c7a1fe31; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f10, f9, f11, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f10, rs2==f8, rd==f9,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f10; op2:f8; dest:f9; op1val:0x7feb0580f98a7dbd; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f9, f10, f8, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f7, rs2==f9, rd==f8,fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x14b33d2e7fe8d and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f7; op2:f9; dest:f8; op1val:0x7f814b33d2e7fe8d; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f8, f7, f9, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f8, rs2==f6, rd==f7,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x14b33d2e7fe8d and  fcsr == 0  
-/* opcode: fminm.d ; op1:f8; op2:f6; dest:f7; op1val:0xfff0000000000000; op2val:0x7f814b33d2e7fe8d;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f7, f8, f6, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f5, rs2==f7, rd==f6,fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x14b33d2e7fe8d and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f5; op2:f7; dest:f6; op1val:0x7f814b33d2e7fe8d; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f6, f5, f7, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f6, rs2==f4, rd==f5,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x14b33d2e7fe8d and  fcsr == 0  
-/* opcode: fminm.d ; op1:f6; op2:f4; dest:f5; op1val:0x7feb0580f98a7dbd; op2val:0x7f814b33d2e7fe8d;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f5, f6, f4, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rs2==f5, rd==f4,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f3; op2:f5; dest:f4; op1val:0x7feb0580f98a7dbd; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f4, f3, f5, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f4, rs2==f2, rd==f3,fs1 == 0 and fe1 == 0x000 and fm1 == 0x11770f6c9c8eb and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f4; op2:f2; dest:f3; op1val:0x11770f6c9c8eb; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f3, f4, f2, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f1, rs2==f3, rd==f2,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x11770f6c9c8eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f1; op2:f3; dest:f2; op1val:0x7ff0000000000000; op2val:0x11770f6c9c8eb;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f2, f1, f3, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f2, rs2==f0, rd==f1,fs1 == 0 and fe1 == 0x000 and fm1 == 0x11770f6c9c8eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f2; op2:f0; dest:f1; op1val:0x11770f6c9c8eb; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f1, f2, f0, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f0,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0x11770f6c9c8eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f0; op2:f30; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x11770f6c9c8eb;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f0, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f1,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f1; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f1, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rd==f0,fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xf0b5e103c0954 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f31; op2:f30; dest:f0; op1val:0xaea69a3e1d929; op2val:0x7fef0b5e103c0954;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xf0b5e103c0954 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fef0b5e103c0954; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:72*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:74*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:76*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:78*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:80*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:82*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x87dfc3c4343fa and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0x7fe87dfc3c4343fa;
-   valaddr_reg:x3; val_offset:84*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x87dfc3c4343fa and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe87dfc3c4343fa; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:86*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:88*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:90*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:92*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:94*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd5a40c379c682 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0xffed5a40c379c682;
-   valaddr_reg:x3; val_offset:96*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd5a40c379c682 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed5a40c379c682; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:98*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb9818fe1eccda and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0xffeb9818fe1eccda;
-   valaddr_reg:x3; val_offset:104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb9818fe1eccda and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffeb9818fe1eccda; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x39e41023e1389 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0xffe39e41023e1389;
-   valaddr_reg:x3; val_offset:112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x39e41023e1389 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe39e41023e1389; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xdaf87e09a11da and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0xffedaf87e09a11da;
-   valaddr_reg:x3; val_offset:120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xdaf87e09a11da and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffedaf87e09a11da; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x11770f6c9c8eb and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x11770f6c9c8eb; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x11770f6c9c8eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x11770f6c9c8eb;
-   valaddr_reg:x3; val_offset:130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x11770f6c9c8eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x11770f6c9c8eb; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x0;
-   valaddr_reg:x3; val_offset:134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x849c649169268 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff849c649169268; op2val:0x0;
-   valaddr_reg:x3; val_offset:136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x849c649169268 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ff849c649169268;
-   valaddr_reg:x3; val_offset:138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x849c649169268 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x3ff849c649169268;
-   valaddr_reg:x3; val_offset:140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x74a1cf1b446af and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7fb74a1cf1b446af;
-   valaddr_reg:x3; val_offset:160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xe77a5b3b92a36 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xffae77a5b3b92a36;
-   valaddr_reg:x3; val_offset:172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xa2d6149828b3c and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x608daef2c2520 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7faa2d6149828b3c; op2val:0xffc608daef2c2520;
-   valaddr_reg:x3; val_offset:188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xa2d6149828b3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0x7faa2d6149828b3c;
-   valaddr_reg:x3; val_offset:190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xa2d6149828b3c and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7faa2d6149828b3c; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xa2d6149828b3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x7faa2d6149828b3c;
-   valaddr_reg:x3; val_offset:194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x69bf113fe2b81 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x0a8686b58e06e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x69bf113fe2b81; op2val:0x7fe0a8686b58e06e;
-   valaddr_reg:x3; val_offset:198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x69bf113fe2b81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x69bf113fe2b81;
-   valaddr_reg:x3; val_offset:200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x69bf113fe2b81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x69bf113fe2b81; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x69bf113fe2b81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x69bf113fe2b81;
-   valaddr_reg:x3; val_offset:204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8d5e4d9c9a110 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x7fb8d5e4d9c9a110;
-   valaddr_reg:x3; val_offset:208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xcc6497dd9aeac and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x7fbcc6497dd9aeac;
-   valaddr_reg:x3; val_offset:218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x397fcfd029cc8 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x7fb397fcfd029cc8;
-   valaddr_reg:x3; val_offset:226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x9ac314c1e5de7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x7fb9ac314c1e5de7;
-   valaddr_reg:x3; val_offset:234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x77b6702c7d202 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0xffb77b6702c7d202;
-   valaddr_reg:x3; val_offset:242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x6134731b23d7b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0xffb6134731b23d7b;
-   valaddr_reg:x3; val_offset:250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf639b36c9b8db and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0xffaf639b36c9b8db;
-   valaddr_reg:x3; val_offset:258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7bf9fe6e1a7e1 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0xffb7bf9fe6e1a7e1;
-   valaddr_reg:x3; val_offset:266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x69bf113fe2b81 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xefff2c6cde040 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x69bf113fe2b81; op2val:0xffbefff2c6cde040;
-   valaddr_reg:x3; val_offset:274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x69bf113fe2b81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x69bf113fe2b81;
-   valaddr_reg:x3; val_offset:276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x69bf113fe2b81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x69bf113fe2b81; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x0;
-   valaddr_reg:x3; val_offset:280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 0 and fe1 == 0x402 and fm1 == 0x261de7cadff67 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x402261de7cadff67; op2val:0x0;
-   valaddr_reg:x3; val_offset:282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x261de7cadff67 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x402261de7cadff67;
-   valaddr_reg:x3; val_offset:284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x261de7cadff67 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x402261de7cadff67;
-   valaddr_reg:x3; val_offset:286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0x866da024aa0c9 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x608daef2c2520 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fa866da024aa0c9; op2val:0xffc608daef2c2520;
-   valaddr_reg:x3; val_offset:316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0x866da024aa0c9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0x7fa866da024aa0c9;
-   valaddr_reg:x3; val_offset:318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0x866da024aa0c9 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fa866da024aa0c9; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x7fa and fm2 == 0x866da024aa0c9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x7fa866da024aa0c9;
-   valaddr_reg:x3; val_offset:322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6292f14fe32c9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x0a8686b58e06e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6292f14fe32c9; op2val:0x7fe0a8686b58e06e;
-   valaddr_reg:x3; val_offset:326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6292f14fe32c9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x6292f14fe32c9;
-   valaddr_reg:x3; val_offset:328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6292f14fe32c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6292f14fe32c9; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6292f14fe32c9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x6292f14fe32c9;
-   valaddr_reg:x3; val_offset:332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8d5e4d9c9a110 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x7fb8d5e4d9c9a110;
-   valaddr_reg:x3; val_offset:336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xcc6497dd9aeac and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x7fbcc6497dd9aeac;
-   valaddr_reg:x3; val_offset:346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x397fcfd029cc8 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x7fb397fcfd029cc8;
-   valaddr_reg:x3; val_offset:354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x9ac314c1e5de7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x7fb9ac314c1e5de7;
-   valaddr_reg:x3; val_offset:362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x77b6702c7d202 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0xffb77b6702c7d202;
-   valaddr_reg:x3; val_offset:370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x6134731b23d7b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0xffb6134731b23d7b;
-   valaddr_reg:x3; val_offset:378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf639b36c9b8db and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0xffaf639b36c9b8db;
-   valaddr_reg:x3; val_offset:386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7bf9fe6e1a7e1 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0xffb7bf9fe6e1a7e1;
-   valaddr_reg:x3; val_offset:394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6292f14fe32c9 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xefff2c6cde040 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6292f14fe32c9; op2val:0xffbefff2c6cde040;
-   valaddr_reg:x3; val_offset:402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6292f14fe32c9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x6292f14fe32c9;
-   valaddr_reg:x3; val_offset:404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6292f14fe32c9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6292f14fe32c9; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x0;
-   valaddr_reg:x3; val_offset:408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0x402 and fm1 == 0x122b0391ed653 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x402122b0391ed653; op2val:0x0;
-   valaddr_reg:x3; val_offset:410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x122b0391ed653 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x402122b0391ed653;
-   valaddr_reg:x3; val_offset:412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x402 and fm2 == 0x122b0391ed653 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x402122b0391ed653;
-   valaddr_reg:x3; val_offset:414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 0 and fe1 == 0x7f9 and fm1 == 0xcdc35c1c9eb3f and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x608daef2c2520 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f9cdc35c1c9eb3f; op2val:0xffc608daef2c2520;
-   valaddr_reg:x3; val_offset:440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 0 and fe2 == 0x7f9 and fm2 == 0xcdc35c1c9eb3f and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0x7f9cdc35c1c9eb3f;
-   valaddr_reg:x3; val_offset:442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 0 and fe1 == 0x7f9 and fm1 == 0xcdc35c1c9eb3f and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f9cdc35c1c9eb3f; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x7f9 and fm2 == 0xcdc35c1c9eb3f and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x7f9cdc35c1c9eb3f;
-   valaddr_reg:x3; val_offset:446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3a4acd3b9460c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x0a8686b58e06e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3a4acd3b9460c; op2val:0x7fe0a8686b58e06e;
-   valaddr_reg:x3; val_offset:450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3a4acd3b9460c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x3a4acd3b9460c;
-   valaddr_reg:x3; val_offset:452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3a4acd3b9460c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3a4acd3b9460c; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3a4acd3b9460c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x3a4acd3b9460c;
-   valaddr_reg:x3; val_offset:456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8d5e4d9c9a110 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x7fb8d5e4d9c9a110;
-   valaddr_reg:x3; val_offset:460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xcc6497dd9aeac and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x7fbcc6497dd9aeac;
-   valaddr_reg:x3; val_offset:470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x397fcfd029cc8 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x7fb397fcfd029cc8;
-   valaddr_reg:x3; val_offset:478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x9ac314c1e5de7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x7fb9ac314c1e5de7;
-   valaddr_reg:x3; val_offset:486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x77b6702c7d202 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0xffb77b6702c7d202;
-   valaddr_reg:x3; val_offset:494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x6134731b23d7b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0xffb6134731b23d7b;
-   valaddr_reg:x3; val_offset:502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf639b36c9b8db and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0xffaf639b36c9b8db;
-   valaddr_reg:x3; val_offset:510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7bf9fe6e1a7e1 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0xffb7bf9fe6e1a7e1;
-   valaddr_reg:x3; val_offset:518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3a4acd3b9460c and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xefff2c6cde040 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3a4acd3b9460c; op2val:0xffbefff2c6cde040;
-   valaddr_reg:x3; val_offset:526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3a4acd3b9460c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x3a4acd3b9460c;
-   valaddr_reg:x3; val_offset:528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3a4acd3b9460c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3a4acd3b9460c; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x0;
-   valaddr_reg:x3; val_offset:532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 0 and fe1 == 0x401 and fm1 == 0x4442d6ffe75f4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x4014442d6ffe75f4; op2val:0x0;
-   valaddr_reg:x3; val_offset:534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x401 and fm2 == 0x4442d6ffe75f4 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x4014442d6ffe75f4;
-   valaddr_reg:x3; val_offset:536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x401 and fm2 == 0x4442d6ffe75f4 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x4014442d6ffe75f4;
-   valaddr_reg:x3; val_offset:538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x74a1cf1b446af and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x7fb74a1cf1b446af;
-   valaddr_reg:x3; val_offset:546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x74a1cf1b446af and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7fb74a1cf1b446af;
-   valaddr_reg:x3; val_offset:560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x2a1b0c15d0559 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f82a1b0c15d0559; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x2a1b0c15d0559 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7f82a1b0c15d0559;
-   valaddr_reg:x3; val_offset:580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x2a1b0c15d0559 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f82a1b0c15d0559; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x2a1b0c15d0559 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x7f82a1b0c15d0559;
-   valaddr_reg:x3; val_offset:584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x12d0f0ec06819 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x12d0f0ec06819; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x12d0f0ec06819 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x12d0f0ec06819;
-   valaddr_reg:x3; val_offset:590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x12d0f0ec06819 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x12d0f0ec06819; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x12d0f0ec06819 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x12d0f0ec06819;
-   valaddr_reg:x3; val_offset:594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xf0b5e103c0954 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x7fef0b5e103c0954;
-   valaddr_reg:x3; val_offset:598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xf0b5e103c0954 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fef0b5e103c0954; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x87dfc3c4343fa and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x7fe87dfc3c4343fa;
-   valaddr_reg:x3; val_offset:616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x87dfc3c4343fa and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe87dfc3c4343fa; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd5a40c379c682 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0xffed5a40c379c682;
-   valaddr_reg:x3; val_offset:628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd5a40c379c682 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed5a40c379c682; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb9818fe1eccda and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0xffeb9818fe1eccda;
-   valaddr_reg:x3; val_offset:636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb9818fe1eccda and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffeb9818fe1eccda; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x39e41023e1389 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0xffe39e41023e1389;
-   valaddr_reg:x3; val_offset:644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x39e41023e1389 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe39e41023e1389; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xdaf87e09a11da and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0xffedaf87e09a11da;
-   valaddr_reg:x3; val_offset:652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xdaf87e09a11da and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffedaf87e09a11da; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x12d0f0ec06819 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x12d0f0ec06819; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x12d0f0ec06819 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x12d0f0ec06819;
-   valaddr_reg:x3; val_offset:662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x12d0f0ec06819 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x12d0f0ec06819; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x0;
-   valaddr_reg:x3; val_offset:666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xa2ac7f4a5aece and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ffa2ac7f4a5aece; op2val:0x0;
-   valaddr_reg:x3; val_offset:668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xa2ac7f4a5aece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ffa2ac7f4a5aece;
-   valaddr_reg:x3; val_offset:670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xa2ac7f4a5aece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x3ffa2ac7f4a5aece;
-   valaddr_reg:x3; val_offset:672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xe77a5b3b92a36 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffae77a5b3b92a36;
-   valaddr_reg:x3; val_offset:688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x8c9148167a613 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x608daef2c2520 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff98c9148167a613; op2val:0xffc608daef2c2520;
-   valaddr_reg:x3; val_offset:704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x8c9148167a613 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0xff98c9148167a613;
-   valaddr_reg:x3; val_offset:706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x8c9148167a613 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff98c9148167a613; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x8c9148167a613 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xff98c9148167a613;
-   valaddr_reg:x3; val_offset:710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x320fdfdfa4c3c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x0a8686b58e06e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800320fdfdfa4c3c; op2val:0x7fe0a8686b58e06e;
-   valaddr_reg:x3; val_offset:714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x320fdfdfa4c3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x800320fdfdfa4c3c;
-   valaddr_reg:x3; val_offset:716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x320fdfdfa4c3c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800320fdfdfa4c3c; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x320fdfdfa4c3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x800320fdfdfa4c3c;
-   valaddr_reg:x3; val_offset:720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8d5e4d9c9a110 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x7fb8d5e4d9c9a110;
-   valaddr_reg:x3; val_offset:724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xcc6497dd9aeac and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x7fbcc6497dd9aeac;
-   valaddr_reg:x3; val_offset:734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x397fcfd029cc8 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x7fb397fcfd029cc8;
-   valaddr_reg:x3; val_offset:742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x9ac314c1e5de7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x7fb9ac314c1e5de7;
-   valaddr_reg:x3; val_offset:750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x77b6702c7d202 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0xffb77b6702c7d202;
-   valaddr_reg:x3; val_offset:758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x6134731b23d7b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0xffb6134731b23d7b;
-   valaddr_reg:x3; val_offset:766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf639b36c9b8db and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0xffaf639b36c9b8db;
-   valaddr_reg:x3; val_offset:774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7bf9fe6e1a7e1 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0xffb7bf9fe6e1a7e1;
-   valaddr_reg:x3; val_offset:782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x320fdfdfa4c3c and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xefff2c6cde040 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800320fdfdfa4c3c; op2val:0xffbefff2c6cde040;
-   valaddr_reg:x3; val_offset:790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x320fdfdfa4c3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x800320fdfdfa4c3c;
-   valaddr_reg:x3; val_offset:792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x320fdfdfa4c3c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800320fdfdfa4c3c; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x0;
-   valaddr_reg:x3; val_offset:796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 1 and fe1 == 0x401 and fm1 == 0x167aab18a177e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc01167aab18a177e; op2val:0x0;
-   valaddr_reg:x3; val_offset:798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x167aab18a177e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc01167aab18a177e;
-   valaddr_reg:x3; val_offset:800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x167aab18a177e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xc01167aab18a177e;
-   valaddr_reg:x3; val_offset:802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xe77a5b3b92a36 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xffae77a5b3b92a36;
-   valaddr_reg:x3; val_offset:810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0x85fb7c2fa882b and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff785fb7c2fa882b; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0x85fb7c2fa882b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xff785fb7c2fa882b;
-   valaddr_reg:x3; val_offset:836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0x85fb7c2fa882b and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff785fb7c2fa882b; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0x85fb7c2fa882b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xff785fb7c2fa882b;
-   valaddr_reg:x3; val_offset:840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c4ec3fe9a819 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000c4ec3fe9a819; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0c4ec3fe9a819 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8000c4ec3fe9a819;
-   valaddr_reg:x3; val_offset:846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c4ec3fe9a819 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000c4ec3fe9a819; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0c4ec3fe9a819 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x8000c4ec3fe9a819;
-   valaddr_reg:x3; val_offset:850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xf0b5e103c0954 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x7fef0b5e103c0954;
-   valaddr_reg:x3; val_offset:854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xf0b5e103c0954 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fef0b5e103c0954; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x87dfc3c4343fa and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x7fe87dfc3c4343fa;
-   valaddr_reg:x3; val_offset:872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x87dfc3c4343fa and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe87dfc3c4343fa; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd5a40c379c682 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0xffed5a40c379c682;
-   valaddr_reg:x3; val_offset:884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd5a40c379c682 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed5a40c379c682; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb9818fe1eccda and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0xffeb9818fe1eccda;
-   valaddr_reg:x3; val_offset:892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb9818fe1eccda and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffeb9818fe1eccda; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x39e41023e1389 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0xffe39e41023e1389;
-   valaddr_reg:x3; val_offset:900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x39e41023e1389 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe39e41023e1389; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xdaf87e09a11da and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0xffedaf87e09a11da;
-   valaddr_reg:x3; val_offset:908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xdaf87e09a11da and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffedaf87e09a11da; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c4ec3fe9a819 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000c4ec3fe9a819; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0c4ec3fe9a819 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8000c4ec3fe9a819;
-   valaddr_reg:x3; val_offset:918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c4ec3fe9a819 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000c4ec3fe9a819; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x0;
-   valaddr_reg:x3; val_offset:922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x11dadc9e4eb85 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbff11dadc9e4eb85; op2val:0x0;
-   valaddr_reg:x3; val_offset:924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x11dadc9e4eb85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbff11dadc9e4eb85;
-   valaddr_reg:x3; val_offset:926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x11dadc9e4eb85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xbff11dadc9e4eb85;
-   valaddr_reg:x3; val_offset:928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x554b1e717e738 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x608daef2c2520 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffa554b1e717e738; op2val:0xffc608daef2c2520;
-   valaddr_reg:x3; val_offset:946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x554b1e717e738 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0xffa554b1e717e738;
-   valaddr_reg:x3; val_offset:948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x554b1e717e738 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffa554b1e717e738; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x554b1e717e738 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xffa554b1e717e738;
-   valaddr_reg:x3; val_offset:952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x562b29f60d7ba and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x0a8686b58e06e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800562b29f60d7ba; op2val:0x7fe0a8686b58e06e;
-   valaddr_reg:x3; val_offset:956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x562b29f60d7ba and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x800562b29f60d7ba;
-   valaddr_reg:x3; val_offset:958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x562b29f60d7ba and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800562b29f60d7ba; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x562b29f60d7ba and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x800562b29f60d7ba;
-   valaddr_reg:x3; val_offset:962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8d5e4d9c9a110 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x7fb8d5e4d9c9a110;
-   valaddr_reg:x3; val_offset:966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xcc6497dd9aeac and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x7fbcc6497dd9aeac;
-   valaddr_reg:x3; val_offset:976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x397fcfd029cc8 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x7fb397fcfd029cc8;
-   valaddr_reg:x3; val_offset:984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:990*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x9ac314c1e5de7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x7fb9ac314c1e5de7;
-   valaddr_reg:x3; val_offset:992*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:994*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:996*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:998*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x77b6702c7d202 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0xffb77b6702c7d202;
-   valaddr_reg:x3; val_offset:1000*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:1002*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1004*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1006*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x6134731b23d7b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0xffb6134731b23d7b;
-   valaddr_reg:x3; val_offset:1008*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:1010*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1012*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1014*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf639b36c9b8db and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0xffaf639b36c9b8db;
-   valaddr_reg:x3; val_offset:1016*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:1018*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1020*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1022*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7bf9fe6e1a7e1 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0xffb7bf9fe6e1a7e1;
-   valaddr_reg:x3; val_offset:1024*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:1026*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1028*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1030*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x562b29f60d7ba and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xefff2c6cde040 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800562b29f60d7ba; op2val:0xffbefff2c6cde040;
-   valaddr_reg:x3; val_offset:1032*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x562b29f60d7ba and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x800562b29f60d7ba;
-   valaddr_reg:x3; val_offset:1034*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x562b29f60d7ba and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800562b29f60d7ba; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1036*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x0;
-   valaddr_reg:x3; val_offset:1038*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0x401 and fm1 == 0xdf542c221f050 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc01df542c221f050; op2val:0x0;
-   valaddr_reg:x3; val_offset:1040*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0xdf542c221f050 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc01df542c221f050;
-   valaddr_reg:x3; val_offset:1042*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x401 and fm2 == 0xdf542c221f050 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xc01df542c221f050;
-   valaddr_reg:x3; val_offset:1044*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1046*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1048*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1050*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1052*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1054*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1056*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x901723ec94233 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x608daef2c2520 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff9901723ec94233; op2val:0xffc608daef2c2520;
-   valaddr_reg:x3; val_offset:1058*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x901723ec94233 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0xff9901723ec94233;
-   valaddr_reg:x3; val_offset:1060*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x901723ec94233 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff9901723ec94233; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1062*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x901723ec94233 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xff9901723ec94233;
-   valaddr_reg:x3; val_offset:1064*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1066*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x3281b93f72b1c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x0a8686b58e06e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8003281b93f72b1c; op2val:0x7fe0a8686b58e06e;
-   valaddr_reg:x3; val_offset:1068*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x3281b93f72b1c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x8003281b93f72b1c;
-   valaddr_reg:x3; val_offset:1070*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x3281b93f72b1c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8003281b93f72b1c; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1072*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x3281b93f72b1c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x8003281b93f72b1c;
-   valaddr_reg:x3; val_offset:1074*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1076*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8d5e4d9c9a110 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x7fb8d5e4d9c9a110;
-   valaddr_reg:x3; val_offset:1078*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1080*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1082*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1084*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1086*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xcc6497dd9aeac and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x7fbcc6497dd9aeac;
-   valaddr_reg:x3; val_offset:1088*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1090*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1092*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1094*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x397fcfd029cc8 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x7fb397fcfd029cc8;
-   valaddr_reg:x3; val_offset:1096*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1098*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x9ac314c1e5de7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x7fb9ac314c1e5de7;
-   valaddr_reg:x3; val_offset:1104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x77b6702c7d202 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0xffb77b6702c7d202;
-   valaddr_reg:x3; val_offset:1112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x6134731b23d7b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0xffb6134731b23d7b;
-   valaddr_reg:x3; val_offset:1120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf639b36c9b8db and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0xffaf639b36c9b8db;
-   valaddr_reg:x3; val_offset:1128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7bf9fe6e1a7e1 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0xffb7bf9fe6e1a7e1;
-   valaddr_reg:x3; val_offset:1136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x3281b93f72b1c and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xefff2c6cde040 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8003281b93f72b1c; op2val:0xffbefff2c6cde040;
-   valaddr_reg:x3; val_offset:1144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x3281b93f72b1c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x8003281b93f72b1c;
-   valaddr_reg:x3; val_offset:1146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x3281b93f72b1c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8003281b93f72b1c; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x0;
-   valaddr_reg:x3; val_offset:1150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 1 and fe1 == 0x401 and fm1 == 0x18f3f99f3a7ab and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc0118f3f99f3a7ab; op2val:0x0;
-   valaddr_reg:x3; val_offset:1152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x18f3f99f3a7ab and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc0118f3f99f3a7ab;
-   valaddr_reg:x3; val_offset:1154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-
-inst_578:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x18f3f99f3a7ab and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xc0118f3f99f3a7ab;
-   valaddr_reg:x3; val_offset:1156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1156*FLEN/8, x4, x1, x2)
-
-inst_579:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1158*FLEN/8, x4, x1, x2)
-
-inst_580:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1160*FLEN/8, x4, x1, x2)
-
-inst_581:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1162*FLEN/8, x4, x1, x2)
-
-inst_582:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1164*FLEN/8, x4, x1, x2)
-
-inst_583:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1166*FLEN/8, x4, x1, x2)
-
-inst_584:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x608daef2c2520 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xffc608daef2c2520;
-   valaddr_reg:x3; val_offset:1168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1168*FLEN/8, x4, x1, x2)
-
-inst_585:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1170*FLEN/8, x4, x1, x2)
-
-inst_586:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1172*FLEN/8, x4, x1, x2)
-
-inst_587:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1174*FLEN/8, x4, x1, x2)
-
-inst_588:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1176*FLEN/8, x4, x1, x2)
-
-inst_589:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1178*FLEN/8, x4, x1, x2)
-
-inst_590:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1180*FLEN/8, x4, x1, x2)
-
-inst_591:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1182*FLEN/8, x4, x1, x2)
-
-inst_592:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1184*FLEN/8, x4, x1, x2)
-
-inst_593:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1186*FLEN/8, x4, x1, x2)
-
-inst_594:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1188*FLEN/8, x4, x1, x2)
-
-inst_595:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1190*FLEN/8, x4, x1, x2)
-
-inst_596:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1192*FLEN/8, x4, x1, x2)
-
-inst_597:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1194*FLEN/8, x4, x1, x2)
-
-inst_598:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x239ac7113abba and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xaa70d788e33e4 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800239ac7113abba; op2val:0x7faaa70d788e33e4;
-   valaddr_reg:x3; val_offset:1196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1196*FLEN/8, x4, x1, x2)
-
-inst_599:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xaa70d788e33e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x239ac7113abba and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7faaa70d788e33e4; op2val:0x800239ac7113abba;
-   valaddr_reg:x3; val_offset:1198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1198*FLEN/8, x4, x1, x2)
-
-inst_600:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x239ac7113abba and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800239ac7113abba; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1200*FLEN/8, x4, x1, x2)
-
-inst_601:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x239ac7113abba and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x800239ac7113abba;
-   valaddr_reg:x3; val_offset:1202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1202*FLEN/8, x4, x1, x2)
-
-inst_602:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1204*FLEN/8, x4, x1, x2)
-
-inst_603:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x3de50ae3ae740 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x7f83de50ae3ae740;
-   valaddr_reg:x3; val_offset:1206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1206*FLEN/8, x4, x1, x2)
-
-inst_604:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x3de50ae3ae740 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f83de50ae3ae740; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1208*FLEN/8, x4, x1, x2)
-
-inst_605:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1210*FLEN/8, x4, x1, x2)
-
-inst_606:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1212*FLEN/8, x4, x1, x2)
-
-inst_607:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1214*FLEN/8, x4, x1, x2)
-
-inst_608:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x7050797e15889 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x7f87050797e15889;
-   valaddr_reg:x3; val_offset:1216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1216*FLEN/8, x4, x1, x2)
-
-inst_609:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x7050797e15889 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f87050797e15889; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1218*FLEN/8, x4, x1, x2)
-
-inst_610:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1220*FLEN/8, x4, x1, x2)
-
-inst_611:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1222*FLEN/8, x4, x1, x2)
-
-inst_612:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xf5994c8042e0c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x7f7f5994c8042e0c;
-   valaddr_reg:x3; val_offset:1224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1224*FLEN/8, x4, x1, x2)
-
-inst_613:
-// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xf5994c8042e0c and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f7f5994c8042e0c; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1226*FLEN/8, x4, x1, x2)
-
-inst_614:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1228*FLEN/8, x4, x1, x2)
-
-inst_615:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1230*FLEN/8, x4, x1, x2)
-
-inst_616:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x489c109b1e4b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x7f8489c109b1e4b9;
-   valaddr_reg:x3; val_offset:1232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1232*FLEN/8, x4, x1, x2)
-
-inst_617:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x489c109b1e4b9 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f8489c109b1e4b9; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1234*FLEN/8, x4, x1, x2)
-
-inst_618:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1236*FLEN/8, x4, x1, x2)
-
-inst_619:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1238*FLEN/8, x4, x1, x2)
-
-inst_620:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x2c91f356ca801 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0xff82c91f356ca801;
-   valaddr_reg:x3; val_offset:1240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1240*FLEN/8, x4, x1, x2)
-
-inst_621:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x2c91f356ca801 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff82c91f356ca801; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1242*FLEN/8, x4, x1, x2)
-
-inst_622:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1244*FLEN/8, x4, x1, x2)
-
-inst_623:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1246*FLEN/8, x4, x1, x2)
-
-inst_624:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x1a905c15b6463 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0xff81a905c15b6463;
-   valaddr_reg:x3; val_offset:1248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1248*FLEN/8, x4, x1, x2)
-
-inst_625:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x1a905c15b6463 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff81a905c15b6463; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1250*FLEN/8, x4, x1, x2)
-
-inst_626:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1252*FLEN/8, x4, x1, x2)
-
-inst_627:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1254*FLEN/8, x4, x1, x2)
-
-inst_628:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0x91c7c2bd493e3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0xff791c7c2bd493e3;
-   valaddr_reg:x3; val_offset:1256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1256*FLEN/8, x4, x1, x2)
-
-inst_629:
-// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0x91c7c2bd493e3 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff791c7c2bd493e3; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1258*FLEN/8, x4, x1, x2)
-
-inst_630:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1260*FLEN/8, x4, x1, x2)
-
-inst_631:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1262*FLEN/8, x4, x1, x2)
-
-inst_632:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x2ffb31f1aecb4 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0xff82ffb31f1aecb4;
-   valaddr_reg:x3; val_offset:1264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1264*FLEN/8, x4, x1, x2)
-
-inst_633:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x2ffb31f1aecb4 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff82ffb31f1aecb4; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1266*FLEN/8, x4, x1, x2)
-
-inst_634:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1268*FLEN/8, x4, x1, x2)
-
-inst_635:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1270*FLEN/8, x4, x1, x2)
-
-inst_636:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x239ac7113abba and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x8ccc238a4b367 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800239ac7113abba; op2val:0xff88ccc238a4b367;
-   valaddr_reg:x3; val_offset:1272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1272*FLEN/8, x4, x1, x2)
-
-inst_637:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x8ccc238a4b367 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x239ac7113abba and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff88ccc238a4b367; op2val:0x800239ac7113abba;
-   valaddr_reg:x3; val_offset:1274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1274*FLEN/8, x4, x1, x2)
-
-inst_638:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x239ac7113abba and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800239ac7113abba; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1276*FLEN/8, x4, x1, x2)
-
-inst_639:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x0;
-   valaddr_reg:x3; val_offset:1278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1278*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_6)
-
-inst_640:
-// fs1 == 1 and fe1 == 0x400 and fm1 == 0x8c1d44531ee36 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc008c1d44531ee36; op2val:0x0;
-   valaddr_reg:x3; val_offset:1280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1280*FLEN/8, x4, x1, x2)
-
-inst_641:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x8c1d44531ee36 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc008c1d44531ee36;
-   valaddr_reg:x3; val_offset:1282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1282*FLEN/8, x4, x1, x2)
-
-inst_642:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x8c1d44531ee36 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xc008c1d44531ee36;
-   valaddr_reg:x3; val_offset:1284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1284*FLEN/8, x4, x1, x2)
-
-inst_643:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1286*FLEN/8, x4, x1, x2)
-
-inst_644:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1288*FLEN/8, x4, x1, x2)
-
-inst_645:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1290*FLEN/8, x4, x1, x2)
-
-inst_646:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1292*FLEN/8, x4, x1, x2)
-
-inst_647:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1294*FLEN/8, x4, x1, x2)
-
-inst_648:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x0a8686b58e06e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7fe0a8686b58e06e;
-   valaddr_reg:x3; val_offset:1296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1296*FLEN/8, x4, x1, x2)
-
-inst_649:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1298*FLEN/8, x4, x1, x2)
-
-inst_650:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1300*FLEN/8, x4, x1, x2)
-
-inst_651:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1302*FLEN/8, x4, x1, x2)
-
-inst_652:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1304*FLEN/8, x4, x1, x2)
-
-inst_653:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1306*FLEN/8, x4, x1, x2)
-
-inst_654:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1308*FLEN/8, x4, x1, x2)
-
-inst_655:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1310*FLEN/8, x4, x1, x2)
-
-inst_656:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1312*FLEN/8, x4, x1, x2)
-
-inst_657:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1314*FLEN/8, x4, x1, x2)
-
-inst_658:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1316*FLEN/8, x4, x1, x2)
-
-inst_659:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1318*FLEN/8, x4, x1, x2)
-
-inst_660:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1320*FLEN/8, x4, x1, x2)
-
-inst_661:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1322*FLEN/8, x4, x1, x2)
-
-inst_662:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xaa70d788e33e4 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7faaa70d788e33e4; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1324*FLEN/8, x4, x1, x2)
-
-inst_663:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xaa70d788e33e4 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7faaa70d788e33e4;
-   valaddr_reg:x3; val_offset:1326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1326*FLEN/8, x4, x1, x2)
-
-inst_664:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1328*FLEN/8, x4, x1, x2)
-
-inst_665:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1410b3d2a7d0c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x1410b3d2a7d0c;
-   valaddr_reg:x3; val_offset:1330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1330*FLEN/8, x4, x1, x2)
-
-inst_666:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1410b3d2a7d0c and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1410b3d2a7d0c; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1332*FLEN/8, x4, x1, x2)
-
-inst_667:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1334*FLEN/8, x4, x1, x2)
-
-inst_668:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1336*FLEN/8, x4, x1, x2)
-
-inst_669:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1338*FLEN/8, x4, x1, x2)
-
-inst_670:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x173f689a4c8c6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x173f689a4c8c6;
-   valaddr_reg:x3; val_offset:1340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1340*FLEN/8, x4, x1, x2)
-
-inst_671:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x173f689a4c8c6 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x173f689a4c8c6; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1342*FLEN/8, x4, x1, x2)
-
-inst_672:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1344*FLEN/8, x4, x1, x2)
-
-inst_673:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1346*FLEN/8, x4, x1, x2)
-
-inst_674:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0fd48b05c2121 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0xfd48b05c2121;
-   valaddr_reg:x3; val_offset:1348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1348*FLEN/8, x4, x1, x2)
-
-inst_675:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fd48b05c2121 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfd48b05c2121; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1350*FLEN/8, x4, x1, x2)
-
-inst_676:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1352*FLEN/8, x4, x1, x2)
-
-inst_677:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1354*FLEN/8, x4, x1, x2)
-
-inst_678:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x14bdd6f520473 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x14bdd6f520473;
-   valaddr_reg:x3; val_offset:1356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1356*FLEN/8, x4, x1, x2)
-
-inst_679:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x14bdd6f520473 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x14bdd6f520473; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1358*FLEN/8, x4, x1, x2)
-
-inst_680:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1360*FLEN/8, x4, x1, x2)
-
-inst_681:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1362*FLEN/8, x4, x1, x2)
-
-inst_682:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x12f8c3601c4a9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x80012f8c3601c4a9;
-   valaddr_reg:x3; val_offset:1364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1364*FLEN/8, x4, x1, x2)
-
-inst_683:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12f8c3601c4a9 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80012f8c3601c4a9; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1366*FLEN/8, x4, x1, x2)
-
-inst_684:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1368*FLEN/8, x4, x1, x2)
-
-inst_685:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1370*FLEN/8, x4, x1, x2)
-
-inst_686:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x11d5cf49b3fa7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x80011d5cf49b3fa7;
-   valaddr_reg:x3; val_offset:1372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1372*FLEN/8, x4, x1, x2)
-
-inst_687:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11d5cf49b3fa7 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80011d5cf49b3fa7; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1374*FLEN/8, x4, x1, x2)
-
-inst_688:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1376*FLEN/8, x4, x1, x2)
-
-inst_689:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1378*FLEN/8, x4, x1, x2)
-
-inst_690:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0cae158f8de83 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x8000cae158f8de83;
-   valaddr_reg:x3; val_offset:1380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1380*FLEN/8, x4, x1, x2)
-
-inst_691:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0cae158f8de83 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000cae158f8de83; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1382*FLEN/8, x4, x1, x2)
-
-inst_692:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1384*FLEN/8, x4, x1, x2)
-
-inst_693:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1386*FLEN/8, x4, x1, x2)
-
-inst_694:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x132fe1b33da32 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x800132fe1b33da32;
-   valaddr_reg:x3; val_offset:1388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1388*FLEN/8, x4, x1, x2)
-
-inst_695:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x132fe1b33da32 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800132fe1b33da32; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1390*FLEN/8, x4, x1, x2)
-
-inst_696:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1392*FLEN/8, x4, x1, x2)
-
-inst_697:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1394*FLEN/8, x4, x1, x2)
-
-inst_698:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1396*FLEN/8, x4, x1, x2)
-
-inst_699:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x0;
-   valaddr_reg:x3; val_offset:1398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1398*FLEN/8, x4, x1, x2)
-
-inst_700:
-// fs1 == 0 and fe1 == 0x402 and fm1 == 0x2b74f7c4aeb28 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x4022b74f7c4aeb28; op2val:0x0;
-   valaddr_reg:x3; val_offset:1400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1400*FLEN/8, x4, x1, x2)
-
-inst_701:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x2b74f7c4aeb28 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x4022b74f7c4aeb28;
-   valaddr_reg:x3; val_offset:1402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1402*FLEN/8, x4, x1, x2)
-
-inst_702:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x402 and fm2 == 0x2b74f7c4aeb28 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x4022b74f7c4aeb28;
-   valaddr_reg:x3; val_offset:1404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1404*FLEN/8, x4, x1, x2)
-
-inst_703:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1406*FLEN/8, x4, x1, x2)
-
-inst_704:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xf0b5e103c0954 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fef0b5e103c0954; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1408*FLEN/8, x4, x1, x2)
-
-inst_705:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xf0b5e103c0954 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7fef0b5e103c0954;
-   valaddr_reg:x3; val_offset:1410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1410*FLEN/8, x4, x1, x2)
-
-inst_706:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1412*FLEN/8, x4, x1, x2)
-
-inst_707:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1414*FLEN/8, x4, x1, x2)
-
-inst_708:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1416*FLEN/8, x4, x1, x2)
-
-inst_709:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8d5e4d9c9a110 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7fb8d5e4d9c9a110;
-   valaddr_reg:x3; val_offset:1418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1418*FLEN/8, x4, x1, x2)
-
-inst_710:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1420*FLEN/8, x4, x1, x2)
-
-inst_711:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1422*FLEN/8, x4, x1, x2)
-
-inst_712:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1424*FLEN/8, x4, x1, x2)
-
-inst_713:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1426*FLEN/8, x4, x1, x2)
-
-inst_714:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1428*FLEN/8, x4, x1, x2)
-
-inst_715:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xf0b5e103c0954 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fef0b5e103c0954; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1430*FLEN/8, x4, x1, x2)
-
-inst_716:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1432*FLEN/8, x4, x1, x2)
-
-inst_717:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1434*FLEN/8, x4, x1, x2)
-
-inst_718:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1436*FLEN/8, x4, x1, x2)
-
-inst_719:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xf0b5e103c0954 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fef0b5e103c0954; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1438*FLEN/8, x4, x1, x2)
-
-inst_720:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1440*FLEN/8, x4, x1, x2)
-
-inst_721:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1442*FLEN/8, x4, x1, x2)
-
-inst_722:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1444*FLEN/8, x4, x1, x2)
-
-inst_723:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1446*FLEN/8, x4, x1, x2)
-
-inst_724:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1448*FLEN/8, x4, x1, x2)
-
-inst_725:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x3de50ae3ae740 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f83de50ae3ae740; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1450*FLEN/8, x4, x1, x2)
-
-inst_726:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x3de50ae3ae740 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7f83de50ae3ae740;
-   valaddr_reg:x3; val_offset:1452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1452*FLEN/8, x4, x1, x2)
-
-inst_727:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1454*FLEN/8, x4, x1, x2)
-
-inst_728:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1410b3d2a7d0c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1410b3d2a7d0c; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1456*FLEN/8, x4, x1, x2)
-
-inst_729:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1410b3d2a7d0c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x1410b3d2a7d0c;
-   valaddr_reg:x3; val_offset:1458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1458*FLEN/8, x4, x1, x2)
-
-inst_730:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1460*FLEN/8, x4, x1, x2)
-
-inst_731:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1462*FLEN/8, x4, x1, x2)
-
-inst_732:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1464*FLEN/8, x4, x1, x2)
-
-inst_733:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1466*FLEN/8, x4, x1, x2)
-
-inst_734:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1468*FLEN/8, x4, x1, x2)
-
-inst_735:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1470*FLEN/8, x4, x1, x2)
-
-inst_736:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1472*FLEN/8, x4, x1, x2)
-
-inst_737:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1474*FLEN/8, x4, x1, x2)
-
-inst_738:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1476*FLEN/8, x4, x1, x2)
-
-inst_739:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1478*FLEN/8, x4, x1, x2)
-
-inst_740:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1480*FLEN/8, x4, x1, x2)
-
-inst_741:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1482*FLEN/8, x4, x1, x2)
-
-inst_742:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1484*FLEN/8, x4, x1, x2)
-
-inst_743:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1486*FLEN/8, x4, x1, x2)
-
-inst_744:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1488*FLEN/8, x4, x1, x2)
-
-inst_745:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1410b3d2a7d0c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1410b3d2a7d0c; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:1490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1490*FLEN/8, x4, x1, x2)
-
-inst_746:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1410b3d2a7d0c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x1410b3d2a7d0c;
-   valaddr_reg:x3; val_offset:1492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1492*FLEN/8, x4, x1, x2)
-
-inst_747:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1410b3d2a7d0c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1410b3d2a7d0c; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1494*FLEN/8, x4, x1, x2)
-
-inst_748:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x0;
-   valaddr_reg:x3; val_offset:1496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1496*FLEN/8, x4, x1, x2)
-
-inst_749:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xbe776c4b9309a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ffbe776c4b9309a; op2val:0x0;
-   valaddr_reg:x3; val_offset:1498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1498*FLEN/8, x4, x1, x2)
-
-inst_750:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xbe776c4b9309a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ffbe776c4b9309a;
-   valaddr_reg:x3; val_offset:1500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1500*FLEN/8, x4, x1, x2)
-
-inst_751:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xbe776c4b9309a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x3ffbe776c4b9309a;
-   valaddr_reg:x3; val_offset:1502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1502*FLEN/8, x4, x1, x2)
-
-inst_752:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1504*FLEN/8, x4, x1, x2)
-
-inst_753:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1506*FLEN/8, x4, x1, x2)
-
-inst_754:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1508*FLEN/8, x4, x1, x2)
-
-inst_755:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1510*FLEN/8, x4, x1, x2)
-
-inst_756:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1512*FLEN/8, x4, x1, x2)
-
-inst_757:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xcc6497dd9aeac and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7fbcc6497dd9aeac;
-   valaddr_reg:x3; val_offset:1514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1514*FLEN/8, x4, x1, x2)
-
-inst_758:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1516*FLEN/8, x4, x1, x2)
-
-inst_759:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1518*FLEN/8, x4, x1, x2)
-
-inst_760:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1520*FLEN/8, x4, x1, x2)
-
-inst_761:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1522*FLEN/8, x4, x1, x2)
-
-inst_762:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1524*FLEN/8, x4, x1, x2)
-
-inst_763:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1526*FLEN/8, x4, x1, x2)
-
-inst_764:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1528*FLEN/8, x4, x1, x2)
-
-inst_765:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1530*FLEN/8, x4, x1, x2)
-
-inst_766:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1532*FLEN/8, x4, x1, x2)
-
-inst_767:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1534*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_7)
-
-inst_768:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1536*FLEN/8, x4, x1, x2)
-
-inst_769:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1538*FLEN/8, x4, x1, x2)
-
-inst_770:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1540*FLEN/8, x4, x1, x2)
-
-inst_771:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x7050797e15889 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f87050797e15889; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1542*FLEN/8, x4, x1, x2)
-
-inst_772:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x7050797e15889 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7f87050797e15889;
-   valaddr_reg:x3; val_offset:1544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1544*FLEN/8, x4, x1, x2)
-
-inst_773:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1546*FLEN/8, x4, x1, x2)
-
-inst_774:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x173f689a4c8c6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x173f689a4c8c6; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1548*FLEN/8, x4, x1, x2)
-
-inst_775:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x173f689a4c8c6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x173f689a4c8c6;
-   valaddr_reg:x3; val_offset:1550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1550*FLEN/8, x4, x1, x2)
-
-inst_776:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1552*FLEN/8, x4, x1, x2)
-
-inst_777:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1554*FLEN/8, x4, x1, x2)
-
-inst_778:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1556*FLEN/8, x4, x1, x2)
-
-inst_779:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1558*FLEN/8, x4, x1, x2)
-
-inst_780:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1560*FLEN/8, x4, x1, x2)
-
-inst_781:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1562*FLEN/8, x4, x1, x2)
-
-inst_782:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1564*FLEN/8, x4, x1, x2)
-
-inst_783:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1566*FLEN/8, x4, x1, x2)
-
-inst_784:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1568*FLEN/8, x4, x1, x2)
-
-inst_785:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1570*FLEN/8, x4, x1, x2)
-
-inst_786:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1572*FLEN/8, x4, x1, x2)
-
-inst_787:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1574*FLEN/8, x4, x1, x2)
-
-inst_788:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1576*FLEN/8, x4, x1, x2)
-
-inst_789:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x173f689a4c8c6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x173f689a4c8c6; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:1578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1578*FLEN/8, x4, x1, x2)
-
-inst_790:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0x173f689a4c8c6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x173f689a4c8c6;
-   valaddr_reg:x3; val_offset:1580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1580*FLEN/8, x4, x1, x2)
-
-inst_791:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x173f689a4c8c6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x173f689a4c8c6; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1582*FLEN/8, x4, x1, x2)
-
-inst_792:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x0;
-   valaddr_reg:x3; val_offset:1584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1584*FLEN/8, x4, x1, x2)
-
-inst_793:
-// fs1 == 0 and fe1 == 0x400 and fm1 == 0x02a39e584db8a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x40002a39e584db8a; op2val:0x0;
-   valaddr_reg:x3; val_offset:1586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1586*FLEN/8, x4, x1, x2)
-
-inst_794:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x02a39e584db8a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x40002a39e584db8a;
-   valaddr_reg:x3; val_offset:1588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1588*FLEN/8, x4, x1, x2)
-
-inst_795:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x02a39e584db8a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x40002a39e584db8a;
-   valaddr_reg:x3; val_offset:1590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1590*FLEN/8, x4, x1, x2)
-
-inst_796:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1592*FLEN/8, x4, x1, x2)
-
-inst_797:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x87dfc3c4343fa and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe87dfc3c4343fa; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1594*FLEN/8, x4, x1, x2)
-
-inst_798:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x87dfc3c4343fa and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7fe87dfc3c4343fa;
-   valaddr_reg:x3; val_offset:1596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1596*FLEN/8, x4, x1, x2)
-
-inst_799:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1598*FLEN/8, x4, x1, x2)
-
-inst_800:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1600*FLEN/8, x4, x1, x2)
-
-inst_801:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1602*FLEN/8, x4, x1, x2)
-
-inst_802:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x397fcfd029cc8 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7fb397fcfd029cc8;
-   valaddr_reg:x3; val_offset:1604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1604*FLEN/8, x4, x1, x2)
-
-inst_803:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1606*FLEN/8, x4, x1, x2)
-
-inst_804:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1608*FLEN/8, x4, x1, x2)
-
-inst_805:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1610*FLEN/8, x4, x1, x2)
-
-inst_806:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1612*FLEN/8, x4, x1, x2)
-
-inst_807:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1614*FLEN/8, x4, x1, x2)
-
-inst_808:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x87dfc3c4343fa and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe87dfc3c4343fa; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1616*FLEN/8, x4, x1, x2)
-
-inst_809:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1618*FLEN/8, x4, x1, x2)
-
-inst_810:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1620*FLEN/8, x4, x1, x2)
-
-inst_811:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1622*FLEN/8, x4, x1, x2)
-
-inst_812:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x87dfc3c4343fa and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe87dfc3c4343fa; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1624*FLEN/8, x4, x1, x2)
-
-inst_813:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1626*FLEN/8, x4, x1, x2)
-
-inst_814:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1628*FLEN/8, x4, x1, x2)
-
-inst_815:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1630*FLEN/8, x4, x1, x2)
-
-inst_816:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1632*FLEN/8, x4, x1, x2)
-
-inst_817:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1634*FLEN/8, x4, x1, x2)
-
-inst_818:
-// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xf5994c8042e0c and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f7f5994c8042e0c; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1636*FLEN/8, x4, x1, x2)
-
-inst_819:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xf5994c8042e0c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7f7f5994c8042e0c;
-   valaddr_reg:x3; val_offset:1638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1638*FLEN/8, x4, x1, x2)
-
-inst_820:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1640*FLEN/8, x4, x1, x2)
-
-inst_821:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fd48b05c2121 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfd48b05c2121; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1642*FLEN/8, x4, x1, x2)
-
-inst_822:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0fd48b05c2121 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xfd48b05c2121;
-   valaddr_reg:x3; val_offset:1644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1644*FLEN/8, x4, x1, x2)
-
-inst_823:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1646*FLEN/8, x4, x1, x2)
-
-inst_824:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1648*FLEN/8, x4, x1, x2)
-
-inst_825:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1650*FLEN/8, x4, x1, x2)
-
-inst_826:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1652*FLEN/8, x4, x1, x2)
-
-inst_827:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1654*FLEN/8, x4, x1, x2)
-
-inst_828:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1656*FLEN/8, x4, x1, x2)
-
-inst_829:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1658*FLEN/8, x4, x1, x2)
-
-inst_830:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1660*FLEN/8, x4, x1, x2)
-
-inst_831:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1662*FLEN/8, x4, x1, x2)
-
-inst_832:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1664*FLEN/8, x4, x1, x2)
-
-inst_833:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1666*FLEN/8, x4, x1, x2)
-
-inst_834:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fd48b05c2121 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfd48b05c2121; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:1668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1668*FLEN/8, x4, x1, x2)
-
-inst_835:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0fd48b05c2121 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0xfd48b05c2121;
-   valaddr_reg:x3; val_offset:1670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1670*FLEN/8, x4, x1, x2)
-
-inst_836:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fd48b05c2121 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfd48b05c2121; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1672*FLEN/8, x4, x1, x2)
-
-inst_837:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x0;
-   valaddr_reg:x3; val_offset:1674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1674*FLEN/8, x4, x1, x2)
-
-inst_838:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x603c137f0d51f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff603c137f0d51f; op2val:0x0;
-   valaddr_reg:x3; val_offset:1676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1676*FLEN/8, x4, x1, x2)
-
-inst_839:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x603c137f0d51f and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ff603c137f0d51f;
-   valaddr_reg:x3; val_offset:1678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1678*FLEN/8, x4, x1, x2)
-
-inst_840:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x603c137f0d51f and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x3ff603c137f0d51f;
-   valaddr_reg:x3; val_offset:1680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1680*FLEN/8, x4, x1, x2)
-
-inst_841:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1682*FLEN/8, x4, x1, x2)
-
-inst_842:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1684*FLEN/8, x4, x1, x2)
-
-inst_843:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1686*FLEN/8, x4, x1, x2)
-
-inst_844:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1688*FLEN/8, x4, x1, x2)
-
-inst_845:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1690*FLEN/8, x4, x1, x2)
-
-inst_846:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x9ac314c1e5de7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7fb9ac314c1e5de7;
-   valaddr_reg:x3; val_offset:1692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1692*FLEN/8, x4, x1, x2)
-
-inst_847:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1694*FLEN/8, x4, x1, x2)
-
-inst_848:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1696*FLEN/8, x4, x1, x2)
-
-inst_849:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1698*FLEN/8, x4, x1, x2)
-
-inst_850:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1700*FLEN/8, x4, x1, x2)
-
-inst_851:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1702*FLEN/8, x4, x1, x2)
-
-inst_852:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1704*FLEN/8, x4, x1, x2)
-
-inst_853:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1706*FLEN/8, x4, x1, x2)
-
-inst_854:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1708*FLEN/8, x4, x1, x2)
-
-inst_855:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1710*FLEN/8, x4, x1, x2)
-
-inst_856:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1712*FLEN/8, x4, x1, x2)
-
-inst_857:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1714*FLEN/8, x4, x1, x2)
-
-inst_858:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1716*FLEN/8, x4, x1, x2)
-
-inst_859:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1718*FLEN/8, x4, x1, x2)
-
-inst_860:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x489c109b1e4b9 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f8489c109b1e4b9; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1720*FLEN/8, x4, x1, x2)
-
-inst_861:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x489c109b1e4b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7f8489c109b1e4b9;
-   valaddr_reg:x3; val_offset:1722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1722*FLEN/8, x4, x1, x2)
-
-inst_862:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1724*FLEN/8, x4, x1, x2)
-
-inst_863:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x14bdd6f520473 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x14bdd6f520473; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1726*FLEN/8, x4, x1, x2)
-
-inst_864:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x14bdd6f520473 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x14bdd6f520473;
-   valaddr_reg:x3; val_offset:1728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1728*FLEN/8, x4, x1, x2)
-
-inst_865:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1730*FLEN/8, x4, x1, x2)
-
-inst_866:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1732*FLEN/8, x4, x1, x2)
-
-inst_867:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1734*FLEN/8, x4, x1, x2)
-
-inst_868:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1736*FLEN/8, x4, x1, x2)
-
-inst_869:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1738*FLEN/8, x4, x1, x2)
-
-inst_870:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1740*FLEN/8, x4, x1, x2)
-
-inst_871:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1742*FLEN/8, x4, x1, x2)
-
-inst_872:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1744*FLEN/8, x4, x1, x2)
-
-inst_873:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1746*FLEN/8, x4, x1, x2)
-
-inst_874:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x14bdd6f520473 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x14bdd6f520473; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:1748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1748*FLEN/8, x4, x1, x2)
-
-inst_875:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0x14bdd6f520473 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x14bdd6f520473;
-   valaddr_reg:x3; val_offset:1750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1750*FLEN/8, x4, x1, x2)
-
-inst_876:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x14bdd6f520473 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x14bdd6f520473; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1752*FLEN/8, x4, x1, x2)
-
-inst_877:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x0;
-   valaddr_reg:x3; val_offset:1754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1754*FLEN/8, x4, x1, x2)
-
-inst_878:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xcd83dac71068d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ffcd83dac71068d; op2val:0x0;
-   valaddr_reg:x3; val_offset:1756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1756*FLEN/8, x4, x1, x2)
-
-inst_879:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xcd83dac71068d and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ffcd83dac71068d;
-   valaddr_reg:x3; val_offset:1758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1758*FLEN/8, x4, x1, x2)
-
-inst_880:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xcd83dac71068d and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x3ffcd83dac71068d;
-   valaddr_reg:x3; val_offset:1760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1760*FLEN/8, x4, x1, x2)
-
-inst_881:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1762*FLEN/8, x4, x1, x2)
-
-inst_882:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd5a40c379c682 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed5a40c379c682; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1764*FLEN/8, x4, x1, x2)
-
-inst_883:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd5a40c379c682 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xffed5a40c379c682;
-   valaddr_reg:x3; val_offset:1766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1766*FLEN/8, x4, x1, x2)
-
-inst_884:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1768*FLEN/8, x4, x1, x2)
-
-inst_885:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1770*FLEN/8, x4, x1, x2)
-
-inst_886:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1772*FLEN/8, x4, x1, x2)
-
-inst_887:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x77b6702c7d202 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xffb77b6702c7d202;
-   valaddr_reg:x3; val_offset:1774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1774*FLEN/8, x4, x1, x2)
-
-inst_888:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1776*FLEN/8, x4, x1, x2)
-
-inst_889:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1778*FLEN/8, x4, x1, x2)
-
-inst_890:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1780*FLEN/8, x4, x1, x2)
-
-inst_891:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1782*FLEN/8, x4, x1, x2)
-
-inst_892:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1784*FLEN/8, x4, x1, x2)
-
-inst_893:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd5a40c379c682 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed5a40c379c682; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1786*FLEN/8, x4, x1, x2)
-
-inst_894:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1788*FLEN/8, x4, x1, x2)
-
-inst_895:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1790*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_8)
-
-inst_896:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1792*FLEN/8, x4, x1, x2)
-
-inst_897:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd5a40c379c682 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed5a40c379c682; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1794*FLEN/8, x4, x1, x2)
-
-inst_898:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1796*FLEN/8, x4, x1, x2)
-
-inst_899:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1798*FLEN/8, x4, x1, x2)
-
-inst_900:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1800*FLEN/8, x4, x1, x2)
-
-inst_901:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1802*FLEN/8, x4, x1, x2)
-
-inst_902:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1804*FLEN/8, x4, x1, x2)
-
-inst_903:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x2c91f356ca801 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff82c91f356ca801; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1806*FLEN/8, x4, x1, x2)
-
-inst_904:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x2c91f356ca801 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xff82c91f356ca801;
-   valaddr_reg:x3; val_offset:1808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1808*FLEN/8, x4, x1, x2)
-
-inst_905:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1810*FLEN/8, x4, x1, x2)
-
-inst_906:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12f8c3601c4a9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80012f8c3601c4a9; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1812*FLEN/8, x4, x1, x2)
-
-inst_907:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x12f8c3601c4a9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x80012f8c3601c4a9;
-   valaddr_reg:x3; val_offset:1814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1814*FLEN/8, x4, x1, x2)
-
-inst_908:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1816*FLEN/8, x4, x1, x2)
-
-inst_909:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1818*FLEN/8, x4, x1, x2)
-
-inst_910:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1820*FLEN/8, x4, x1, x2)
-
-inst_911:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1822*FLEN/8, x4, x1, x2)
-
-inst_912:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1824*FLEN/8, x4, x1, x2)
-
-inst_913:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1826*FLEN/8, x4, x1, x2)
-
-inst_914:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1828*FLEN/8, x4, x1, x2)
-
-inst_915:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12f8c3601c4a9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80012f8c3601c4a9; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:1830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1830*FLEN/8, x4, x1, x2)
-
-inst_916:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0x12f8c3601c4a9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x80012f8c3601c4a9;
-   valaddr_reg:x3; val_offset:1832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1832*FLEN/8, x4, x1, x2)
-
-inst_917:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12f8c3601c4a9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80012f8c3601c4a9; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1834*FLEN/8, x4, x1, x2)
-
-inst_918:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x0;
-   valaddr_reg:x3; val_offset:1836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1836*FLEN/8, x4, x1, x2)
-
-inst_919:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xa6229168cb10d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbffa6229168cb10d; op2val:0x0;
-   valaddr_reg:x3; val_offset:1838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1838*FLEN/8, x4, x1, x2)
-
-inst_920:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xa6229168cb10d and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbffa6229168cb10d;
-   valaddr_reg:x3; val_offset:1840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1840*FLEN/8, x4, x1, x2)
-
-inst_921:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xa6229168cb10d and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xbffa6229168cb10d;
-   valaddr_reg:x3; val_offset:1842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1842*FLEN/8, x4, x1, x2)
-
-inst_922:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1844*FLEN/8, x4, x1, x2)
-
-inst_923:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb9818fe1eccda and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffeb9818fe1eccda; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1846*FLEN/8, x4, x1, x2)
-
-inst_924:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb9818fe1eccda and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xffeb9818fe1eccda;
-   valaddr_reg:x3; val_offset:1848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1848*FLEN/8, x4, x1, x2)
-
-inst_925:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1850*FLEN/8, x4, x1, x2)
-
-inst_926:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1852*FLEN/8, x4, x1, x2)
-
-inst_927:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1854*FLEN/8, x4, x1, x2)
-
-inst_928:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x6134731b23d7b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xffb6134731b23d7b;
-   valaddr_reg:x3; val_offset:1856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1856*FLEN/8, x4, x1, x2)
-
-inst_929:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1858*FLEN/8, x4, x1, x2)
-
-inst_930:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1860*FLEN/8, x4, x1, x2)
-
-inst_931:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1862*FLEN/8, x4, x1, x2)
-
-inst_932:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1864*FLEN/8, x4, x1, x2)
-
-inst_933:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1866*FLEN/8, x4, x1, x2)
-
-inst_934:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb9818fe1eccda and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffeb9818fe1eccda; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1868*FLEN/8, x4, x1, x2)
-
-inst_935:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1870*FLEN/8, x4, x1, x2)
-
-inst_936:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1872*FLEN/8, x4, x1, x2)
-
-inst_937:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1874*FLEN/8, x4, x1, x2)
-
-inst_938:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb9818fe1eccda and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffeb9818fe1eccda; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1876*FLEN/8, x4, x1, x2)
-
-inst_939:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1878*FLEN/8, x4, x1, x2)
-
-inst_940:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1880*FLEN/8, x4, x1, x2)
-
-inst_941:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1882*FLEN/8, x4, x1, x2)
-
-inst_942:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1884*FLEN/8, x4, x1, x2)
-
-inst_943:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1886*FLEN/8, x4, x1, x2)
-
-inst_944:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x1a905c15b6463 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff81a905c15b6463; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1888*FLEN/8, x4, x1, x2)
-
-inst_945:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x1a905c15b6463 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xff81a905c15b6463;
-   valaddr_reg:x3; val_offset:1890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1890*FLEN/8, x4, x1, x2)
-
-inst_946:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1892*FLEN/8, x4, x1, x2)
-
-inst_947:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11d5cf49b3fa7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80011d5cf49b3fa7; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1894*FLEN/8, x4, x1, x2)
-
-inst_948:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x11d5cf49b3fa7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x80011d5cf49b3fa7;
-   valaddr_reg:x3; val_offset:1896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1896*FLEN/8, x4, x1, x2)
-
-inst_949:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1898*FLEN/8, x4, x1, x2)
-
-inst_950:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1900*FLEN/8, x4, x1, x2)
-
-inst_951:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1902*FLEN/8, x4, x1, x2)
-
-inst_952:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1904*FLEN/8, x4, x1, x2)
-
-inst_953:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1906*FLEN/8, x4, x1, x2)
-
-inst_954:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11d5cf49b3fa7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80011d5cf49b3fa7; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:1908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1908*FLEN/8, x4, x1, x2)
-
-inst_955:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0x11d5cf49b3fa7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x80011d5cf49b3fa7;
-   valaddr_reg:x3; val_offset:1910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1910*FLEN/8, x4, x1, x2)
-
-inst_956:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11d5cf49b3fa7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80011d5cf49b3fa7; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1912*FLEN/8, x4, x1, x2)
-
-inst_957:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x0;
-   valaddr_reg:x3; val_offset:1914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1914*FLEN/8, x4, x1, x2)
-
-inst_958:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8cd8a372f0f06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbff8cd8a372f0f06; op2val:0x0;
-   valaddr_reg:x3; val_offset:1916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1916*FLEN/8, x4, x1, x2)
-
-inst_959:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x8cd8a372f0f06 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbff8cd8a372f0f06;
-   valaddr_reg:x3; val_offset:1918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1918*FLEN/8, x4, x1, x2)
-
-inst_960:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x8cd8a372f0f06 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xbff8cd8a372f0f06;
-   valaddr_reg:x3; val_offset:1920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1920*FLEN/8, x4, x1, x2)
-
-inst_961:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1922*FLEN/8, x4, x1, x2)
-
-inst_962:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x39e41023e1389 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe39e41023e1389; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1924*FLEN/8, x4, x1, x2)
-
-inst_963:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x39e41023e1389 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xffe39e41023e1389;
-   valaddr_reg:x3; val_offset:1926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1926*FLEN/8, x4, x1, x2)
-
-inst_964:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1928*FLEN/8, x4, x1, x2)
-
-inst_965:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1930*FLEN/8, x4, x1, x2)
-
-inst_966:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1932*FLEN/8, x4, x1, x2)
-
-inst_967:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf639b36c9b8db and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xffaf639b36c9b8db;
-   valaddr_reg:x3; val_offset:1934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1934*FLEN/8, x4, x1, x2)
-
-inst_968:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1936*FLEN/8, x4, x1, x2)
-
-inst_969:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1938*FLEN/8, x4, x1, x2)
-
-inst_970:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1940*FLEN/8, x4, x1, x2)
-
-inst_971:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1942*FLEN/8, x4, x1, x2)
-
-inst_972:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1944*FLEN/8, x4, x1, x2)
-
-inst_973:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x39e41023e1389 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe39e41023e1389; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1946*FLEN/8, x4, x1, x2)
-
-inst_974:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1948*FLEN/8, x4, x1, x2)
-
-inst_975:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1950*FLEN/8, x4, x1, x2)
-
-inst_976:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1952*FLEN/8, x4, x1, x2)
-
-inst_977:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x39e41023e1389 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe39e41023e1389; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1954*FLEN/8, x4, x1, x2)
-
-inst_978:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1956*FLEN/8, x4, x1, x2)
-
-inst_979:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1958*FLEN/8, x4, x1, x2)
-
-inst_980:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1960*FLEN/8, x4, x1, x2)
-
-inst_981:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1962*FLEN/8, x4, x1, x2)
-
-inst_982:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1964*FLEN/8, x4, x1, x2)
-
-inst_983:
-// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0x91c7c2bd493e3 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff791c7c2bd493e3; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1966*FLEN/8, x4, x1, x2)
-
-inst_984:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0x91c7c2bd493e3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xff791c7c2bd493e3;
-   valaddr_reg:x3; val_offset:1968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1968*FLEN/8, x4, x1, x2)
-
-inst_985:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1970*FLEN/8, x4, x1, x2)
-
-inst_986:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0cae158f8de83 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000cae158f8de83; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1972*FLEN/8, x4, x1, x2)
-
-inst_987:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0cae158f8de83 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x8000cae158f8de83;
-   valaddr_reg:x3; val_offset:1974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1974*FLEN/8, x4, x1, x2)
-
-inst_988:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1976*FLEN/8, x4, x1, x2)
-
-inst_989:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1978*FLEN/8, x4, x1, x2)
-
-inst_990:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1980*FLEN/8, x4, x1, x2)
-
-inst_991:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0cae158f8de83 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000cae158f8de83; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:1982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1982*FLEN/8, x4, x1, x2)
-
-inst_992:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0cae158f8de83 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x8000cae158f8de83;
-   valaddr_reg:x3; val_offset:1984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1984*FLEN/8, x4, x1, x2)
-
-inst_993:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0cae158f8de83 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000cae158f8de83; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1986*FLEN/8, x4, x1, x2)
-
-inst_994:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x0;
-   valaddr_reg:x3; val_offset:1988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1988*FLEN/8, x4, x1, x2)
-
-inst_995:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1a23c57d41a27 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbff1a23c57d41a27; op2val:0x0;
-   valaddr_reg:x3; val_offset:1990*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1990*FLEN/8, x4, x1, x2)
-
-inst_996:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x1a23c57d41a27 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbff1a23c57d41a27;
-   valaddr_reg:x3; val_offset:1992*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1992*FLEN/8, x4, x1, x2)
-
-inst_997:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x1a23c57d41a27 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xbff1a23c57d41a27;
-   valaddr_reg:x3; val_offset:1994*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1994*FLEN/8, x4, x1, x2)
-
-inst_998:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1996*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1996*FLEN/8, x4, x1, x2)
-
-inst_999:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xdaf87e09a11da and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffedaf87e09a11da; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1998*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1998*FLEN/8, x4, x1, x2)
-
-inst_1000:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xdaf87e09a11da and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xffedaf87e09a11da;
-   valaddr_reg:x3; val_offset:2000*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2000*FLEN/8, x4, x1, x2)
-
-inst_1001:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:2002*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2002*FLEN/8, x4, x1, x2)
-
-inst_1002:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:2004*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2004*FLEN/8, x4, x1, x2)
-
-inst_1003:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:2006*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2006*FLEN/8, x4, x1, x2)
-
-inst_1004:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7bf9fe6e1a7e1 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xffb7bf9fe6e1a7e1;
-   valaddr_reg:x3; val_offset:2008*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2008*FLEN/8, x4, x1, x2)
-
-inst_1005:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:2010*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2010*FLEN/8, x4, x1, x2)
-
-inst_1006:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:2012*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2012*FLEN/8, x4, x1, x2)
-
-inst_1007:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:2014*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2014*FLEN/8, x4, x1, x2)
-
-inst_1008:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:2016*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2016*FLEN/8, x4, x1, x2)
-
-inst_1009:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:2018*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2018*FLEN/8, x4, x1, x2)
-
-inst_1010:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xdaf87e09a11da and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffedaf87e09a11da; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:2020*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2020*FLEN/8, x4, x1, x2)
-
-inst_1011:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:2022*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2022*FLEN/8, x4, x1, x2)
-
-inst_1012:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:2024*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2024*FLEN/8, x4, x1, x2)
-
-inst_1013:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:2026*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2026*FLEN/8, x4, x1, x2)
-
-inst_1014:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xdaf87e09a11da and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffedaf87e09a11da; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:2028*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2028*FLEN/8, x4, x1, x2)
-
-inst_1015:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:2030*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2030*FLEN/8, x4, x1, x2)
-
-inst_1016:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:2032*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2032*FLEN/8, x4, x1, x2)
-
-inst_1017:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:2034*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2034*FLEN/8, x4, x1, x2)
-
-inst_1018:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:2036*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2036*FLEN/8, x4, x1, x2)
-
-inst_1019:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:2038*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2038*FLEN/8, x4, x1, x2)
-
-inst_1020:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x2ffb31f1aecb4 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff82ffb31f1aecb4; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:2040*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2040*FLEN/8, x4, x1, x2)
-
-inst_1021:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x2ffb31f1aecb4 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xff82ffb31f1aecb4;
-   valaddr_reg:x3; val_offset:2042*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2042*FLEN/8, x4, x1, x2)
-
-inst_1022:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:2044*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2044*FLEN/8, x4, x1, x2)
-
-inst_1023:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x132fe1b33da32 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800132fe1b33da32; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:2046*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2046*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_9)
-
-inst_1024:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x132fe1b33da32 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x800132fe1b33da32;
-   valaddr_reg:x3; val_offset:2048*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2048*FLEN/8, x4, x1, x2)
-
-inst_1025:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:2050*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2050*FLEN/8, x4, x1, x2)
-
-inst_1026:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x132fe1b33da32 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800132fe1b33da32; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:2052*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2052*FLEN/8, x4, x1, x2)
-
-inst_1027:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0x132fe1b33da32 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x800132fe1b33da32;
-   valaddr_reg:x3; val_offset:2054*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2054*FLEN/8, x4, x1, x2)
-
-inst_1028:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x132fe1b33da32 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800132fe1b33da32; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:2056*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2056*FLEN/8, x4, x1, x2)
-
-inst_1029:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x0;
-   valaddr_reg:x3; val_offset:2058*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2058*FLEN/8, x4, x1, x2)
-
-inst_1030:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xaaecfe8e63ec3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbffaaecfe8e63ec3; op2val:0x0;
-   valaddr_reg:x3; val_offset:2060*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2060*FLEN/8, x4, x1, x2)
-
-inst_1031:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xaaecfe8e63ec3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbffaaecfe8e63ec3;
-   valaddr_reg:x3; val_offset:2062*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2062*FLEN/8, x4, x1, x2)
-
-inst_1032:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xaaecfe8e63ec3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xbffaaecfe8e63ec3;
-   valaddr_reg:x3; val_offset:2064*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2064*FLEN/8, x4, x1, x2)
-
-inst_1033:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:2066*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2066*FLEN/8, x4, x1, x2)
-
-inst_1034:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:2068*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2068*FLEN/8, x4, x1, x2)
-
-inst_1035:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:2070*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2070*FLEN/8, x4, x1, x2)
-
-inst_1036:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:2072*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2072*FLEN/8, x4, x1, x2)
-
-inst_1037:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:2074*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2074*FLEN/8, x4, x1, x2)
-
-inst_1038:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xefff2c6cde040 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xffbefff2c6cde040;
-   valaddr_reg:x3; val_offset:2076*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2076*FLEN/8, x4, x1, x2)
-
-inst_1039:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:2078*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2078*FLEN/8, x4, x1, x2)
-
-inst_1040:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:2080*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2080*FLEN/8, x4, x1, x2)
-
-inst_1041:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:2082*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2082*FLEN/8, x4, x1, x2)
-
-inst_1042:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:2084*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2084*FLEN/8, x4, x1, x2)
-
-inst_1043:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:2086*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2086*FLEN/8, x4, x1, x2)
-
-inst_1044:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:2088*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2088*FLEN/8, x4, x1, x2)
-
-inst_1045:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:2090*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2090*FLEN/8, x4, x1, x2)
-
-inst_1046:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:2092*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2092*FLEN/8, x4, x1, x2)
-
-inst_1047:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:2094*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2094*FLEN/8, x4, x1, x2)
-
-inst_1048:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:2096*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2096*FLEN/8, x4, x1, x2)
-
-inst_1049:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:2098*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2098*FLEN/8, x4, x1, x2)
-
-inst_1050:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:2100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2100*FLEN/8, x4, x1, x2)
-
-inst_1051:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:2102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2102*FLEN/8, x4, x1, x2)
-
-inst_1052:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x8ccc238a4b367 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff88ccc238a4b367; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:2104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2104*FLEN/8, x4, x1, x2)
-
-inst_1053:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x8ccc238a4b367 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xff88ccc238a4b367;
-   valaddr_reg:x3; val_offset:2106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2106*FLEN/8, x4, x1, x2)
-
-inst_1054:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:2108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2108*FLEN/8, x4, x1, x2)
-
-inst_1055:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:2110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2110*FLEN/8, x4, x1, x2)
-
-inst_1056:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:2112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2112*FLEN/8, x4, x1, x2)
-
-inst_1057:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:2114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2114*FLEN/8, x4, x1, x2)
-
-inst_1058:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:2116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2116*FLEN/8, x4, x1, x2)
-
-inst_1059:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:2118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2118*FLEN/8, x4, x1, x2)
-
-inst_1060:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:2120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2120*FLEN/8, x4, x1, x2)
-
-inst_1061:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:2122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2122*FLEN/8, x4, x1, x2)
-
-inst_1062:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:2124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2124*FLEN/8, x4, x1, x2)
-
-inst_1063:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:2126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2126*FLEN/8, x4, x1, x2)
-
-inst_1064:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:2128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2128*FLEN/8, x4, x1, x2)
-
-inst_1065:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:2130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2130*FLEN/8, x4, x1, x2)
-
-inst_1066:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:2132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2132*FLEN/8, x4, x1, x2)
-
-inst_1067:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:2134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2134*FLEN/8, x4, x1, x2)
-
-inst_1068:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:2136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2136*FLEN/8, x4, x1, x2)
-
-inst_1069:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:2138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2138*FLEN/8, x4, x1, x2)
-
-inst_1070:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:2140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2140*FLEN/8, x4, x1, x2)
-
-inst_1071:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x0;
-   valaddr_reg:x3; val_offset:2142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2142*FLEN/8, x4, x1, x2)
-
-inst_1072:
-// fs1 == 1 and fe1 == 0x400 and fm1 == 0x16a3ffd234a38 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc0016a3ffd234a38; op2val:0x0;
-   valaddr_reg:x3; val_offset:2144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2144*FLEN/8, x4, x1, x2)
-
-inst_1073:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x16a3ffd234a38 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc0016a3ffd234a38;
-   valaddr_reg:x3; val_offset:2146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2146*FLEN/8, x4, x1, x2)
-
-inst_1074:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x400 and fm2 == 0x16a3ffd234a38 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xc0016a3ffd234a38;
-   valaddr_reg:x3; val_offset:2148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2148*FLEN/8, x4, x1, x2)
-
-inst_1075:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:2150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2150*FLEN/8, x4, x1, x2)
-
-inst_1076:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:2152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2152*FLEN/8, x4, x1, x2)
-
-inst_1077:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:2154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2154*FLEN/8, x4, x1, x2)
-
-inst_1078:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:2156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2156*FLEN/8, x4, x1, x2)
-
-inst_1079:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:2158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2158*FLEN/8, x4, x1, x2)
-
-inst_1080:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:2160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2160*FLEN/8, x4, x1, x2)
-
-inst_1081:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:2162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2162*FLEN/8, x4, x1, x2)
-
-inst_1082:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:2164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2164*FLEN/8, x4, x1, x2)
-
-inst_1083:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:2166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2166*FLEN/8, x4, x1, x2)
-
-inst_1084:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:2168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2168*FLEN/8, x4, x1, x2)
-
-inst_1085:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:2170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2170*FLEN/8, x4, x1, x2)
-
-inst_1086:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:2172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2172*FLEN/8, x4, x1, x2)
-
-inst_1087:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:2174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2174*FLEN/8, x4, x1, x2)
-
-inst_1088:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:2176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2176*FLEN/8, x4, x1, x2)
-
-inst_1089:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:2178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2178*FLEN/8, x4, x1, x2)
-
-inst_1090:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:2180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2180*FLEN/8, x4, x1, x2)
-
-inst_1091:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:2182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2182*FLEN/8, x4, x1, x2)
-
-inst_1092:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:2184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2184*FLEN/8, x4, x1, x2)
-
-inst_1093:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:2186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2186*FLEN/8, x4, x1, x2)
-
-inst_1094:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:2188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2188*FLEN/8, x4, x1, x2)
-
-inst_1095:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:2190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2190*FLEN/8, x4, x1, x2)
-
-inst_1096:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:2192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2192*FLEN/8, x4, x1, x2)
-
-inst_1097:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb59e00c7a1fe31; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:2194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2194*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9213943245805799675,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(9213943245805799675,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9210434777589363463,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(9210434777589363463,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9218055503771424859,64,FLEN)
-NAN_BOXED(9218055503771424859,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(18432946687258496920,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(18432946687258496920,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(18438593151621118562,64,FLEN)
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-NAN_BOXED(18415677025407527552,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(1894086014712414,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(3529915033510522,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(4089776851376057,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2784886383004491,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(3648894042123393,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9226709579102006934,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9226509637402000517,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9225602728946348318,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9226747456216532470,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223812642243920251,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9214466391261943558,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(9214466391261943558,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_7:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_8:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_9:
-    .fill 148*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fminm_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fminm_b1-01.S
deleted file mode 100644
index edee03a16..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fminm_b1-01.S
+++ /dev/null
@@ -1,429 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:08:59 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fminm.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fminm.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fminm_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rd != rs2, rs1==f31, rs2==f30, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f31; op2:f30; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f29, rs2==f31, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f29; op2:f31; dest:f30; op1val:0x0; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f30, f29, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f29; op1val:0x0; op2val:0x1;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f29, f30, f29, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 == rs2 != rd, rs1==f27, rs2==f27, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f27; op2:f27; dest:f28; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f28, f27, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rs2 == rd, rs1==f26, rs2==f26, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f26; op2:f26; dest:f26; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f26, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f28, rs2==f25, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f28; op2:f25; dest:f27; op1val:0x0; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f27, f28, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f28, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f24; op2:f28; dest:f25; op1val:0x0; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f25, f24, f28, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f25; op2:f23; dest:f24; op1val:0x0; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f24, f25, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f22; op2:f24; dest:f23; op1val:0x0; op2val:0x800000;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f23, f22, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f23; op2:f21; dest:f22; op1val:0x0; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f22, f23, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x800001;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f21; op2:f19; dest:f20; op1val:0x0; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f20, f21, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f18; op2:f20; dest:f19; op1val:0x0; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f19; op2:f17; dest:f18; op1val:0x0; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f18, f19, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f16; op2:f18; dest:f17; op1val:0x0; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f17, f16, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f17; op2:f15; dest:f16; op1val:0x0; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f16, f17, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f15; op2:f13; dest:f14; op1val:0x0; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f14, f15, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f12; op2:f14; dest:f13; op1val:0x0; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f13; op2:f11; dest:f12; op1val:0x0; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f12, f13, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f10; op2:f12; dest:f11; op1val:0x0; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f11, f10, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f11; op2:f9; dest:f10; op1val:0x0; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f10, f11, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f9; op2:f7; dest:f8; op1val:0x0; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f8, f9, f7, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f6; op2:f8; dest:f7; op1val:0x80000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f7, rs2==f5, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f7; op2:f5; dest:f6; op1val:0x80000000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f6, f7, f5, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f4; op2:f6; dest:f5; op1val:0x80000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f5, f4, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f5, rs2==f3, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f5; op2:f3; dest:f4; op1val:0x80000000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f4, f5, f3, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f2; op2:f4; dest:f3; op1val:0x80000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f3, rs2==f1, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f3; op2:f1; dest:f2; op1val:0x80000000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f2, f3, f1, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f0; op2:f2; dest:f1; op1val:0x80000000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f1; op2:f30; dest:f31; op1val:0x80000000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f1, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f30; op2:f0; dest:f31; op1val:0x80000000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f0, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rd==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f31; op2:f30; dest:f0; op1val:0x80000000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 68*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fminm_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fminm_b19-01.S
deleted file mode 100644
index 129473751..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fminm_b19-01.S
+++ /dev/null
@@ -1,429 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:08:59 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fminm.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fminm.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fminm_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rd != rs2, rs1==f31, rs2==f30, rd==f31,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f31; op2:f30; dest:f31; op1val:0x7f222105; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f29, rs2==f31, rd==f30,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f29; op2:f31; dest:f30; op1val:0x7f222105; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f30, f29, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f29; op1val:0x7ec45459; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f29, f30, f29, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 == rs2 != rd, rs1==f27, rs2==f27, rd==f28,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f27; op2:f27; dest:f28; op1val:0x7f222105; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f28, f27, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rs2 == rd, rs1==f26, rs2==f26, rd==f26,fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f26; op2:f26; dest:f26; op1val:0x7eb70362; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f26, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f28, rs2==f25, rd==f27,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f28; op2:f25; dest:f27; op1val:0x7f222105; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f27, f28, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f28, rd==f25,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f24; op2:f28; dest:f25; op1val:0x7d81b404; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f25, f24, f28, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x01b404 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f25; op2:f23; dest:f24; op1val:0x7f7fffff; op2val:0x7d81b404;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f24, f25, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f22; op2:f24; dest:f23; op1val:0x7d81b404; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f23, f22, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x01b404 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f23; op2:f21; dest:f22; op1val:0x7f222105; op2val:0x7d81b404;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f22, f23, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f20; op2:f22; dest:f21; op1val:0x7f222105; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f21; op2:f19; dest:f20; op1val:0x7f2eabd8; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f20, f21, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f18; op2:f20; dest:f19; op1val:0x7f222105; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f19; op2:f17; dest:f18; op1val:0x7d81b404; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f18, f19, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f18, rd==f17,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x01b404 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f16; op2:f18; dest:f17; op1val:0xff7fffff; op2val:0x7d81b404;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f17, f16, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f17; op2:f15; dest:f16; op1val:0x7d81b404; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f16, f17, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f14; op2:f16; dest:f15; op1val:0x7f222105; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f15, rs2==f13, rd==f14,fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f15; op2:f13; dest:f14; op1val:0xfee4815a; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f14, f15, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f12; op2:f14; dest:f13; op1val:0x7f222105; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f13, rs2==f11, rd==f12,fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f13; op2:f11; dest:f12; op1val:0xfe9ffb35; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f12, f13, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f10; op2:f12; dest:f11; op1val:0x7f222105; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f11, f10, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f11; op2:f9; dest:f10; op1val:0x7d81b404; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f10, f11, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f8; op2:f10; dest:f9; op1val:0x7f222105; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0xf7 and fm1 == 0x4f866d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f9; op2:f7; dest:f8; op1val:0x7bcf866d; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f8, f9, f7, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x4f866d and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f6; op2:f8; dest:f7; op1val:0xff7fffff; op2val:0x7bcf866d;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f7, rs2==f5, rd==f6,fs1 == 0 and fe1 == 0xf7 and fm1 == 0x4f866d and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f7; op2:f5; dest:f6; op1val:0x7bcf866d; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f6, f7, f5, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f6, rd==f5,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x4f866d and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f4; op2:f6; dest:f5; op1val:0x7f222105; op2val:0x7bcf866d;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f5, f4, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f5, rs2==f3, rd==f4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f5; op2:f3; dest:f4; op1val:0x7f222105; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f4, f5, f3, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f2; op2:f4; dest:f3; op1val:0x177770; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f3, rs2==f1, rd==f2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f3; op2:f1; dest:f2; op1val:0x7f39f704; op2val:0x177770;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f2, f3, f1, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f0; op2:f2; dest:f1; op1val:0x177770; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f1,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f1; op2:f30; dest:f31; op1val:0x7f222105; op2val:0x177770;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f1, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f30; op2:f0; dest:f31; op1val:0x7f222105; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f0, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rd==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f31; op2:f30; dest:f0; op1val:0x177770; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2125923170,32,FLEN)
-NAN_BOXED(2125923170,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2133765080,32,FLEN)
-NAN_BOXED(2133765080,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4276388186,32,FLEN)
-NAN_BOXED(4276388186,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4271897397,32,FLEN)
-NAN_BOXED(4271897397,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(2077197933,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2077197933,32,FLEN)
-NAN_BOXED(2077197933,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2077197933,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(1764005,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(2134505220,32,FLEN)
-NAN_BOXED(2134505220,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(1764005,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(3287489,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 68*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b1-01.S
deleted file mode 100644
index fe83803ce..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b1-01.S
+++ /dev/null
@@ -1,320 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:48 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmvh.x.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmvh.x.d instruction of the RISC-V RV32FD_Zicsr_Zfa extension for the fmvh.x.d_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmvh.x.d_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
-val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f30; dest:x30; op1val:0x8000000000000000; valaddr_reg:x3;
-val_offset:1*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f29; dest:x29; op1val:0x1; valaddr_reg:x3;
-val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f28; dest:x28; op1val:0x8000000000000001; valaddr_reg:x3;
-val_offset:3*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f27; dest:x27; op1val:0x2; valaddr_reg:x3;
-val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f26; dest:x26; op1val:0x8000000000000002; valaddr_reg:x3;
-val_offset:5*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f25; dest:x25; op1val:0xfffffffffffff; valaddr_reg:x3;
-val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f24; dest:x24; op1val:0x800fffffffffffff; valaddr_reg:x3;
-val_offset:7*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f23; dest:x23; op1val:0x10000000000000; valaddr_reg:x3;
-val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f22; dest:x22; op1val:0x8010000000000000; valaddr_reg:x3;
-val_offset:9*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f21; dest:x21; op1val:0x10000000000002; valaddr_reg:x3;
-val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f20; dest:x20; op1val:0x8010000000000002; valaddr_reg:x3;
-val_offset:11*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f19; dest:x19; op1val:0x7fefffffffffffff; valaddr_reg:x3;
-val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f18; dest:x18; op1val:0xffefffffffffffff; valaddr_reg:x3;
-val_offset:13*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f17; dest:x17; op1val:0x7ff0000000000000; valaddr_reg:x3;
-val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f16; dest:x16; op1val:0xfff0000000000000; valaddr_reg:x3;
-val_offset:15*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f15; dest:x15; op1val:0x7ff8000000000000; valaddr_reg:x3;
-val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f14; dest:x14; op1val:0xfff8000000000000; valaddr_reg:x3;
-val_offset:17*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f13; dest:x13; op1val:0x7ff8000000000001; valaddr_reg:x3;
-val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f12; dest:x12; op1val:0xfff8000000000001; valaddr_reg:x3;
-val_offset:19*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f11; dest:x11; op1val:0x7ff0000000000001; valaddr_reg:x3;
-val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f10; dest:x10; op1val:0xfff0000000000001; valaddr_reg:x3;
-val_offset:21*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f9; dest:x9; op1val:0x3ff0000000000000; valaddr_reg:x3;
-val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f8; dest:x8; op1val:0xbf80000000000000; valaddr_reg:x3;
-val_offset:23*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,
-/* opcode: fmvh.x.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
-val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
-
-inst_25:// rs1==f6, rd==x6,
-/* opcode: fmvh.x.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
-val_offset:1*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
-
-inst_26:// rs1==f5, rd==x5,
-/* opcode: fmvh.x.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
-val_offset:2*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,
-/* opcode: fmvh.x.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
-val_offset:3*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
-
-inst_28:// rs1==f3, rd==x3,
-/* opcode: fmvh.x.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
-val_offset:4*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
-
-inst_29:// rs1==f2, rd==x2,
-/* opcode: fmvh.x.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
-val_offset:5*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
-
-inst_30:// rs1==f1, rd==x1,
-/* opcode: fmvh.x.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
-val_offset:6*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
-
-inst_31:// rs1==f0, rd==x0,
-/* opcode: fmvh.x.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
-val_offset:7*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-test_dataset_1:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 10*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b22-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b22-01.S
deleted file mode 100644
index 51d2b6458..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b22-01.S
+++ /dev/null
@@ -1,320 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:48 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmvh.x.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmvh.x.d instruction of the RISC-V RV32FD_Zicsr_Zfa extension for the fmvh.x.d_b22 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmvh.x.d_b22)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08577924770d3 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f31; dest:x31; op1val:0x3fc08577924770d3; valaddr_reg:x3;
-val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fd and fm1 == 0x93fdc7b89296c and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f30; dest:x30; op1val:0x3fd93fdc7b89296c; valaddr_reg:x3;
-val_offset:1*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 1 and fe1 == 0x3fe and fm1 == 0x766ba34c2da80 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f29; dest:x29; op1val:0xbfe766ba34c2da80; valaddr_reg:x3;
-val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xd2d6b7dc59a3a and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f28; dest:x28; op1val:0x3ffd2d6b7dc59a3a; valaddr_reg:x3;
-val_offset:3*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x400 and fm1 == 0xcf84ba749f9c5 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f27; dest:x27; op1val:0x400cf84ba749f9c5; valaddr_reg:x3;
-val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x401 and fm1 == 0x854a908ceac39 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f26; dest:x26; op1val:0x401854a908ceac39; valaddr_reg:x3;
-val_offset:5*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 1 and fe1 == 0x0ff and fm1 == 0x137a953e8eb43 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f25; dest:x25; op1val:0x8ff137a953e8eb43; valaddr_reg:x3;
-val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xbedc2f3ebcf12 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f24; dest:x24; op1val:0x7febedc2f3ebcf12; valaddr_reg:x3;
-val_offset:7*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rd==x23,
-/* opcode: fmvh.x.d ; op1:f23; dest:x23; op1val:0x0; valaddr_reg:x3;
-val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rd==x22,
-/* opcode: fmvh.x.d ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
-val_offset:9*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rd==x21,
-/* opcode: fmvh.x.d ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
-val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rd==x20,
-/* opcode: fmvh.x.d ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
-val_offset:11*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rd==x19,
-/* opcode: fmvh.x.d ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
-val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rd==x18,
-/* opcode: fmvh.x.d ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
-val_offset:13*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rd==x17,
-/* opcode: fmvh.x.d ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
-val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rd==x16,
-/* opcode: fmvh.x.d ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
-val_offset:15*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rd==x15,
-/* opcode: fmvh.x.d ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
-val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rd==x14,
-/* opcode: fmvh.x.d ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
-val_offset:17*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rd==x13,
-/* opcode: fmvh.x.d ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
-val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rd==x12,
-/* opcode: fmvh.x.d ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
-val_offset:19*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rd==x11,
-/* opcode: fmvh.x.d ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
-val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rd==x10,
-/* opcode: fmvh.x.d ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
-val_offset:21*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rd==x9,
-/* opcode: fmvh.x.d ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
-val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_23:// rs1==f8, rd==x8,
-/* opcode: fmvh.x.d ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
-val_offset:23*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,
-/* opcode: fmvh.x.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
-val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
-
-inst_25:// rs1==f6, rd==x6,
-/* opcode: fmvh.x.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
-val_offset:1*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
-
-inst_26:// rs1==f5, rd==x5,
-/* opcode: fmvh.x.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
-val_offset:2*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,
-/* opcode: fmvh.x.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
-val_offset:3*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
-
-inst_28:// rs1==f3, rd==x3,
-/* opcode: fmvh.x.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
-val_offset:4*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
-
-inst_29:// rs1==f2, rd==x2,
-/* opcode: fmvh.x.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
-val_offset:5*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
-
-inst_30:// rs1==f1, rd==x1,
-/* opcode: fmvh.x.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
-val_offset:6*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
-
-inst_31:// rs1==f0, rd==x0,
-/* opcode: fmvh.x.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
-val_offset:7*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(4593818368519663827,64,FLEN)
-NAN_BOXED(4600778710533613932,64,FLEN)
-NAN_BOXED(13828134130799532672,64,FLEN)
-NAN_BOXED(4610891533192108602,64,FLEN)
-NAN_BOXED(4615336721960794565,64,FLEN)
-NAN_BOXED(4618534502842412089,64,FLEN)
-NAN_BOXED(10372132617207737155,64,FLEN)
-NAN_BOXED(9217722483915607826,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-test_dataset_1:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 10*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b23-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b23-01.S
deleted file mode 100644
index d54e70404..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b23-01.S
+++ /dev/null
@@ -1,320 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:48 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmvh.x.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmvh.x.d instruction of the RISC-V RV32FD_Zicsr_Zfa extension for the fmvh.x.d_b23 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmvh.x.d_b23)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f31; dest:x31; op1val:0x43dffffffffffffc; valaddr_reg:x3;
-val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f30; dest:x30; op1val:0x43dffffffffffffd; valaddr_reg:x3;
-val_offset:1*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f29; dest:x29; op1val:0x43dffffffffffffe; valaddr_reg:x3;
-val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f28; dest:x28; op1val:0x43dfffffffffffff; valaddr_reg:x3;
-val_offset:3*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f27; dest:x27; op1val:0x43e0000000000000; valaddr_reg:x3;
-val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f26; dest:x26; op1val:0x43e0000000000001; valaddr_reg:x3;
-val_offset:5*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f25; dest:x25; op1val:0x43e0000000000002; valaddr_reg:x3;
-val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f24; dest:x24; op1val:0x43e0000000000003; valaddr_reg:x3;
-val_offset:7*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f23; dest:x23; op1val:0x43e0000000000004; valaddr_reg:x3;
-val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rd==x22,
-/* opcode: fmvh.x.d ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
-val_offset:9*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rd==x21,
-/* opcode: fmvh.x.d ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
-val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rd==x20,
-/* opcode: fmvh.x.d ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
-val_offset:11*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rd==x19,
-/* opcode: fmvh.x.d ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
-val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rd==x18,
-/* opcode: fmvh.x.d ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
-val_offset:13*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rd==x17,
-/* opcode: fmvh.x.d ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
-val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rd==x16,
-/* opcode: fmvh.x.d ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
-val_offset:15*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rd==x15,
-/* opcode: fmvh.x.d ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
-val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rd==x14,
-/* opcode: fmvh.x.d ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
-val_offset:17*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rd==x13,
-/* opcode: fmvh.x.d ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
-val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rd==x12,
-/* opcode: fmvh.x.d ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
-val_offset:19*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rd==x11,
-/* opcode: fmvh.x.d ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
-val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rd==x10,
-/* opcode: fmvh.x.d ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
-val_offset:21*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rd==x9,
-/* opcode: fmvh.x.d ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
-val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_23:// rs1==f8, rd==x8,
-/* opcode: fmvh.x.d ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
-val_offset:23*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,
-/* opcode: fmvh.x.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
-val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
-
-inst_25:// rs1==f6, rd==x6,
-/* opcode: fmvh.x.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
-val_offset:1*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
-
-inst_26:// rs1==f5, rd==x5,
-/* opcode: fmvh.x.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
-val_offset:2*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,
-/* opcode: fmvh.x.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
-val_offset:3*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
-
-inst_28:// rs1==f3, rd==x3,
-/* opcode: fmvh.x.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
-val_offset:4*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
-
-inst_29:// rs1==f2, rd==x2,
-/* opcode: fmvh.x.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
-val_offset:5*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
-
-inst_30:// rs1==f1, rd==x1,
-/* opcode: fmvh.x.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
-val_offset:6*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
-
-inst_31:// rs1==f0, rd==x0,
-/* opcode: fmvh.x.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
-val_offset:7*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(4890909195324358652,64,FLEN)
-NAN_BOXED(4890909195324358653,64,FLEN)
-NAN_BOXED(4890909195324358654,64,FLEN)
-NAN_BOXED(4890909195324358655,64,FLEN)
-NAN_BOXED(4890909195324358656,64,FLEN)
-NAN_BOXED(4890909195324358657,64,FLEN)
-NAN_BOXED(4890909195324358658,64,FLEN)
-NAN_BOXED(4890909195324358659,64,FLEN)
-NAN_BOXED(4890909195324358660,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-test_dataset_1:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 10*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b24-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b24-01.S
deleted file mode 100644
index bbdb21f8a..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b24-01.S
+++ /dev/null
@@ -1,320 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:48 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmvh.x.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmvh.x.d instruction of the RISC-V RV32FD_Zicsr_Zfa extension for the fmvh.x.d_b24 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmvh.x.d_b24)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x3;
-val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f30; dest:x30; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
-val_offset:1*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f29; dest:x29; op1val:0xbff028f5c28f5c29; valaddr_reg:x3;
-val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f28; dest:x28; op1val:0xbff199999999999a; valaddr_reg:x3;
-val_offset:3*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f27; dest:x27; op1val:0x3fb999999999999a; valaddr_reg:x3;
-val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f26; dest:x26; op1val:0x3fefae147ae147ae; valaddr_reg:x3;
-val_offset:5*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f25; dest:x25; op1val:0xbfb999999999999a; valaddr_reg:x3;
-val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f24; dest:x24; op1val:0xbff0000000000000; valaddr_reg:x3;
-val_offset:7*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f23; dest:x23; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
-val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f22; dest:x22; op1val:0x3ff199999999999a; valaddr_reg:x3;
-val_offset:9*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f21; dest:x21; op1val:0x3ff0000000000000; valaddr_reg:x3;
-val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f20; dest:x20; op1val:0xbf847ae147ae147b; valaddr_reg:x3;
-val_offset:11*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f19; dest:x19; op1val:0xbfeccccccccccccd; valaddr_reg:x3;
-val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f18; dest:x18; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x3;
-val_offset:13*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f17; dest:x17; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
-val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f16; dest:x16; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x3;
-val_offset:15*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f15; dest:x15; op1val:0x3feccccccccccccd; valaddr_reg:x3;
-val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
-val_offset:17*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f13; dest:x13; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
-val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f12; dest:x12; op1val:0xbfefae147ae147ae; valaddr_reg:x3;
-val_offset:19*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f11; dest:x11; op1val:0x3ff028f5c28f5c29; valaddr_reg:x3;
-val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rd==x10,
-/* opcode: fmvh.x.d ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
-val_offset:21*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rd==x9,
-/* opcode: fmvh.x.d ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
-val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_23:// rs1==f8, rd==x8,
-/* opcode: fmvh.x.d ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
-val_offset:23*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,
-/* opcode: fmvh.x.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
-val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
-
-inst_25:// rs1==f6, rd==x6,
-/* opcode: fmvh.x.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
-val_offset:1*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
-
-inst_26:// rs1==f5, rd==x5,
-/* opcode: fmvh.x.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
-val_offset:2*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,
-/* opcode: fmvh.x.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
-val_offset:3*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
-
-inst_28:// rs1==f3, rd==x3,
-/* opcode: fmvh.x.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
-val_offset:4*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
-
-inst_29:// rs1==f2, rd==x2,
-/* opcode: fmvh.x.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
-val_offset:5*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
-
-inst_30:// rs1==f1, rd==x1,
-/* opcode: fmvh.x.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
-val_offset:6*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
-
-inst_31:// rs1==f0, rd==x0,
-/* opcode: fmvh.x.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
-val_offset:7*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(13829563663736771707,64,FLEN)
-NAN_BOXED(4576918229304087675,64,FLEN)
-NAN_BOXED(13830599491651066921,64,FLEN)
-NAN_BOXED(13831004815617530266,64,FLEN)
-NAN_BOXED(4591870180066957722,64,FLEN)
-NAN_BOXED(4607092346807469998,64,FLEN)
-NAN_BOXED(13815242216921733530,64,FLEN)
-NAN_BOXED(13830554455654793216,64,FLEN)
-NAN_BOXED(4606191626881995899,64,FLEN)
-NAN_BOXED(4607632778762754458,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13800290266158863483,64,FLEN)
-NAN_BOXED(13829653735729319117,64,FLEN)
-NAN_BOXED(13831049851613803971,64,FLEN)
-NAN_BOXED(4607677814759028163,64,FLEN)
-NAN_BOXED(4592590756007337001,64,FLEN)
-NAN_BOXED(4606281698874543309,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13815962792862112809,64,FLEN)
-NAN_BOXED(13830464383662245806,64,FLEN)
-NAN_BOXED(4607227454796291113,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-test_dataset_1:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 10*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b27-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b27-01.S
deleted file mode 100644
index 59c52bf73..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b27-01.S
+++ /dev/null
@@ -1,320 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:48 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmvh.x.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmvh.x.d instruction of the RISC-V RV32FD_Zicsr_Zfa extension for the fmvh.x.d_b27 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmvh.x.d_b27)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f31; dest:x31; op1val:0x7ff0000000000001; valaddr_reg:x3;
-val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f30; dest:x30; op1val:0xfff0000000000001; valaddr_reg:x3;
-val_offset:1*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f29; dest:x29; op1val:0x7ff4aaaaaaaaaaaa; valaddr_reg:x3;
-val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f28; dest:x28; op1val:0xfff4aaaaaaaaaaaa; valaddr_reg:x3;
-val_offset:3*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f27; dest:x27; op1val:0x7ff8000000000001; valaddr_reg:x3;
-val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f26; dest:x26; op1val:0xfff8000000000001; valaddr_reg:x3;
-val_offset:5*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x7ff and fm1 == 0xc000000000001 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f25; dest:x25; op1val:0x7ffc000000000001; valaddr_reg:x3;
-val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x7ff and fm1 == 0xc000000000001 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f24; dest:x24; op1val:0xfffc000000000001; valaddr_reg:x3;
-val_offset:7*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rd==x23,
-/* opcode: fmvh.x.d ; op1:f23; dest:x23; op1val:0x0; valaddr_reg:x3;
-val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rd==x22,
-/* opcode: fmvh.x.d ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
-val_offset:9*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rd==x21,
-/* opcode: fmvh.x.d ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
-val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rd==x20,
-/* opcode: fmvh.x.d ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
-val_offset:11*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rd==x19,
-/* opcode: fmvh.x.d ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
-val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rd==x18,
-/* opcode: fmvh.x.d ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
-val_offset:13*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rd==x17,
-/* opcode: fmvh.x.d ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
-val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rd==x16,
-/* opcode: fmvh.x.d ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
-val_offset:15*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rd==x15,
-/* opcode: fmvh.x.d ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
-val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rd==x14,
-/* opcode: fmvh.x.d ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
-val_offset:17*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rd==x13,
-/* opcode: fmvh.x.d ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
-val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rd==x12,
-/* opcode: fmvh.x.d ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
-val_offset:19*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rd==x11,
-/* opcode: fmvh.x.d ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
-val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rd==x10,
-/* opcode: fmvh.x.d ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
-val_offset:21*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rd==x9,
-/* opcode: fmvh.x.d ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
-val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_23:// rs1==f8, rd==x8,
-/* opcode: fmvh.x.d ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
-val_offset:23*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,
-/* opcode: fmvh.x.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
-val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
-
-inst_25:// rs1==f6, rd==x6,
-/* opcode: fmvh.x.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
-val_offset:1*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
-
-inst_26:// rs1==f5, rd==x5,
-/* opcode: fmvh.x.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
-val_offset:2*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,
-/* opcode: fmvh.x.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
-val_offset:3*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
-
-inst_28:// rs1==f3, rd==x3,
-/* opcode: fmvh.x.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
-val_offset:4*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
-
-inst_29:// rs1==f2, rd==x2,
-/* opcode: fmvh.x.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
-val_offset:5*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
-
-inst_30:// rs1==f1, rd==x1,
-/* opcode: fmvh.x.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
-val_offset:6*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
-
-inst_31:// rs1==f0, rd==x0,
-/* opcode: fmvh.x.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
-val_offset:7*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9220181987118721706,64,FLEN)
-NAN_BOXED(18443554023973497514,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9222246136947933185,64,FLEN)
-NAN_BOXED(18445618173802708993,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-test_dataset_1:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 10*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b28-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b28-01.S
deleted file mode 100644
index f2c449138..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b28-01.S
+++ /dev/null
@@ -1,320 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:48 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmvh.x.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmvh.x.d instruction of the RISC-V RV32FD_Zicsr_Zfa extension for the fmvh.x.d_b28 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmvh.x.d_b28)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
-val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fe and fm1 == 0x248ee18215dfa and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f30; dest:x30; op1val:0x3fe248ee18215dfa; valaddr_reg:x3;
-val_offset:1*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f29; dest:x29; op1val:0x3ff0000000000000; valaddr_reg:x3;
-val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x4000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f28; dest:x28; op1val:0x3ff4000000000000; valaddr_reg:x3;
-val_offset:3*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f27; dest:x27; op1val:0x3ff8000000000000; valaddr_reg:x3;
-val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xc000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f26; dest:x26; op1val:0x3ffc000000000000; valaddr_reg:x3;
-val_offset:5*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x400 and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f25; dest:x25; op1val:0x4000000000000000; valaddr_reg:x3;
-val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x400 and fm1 == 0x2000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f24; dest:x24; op1val:0x4002000000000000; valaddr_reg:x3;
-val_offset:7*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x400 and fm1 == 0x4000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f23; dest:x23; op1val:0x4004000000000000; valaddr_reg:x3;
-val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x400 and fm1 == 0x6000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f22; dest:x22; op1val:0x4006000000000000; valaddr_reg:x3;
-val_offset:9*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x43c and fm1 == 0xb72eb13dc494a and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f21; dest:x21; op1val:0x43cb72eb13dc494a; valaddr_reg:x3;
-val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f20; dest:x20; op1val:0x43e0000000000000; valaddr_reg:x3;
-val_offset:11*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f19; dest:x19; op1val:0x7ff0000000000000; valaddr_reg:x3;
-val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f18; dest:x18; op1val:0x7ff0000000000001; valaddr_reg:x3;
-val_offset:13*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f17; dest:x17; op1val:0x7ff8000000000001; valaddr_reg:x3;
-val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f16; dest:x16; op1val:0x8000000000000000; valaddr_reg:x3;
-val_offset:15*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x3fd and fm1 == 0xb008d57e19f88 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f15; dest:x15; op1val:0xbfdb008d57e19f88; valaddr_reg:x3;
-val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f14; dest:x14; op1val:0xbf80000000000000; valaddr_reg:x3;
-val_offset:17*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x400 and fm1 == 0x6000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f13; dest:x13; op1val:0xc006000000000000; valaddr_reg:x3;
-val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x400 and fm1 == 0x4000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f12; dest:x12; op1val:0xc004000000000000; valaddr_reg:x3;
-val_offset:19*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x400 and fm1 == 0x2000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f11; dest:x11; op1val:0xc002000000000000; valaddr_reg:x3;
-val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x400 and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f10; dest:x10; op1val:0xc000000000000000; valaddr_reg:x3;
-val_offset:21*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x3ff and fm1 == 0xc000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f9; dest:x9; op1val:0xbffc000000000000; valaddr_reg:x3;
-val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f8; dest:x8; op1val:0xbff8000000000000; valaddr_reg:x3;
-val_offset:23*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x4000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f7; dest:x7; op1val:0xbff4000000000000; valaddr_reg:x8;
-val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
-
-inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x43d and fm1 == 0x967a4ae26514c and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f6; dest:x6; op1val:0xc3d967a4ae26514c; valaddr_reg:x8;
-val_offset:1*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
-
-inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f5; dest:x5; op1val:0xc3e0000000000000; valaddr_reg:x8;
-val_offset:2*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f4; dest:x4; op1val:0xfff0000000000000; valaddr_reg:x8;
-val_offset:3*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
-
-inst_28:// rs1==f3, rd==x3,
-/* opcode: fmvh.x.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
-val_offset:4*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
-
-inst_29:// rs1==f2, rd==x2,
-/* opcode: fmvh.x.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
-val_offset:5*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
-
-inst_30:// rs1==f1, rd==x1,
-/* opcode: fmvh.x.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
-val_offset:6*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
-
-inst_31:// rs1==f0, rd==x0,
-/* opcode: fmvh.x.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
-val_offset:7*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(4603321956570324474,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4608308318706860032,64,FLEN)
-NAN_BOXED(4609434218613702656,64,FLEN)
-NAN_BOXED(4610560118520545280,64,FLEN)
-NAN_BOXED(4611686018427387904,64,FLEN)
-NAN_BOXED(4612248968380809216,64,FLEN)
-NAN_BOXED(4612811918334230528,64,FLEN)
-NAN_BOXED(4613374868287651840,64,FLEN)
-NAN_BOXED(4885124574789519690,64,FLEN)
-NAN_BOXED(4890909195324358656,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(13824644088208662408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13836746905142427648,64,FLEN)
-NAN_BOXED(13836183955189006336,64,FLEN)
-NAN_BOXED(13835621005235585024,64,FLEN)
-NAN_BOXED(13835058055282163712,64,FLEN)
-NAN_BOXED(13833932155375321088,64,FLEN)
-NAN_BOXED(13832806255468478464,64,FLEN)
-test_dataset_1:
-NAN_BOXED(13831680355561635840,64,FLEN)
-NAN_BOXED(14112424864336204108,64,FLEN)
-NAN_BOXED(14114281232179134464,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 10*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b29-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b29-01.S
deleted file mode 100644
index f65147292..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fmvh.x.d_b29-01.S
+++ /dev/null
@@ -1,320 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:48 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmvh.x.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmvh.x.d instruction of the RISC-V RV32FD_Zicsr_Zfa extension for the fmvh.x.d_b29 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmvh.x.d_b29)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f31; dest:x31; op1val:0x3fc08574923b8698; valaddr_reg:x3;
-val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f30; dest:x30; op1val:0x3fc08574923b8699; valaddr_reg:x3;
-val_offset:1*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f29; dest:x29; op1val:0x3fc08574923b869a; valaddr_reg:x3;
-val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f28; dest:x28; op1val:0x3fc08574923b869b; valaddr_reg:x3;
-val_offset:3*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f27; dest:x27; op1val:0x3fc08574923b869c; valaddr_reg:x3;
-val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f26; dest:x26; op1val:0x3fc08574923b869d; valaddr_reg:x3;
-val_offset:5*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f25; dest:x25; op1val:0x3fc08574923b869e; valaddr_reg:x3;
-val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f24; dest:x24; op1val:0x3fc08574923b869f; valaddr_reg:x3;
-val_offset:7*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f23; dest:x23; op1val:0xbfc08574923b8698; valaddr_reg:x3;
-val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f22; dest:x22; op1val:0xbfc08574923b8699; valaddr_reg:x3;
-val_offset:9*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f21; dest:x21; op1val:0xbfc08574923b869a; valaddr_reg:x3;
-val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f20; dest:x20; op1val:0xbfc08574923b869b; valaddr_reg:x3;
-val_offset:11*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f19; dest:x19; op1val:0xbfc08574923b869c; valaddr_reg:x3;
-val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f18; dest:x18; op1val:0xbfc08574923b869d; valaddr_reg:x3;
-val_offset:13*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f17; dest:x17; op1val:0xbfc08574923b869e; valaddr_reg:x3;
-val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0  
-/* opcode: fmvh.x.d ; op1:f16; dest:x16; op1val:0xbfc08574923b869f; valaddr_reg:x3;
-val_offset:15*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rd==x15,
-/* opcode: fmvh.x.d ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
-val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rd==x14,
-/* opcode: fmvh.x.d ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
-val_offset:17*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rd==x13,
-/* opcode: fmvh.x.d ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
-val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rd==x12,
-/* opcode: fmvh.x.d ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
-val_offset:19*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rd==x11,
-/* opcode: fmvh.x.d ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
-val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rd==x10,
-/* opcode: fmvh.x.d ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
-val_offset:21*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rd==x9,
-/* opcode: fmvh.x.d ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
-val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_23:// rs1==f8, rd==x8,
-/* opcode: fmvh.x.d ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
-val_offset:23*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,
-/* opcode: fmvh.x.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
-val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
-
-inst_25:// rs1==f6, rd==x6,
-/* opcode: fmvh.x.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
-val_offset:1*FLEN/8; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
-
-inst_26:// rs1==f5, rd==x5,
-/* opcode: fmvh.x.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
-val_offset:2*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,
-/* opcode: fmvh.x.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
-val_offset:3*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
-
-inst_28:// rs1==f3, rd==x3,
-/* opcode: fmvh.x.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
-val_offset:4*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
-
-inst_29:// rs1==f2, rd==x2,
-/* opcode: fmvh.x.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
-val_offset:5*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
-
-inst_30:// rs1==f1, rd==x1,
-/* opcode: fmvh.x.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
-val_offset:6*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
-
-inst_31:// rs1==f0, rd==x0,
-/* opcode: fmvh.x.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
-val_offset:7*FLEN/8; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP_NRM(fmvh.x.d, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(4593818355633981080,64,FLEN)
-NAN_BOXED(4593818355633981081,64,FLEN)
-NAN_BOXED(4593818355633981082,64,FLEN)
-NAN_BOXED(4593818355633981083,64,FLEN)
-NAN_BOXED(4593818355633981084,64,FLEN)
-NAN_BOXED(4593818355633981085,64,FLEN)
-NAN_BOXED(4593818355633981086,64,FLEN)
-NAN_BOXED(4593818355633981087,64,FLEN)
-NAN_BOXED(13817190392488756888,64,FLEN)
-NAN_BOXED(13817190392488756889,64,FLEN)
-NAN_BOXED(13817190392488756890,64,FLEN)
-NAN_BOXED(13817190392488756891,64,FLEN)
-NAN_BOXED(13817190392488756892,64,FLEN)
-NAN_BOXED(13817190392488756893,64,FLEN)
-NAN_BOXED(13817190392488756894,64,FLEN)
-NAN_BOXED(13817190392488756895,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-test_dataset_1:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 10*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fround.d_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fround.d_b1-01.S
deleted file mode 100644
index d28631a34..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fround.d_b1-01.S
+++ /dev/null
@@ -1,353 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:11:52 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fround.d.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fround.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fround.d_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fround.d_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f29; dest:f30; op1val:0x8000000000000000; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f30, f29, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f29, f30, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f27; dest:f28; op1val:0x8000000000000001; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f28, f27, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f27, f28, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f25; dest:f26; op1val:0x8000000000000002; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f26, f25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f26; dest:f25; op1val:0xfffffffffffff; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f25, f26, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f23; dest:f24; op1val:0x800fffffffffffff; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f24, f23, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f24; dest:f23; op1val:0x10000000000000; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f23, f24, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f21; dest:f22; op1val:0x8010000000000000; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f22, f21, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f22; dest:f21; op1val:0x10000000000002; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f21, f22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f19; dest:f20; op1val:0x8010000000000002; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f20, f19, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f20; dest:f19; op1val:0x7fefffffffffffff; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f19, f20, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f17; dest:f18; op1val:0xffefffffffffffff; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f18, f17, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f18; dest:f17; op1val:0x7ff0000000000000; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f17, f18, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f15; dest:f16; op1val:0xfff0000000000000; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f16, f15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f16; dest:f15; op1val:0x7ff8000000000000; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f15, f16, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f13; dest:f14; op1val:0xfff8000000000000; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f14, f13, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f14; dest:f13; op1val:0x7ff8000000000001; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f13, f14, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f11; dest:f12; op1val:0xfff8000000000001; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f12, f11, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f12; dest:f11; op1val:0x7ff0000000000001; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f11, f12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f9; dest:f10; op1val:0xfff0000000000001; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f10, f9, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f10; dest:f9; op1val:0x3ff0000000000000; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f9, f10, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f7; dest:f8; op1val:0xbf80000000000000; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f8, f7, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f8, rd==f7,
-/* opcode: fround.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
-val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f7, f8, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f5, rd==f6,
-/* opcode: fround.d ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
-val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f6, f5, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f6, rd==f5,
-/* opcode: fround.d ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
-val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f5, f6, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rd==f4,
-/* opcode: fround.d ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
-val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f4, f3, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f4, rd==f3,
-/* opcode: fround.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
-val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f3, f4, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f1, rd==f2,
-/* opcode: fround.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
-val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f2, f1, dyn, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f2, rd==f1,
-/* opcode: fround.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
-val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f1, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f0,
-/* opcode: fround.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
-val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f31, f0, dyn, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rd==f0,
-/* opcode: fround.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
-val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f0, f31, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 66*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fround_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fround_b1-01.S
deleted file mode 100644
index b526bfc48..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D_Zfa/src/fround_b1-01.S
+++ /dev/null
@@ -1,353 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:11:45 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fround.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fround.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fround_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fround_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f29; dest:f30; op1val:0x80000000; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f30, f29, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f29, f30, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f28, f27, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f27, f28, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f25; dest:f26; op1val:0x807ffffe; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f26, f25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f26; dest:f25; op1val:0x7fffff; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f25, f26, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f23; dest:f24; op1val:0x807fffff; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f24, f23, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f23, f24, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f22, f21, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f22; dest:f21; op1val:0x800001; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f21, f22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f19; dest:f20; op1val:0x80855555; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f20, f19, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f20; dest:f19; op1val:0x7f7fffff; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f19, f20, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f17; dest:f18; op1val:0xff7fffff; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f18, f17, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f18; dest:f17; op1val:0x7f800000; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f17, f18, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f15; dest:f16; op1val:0xff800000; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f16, f15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f16; dest:f15; op1val:0x7fc00000; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f15, f16, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f13; dest:f14; op1val:0xffc00000; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f14, f13, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f14; dest:f13; op1val:0x7fc00001; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f13, f14, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f11; dest:f12; op1val:0xffc55555; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f12, f11, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f12; dest:f11; op1val:0x7f800001; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f11, f12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f9; dest:f10; op1val:0xffaaaaaa; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f10, f9, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f10; dest:f9; op1val:0x3f800000; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f9, f10, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f7; dest:f8; op1val:0xbf800000; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f8, f7, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f8, rd==f7,
-/* opcode: fround.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
-val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f7, f8, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f5, rd==f6,
-/* opcode: fround.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
-val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f6, f5, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f6, rd==f5,
-/* opcode: fround.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
-val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f5, f6, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rd==f4,
-/* opcode: fround.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
-val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f4, f3, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f4, rd==f3,
-/* opcode: fround.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
-val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f3, f4, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f1, rd==f2,
-/* opcode: fround.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
-val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f2, f1, dyn, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f2, rd==f1,
-/* opcode: fround.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
-val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f1, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f0,
-/* opcode: fround.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
-val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f31, f0, dyn, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rd==f0,
-/* opcode: fround.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
-val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f0, f31, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 66*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fleq_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fleq_b1-01.S
deleted file mode 100644
index 4d6cc500f..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fleq_b1-01.S
+++ /dev/null
@@ -1,4740 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:12:09 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fleq.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fleq.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fleq_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f29; op2:f29; dest:x30; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f30; op2:f31; dest:x29; op1val:0x0; op2val:0x1;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f28; op2:f27; dest:x28; op1val:0x0; op2val:0x80000001;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f27; op2:f28; dest:x27; op1val:0x0; op2val:0x2;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f26; op2:f25; dest:x26; op1val:0x0; op2val:0x807ffffe;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f25; op2:f26; dest:x25; op1val:0x0; op2val:0x7fffff;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f24; op2:f23; dest:x24; op1val:0x0; op2val:0x807fffff;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f23; op2:f24; dest:x23; op1val:0x0; op2val:0x800000;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f22; op2:f21; dest:x22; op1val:0x0; op2val:0x80800000;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f21; op2:f22; dest:x21; op1val:0x0; op2val:0x800001;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f20; op2:f19; dest:x20; op1val:0x0; op2val:0x80855555;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f19; op2:f20; dest:x19; op1val:0x0; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f18; op2:f17; dest:x18; op1val:0x0; op2val:0xff7fffff;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f17; op2:f18; dest:x17; op1val:0x0; op2val:0x7f800000;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f16; op2:f15; dest:x16; op1val:0x0; op2val:0xff800000;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f15; op2:f16; dest:x15; op1val:0x0; op2val:0x7fc00000;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f14; op2:f13; dest:x14; op1val:0x0; op2val:0xffc00000;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f13; op2:f14; dest:x13; op1val:0x0; op2val:0x7fc00001;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f12; op2:f11; dest:x12; op1val:0x0; op2val:0xffc55555;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f11; op2:f12; dest:x11; op1val:0x0; op2val:0x7f800001;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f10; op2:f9; dest:x10; op1val:0x0; op2val:0xffaaaaaa;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f9; op2:f10; dest:x9; op1val:0x0; op2val:0x3f800000;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f8; op2:f7; dest:x8; op1val:0x0; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f7; op2:f8; dest:x7; op1val:0x80000000; op2val:0x0;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f6; op2:f5; dest:x6; op1val:0x80000000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f5; op2:f6; dest:x5; op1val:0x80000000; op2val:0x1;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f4; op2:f3; dest:x4; op1val:0x80000000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f3; op2:f4; dest:x3; op1val:0x80000000; op2val:0x2;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f2; op2:f1; dest:x2; op1val:0x80000000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f1; op2:f2; dest:x1; op1val:0x80000000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f0; op2:f31; dest:x31; op1val:0x80000000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f0; dest:x31; op1val:0x80000000; op2val:0x800000;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x0; op1val:0x80000000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x800001;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x0;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80000000;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x1;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80000001;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x2;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x800000;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80800000;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x800001;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80855555;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xff800000;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x0;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x1;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x2;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x800000;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x800001;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x0;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80000000;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x1;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80000001;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x2;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x800000;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80800000;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x800001;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80855555;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xff800000;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x0;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x1;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x2;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x800000;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x800001;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x0;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x1;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x2;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x0;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x1;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x2;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x0;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x1;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x2;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x800000;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x800001;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x0;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80000000;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x1;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80000001;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x2;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x800000;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80800000;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x800001;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80855555;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xff800000;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x0;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x1;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x2;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x0;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x1;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x2;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x0;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x1;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x2;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x800000;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x800001;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x0;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x1;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x2;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x800000;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x800001;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x0;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x1;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x2;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x800000;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x800001;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x0;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80000000;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x1;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80000001;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x2;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x800000;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80800000;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x800001;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80855555;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xff800000;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x0;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x1;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x2;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x800000;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x800001;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x0;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x1;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x2;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x0;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x1;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x2;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x80000000;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-test_dataset_1:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
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-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
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-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
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-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
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-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 80*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fleq_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fleq_b19-01.S
deleted file mode 100644
index 73b140654..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fleq_b19-01.S
+++ /dev/null
@@ -1,8712 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:12:09 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fleq.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fleq.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fleq_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x7e36c1bf;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f29; op2:f29; dest:x30; op1val:0x7e36c1bf; op2val:0x7e36c1bf;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x4038a5 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f30; op2:f31; dest:x29; op1val:0x7f7fffff; op2val:0x7d4038a5;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0xfa and fm1 == 0x4038a5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f28; op2:f27; dest:x28; op1val:0x7d4038a5; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f27; op2:f28; dest:x27; op1val:0x7f7fffff; op2val:0x7ef046ce;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f26; op2:f25; dest:x26; op1val:0x7e36c1bf; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f25; op2:f26; dest:x25; op1val:0x7e36c1bf; op2val:0x7e472f12;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f24; op2:f23; dest:x24; op1val:0x7e472f12; op2val:0x7e36c1bf;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f23; op2:f24; dest:x23; op1val:0x7e36c1bf; op2val:0x7f2099c0;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x007b00 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f22; op2:f21; dest:x22; op1val:0x7f7fffff; op2val:0x7d807b00;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0xfb and fm1 == 0x007b00 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f21; op2:f22; dest:x21; op1val:0x7d807b00; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f20; op2:f19; dest:x20; op1val:0x7f7fffff; op2val:0x7f2099c0;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f19; op2:f20; dest:x19; op1val:0x7e36c1bf; op2val:0x7ef3c956;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x430778 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f18; op2:f17; dest:x18; op1val:0x7f7fffff; op2val:0x7d430778;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0xfa and fm1 == 0x430778 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f17; op2:f18; dest:x17; op1val:0x7d430778; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f16; op2:f15; dest:x16; op1val:0x7f7fffff; op2val:0x7ef3c956;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f15; op2:f16; dest:x15; op1val:0x7e36c1bf; op2val:0xfeaf0416;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x0c0345 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f14; op2:f13; dest:x14; op1val:0x7f7fffff; op2val:0xfd0c0345;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c0345 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f13; op2:f14; dest:x13; op1val:0xfd0c0345; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f12; op2:f11; dest:x12; op1val:0x7f7fffff; op2val:0xfeaf0416;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f11; op2:f12; dest:x11; op1val:0x7e36c1bf; op2val:0xff336b1f;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0f88e6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f10; op2:f9; dest:x10; op1val:0x7f7fffff; op2val:0xfd8f88e6;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 1 and fe1 == 0xfb and fm1 == 0x0f88e6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f9; op2:f10; dest:x9; op1val:0xfd8f88e6; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f8; op2:f7; dest:x8; op1val:0x7f7fffff; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f7; op2:f8; dest:x7; op1val:0x7e36c1bf; op2val:0xff130229;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x6b36a9 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f6; op2:f5; dest:x6; op1val:0x7f7fffff; op2val:0xfd6b36a9;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0xfa and fm1 == 0x6b36a9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f5; op2:f6; dest:x5; op1val:0xfd6b36a9; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f4; op2:f3; dest:x4; op1val:0x7f7fffff; op2val:0xff130229;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f3; op2:f4; dest:x3; op1val:0x7e36c1bf; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x20dd41 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f2; op2:f1; dest:x2; op1val:0x7f7fffff; op2val:0xfd20dd41;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0xfa and fm1 == 0x20dd41 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f1; op2:f2; dest:x1; op1val:0xfd20dd41; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f0; op2:f31; dest:x31; op1val:0x7f7fffff; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f0; dest:x31; op1val:0x7e36c1bf; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x0; op1val:0xfdcaaeb1; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0xfb and fm2 == 0x02ddf4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x7d82ddf4;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x02ddf4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d82ddf4; op2val:0x42216f;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x42216f;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a94b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68e714 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xa94b; op2val:0x7e68e714;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68e714 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a94b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e68e714; op2val:0xa94b;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a94b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xa94b; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a94b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0xa94b;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0xfc and fm2 == 0x301931 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x7e301931;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x301931 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e301931; op2val:0x42216f;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0xfb and fm2 == 0x620ff4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x7de20ff4;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x620ff4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7de20ff4; op2val:0x42216f;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39119c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x7db9119c;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39119c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7db9119c; op2val:0x42216f;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0c1bbb and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0xfd8c1bbb;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0c1bbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8c1bbb; op2val:0x42216f;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x069cf1 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x0fbbb6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x69cf1; op2val:0xfe8fbbb6;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x0fbbb6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x069cf1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe8fbbb6; op2val:0x69cf1;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x069cf1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x69cf1; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x069cf1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x69cf1;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x3b633c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0xfdbb633c;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x3b633c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdbb633c; op2val:0x42216f;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0xfc and fm2 == 0x163ab8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0xfe163ab8;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x163ab8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe163ab8; op2val:0x42216f;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0xfa and fm2 == 0x370ed0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0xfd370ed0;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x370ed0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd370ed0; op2val:0x42216f;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x7f0;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 0 and fe1 == 0x81 and fm1 == 0x425723 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x40c25723; op2val:0x7f0;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x425723 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x40c25723;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x81 and fm2 == 0x425723 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x40c25723;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x4038a5 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d4038a5; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0xfa and fm2 == 0x4038a5 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x7d4038a5;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x4038a5 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d4038a5; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0xff130229;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x4038a5 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d4038a5; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 0 and fe2 == 0xfa and fm2 == 0x4038a5 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0x7d4038a5;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x4038a5 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d4038a5; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x11638a;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x11638a;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002c83 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2c83; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002c83 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x2c83;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002c83 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2c83; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002c83 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x2c83;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x11638a;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x11638a;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x11638a;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01bd27 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1bd27; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01bd27 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x1bd27;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01bd27 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1bd27; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01bd27 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x1bd27;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x11638a;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x11638a;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x11638a;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x7f0;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x4c679b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fcc679b; op2val:0x7f0;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c679b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x3fcc679b;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c679b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x3fcc679b;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0xff130229;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x02ddf4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x7d82ddf4;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x02ddf4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d82ddf4; op2val:0x481322;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x481322;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b882 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68e714 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xb882; op2val:0x7e68e714;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68e714 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b882 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e68e714; op2val:0xb882;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b882 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xb882; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b882 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0xb882;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x301931 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x7e301931;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x301931 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e301931; op2val:0x481322;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x620ff4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x7de20ff4;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x620ff4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7de20ff4; op2val:0x481322;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39119c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x7db9119c;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39119c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7db9119c; op2val:0x481322;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0c1bbb and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0xfd8c1bbb;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0c1bbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8c1bbb; op2val:0x481322;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x07351d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x0fbbb6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7351d; op2val:0xfe8fbbb6;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x0fbbb6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07351d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe8fbbb6; op2val:0x7351d;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x07351d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7351d; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07351d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x7351d;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x3b633c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0xfdbb633c;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x3b633c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdbb633c; op2val:0x481322;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x163ab8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0xfe163ab8;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x163ab8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe163ab8; op2val:0x481322;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x370ed0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0xfd370ed0;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x370ed0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd370ed0; op2val:0x481322;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x7f0;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x81 and fm1 == 0x53cf02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x40d3cf02; op2val:0x7f0;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x53cf02 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x40d3cf02;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x53cf02 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x40d3cf02;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x007b00 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d807b00; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x007b00 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x7d807b00;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x007b00 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d807b00; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0xff130229;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x007b00 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d807b00; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 0 and fe2 == 0xfb and fm2 == 0x007b00 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0x7d807b00;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x007b00 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d807b00; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003b82 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3b82; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003b82 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x3b82;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003b82 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3b82; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003b82 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x3b82;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025314 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x25314; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025314 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x25314;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025314 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x25314; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025314 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x25314;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x7f0;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x089fb6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x40089fb6; op2val:0x7f0;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x089fb6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x40089fb6;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x089fb6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x40089fb6;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x430778 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d430778; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0xfa and fm2 == 0x430778 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x7d430778;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x430778 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d430778; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0xff130229;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x430778 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d430778; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 0 and fe2 == 0xfa and fm2 == 0x430778 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0x7d430778;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x430778 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d430778; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x11a491;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x11a491;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002d2a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2d2a; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002d2a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x2d2a;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002d2a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2d2a; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002d2a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x2d2a;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x11a491;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x11a491;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x11a491;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c3a8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c3a8; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01c3a8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x1c3a8;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c3a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c3a8; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01c3a8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x1c3a8;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x11a491;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x11a491;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x11a491;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x7f0;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x4f63fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fcf63fe; op2val:0x7f0;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4f63fe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x3fcf63fe;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4f63fe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x3fcf63fe;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c0345 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c0345; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x0c0345 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xfd0c0345;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c0345 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c0345; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xff130229;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c0345 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c0345; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x0c0345 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xfd0c0345;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c0345 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c0345; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00206c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000206c; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00206c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x8000206c;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00206c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000206c; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00206c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x8000206c;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01443f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001443f; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01443f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x8001443f;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01443f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001443f; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01443f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x8001443f;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x7f0;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x14e31a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf94e31a; op2val:0x7f0;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x14e31a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbf94e31a;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x14e31a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xbf94e31a;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0f88e6 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8f88e6; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0f88e6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xfd8f88e6;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0f88e6 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8f88e6; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xff130229;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0f88e6 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8f88e6; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0f88e6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xfd8f88e6;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0f88e6 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8f88e6; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00427b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000427b; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00427b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x8000427b;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00427b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000427b; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00427b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x8000427b;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0298ce and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800298ce; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0298ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800298ce;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0298ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800298ce; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0298ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x800298ce;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x7f0;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 1 and fe1 == 0x80 and fm1 == 0x18a1e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc018a1e0; op2val:0x7f0;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x18a1e0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc018a1e0;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x80 and fm2 == 0x18a1e0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xc018a1e0;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x6b36a9 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd6b36a9; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x6b36a9 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xfd6b36a9;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xff130229;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x6b36a9 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd6b36a9; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xff130229;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x6b36a9 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd6b36a9; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x6b36a9 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xfd6b36a9;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x6b36a9 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd6b36a9; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003678 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80003678; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003678 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80003678;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003678 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80003678; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003678 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x80003678;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0220b7 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800220b7; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0220b7 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800220b7;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0220b7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800220b7; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0220b7 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x800220b7;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x7f0;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x7a1f35 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbffa1f35; op2val:0x7f0;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x7a1f35 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbffa1f35;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x7a1f35 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xbffa1f35;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x20dd41 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd20dd41; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x20dd41 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xfd20dd41;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x20dd41 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd20dd41; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x20dd41 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd20dd41; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x20dd41 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xfd20dd41;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x20dd41 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd20dd41; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002540 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80002540; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002540 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80002540;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002540 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80002540; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002540 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x80002540;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x017489 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80017489; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x017489 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80017489;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x017489 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80017489; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x017489 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x80017489;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x2b0f6c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbfab0f6c; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x2b0f6c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbfab0f6c;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x2b0f6c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xbfab0f6c;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-
-inst_578:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1110*FLEN/8, x10, x6, x7)
-
-inst_579:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1112*FLEN/8, x10, x6, x7)
-
-inst_580:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1114*FLEN/8, x10, x6, x7)
-
-inst_581:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1116*FLEN/8, x10, x6, x7)
-
-inst_582:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1118*FLEN/8, x10, x6, x7)
-
-inst_583:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x02ddf4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x7d82ddf4;
-valaddr_reg:x9; val_offset:1120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1120*FLEN/8, x10, x6, x7)
-
-inst_584:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x02ddf4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d82ddf4; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1122*FLEN/8, x10, x6, x7)
-
-inst_585:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1124*FLEN/8, x10, x6, x7)
-
-inst_586:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1126*FLEN/8, x10, x6, x7)
-
-inst_587:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1128*FLEN/8, x10, x6, x7)
-
-inst_588:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x005de0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68e714 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80005de0; op2val:0x7e68e714;
-valaddr_reg:x9; val_offset:1130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1130*FLEN/8, x10, x6, x7)
-
-inst_589:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68e714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005de0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e68e714; op2val:0x80005de0;
-valaddr_reg:x9; val_offset:1132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1132*FLEN/8, x10, x6, x7)
-
-inst_590:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x005de0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80005de0; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1134*FLEN/8, x10, x6, x7)
-
-inst_591:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005de0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x80005de0;
-valaddr_reg:x9; val_offset:1136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1136*FLEN/8, x10, x6, x7)
-
-inst_592:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1138*FLEN/8, x10, x6, x7)
-
-inst_593:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x301931 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x7e301931;
-valaddr_reg:x9; val_offset:1140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1140*FLEN/8, x10, x6, x7)
-
-inst_594:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x301931 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e301931; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1142*FLEN/8, x10, x6, x7)
-
-inst_595:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1144*FLEN/8, x10, x6, x7)
-
-inst_596:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1146*FLEN/8, x10, x6, x7)
-
-inst_597:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x620ff4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x7de20ff4;
-valaddr_reg:x9; val_offset:1148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1148*FLEN/8, x10, x6, x7)
-
-inst_598:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x620ff4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7de20ff4; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1150*FLEN/8, x10, x6, x7)
-
-inst_599:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1152*FLEN/8, x10, x6, x7)
-
-inst_600:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1154*FLEN/8, x10, x6, x7)
-
-inst_601:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39119c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x7db9119c;
-valaddr_reg:x9; val_offset:1156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1156*FLEN/8, x10, x6, x7)
-
-inst_602:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39119c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7db9119c; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1158*FLEN/8, x10, x6, x7)
-
-inst_603:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1160*FLEN/8, x10, x6, x7)
-
-inst_604:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1162*FLEN/8, x10, x6, x7)
-
-inst_605:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0c1bbb and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0xfd8c1bbb;
-valaddr_reg:x9; val_offset:1164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1164*FLEN/8, x10, x6, x7)
-
-inst_606:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0c1bbb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8c1bbb; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1166*FLEN/8, x10, x6, x7)
-
-inst_607:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1168*FLEN/8, x10, x6, x7)
-
-inst_608:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1170*FLEN/8, x10, x6, x7)
-
-inst_609:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03aac2 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x0fbbb6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8003aac2; op2val:0xfe8fbbb6;
-valaddr_reg:x9; val_offset:1172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1172*FLEN/8, x10, x6, x7)
-
-inst_610:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x0fbbb6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03aac2 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe8fbbb6; op2val:0x8003aac2;
-valaddr_reg:x9; val_offset:1174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1174*FLEN/8, x10, x6, x7)
-
-inst_611:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03aac2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8003aac2; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1176*FLEN/8, x10, x6, x7)
-
-inst_612:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03aac2 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x8003aac2;
-valaddr_reg:x9; val_offset:1178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1178*FLEN/8, x10, x6, x7)
-
-inst_613:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1180*FLEN/8, x10, x6, x7)
-
-inst_614:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x3b633c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0xfdbb633c;
-valaddr_reg:x9; val_offset:1182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1182*FLEN/8, x10, x6, x7)
-
-inst_615:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x3b633c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdbb633c; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1184*FLEN/8, x10, x6, x7)
-
-inst_616:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1186*FLEN/8, x10, x6, x7)
-
-inst_617:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1188*FLEN/8, x10, x6, x7)
-
-inst_618:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x163ab8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0xfe163ab8;
-valaddr_reg:x9; val_offset:1190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1190*FLEN/8, x10, x6, x7)
-
-inst_619:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x163ab8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe163ab8; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1192*FLEN/8, x10, x6, x7)
-
-inst_620:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1194*FLEN/8, x10, x6, x7)
-
-inst_621:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1196*FLEN/8, x10, x6, x7)
-
-inst_622:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x370ed0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0xfd370ed0;
-valaddr_reg:x9; val_offset:1198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1198*FLEN/8, x10, x6, x7)
-
-inst_623:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x370ed0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd370ed0; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1200*FLEN/8, x10, x6, x7)
-
-inst_624:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1202*FLEN/8, x10, x6, x7)
-
-inst_625:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1204*FLEN/8, x10, x6, x7)
-
-inst_626:// fs1 == 1 and fe1 == 0x80 and fm1 == 0x578765 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc0578765; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1206*FLEN/8, x10, x6, x7)
-
-inst_627:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x578765 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc0578765;
-valaddr_reg:x9; val_offset:1208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1208*FLEN/8, x10, x6, x7)
-
-inst_628:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x578765 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xc0578765;
-valaddr_reg:x9; val_offset:1210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1210*FLEN/8, x10, x6, x7)
-
-inst_629:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1212*FLEN/8, x10, x6, x7)
-
-inst_630:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x02ddf4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d82ddf4; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1214*FLEN/8, x10, x6, x7)
-
-inst_631:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x02ddf4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7d82ddf4;
-valaddr_reg:x9; val_offset:1216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1216*FLEN/8, x10, x6, x7)
-
-inst_632:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1218*FLEN/8, x10, x6, x7)
-
-inst_633:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1220*FLEN/8, x10, x6, x7)
-
-inst_634:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1222*FLEN/8, x10, x6, x7)
-
-inst_635:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:1224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1224*FLEN/8, x10, x6, x7)
-
-inst_636:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1226*FLEN/8, x10, x6, x7)
-
-inst_637:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x02ddf4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d82ddf4; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1228*FLEN/8, x10, x6, x7)
-
-inst_638:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1230*FLEN/8, x10, x6, x7)
-
-inst_639:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1232*FLEN/8, x10, x6, x7)
-
-inst_640:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1234*FLEN/8, x10, x6, x7)
-
-inst_641:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1236*FLEN/8, x10, x6, x7)
-
-inst_642:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1238*FLEN/8, x10, x6, x7)
-
-inst_643:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1240*FLEN/8, x10, x6, x7)
-
-inst_644:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1242*FLEN/8, x10, x6, x7)
-
-inst_645:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1244*FLEN/8, x10, x6, x7)
-
-inst_646:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1246*FLEN/8, x10, x6, x7)
-
-inst_647:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1248*FLEN/8, x10, x6, x7)
-
-inst_648:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1250*FLEN/8, x10, x6, x7)
-
-inst_649:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1252*FLEN/8, x10, x6, x7)
-
-inst_650:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1254*FLEN/8, x10, x6, x7)
-
-inst_651:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x02ddf4 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d82ddf4; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1256*FLEN/8, x10, x6, x7)
-
-inst_652:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1258*FLEN/8, x10, x6, x7)
-
-inst_653:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003c9d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3c9d; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1260*FLEN/8, x10, x6, x7)
-
-inst_654:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003c9d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x3c9d;
-valaddr_reg:x9; val_offset:1262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1262*FLEN/8, x10, x6, x7)
-
-inst_655:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003c9d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3c9d; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1264*FLEN/8, x10, x6, x7)
-
-inst_656:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003c9d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x3c9d;
-valaddr_reg:x9; val_offset:1266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1266*FLEN/8, x10, x6, x7)
-
-inst_657:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1268*FLEN/8, x10, x6, x7)
-
-inst_658:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1270*FLEN/8, x10, x6, x7)
-
-inst_659:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1272*FLEN/8, x10, x6, x7)
-
-inst_660:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1274*FLEN/8, x10, x6, x7)
-
-inst_661:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1276*FLEN/8, x10, x6, x7)
-
-inst_662:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1278*FLEN/8, x10, x6, x7)
-
-inst_663:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1280*FLEN/8, x10, x6, x7)
-
-inst_664:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1282*FLEN/8, x10, x6, x7)
-
-inst_665:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1284*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_5)
-
-inst_666:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025e22 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x25e22; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1286*FLEN/8, x10, x6, x7)
-
-inst_667:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025e22 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x25e22;
-valaddr_reg:x9; val_offset:1288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1288*FLEN/8, x10, x6, x7)
-
-inst_668:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025e22 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x25e22; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1290*FLEN/8, x10, x6, x7)
-
-inst_669:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025e22 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x25e22;
-valaddr_reg:x9; val_offset:1292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1292*FLEN/8, x10, x6, x7)
-
-inst_670:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1294*FLEN/8, x10, x6, x7)
-
-inst_671:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1296*FLEN/8, x10, x6, x7)
-
-inst_672:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1298*FLEN/8, x10, x6, x7)
-
-inst_673:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1300*FLEN/8, x10, x6, x7)
-
-inst_674:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1302*FLEN/8, x10, x6, x7)
-
-inst_675:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1304*FLEN/8, x10, x6, x7)
-
-inst_676:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1306*FLEN/8, x10, x6, x7)
-
-inst_677:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x0b2963 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x400b2963; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1308*FLEN/8, x10, x6, x7)
-
-inst_678:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0b2963 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x400b2963;
-valaddr_reg:x9; val_offset:1310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1310*FLEN/8, x10, x6, x7)
-
-inst_679:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0b2963 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x400b2963;
-valaddr_reg:x9; val_offset:1312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1312*FLEN/8, x10, x6, x7)
-
-inst_680:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1314*FLEN/8, x10, x6, x7)
-
-inst_681:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68e714 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e68e714; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1316*FLEN/8, x10, x6, x7)
-
-inst_682:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68e714 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7e68e714;
-valaddr_reg:x9; val_offset:1318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1318*FLEN/8, x10, x6, x7)
-
-inst_683:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1320*FLEN/8, x10, x6, x7)
-
-inst_684:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1322*FLEN/8, x10, x6, x7)
-
-inst_685:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1324*FLEN/8, x10, x6, x7)
-
-inst_686:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1326*FLEN/8, x10, x6, x7)
-
-inst_687:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68e714 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e68e714; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1328*FLEN/8, x10, x6, x7)
-
-inst_688:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1330*FLEN/8, x10, x6, x7)
-
-inst_689:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1332*FLEN/8, x10, x6, x7)
-
-inst_690:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1334*FLEN/8, x10, x6, x7)
-
-inst_691:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1336*FLEN/8, x10, x6, x7)
-
-inst_692:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1338*FLEN/8, x10, x6, x7)
-
-inst_693:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1340*FLEN/8, x10, x6, x7)
-
-inst_694:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1342*FLEN/8, x10, x6, x7)
-
-inst_695:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68e714 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e68e714; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1344*FLEN/8, x10, x6, x7)
-
-inst_696:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1346*FLEN/8, x10, x6, x7)
-
-inst_697:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1348*FLEN/8, x10, x6, x7)
-
-inst_698:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1350*FLEN/8, x10, x6, x7)
-
-inst_699:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1352*FLEN/8, x10, x6, x7)
-
-inst_700:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a320 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0xa320;
-valaddr_reg:x9; val_offset:1354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1354*FLEN/8, x10, x6, x7)
-
-inst_701:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a320 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xa320; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1356*FLEN/8, x10, x6, x7)
-
-inst_702:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1358*FLEN/8, x10, x6, x7)
-
-inst_703:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1360*FLEN/8, x10, x6, x7)
-
-inst_704:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0068b4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x68b4;
-valaddr_reg:x9; val_offset:1362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1362*FLEN/8, x10, x6, x7)
-
-inst_705:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0068b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x68b4; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1364*FLEN/8, x10, x6, x7)
-
-inst_706:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1366*FLEN/8, x10, x6, x7)
-
-inst_707:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1368*FLEN/8, x10, x6, x7)
-
-inst_708:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0055b7 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x55b7;
-valaddr_reg:x9; val_offset:1370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1370*FLEN/8, x10, x6, x7)
-
-inst_709:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0055b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x55b7; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1372*FLEN/8, x10, x6, x7)
-
-inst_710:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1374*FLEN/8, x10, x6, x7)
-
-inst_711:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1376*FLEN/8, x10, x6, x7)
-
-inst_712:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0040e4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x800040e4;
-valaddr_reg:x9; val_offset:1378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1378*FLEN/8, x10, x6, x7)
-
-inst_713:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0040e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800040e4; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1380*FLEN/8, x10, x6, x7)
-
-inst_714:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1382*FLEN/8, x10, x6, x7)
-
-inst_715:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1384*FLEN/8, x10, x6, x7)
-
-inst_716:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x086d76 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x010a4a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x86d76; op2val:0x80010a4a;
-valaddr_reg:x9; val_offset:1386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1386*FLEN/8, x10, x6, x7)
-
-inst_717:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x010a4a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x086d76 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80010a4a; op2val:0x86d76;
-valaddr_reg:x9; val_offset:1388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1388*FLEN/8, x10, x6, x7)
-
-inst_718:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x086d76 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x86d76; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1390*FLEN/8, x10, x6, x7)
-
-inst_719:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x086d76 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x86d76;
-valaddr_reg:x9; val_offset:1392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1392*FLEN/8, x10, x6, x7)
-
-inst_720:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1394*FLEN/8, x10, x6, x7)
-
-inst_721:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0056ca and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x800056ca;
-valaddr_reg:x9; val_offset:1396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1396*FLEN/8, x10, x6, x7)
-
-inst_722:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0056ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800056ca; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1398*FLEN/8, x10, x6, x7)
-
-inst_723:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1400*FLEN/8, x10, x6, x7)
-
-inst_724:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1402*FLEN/8, x10, x6, x7)
-
-inst_725:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008b29 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x80008b29;
-valaddr_reg:x9; val_offset:1404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1404*FLEN/8, x10, x6, x7)
-
-inst_726:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x008b29 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80008b29; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1406*FLEN/8, x10, x6, x7)
-
-inst_727:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1408*FLEN/8, x10, x6, x7)
-
-inst_728:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1410*FLEN/8, x10, x6, x7)
-
-inst_729:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002a64 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x80002a64;
-valaddr_reg:x9; val_offset:1412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1412*FLEN/8, x10, x6, x7)
-
-inst_730:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002a64 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80002a64; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1414*FLEN/8, x10, x6, x7)
-
-inst_731:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1416*FLEN/8, x10, x6, x7)
-
-inst_732:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1418*FLEN/8, x10, x6, x7)
-
-inst_733:// fs1 == 0 and fe1 == 0x81 and fm1 == 0x77aa21 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x40f7aa21; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1420*FLEN/8, x10, x6, x7)
-
-inst_734:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x77aa21 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x40f7aa21;
-valaddr_reg:x9; val_offset:1422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1422*FLEN/8, x10, x6, x7)
-
-inst_735:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x81 and fm2 == 0x77aa21 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x40f7aa21;
-valaddr_reg:x9; val_offset:1424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1424*FLEN/8, x10, x6, x7)
-
-inst_736:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1426*FLEN/8, x10, x6, x7)
-
-inst_737:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x301931 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e301931; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1428*FLEN/8, x10, x6, x7)
-
-inst_738:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x301931 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7e301931;
-valaddr_reg:x9; val_offset:1430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1430*FLEN/8, x10, x6, x7)
-
-inst_739:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1432*FLEN/8, x10, x6, x7)
-
-inst_740:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1434*FLEN/8, x10, x6, x7)
-
-inst_741:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1436*FLEN/8, x10, x6, x7)
-
-inst_742:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1438*FLEN/8, x10, x6, x7)
-
-inst_743:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x301931 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e301931; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1440*FLEN/8, x10, x6, x7)
-
-inst_744:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1442*FLEN/8, x10, x6, x7)
-
-inst_745:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1444*FLEN/8, x10, x6, x7)
-
-inst_746:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1446*FLEN/8, x10, x6, x7)
-
-inst_747:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1448*FLEN/8, x10, x6, x7)
-
-inst_748:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1450*FLEN/8, x10, x6, x7)
-
-inst_749:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1452*FLEN/8, x10, x6, x7)
-
-inst_750:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1454*FLEN/8, x10, x6, x7)
-
-inst_751:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x301931 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e301931; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1456*FLEN/8, x10, x6, x7)
-
-inst_752:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1458*FLEN/8, x10, x6, x7)
-
-inst_753:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a320 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xa320; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1460*FLEN/8, x10, x6, x7)
-
-inst_754:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a320 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0xa320;
-valaddr_reg:x9; val_offset:1462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1462*FLEN/8, x10, x6, x7)
-
-inst_755:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1464*FLEN/8, x10, x6, x7)
-
-inst_756:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1466*FLEN/8, x10, x6, x7)
-
-inst_757:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1468*FLEN/8, x10, x6, x7)
-
-inst_758:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1470*FLEN/8, x10, x6, x7)
-
-inst_759:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1472*FLEN/8, x10, x6, x7)
-
-inst_760:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1474*FLEN/8, x10, x6, x7)
-
-inst_761:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1476*FLEN/8, x10, x6, x7)
-
-inst_762:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x065f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x65f43; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1478*FLEN/8, x10, x6, x7)
-
-inst_763:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x065f43 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x65f43;
-valaddr_reg:x9; val_offset:1480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1480*FLEN/8, x10, x6, x7)
-
-inst_764:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x065f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x65f43; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1482*FLEN/8, x10, x6, x7)
-
-inst_765:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x065f43 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x65f43;
-valaddr_reg:x9; val_offset:1484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1484*FLEN/8, x10, x6, x7)
-
-inst_766:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1486*FLEN/8, x10, x6, x7)
-
-inst_767:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1488*FLEN/8, x10, x6, x7)
-
-inst_768:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1490*FLEN/8, x10, x6, x7)
-
-inst_769:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1492*FLEN/8, x10, x6, x7)
-
-inst_770:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1494*FLEN/8, x10, x6, x7)
-
-inst_771:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1496*FLEN/8, x10, x6, x7)
-
-inst_772:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1498*FLEN/8, x10, x6, x7)
-
-inst_773:// fs1 == 0 and fe1 == 0x81 and fm1 == 0x3b428c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x40bb428c; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1500*FLEN/8, x10, x6, x7)
-
-inst_774:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3b428c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x40bb428c;
-valaddr_reg:x9; val_offset:1502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1502*FLEN/8, x10, x6, x7)
-
-inst_775:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3b428c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x40bb428c;
-valaddr_reg:x9; val_offset:1504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1504*FLEN/8, x10, x6, x7)
-
-inst_776:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1506*FLEN/8, x10, x6, x7)
-
-inst_777:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x620ff4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7de20ff4; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1508*FLEN/8, x10, x6, x7)
-
-inst_778:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0xfb and fm2 == 0x620ff4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7de20ff4;
-valaddr_reg:x9; val_offset:1510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1510*FLEN/8, x10, x6, x7)
-
-inst_779:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1512*FLEN/8, x10, x6, x7)
-
-inst_780:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1514*FLEN/8, x10, x6, x7)
-
-inst_781:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1516*FLEN/8, x10, x6, x7)
-
-inst_782:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1518*FLEN/8, x10, x6, x7)
-
-inst_783:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x620ff4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7de20ff4; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1520*FLEN/8, x10, x6, x7)
-
-inst_784:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1522*FLEN/8, x10, x6, x7)
-
-inst_785:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1524*FLEN/8, x10, x6, x7)
-
-inst_786:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1526*FLEN/8, x10, x6, x7)
-
-inst_787:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1528*FLEN/8, x10, x6, x7)
-
-inst_788:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1530*FLEN/8, x10, x6, x7)
-
-inst_789:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1532*FLEN/8, x10, x6, x7)
-
-inst_790:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1534*FLEN/8, x10, x6, x7)
-
-inst_791:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x620ff4 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7de20ff4; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1536*FLEN/8, x10, x6, x7)
-
-inst_792:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1538*FLEN/8, x10, x6, x7)
-
-inst_793:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0068b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x68b4; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1540*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_6)
-
-inst_794:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0068b4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x68b4;
-valaddr_reg:x9; val_offset:1542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1542*FLEN/8, x10, x6, x7)
-
-inst_795:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1544*FLEN/8, x10, x6, x7)
-
-inst_796:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1546*FLEN/8, x10, x6, x7)
-
-inst_797:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1548*FLEN/8, x10, x6, x7)
-
-inst_798:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1550*FLEN/8, x10, x6, x7)
-
-inst_799:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1552*FLEN/8, x10, x6, x7)
-
-inst_800:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04170c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4170c; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1554*FLEN/8, x10, x6, x7)
-
-inst_801:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x04170c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x4170c;
-valaddr_reg:x9; val_offset:1556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1556*FLEN/8, x10, x6, x7)
-
-inst_802:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04170c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4170c; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1558*FLEN/8, x10, x6, x7)
-
-inst_803:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x04170c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x4170c;
-valaddr_reg:x9; val_offset:1560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1560*FLEN/8, x10, x6, x7)
-
-inst_804:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1562*FLEN/8, x10, x6, x7)
-
-inst_805:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1564*FLEN/8, x10, x6, x7)
-
-inst_806:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1566*FLEN/8, x10, x6, x7)
-
-inst_807:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1568*FLEN/8, x10, x6, x7)
-
-inst_808:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1570*FLEN/8, x10, x6, x7)
-
-inst_809:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1572*FLEN/8, x10, x6, x7)
-
-inst_810:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1574*FLEN/8, x10, x6, x7)
-
-inst_811:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x706405 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x40706405; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1576*FLEN/8, x10, x6, x7)
-
-inst_812:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x706405 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x40706405;
-valaddr_reg:x9; val_offset:1578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1578*FLEN/8, x10, x6, x7)
-
-inst_813:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x706405 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x40706405;
-valaddr_reg:x9; val_offset:1580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1580*FLEN/8, x10, x6, x7)
-
-inst_814:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1582*FLEN/8, x10, x6, x7)
-
-inst_815:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39119c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7db9119c; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1584*FLEN/8, x10, x6, x7)
-
-inst_816:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39119c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7db9119c;
-valaddr_reg:x9; val_offset:1586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1586*FLEN/8, x10, x6, x7)
-
-inst_817:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1588*FLEN/8, x10, x6, x7)
-
-inst_818:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1590*FLEN/8, x10, x6, x7)
-
-inst_819:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1592*FLEN/8, x10, x6, x7)
-
-inst_820:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:1594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1594*FLEN/8, x10, x6, x7)
-
-inst_821:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1596*FLEN/8, x10, x6, x7)
-
-inst_822:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39119c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7db9119c; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1598*FLEN/8, x10, x6, x7)
-
-inst_823:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1600*FLEN/8, x10, x6, x7)
-
-inst_824:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1602*FLEN/8, x10, x6, x7)
-
-inst_825:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1604*FLEN/8, x10, x6, x7)
-
-inst_826:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1606*FLEN/8, x10, x6, x7)
-
-inst_827:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1608*FLEN/8, x10, x6, x7)
-
-inst_828:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1610*FLEN/8, x10, x6, x7)
-
-inst_829:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1612*FLEN/8, x10, x6, x7)
-
-inst_830:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1614*FLEN/8, x10, x6, x7)
-
-inst_831:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1616*FLEN/8, x10, x6, x7)
-
-inst_832:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1618*FLEN/8, x10, x6, x7)
-
-inst_833:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1620*FLEN/8, x10, x6, x7)
-
-inst_834:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1622*FLEN/8, x10, x6, x7)
-
-inst_835:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1624*FLEN/8, x10, x6, x7)
-
-inst_836:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39119c and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7db9119c; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1626*FLEN/8, x10, x6, x7)
-
-inst_837:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1628*FLEN/8, x10, x6, x7)
-
-inst_838:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0055b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x55b7; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1630*FLEN/8, x10, x6, x7)
-
-inst_839:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0055b7 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x55b7;
-valaddr_reg:x9; val_offset:1632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1632*FLEN/8, x10, x6, x7)
-
-inst_840:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1634*FLEN/8, x10, x6, x7)
-
-inst_841:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1636*FLEN/8, x10, x6, x7)
-
-inst_842:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1638*FLEN/8, x10, x6, x7)
-
-inst_843:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03592e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3592e; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1640*FLEN/8, x10, x6, x7)
-
-inst_844:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03592e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x3592e;
-valaddr_reg:x9; val_offset:1642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1642*FLEN/8, x10, x6, x7)
-
-inst_845:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03592e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3592e; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1644*FLEN/8, x10, x6, x7)
-
-inst_846:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03592e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x3592e;
-valaddr_reg:x9; val_offset:1646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1646*FLEN/8, x10, x6, x7)
-
-inst_847:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1648*FLEN/8, x10, x6, x7)
-
-inst_848:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1650*FLEN/8, x10, x6, x7)
-
-inst_849:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1652*FLEN/8, x10, x6, x7)
-
-inst_850:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1654*FLEN/8, x10, x6, x7)
-
-inst_851:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1656*FLEN/8, x10, x6, x7)
-
-inst_852:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1658*FLEN/8, x10, x6, x7)
-
-inst_853:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1660*FLEN/8, x10, x6, x7)
-
-inst_854:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x44cc84 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4044cc84; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1662*FLEN/8, x10, x6, x7)
-
-inst_855:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x44cc84 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x4044cc84;
-valaddr_reg:x9; val_offset:1664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1664*FLEN/8, x10, x6, x7)
-
-inst_856:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x80 and fm2 == 0x44cc84 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x4044cc84;
-valaddr_reg:x9; val_offset:1666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1666*FLEN/8, x10, x6, x7)
-
-inst_857:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1668*FLEN/8, x10, x6, x7)
-
-inst_858:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0c1bbb and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8c1bbb; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1670*FLEN/8, x10, x6, x7)
-
-inst_859:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0c1bbb and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xfd8c1bbb;
-valaddr_reg:x9; val_offset:1672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1672*FLEN/8, x10, x6, x7)
-
-inst_860:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1674*FLEN/8, x10, x6, x7)
-
-inst_861:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1676*FLEN/8, x10, x6, x7)
-
-inst_862:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1678*FLEN/8, x10, x6, x7)
-
-inst_863:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:1680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1680*FLEN/8, x10, x6, x7)
-
-inst_864:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1682*FLEN/8, x10, x6, x7)
-
-inst_865:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0c1bbb and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8c1bbb; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1684*FLEN/8, x10, x6, x7)
-
-inst_866:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1686*FLEN/8, x10, x6, x7)
-
-inst_867:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1688*FLEN/8, x10, x6, x7)
-
-inst_868:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1690*FLEN/8, x10, x6, x7)
-
-inst_869:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1692*FLEN/8, x10, x6, x7)
-
-inst_870:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1694*FLEN/8, x10, x6, x7)
-
-inst_871:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1696*FLEN/8, x10, x6, x7)
-
-inst_872:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1698*FLEN/8, x10, x6, x7)
-
-inst_873:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1700*FLEN/8, x10, x6, x7)
-
-inst_874:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1702*FLEN/8, x10, x6, x7)
-
-inst_875:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1704*FLEN/8, x10, x6, x7)
-
-inst_876:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1706*FLEN/8, x10, x6, x7)
-
-inst_877:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1708*FLEN/8, x10, x6, x7)
-
-inst_878:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1710*FLEN/8, x10, x6, x7)
-
-inst_879:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0c1bbb and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8c1bbb; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1712*FLEN/8, x10, x6, x7)
-
-inst_880:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1714*FLEN/8, x10, x6, x7)
-
-inst_881:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0040e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800040e4; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1716*FLEN/8, x10, x6, x7)
-
-inst_882:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0040e4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x800040e4;
-valaddr_reg:x9; val_offset:1718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1718*FLEN/8, x10, x6, x7)
-
-inst_883:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1720*FLEN/8, x10, x6, x7)
-
-inst_884:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0288ef and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800288ef; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1722*FLEN/8, x10, x6, x7)
-
-inst_885:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0288ef and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x800288ef;
-valaddr_reg:x9; val_offset:1724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1724*FLEN/8, x10, x6, x7)
-
-inst_886:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0288ef and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800288ef; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1726*FLEN/8, x10, x6, x7)
-
-inst_887:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0288ef and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x800288ef;
-valaddr_reg:x9; val_offset:1728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1728*FLEN/8, x10, x6, x7)
-
-inst_888:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1730*FLEN/8, x10, x6, x7)
-
-inst_889:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1732*FLEN/8, x10, x6, x7)
-
-inst_890:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1734*FLEN/8, x10, x6, x7)
-
-inst_891:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1736*FLEN/8, x10, x6, x7)
-
-inst_892:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1738*FLEN/8, x10, x6, x7)
-
-inst_893:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1740*FLEN/8, x10, x6, x7)
-
-inst_894:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1742*FLEN/8, x10, x6, x7)
-
-inst_895:// fs1 == 1 and fe1 == 0x80 and fm1 == 0x14fd1d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc014fd1d; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1744*FLEN/8, x10, x6, x7)
-
-inst_896:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x14fd1d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc014fd1d;
-valaddr_reg:x9; val_offset:1746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1746*FLEN/8, x10, x6, x7)
-
-inst_897:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x80 and fm2 == 0x14fd1d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xc014fd1d;
-valaddr_reg:x9; val_offset:1748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1748*FLEN/8, x10, x6, x7)
-
-inst_898:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1750*FLEN/8, x10, x6, x7)
-
-inst_899:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x0fbbb6 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe8fbbb6; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1752*FLEN/8, x10, x6, x7)
-
-inst_900:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x0fbbb6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xfe8fbbb6;
-valaddr_reg:x9; val_offset:1754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1754*FLEN/8, x10, x6, x7)
-
-inst_901:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1756*FLEN/8, x10, x6, x7)
-
-inst_902:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1758*FLEN/8, x10, x6, x7)
-
-inst_903:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1760*FLEN/8, x10, x6, x7)
-
-inst_904:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1762*FLEN/8, x10, x6, x7)
-
-inst_905:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1764*FLEN/8, x10, x6, x7)
-
-inst_906:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x0fbbb6 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe8fbbb6; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1766*FLEN/8, x10, x6, x7)
-
-inst_907:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1768*FLEN/8, x10, x6, x7)
-
-inst_908:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1770*FLEN/8, x10, x6, x7)
-
-inst_909:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1772*FLEN/8, x10, x6, x7)
-
-inst_910:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1774*FLEN/8, x10, x6, x7)
-
-inst_911:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1776*FLEN/8, x10, x6, x7)
-
-inst_912:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1778*FLEN/8, x10, x6, x7)
-
-inst_913:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1780*FLEN/8, x10, x6, x7)
-
-inst_914:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1782*FLEN/8, x10, x6, x7)
-
-inst_915:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1784*FLEN/8, x10, x6, x7)
-
-inst_916:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1786*FLEN/8, x10, x6, x7)
-
-inst_917:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1788*FLEN/8, x10, x6, x7)
-
-inst_918:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1790*FLEN/8, x10, x6, x7)
-
-inst_919:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1792*FLEN/8, x10, x6, x7)
-
-inst_920:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x0fbbb6 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe8fbbb6; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1794*FLEN/8, x10, x6, x7)
-
-inst_921:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1796*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_7)
-
-inst_922:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1798*FLEN/8, x10, x6, x7)
-
-inst_923:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1800*FLEN/8, x10, x6, x7)
-
-inst_924:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1802*FLEN/8, x10, x6, x7)
-
-inst_925:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x010a4a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80010a4a; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1804*FLEN/8, x10, x6, x7)
-
-inst_926:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x010a4a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x80010a4a;
-valaddr_reg:x9; val_offset:1806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1806*FLEN/8, x10, x6, x7)
-
-inst_927:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1808*FLEN/8, x10, x6, x7)
-
-inst_928:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1810*FLEN/8, x10, x6, x7)
-
-inst_929:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1812*FLEN/8, x10, x6, x7)
-
-inst_930:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1814*FLEN/8, x10, x6, x7)
-
-inst_931:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1816*FLEN/8, x10, x6, x7)
-
-inst_932:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1818*FLEN/8, x10, x6, x7)
-
-inst_933:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1820*FLEN/8, x10, x6, x7)
-
-inst_934:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1822*FLEN/8, x10, x6, x7)
-
-inst_935:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1824*FLEN/8, x10, x6, x7)
-
-inst_936:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0363eb and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x800363eb;
-valaddr_reg:x9; val_offset:1826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1826*FLEN/8, x10, x6, x7)
-
-inst_937:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0363eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800363eb; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1828*FLEN/8, x10, x6, x7)
-
-inst_938:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1830*FLEN/8, x10, x6, x7)
-
-inst_939:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1832*FLEN/8, x10, x6, x7)
-
-inst_940:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x056fa1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x80056fa1;
-valaddr_reg:x9; val_offset:1834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1834*FLEN/8, x10, x6, x7)
-
-inst_941:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x056fa1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80056fa1; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1836*FLEN/8, x10, x6, x7)
-
-inst_942:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1838*FLEN/8, x10, x6, x7)
-
-inst_943:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1840*FLEN/8, x10, x6, x7)
-
-inst_944:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a7ee and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x8001a7ee;
-valaddr_reg:x9; val_offset:1842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1842*FLEN/8, x10, x6, x7)
-
-inst_945:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01a7ee and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001a7ee; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1844*FLEN/8, x10, x6, x7)
-
-inst_946:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1846*FLEN/8, x10, x6, x7)
-
-inst_947:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1848*FLEN/8, x10, x6, x7)
-
-inst_948:// fs1 == 1 and fe1 == 0x82 and fm1 == 0x18d7ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc118d7ea; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1850*FLEN/8, x10, x6, x7)
-
-inst_949:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x18d7ea and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc118d7ea;
-valaddr_reg:x9; val_offset:1852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1852*FLEN/8, x10, x6, x7)
-
-inst_950:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x18d7ea and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xc118d7ea;
-valaddr_reg:x9; val_offset:1854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1854*FLEN/8, x10, x6, x7)
-
-inst_951:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1856*FLEN/8, x10, x6, x7)
-
-inst_952:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x3b633c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdbb633c; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1858*FLEN/8, x10, x6, x7)
-
-inst_953:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x3b633c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xfdbb633c;
-valaddr_reg:x9; val_offset:1860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1860*FLEN/8, x10, x6, x7)
-
-inst_954:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1862*FLEN/8, x10, x6, x7)
-
-inst_955:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1864*FLEN/8, x10, x6, x7)
-
-inst_956:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1866*FLEN/8, x10, x6, x7)
-
-inst_957:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:1868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1868*FLEN/8, x10, x6, x7)
-
-inst_958:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1870*FLEN/8, x10, x6, x7)
-
-inst_959:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x3b633c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdbb633c; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1872*FLEN/8, x10, x6, x7)
-
-inst_960:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1874*FLEN/8, x10, x6, x7)
-
-inst_961:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1876*FLEN/8, x10, x6, x7)
-
-inst_962:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1878*FLEN/8, x10, x6, x7)
-
-inst_963:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1880*FLEN/8, x10, x6, x7)
-
-inst_964:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1882*FLEN/8, x10, x6, x7)
-
-inst_965:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1884*FLEN/8, x10, x6, x7)
-
-inst_966:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1886*FLEN/8, x10, x6, x7)
-
-inst_967:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1888*FLEN/8, x10, x6, x7)
-
-inst_968:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1890*FLEN/8, x10, x6, x7)
-
-inst_969:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1892*FLEN/8, x10, x6, x7)
-
-inst_970:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1894*FLEN/8, x10, x6, x7)
-
-inst_971:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1896*FLEN/8, x10, x6, x7)
-
-inst_972:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1898*FLEN/8, x10, x6, x7)
-
-inst_973:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x3b633c and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdbb633c; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1900*FLEN/8, x10, x6, x7)
-
-inst_974:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1902*FLEN/8, x10, x6, x7)
-
-inst_975:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0056ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800056ca; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1904*FLEN/8, x10, x6, x7)
-
-inst_976:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0056ca and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x800056ca;
-valaddr_reg:x9; val_offset:1906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1906*FLEN/8, x10, x6, x7)
-
-inst_977:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1908*FLEN/8, x10, x6, x7)
-
-inst_978:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0363eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800363eb; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1910*FLEN/8, x10, x6, x7)
-
-inst_979:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0363eb and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x800363eb;
-valaddr_reg:x9; val_offset:1912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1912*FLEN/8, x10, x6, x7)
-
-inst_980:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1914*FLEN/8, x10, x6, x7)
-
-inst_981:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1916*FLEN/8, x10, x6, x7)
-
-inst_982:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1918*FLEN/8, x10, x6, x7)
-
-inst_983:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1920*FLEN/8, x10, x6, x7)
-
-inst_984:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1922*FLEN/8, x10, x6, x7)
-
-inst_985:// fs1 == 1 and fe1 == 0x80 and fm1 == 0x4743c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc04743c4; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1924*FLEN/8, x10, x6, x7)
-
-inst_986:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4743c4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc04743c4;
-valaddr_reg:x9; val_offset:1926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1926*FLEN/8, x10, x6, x7)
-
-inst_987:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4743c4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xc04743c4;
-valaddr_reg:x9; val_offset:1928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1928*FLEN/8, x10, x6, x7)
-
-inst_988:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1930*FLEN/8, x10, x6, x7)
-
-inst_989:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x163ab8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe163ab8; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1932*FLEN/8, x10, x6, x7)
-
-inst_990:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0xfc and fm2 == 0x163ab8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xfe163ab8;
-valaddr_reg:x9; val_offset:1934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1934*FLEN/8, x10, x6, x7)
-
-inst_991:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1936*FLEN/8, x10, x6, x7)
-
-inst_992:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1938*FLEN/8, x10, x6, x7)
-
-inst_993:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1940*FLEN/8, x10, x6, x7)
-
-inst_994:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1942*FLEN/8, x10, x6, x7)
-
-inst_995:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x163ab8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe163ab8; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1944*FLEN/8, x10, x6, x7)
-
-inst_996:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1946*FLEN/8, x10, x6, x7)
-
-inst_997:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1948*FLEN/8, x10, x6, x7)
-
-inst_998:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1950*FLEN/8, x10, x6, x7)
-
-inst_999:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1952*FLEN/8, x10, x6, x7)
-
-inst_1000:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1954*FLEN/8, x10, x6, x7)
-
-inst_1001:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1956*FLEN/8, x10, x6, x7)
-
-inst_1002:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1958*FLEN/8, x10, x6, x7)
-
-inst_1003:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x163ab8 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe163ab8; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1960*FLEN/8, x10, x6, x7)
-
-inst_1004:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1962*FLEN/8, x10, x6, x7)
-
-inst_1005:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x008b29 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80008b29; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1964*FLEN/8, x10, x6, x7)
-
-inst_1006:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008b29 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x80008b29;
-valaddr_reg:x9; val_offset:1966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1966*FLEN/8, x10, x6, x7)
-
-inst_1007:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1968*FLEN/8, x10, x6, x7)
-
-inst_1008:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x056fa1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80056fa1; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1970*FLEN/8, x10, x6, x7)
-
-inst_1009:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x056fa1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x80056fa1;
-valaddr_reg:x9; val_offset:1972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1972*FLEN/8, x10, x6, x7)
-
-inst_1010:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1974*FLEN/8, x10, x6, x7)
-
-inst_1011:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1976*FLEN/8, x10, x6, x7)
-
-inst_1012:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1978*FLEN/8, x10, x6, x7)
-
-inst_1013:// fs1 == 1 and fe1 == 0x81 and fm1 == 0x1fc053 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc09fc053; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1980*FLEN/8, x10, x6, x7)
-
-inst_1014:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1fc053 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc09fc053;
-valaddr_reg:x9; val_offset:1982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1982*FLEN/8, x10, x6, x7)
-
-inst_1015:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1fc053 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xc09fc053;
-valaddr_reg:x9; val_offset:1984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1984*FLEN/8, x10, x6, x7)
-
-inst_1016:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1986*FLEN/8, x10, x6, x7)
-
-inst_1017:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x370ed0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd370ed0; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1988*FLEN/8, x10, x6, x7)
-
-inst_1018:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x370ed0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xfd370ed0;
-valaddr_reg:x9; val_offset:1990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1990*FLEN/8, x10, x6, x7)
-
-inst_1019:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1992*FLEN/8, x10, x6, x7)
-
-inst_1020:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1994*FLEN/8, x10, x6, x7)
-
-inst_1021:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1996*FLEN/8, x10, x6, x7)
-
-inst_1022:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:1998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1998*FLEN/8, x10, x6, x7)
-
-inst_1023:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:2000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2000*FLEN/8, x10, x6, x7)
-
-inst_1024:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x370ed0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd370ed0; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:2002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2002*FLEN/8, x10, x6, x7)
-
-inst_1025:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:2004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2004*FLEN/8, x10, x6, x7)
-
-inst_1026:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:2006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2006*FLEN/8, x10, x6, x7)
-
-inst_1027:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:2008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2008*FLEN/8, x10, x6, x7)
-
-inst_1028:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:2010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2010*FLEN/8, x10, x6, x7)
-
-inst_1029:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:2012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2012*FLEN/8, x10, x6, x7)
-
-inst_1030:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:2014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2014*FLEN/8, x10, x6, x7)
-
-inst_1031:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:2016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2016*FLEN/8, x10, x6, x7)
-
-inst_1032:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:2018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2018*FLEN/8, x10, x6, x7)
-
-inst_1033:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xff130229;
-valaddr_reg:x9; val_offset:2020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2020*FLEN/8, x10, x6, x7)
-
-inst_1034:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0xff130229;
-valaddr_reg:x9; val_offset:2022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2022*FLEN/8, x10, x6, x7)
-
-inst_1035:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:2024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2024*FLEN/8, x10, x6, x7)
-
-inst_1036:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:2026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2026*FLEN/8, x10, x6, x7)
-
-inst_1037:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:2028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2028*FLEN/8, x10, x6, x7)
-
-inst_1038:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x370ed0 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd370ed0; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:2030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2030*FLEN/8, x10, x6, x7)
-
-inst_1039:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:2032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2032*FLEN/8, x10, x6, x7)
-
-inst_1040:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002a64 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80002a64; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:2034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2034*FLEN/8, x10, x6, x7)
-
-inst_1041:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002a64 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x80002a64;
-valaddr_reg:x9; val_offset:2036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2036*FLEN/8, x10, x6, x7)
-
-inst_1042:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:2038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2038*FLEN/8, x10, x6, x7)
-
-inst_1043:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01a7ee and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001a7ee; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:2040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2040*FLEN/8, x10, x6, x7)
-
-inst_1044:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a7ee and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x8001a7ee;
-valaddr_reg:x9; val_offset:2042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2042*FLEN/8, x10, x6, x7)
-
-inst_1045:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x7f0;
-valaddr_reg:x9; val_offset:2044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2044*FLEN/8, x10, x6, x7)
-
-inst_1046:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x42a917 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbfc2a917; op2val:0x7f0;
-valaddr_reg:x9; val_offset:2046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2046*FLEN/8, x10, x6, x7)
-
-inst_1047:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x42a917 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbfc2a917;
-valaddr_reg:x9; val_offset:2048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2048*FLEN/8, x10, x6, x7)
-
-inst_1048:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x42a917 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xbfc2a917;
-valaddr_reg:x9; val_offset:2050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2050*FLEN/8, x10, x6, x7)
-
-inst_1049:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:2052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2052*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_8)
-
-inst_1050:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7f0;
-valaddr_reg:x9; val_offset:2054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2054*FLEN/8, x10, x6, x7)
-
-inst_1051:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:2056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2056*FLEN/8, x10, x6, x7)
-
-inst_1052:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:2058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2058*FLEN/8, x10, x6, x7)
-
-inst_1053:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:2060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2060*FLEN/8, x10, x6, x7)
-
-inst_1054:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:2062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2062*FLEN/8, x10, x6, x7)
-
-inst_1055:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:2064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2064*FLEN/8, x10, x6, x7)
-
-inst_1056:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:2066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2066*FLEN/8, x10, x6, x7)
-
-inst_1057:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xff130229;
-valaddr_reg:x9; val_offset:2068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2068*FLEN/8, x10, x6, x7)
-
-inst_1058:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:2070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2070*FLEN/8, x10, x6, x7)
-
-inst_1059:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:2072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2072*FLEN/8, x10, x6, x7)
-
-inst_1060:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:2074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2074*FLEN/8, x10, x6, x7)
-
-inst_1061:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:2076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2076*FLEN/8, x10, x6, x7)
-
-inst_1062:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:2078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2078*FLEN/8, x10, x6, x7)
-
-inst_1063:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:2080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2080*FLEN/8, x10, x6, x7)
-
-inst_1064:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:2082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2082*FLEN/8, x10, x6, x7)
-
-inst_1065:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:2084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2084*FLEN/8, x10, x6, x7)
-
-inst_1066:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:2086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2086*FLEN/8, x10, x6, x7)
-
-inst_1067:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:2088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2088*FLEN/8, x10, x6, x7)
-
-inst_1068:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:2090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2090*FLEN/8, x10, x6, x7)
-
-inst_1069:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:2092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2092*FLEN/8, x10, x6, x7)
-
-inst_1070:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:2094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2094*FLEN/8, x10, x6, x7)
-
-inst_1071:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:2096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2096*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2101360805,32,FLEN)
-NAN_BOXED(2101360805,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2105572096,32,FLEN)
-NAN_BOXED(2105572096,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2101544824,32,FLEN)
-NAN_BOXED(2101544824,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4245422917,32,FLEN)
-NAN_BOXED(4245422917,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
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-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2149144927,32,FLEN)
-NAN_BOXED(2149144927,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3222600989,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3222600989,32,FLEN)
-NAN_BOXED(2149144927,32,FLEN)
-NAN_BOXED(3222600989,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4270832566,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(4270832566,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(4270832566,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(4270832566,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(1551704,32,FLEN)
-NAN_BOXED(2154300692,32,FLEN)
-NAN_BOXED(1551704,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2154300692,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(2147551818,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2147551818,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(4176036,32,FLEN)
-NAN_BOXED(2154300692,32,FLEN)
-NAN_BOXED(4176036,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2680445,32,FLEN)
-NAN_BOXED(2154300692,32,FLEN)
-NAN_BOXED(2680445,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2194381,32,FLEN)
-NAN_BOXED(2154300692,32,FLEN)
-NAN_BOXED(2194381,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2149144927,32,FLEN)
-NAN_BOXED(2154300692,32,FLEN)
-NAN_BOXED(2149144927,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2154300692,32,FLEN)
-NAN_BOXED(2147705835,32,FLEN)
-NAN_BOXED(2147705835,32,FLEN)
-NAN_BOXED(2154300692,32,FLEN)
-NAN_BOXED(2154300692,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2154300692,32,FLEN)
-NAN_BOXED(2147839905,32,FLEN)
-NAN_BOXED(2147839905,32,FLEN)
-NAN_BOXED(2154300692,32,FLEN)
-NAN_BOXED(2154300692,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2154300692,32,FLEN)
-NAN_BOXED(2147592174,32,FLEN)
-NAN_BOXED(2147592174,32,FLEN)
-NAN_BOXED(2154300692,32,FLEN)
-NAN_BOXED(2154300692,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3239630826,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3239630826,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(3239630826,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4256916284,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(4256916284,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(4285152267,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(4285152267,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(4256916284,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(4285152267,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(4285152267,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(4285152267,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(4285152267,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(4285152267,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(4285152267,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(4256916284,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(2147505866,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2147505866,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2147705835,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2147705835,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3225895876,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3225895876,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(3225895876,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4262869688,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(4262869688,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(4262869688,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(4262869688,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(2147519273,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2147519273,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2147839905,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2147839905,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3231694931,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3231694931,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(3231694931,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4248243920,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(4248243920,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(4248243920,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(4248243920,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(2147494500,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2147494500,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2147592174,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2147592174,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3217205527,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3217205527,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(3217205527,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1551704,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4176036,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2680445,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2194381,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2149144927,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_7:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_8:
-    .fill 44*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fli.s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fli.s-01.S
deleted file mode 100644
index 1558be873..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fli.s-01.S
+++ /dev/null
@@ -1,204 +0,0 @@
-// Copyright (c) 2023. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fli.s instruction
-// for the following ISA configurations:
-// * RV32IF_Zfa
-// * RV64IF_Zfa
-
-#include "model_test.h"
-#include "arch_test.h"
-
-RVTEST_ISA("RV32IF_Zfa,RV64IF_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-
-RVMODEL_BOOT
-
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fli.s)
-
-// Registers with a special purpose
-#define SIG_BASEREG x1
-#define FCSR_REG x2
-#define DATA_BASEREG x3
-
-// Initialize the FPU
-RVTEST_FP_ENABLE()
-// Prepare the DATA_BASEREG register
-RVTEST_VALBASEUPD(DATA_BASEREG, dataset_tc1)
-// Prepare the SIG_BASEREG register
-RVTEST_SIGBASE(SIG_BASEREG, signature_tc1)
-
-// FLI.S loads a pre-defined constant into a FP register.
-// FLI.S has the following inputs and outputs:
-// - input rs1: 5-bit immediate holding the constants ID
-// - output fld: FP register
-
-// TEST_CASE_FLI_S executes a FLI.S insn and stores the result in the sig
-// 1) the FCSR_OLD value will be store into FCSR using FCSR_REG
-// 2) fli.s is executed using FLD as dest register and FLI_CONST as constant
-// 3) The constents of FLD and FCSR are stored in the signature
-#define TEST_CASE_FLI_S(fld, fli_const, fcsr_old, fcsr_reg) \
-    li fcsr_reg, fcsr_old ;\
-    csrw fcsr, fcsr_reg   ;\
-    fli.s fld, fli_const  ;\
-    csrr fcsr_reg, fcsr   ;\
-    RVTEST_SIGUPD_F(SIG_BASEREG, fld, fcsr_reg) ;\
-
-// Below we have one instruction test per constant
-
-inst_0:
-TEST_CASE_FLI_S(f16, -0x1p+0, 0, FCSR_REG)
-
-inst_1:
-TEST_CASE_FLI_S(f17, min, 0, FCSR_REG)
-
-inst_2:
-TEST_CASE_FLI_S(f18, 0x1p-16, 0, FCSR_REG)
-
-inst_3:
-TEST_CASE_FLI_S(f19, 0x1p-15, 0, FCSR_REG)
-
-inst_4:
-TEST_CASE_FLI_S(f20, 0x1p-8, 0, FCSR_REG)
-
-inst_5:
-TEST_CASE_FLI_S(f21, 0x1p-7, 0, FCSR_REG)
-
-inst_6:
-TEST_CASE_FLI_S(f22, 0x1p-4, 0, FCSR_REG)
-
-inst_7:
-TEST_CASE_FLI_S(f23, 0x1p-3, 0, FCSR_REG)
-
-inst_8:
-TEST_CASE_FLI_S(f24, 0x1p-2, 0, FCSR_REG)
-
-inst_9:
-TEST_CASE_FLI_S(f25, 0x1.4p-2, 0, FCSR_REG)
-
-inst_10:
-TEST_CASE_FLI_S(f26, 0x1.8p-2, 0, FCSR_REG)
-
-inst_11:
-TEST_CASE_FLI_S(f27, 0x1.cp-2, 0, FCSR_REG)
-
-inst_12:
-TEST_CASE_FLI_S(f28, 0x1p-1, 0, FCSR_REG)
-
-inst_13:
-TEST_CASE_FLI_S(f29, 0x1.4p-1, 0, FCSR_REG)
-
-inst_14:
-TEST_CASE_FLI_S(f30, 0x1.8p-1, 0, FCSR_REG)
-
-inst_15:
-TEST_CASE_FLI_S(f31, 0x1.cp-1, 0, FCSR_REG)
-
-inst_16:
-TEST_CASE_FLI_S(f0, 0x1p0, 0, FCSR_REG)
-
-inst_17:
-TEST_CASE_FLI_S(f1, 0x1.4p+0, 0, FCSR_REG)
-
-inst_18:
-TEST_CASE_FLI_S(f2, 0x1.8p+0, 0, FCSR_REG)
-
-inst_19:
-TEST_CASE_FLI_S(f3, 0x1.cp+0, 0, FCSR_REG)
-
-inst_20:
-TEST_CASE_FLI_S(f4, 0x1p+1, 0, FCSR_REG)
-
-inst_21:
-TEST_CASE_FLI_S(f5, 0x1.4p+1, 0, FCSR_REG)
-
-inst_22:
-TEST_CASE_FLI_S(f6, 0x1.8p+1, 0, FCSR_REG)
-
-inst_23:
-TEST_CASE_FLI_S(f7, 0x1p+2, 0, FCSR_REG)
-
-inst_24:
-TEST_CASE_FLI_S(f8, 0x1p+3, 0, FCSR_REG)
-
-inst_25:
-TEST_CASE_FLI_S(f9, 0x1p+4, 0, FCSR_REG)
-
-inst_26:
-TEST_CASE_FLI_S(f10, 0x1p+7, 0, FCSR_REG)
-
-inst_27:
-TEST_CASE_FLI_S(f11, 0x1p+8, 0, FCSR_REG)
-
-inst_28:
-TEST_CASE_FLI_S(f12, 0x1p+15, 0, FCSR_REG)
-
-inst_29:
-TEST_CASE_FLI_S(f13, 0x1p+16, 0, FCSR_REG)
-
-inst_30:
-TEST_CASE_FLI_S(f14, inf, 0, FCSR_REG)
-
-inst_31:
-TEST_CASE_FLI_S(f15, nan, 0, FCSR_REG)
-
-#endif // TEST_CASE_1
-
-RVTEST_CODE_END
-
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.word 0xbabecafe // trapreg_sv
-.word 0xabecafeb // tramptbl_sv
-.word 0xbecafeba // mtvec_save
-.word 0xecafebab // mscratch_save
-dataset_tc1:
-/* empty */
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-signature_tc1:
-// We have 32 test cases and store for each test case:
-// - 32-bit FP register (fld)
-// - 32-bit FCSR content after the instruction
-    .fill 64*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-
-tsig_begin_canary:
-CANARY;
-tsig_begin_canary:
-CANARY;
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-tsig_end_canary:
-CANARY;
-tsig_end_canary:
-CANARY;
-
-#endif // rvtest_mtrap_routine
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif // rvtest_gpr_save
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fltq_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fltq_b1-01.S
deleted file mode 100644
index c647d9789..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fltq_b1-01.S
+++ /dev/null
@@ -1,4740 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:15:33 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fltq.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fltq.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fltq_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f29; op2:f29; dest:x30; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f30; op2:f31; dest:x29; op1val:0x0; op2val:0x1;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f28; op2:f27; dest:x28; op1val:0x0; op2val:0x80000001;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f27; op2:f28; dest:x27; op1val:0x0; op2val:0x2;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f26; op2:f25; dest:x26; op1val:0x0; op2val:0x807ffffe;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f25; op2:f26; dest:x25; op1val:0x0; op2val:0x7fffff;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f24; op2:f23; dest:x24; op1val:0x0; op2val:0x807fffff;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f23; op2:f24; dest:x23; op1val:0x0; op2val:0x800000;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f22; op2:f21; dest:x22; op1val:0x0; op2val:0x80800000;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f21; op2:f22; dest:x21; op1val:0x0; op2val:0x800001;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f20; op2:f19; dest:x20; op1val:0x0; op2val:0x80855555;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f19; op2:f20; dest:x19; op1val:0x0; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f18; op2:f17; dest:x18; op1val:0x0; op2val:0xff7fffff;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f17; op2:f18; dest:x17; op1val:0x0; op2val:0x7f800000;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f16; op2:f15; dest:x16; op1val:0x0; op2val:0xff800000;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f15; op2:f16; dest:x15; op1val:0x0; op2val:0x7fc00000;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f14; op2:f13; dest:x14; op1val:0x0; op2val:0xffc00000;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f13; op2:f14; dest:x13; op1val:0x0; op2val:0x7fc00001;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f12; op2:f11; dest:x12; op1val:0x0; op2val:0xffc55555;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f11; op2:f12; dest:x11; op1val:0x0; op2val:0x7f800001;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f10; op2:f9; dest:x10; op1val:0x0; op2val:0xffaaaaaa;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f9; op2:f10; dest:x9; op1val:0x0; op2val:0x3f800000;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f8; op2:f7; dest:x8; op1val:0x0; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f7; op2:f8; dest:x7; op1val:0x80000000; op2val:0x0;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f6; op2:f5; dest:x6; op1val:0x80000000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f5; op2:f6; dest:x5; op1val:0x80000000; op2val:0x1;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f4; op2:f3; dest:x4; op1val:0x80000000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f3; op2:f4; dest:x3; op1val:0x80000000; op2val:0x2;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f2; op2:f1; dest:x2; op1val:0x80000000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f1; op2:f2; dest:x1; op1val:0x80000000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f0; op2:f31; dest:x31; op1val:0x80000000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f0; dest:x31; op1val:0x80000000; op2val:0x800000;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x0; op1val:0x80000000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x800001;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x0;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80000000;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x1;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80000001;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x2;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x800000;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80800000;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x800001;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80855555;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xff800000;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x0;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x1;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x2;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x800000;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x800001;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x0;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80000000;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x1;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80000001;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x2;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x800000;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80800000;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x800001;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80855555;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xff800000;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x0;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x1;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x2;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x800000;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x800001;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x0;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x1;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x2;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x0;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x1;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x2;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x0;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x1;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x2;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x800000;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x800001;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x0;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80000000;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x1;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80000001;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x2;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x800000;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80800000;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x800001;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80855555;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xff800000;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x0;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x1;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x2;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x0;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x1;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x2;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x0;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x1;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x2;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x800000;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x800001;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x0;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x1;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x2;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x800000;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x800001;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x0;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x1;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x2;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x800000;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x800001;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x0;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80000000;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x1;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80000001;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x2;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x800000;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80800000;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x800001;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80855555;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xff800000;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x0;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x1;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x2;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x800000;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x800001;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x0;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x1;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x2;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x0;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x1;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x2;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x80000000;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-test_dataset_1:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2,32,FLEN)
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-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 80*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fltq_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fltq_b19-01.S
deleted file mode 100644
index 37320ed5b..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fltq_b19-01.S
+++ /dev/null
@@ -1,8027 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:15:33 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fltq.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fltq.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fltq_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f29; op2:f29; dest:x30; op1val:0x7f378efe; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f30; op2:f31; dest:x29; op1val:0x7f206a70; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f28; op2:f27; dest:x28; op1val:0x7f378efe; op2val:0x7ee8aebb;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f27; op2:f28; dest:x27; op1val:0x7ee8aebb; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f26; op2:f25; dest:x26; op1val:0x7f378efe; op2val:0x7ea5608b;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f25; op2:f26; dest:x25; op1val:0x7ea5608b; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f24; op2:f23; dest:x24; op1val:0x7f378efe; op2val:0x7f3648af;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f23; op2:f24; dest:x23; op1val:0x7f3648af; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f22; op2:f21; dest:x22; op1val:0x7f378efe; op2val:0xfd204621;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f21; op2:f22; dest:x21; op1val:0x7d92d8cb; op2val:0xfec857aa;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfb and fm2 == 0x12d8cb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f20; op2:f19; dest:x20; op1val:0xfec857aa; op2val:0x7d92d8cb;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f19; op2:f20; dest:x19; op1val:0x7d92d8cb; op2val:0xfd204621;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfb and fm2 == 0x12d8cb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f18; op2:f17; dest:x18; op1val:0x7f378efe; op2val:0x7d92d8cb;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f17; op2:f18; dest:x17; op1val:0x7f378efe; op2val:0xfe4ac669;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f16; op2:f15; dest:x16; op1val:0x7d92d8cb; op2val:0xff7fffff;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x12d8cb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f15; op2:f16; dest:x15; op1val:0xff7fffff; op2val:0x7d92d8cb;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f14; op2:f13; dest:x14; op1val:0x7d92d8cb; op2val:0xfe4ac669;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f13; op2:f14; dest:x13; op1val:0x7f378efe; op2val:0xfe96fcf5;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f12; op2:f11; dest:x12; op1val:0xfe96fcf5; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f11; op2:f12; dest:x11; op1val:0x7f378efe; op2val:0xfee8e23e;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f10; op2:f9; dest:x10; op1val:0xfee8e23e; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f9; op2:f10; dest:x9; op1val:0x7f378efe; op2val:0xfeaf0937;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f8; op2:f7; dest:x8; op1val:0xfeaf0937; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f7; op2:f8; dest:x7; op1val:0x7f378efe; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a825 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f6; op2:f5; dest:x6; op1val:0x2a825; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a825 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f5; op2:f6; dest:x5; op1val:0x7f7a0dff; op2val:0x2a825;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a825 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f4; op2:f3; dest:x4; op1val:0x2a825; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a825 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f3; op2:f4; dest:x3; op1val:0x7f378efe; op2val:0x2a825;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f2; op2:f1; dest:x2; op1val:0x7f378efe; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f1; op2:f2; dest:x1; op1val:0x1a917b; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f0; op2:f31; dest:x31; op1val:0x7f7fffff; op2val:0x1a917b;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f0; dest:x31; op1val:0x1a917b; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x0; op1val:0x7f378efe; op2val:0x1a917b;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x253272;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x253272;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x1a917b;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x1a917b;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x004403 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4403; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004403 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x4403;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x004403 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4403; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004403 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x4403;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x7f0;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x1c2784 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x401c2784; op2val:0x7f0;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1c2784 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x401c2784;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1c2784 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x401c2784;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x005526 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d805526; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfb and fm2 == 0x005526 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7d805526;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x005526 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d805526; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x005526 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x7d805526;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x005526 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d805526; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x005526 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7d805526;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x005526 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d805526; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025265 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x25265; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025265 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x25265;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025265 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x25265; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025265 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x25265;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1737f6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x1737f6;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1737f6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x1737f6;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x253272;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x253272;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1737f6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x1737f6;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1737f6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x1737f6;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003b70 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3b70; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003b70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x3b70;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003b70 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3b70; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003b70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x3b70;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x7f0;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x087776 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x40087776; op2val:0x7f0;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x087776 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x40087776;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x087776 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x40087776;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x3a2562 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d3a2562; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfa and fm2 == 0x3a2562 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7d3a2562;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x3a2562 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d3a2562; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0xfa and fm2 == 0x3a2562 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x7d3a2562;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x3a2562 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d3a2562; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x3a2562 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7d3a2562;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x3a2562 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d3a2562; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01af15 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1af15; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01af15 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x1af15;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01af15 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1af15; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01af15 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x1af15;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x10d6d9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x10d6d9;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x10d6d9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x10d6d9;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x253272;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x253272;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x10d6d9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x10d6d9;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x10d6d9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x10d6d9;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002b1b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2b1b; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002b1b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x2b1b;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002b1b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2b1b; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002b1b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x2b1b;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x7f0;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x45f1c5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fc5f1c5; op2val:0x7f0;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x45f1c5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x3fc5f1c5;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x7f and fm2 == 0x45f1c5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x3fc5f1c5;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x044d3c and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d044d3c; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfa and fm2 == 0x044d3c and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7d044d3c;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x044d3c and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d044d3c; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0xfa and fm2 == 0x044d3c and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x7d044d3c;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x044d3c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d044d3c; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x044d3c and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7d044d3c;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x044d3c and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d044d3c; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x013263 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x13263; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x013263 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x13263;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x013263 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x13263; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x013263 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x13263;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0bf7e5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xbf7e5;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0bf7e5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0xbf7e5;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x253272;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x253272;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0bf7e5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0xbf7e5;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0bf7e5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xbf7e5;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001ea3 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1ea3; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001ea3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x1ea3;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001ea3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1ea3; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001ea3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x1ea3;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x7f0;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0caff3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f8caff3; op2val:0x7f0;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0caff3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x3f8caff3;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0caff3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x3f8caff3;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x11d3bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d91d3bf; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfb and fm2 == 0x11d3bf and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7d91d3bf;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x11d3bf and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d91d3bf; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0xfb and fm2 == 0x11d3bf and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x7d91d3bf;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x11d3bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d91d3bf; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x11d3bf and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7d91d3bf;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x11d3bf and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d91d3bf; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a36c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2a36c; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a36c and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x2a36c;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a36c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2a36c; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a36c and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x2a36c;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a6240 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x1a6240;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a6240 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x1a6240;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x253272;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x253272;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a6240 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x1a6240;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a6240 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x1a6240;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00438a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x438a; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00438a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x438a;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00438a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x438a; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00438a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x438a;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x7f0;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x1b11ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x401b11ec; op2val:0x7f0;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1b11ec and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x401b11ec;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1b11ec and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x401b11ec;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x7194bc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0xfcf194bc;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7194bc and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfcf194bc; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 1 and fe2 == 0xfa and fm2 == 0x3a4e98 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0xfd3a4e98;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x3a4e98 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd3a4e98; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 1 and fe2 == 0xfa and fm2 == 0x0c075f and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0xfd0c075f;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c075f and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c075f; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01732b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x480b33 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001732b; op2val:0x7dc80b33;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x480b33 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01732b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dc80b33; op2val:0x8001732b;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01732b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001732b; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01732b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x8001732b;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x6ce8a1 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x7dece8a1;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x6ce8a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dece8a1; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x253272;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4d97f8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x7dcd97f8;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4d97f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dcd97f8; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x253272;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x7fc1a6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x7dffc1a6;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7fc1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dffc1a6; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d5c91 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x7d9d5c91;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d5c91 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d9d5c91; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x21db85 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0xfe21db85;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x21db85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe21db85; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x74bcf0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0xfdf4bcf0;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x74bcf0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdf4bcf0; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x14db11 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0xfe14db11;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x14db11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe14db11; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00251d and fs2 == 1 and fe2 == 0xfb and fm2 == 0x374171 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000251d; op2val:0xfdb74171;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x374171 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00251d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdb74171; op2val:0x8000251d;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00251d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000251d; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00251d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x8000251d;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x016ce1 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0xfe016ce1;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x016ce1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe016ce1; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x7f0;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x2a6eb8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbfaa6eb8; op2val:0x7f0;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x2a6eb8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbfaa6eb8;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x2a6eb8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0xbfaa6eb8;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x7194bc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfcf194bc;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7194bc and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfcf194bc; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x3a4e98 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfd3a4e98;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x3a4e98 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd3a4e98; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x0c075f and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfd0c075f;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c075f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c075f; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x075661 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x480b33 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80075661; op2val:0x7dc80b33;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x480b33 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x075661 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dc80b33; op2val:0x80075661;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x075661 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80075661; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x075661 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x80075661;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0xfb and fm2 == 0x6ce8a1 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x7dece8a1;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x6ce8a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dece8a1; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x253272;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4d97f8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x7dcd97f8;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4d97f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dcd97f8; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x253272;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0xfb and fm2 == 0x7fc1a6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x7dffc1a6;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7fc1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dffc1a6; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d5c91 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x7d9d5c91;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d5c91 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d9d5c91; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x21db85 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0xfe21db85;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x21db85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe21db85; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0xfb and fm2 == 0x74bcf0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0xfdf4bcf0;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x74bcf0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdf4bcf0; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x14db11 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0xfe14db11;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x14db11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe14db11; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00bbd6 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x374171 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000bbd6; op2val:0xfdb74171;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x374171 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00bbd6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdb74171; op2val:0x8000bbd6;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00bbd6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000bbd6; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00bbd6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x8000bbd6;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x016ce1 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0xfe016ce1;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x016ce1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe016ce1; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x7f0;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0x81 and fm1 == 0x57a09d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc0d7a09d; op2val:0x7f0;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x57a09d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc0d7a09d;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x57a09d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0xc0d7a09d;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7194bc and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfcf194bc; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x7194bc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0xfcf194bc;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7194bc and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfcf194bc; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0117bb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800117bb; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0117bb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x800117bb;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0117bb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800117bb; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0117bb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x800117bb;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0aed51 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800aed51;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0aed51 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x800aed51;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x253272;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x253272;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0aed51 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x800aed51;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0aed51 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800aed51;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001bf9 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80001bf9; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001bf9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x80001bf9;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001bf9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80001bf9; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001bf9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x80001bf9;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x7f0;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x00724d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf80724d; op2val:0x7f0;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x00724d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbf80724d;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x00724d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0xbf80724d;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x3a4e98 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd3a4e98; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x3a4e98 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0xfd3a4e98;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x3a4e98 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd3a4e98; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01af75 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001af75; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01af75 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x8001af75;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01af75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001af75; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01af75 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x8001af75;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10da93 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x8010da93;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10da93 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x8010da93;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x253272;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x253272;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10da93 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x8010da93;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10da93 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x8010da93;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002b25 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80002b25; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002b25 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x80002b25;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002b25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80002b25; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002b25 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x80002b25;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x7f0;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x461d98 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbfc61d98; op2val:0x7f0;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x461d98 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbfc61d98;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x7f and fm2 == 0x461d98 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0xbfc61d98;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c075f and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c075f; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x0c075f and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0xfd0c075f;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c075f and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c075f; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x014448 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80014448; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x014448 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x80014448;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x014448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80014448; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x014448 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x80014448;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caad8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800caad8;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caad8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x800caad8;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x253272;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x253272;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caad8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x800caad8;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caad8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800caad8;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00206d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000206d; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00206d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x8000206d;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00206d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000206d; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00206d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x8000206d;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x14e777 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf94e777; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x14e777 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbf94e777;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x14e777 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0xbf94e777;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x480b33 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dc80b33; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-
-inst_578:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0xfb and fm2 == 0x480b33 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7dc80b33;
-valaddr_reg:x9; val_offset:1110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1110*FLEN/8, x10, x6, x7)
-
-inst_579:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1112*FLEN/8, x10, x6, x7)
-
-inst_580:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x480b33 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dc80b33; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1114*FLEN/8, x10, x6, x7)
-
-inst_581:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1116*FLEN/8, x10, x6, x7)
-
-inst_582:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1118*FLEN/8, x10, x6, x7)
-
-inst_583:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1120*FLEN/8, x10, x6, x7)
-
-inst_584:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1122*FLEN/8, x10, x6, x7)
-
-inst_585:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1124*FLEN/8, x10, x6, x7)
-
-inst_586:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1126*FLEN/8, x10, x6, x7)
-
-inst_587:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1128*FLEN/8, x10, x6, x7)
-
-inst_588:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x044949 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x44949;
-valaddr_reg:x9; val_offset:1130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1130*FLEN/8, x10, x6, x7)
-
-inst_589:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044949 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x44949; op2val:0x243164;
-valaddr_reg:x9; val_offset:1132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1132*FLEN/8, x10, x6, x7)
-
-inst_590:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1134*FLEN/8, x10, x6, x7)
-
-inst_591:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x243164;
-valaddr_reg:x9; val_offset:1136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1136*FLEN/8, x10, x6, x7)
-
-inst_592:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x253272;
-valaddr_reg:x9; val_offset:1138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1138*FLEN/8, x10, x6, x7)
-
-inst_593:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03b83e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x3b83e;
-valaddr_reg:x9; val_offset:1140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1140*FLEN/8, x10, x6, x7)
-
-inst_594:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03b83e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3b83e; op2val:0x243164;
-valaddr_reg:x9; val_offset:1142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1142*FLEN/8, x10, x6, x7)
-
-inst_595:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x253272;
-valaddr_reg:x9; val_offset:1144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1144*FLEN/8, x10, x6, x7)
-
-inst_596:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1146*FLEN/8, x10, x6, x7)
-
-inst_597:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x04a095 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x4a095;
-valaddr_reg:x9; val_offset:1148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1148*FLEN/8, x10, x6, x7)
-
-inst_598:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a095 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4a095; op2val:0x243164;
-valaddr_reg:x9; val_offset:1150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1150*FLEN/8, x10, x6, x7)
-
-inst_599:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1152*FLEN/8, x10, x6, x7)
-
-inst_600:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1154*FLEN/8, x10, x6, x7)
-
-inst_601:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02d8d9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x2d8d9;
-valaddr_reg:x9; val_offset:1156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1156*FLEN/8, x10, x6, x7)
-
-inst_602:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02d8d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2d8d9; op2val:0x243164;
-valaddr_reg:x9; val_offset:1158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1158*FLEN/8, x10, x6, x7)
-
-inst_603:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1160*FLEN/8, x10, x6, x7)
-
-inst_604:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1162*FLEN/8, x10, x6, x7)
-
-inst_605:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x05db58 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x8005db58;
-valaddr_reg:x9; val_offset:1164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1164*FLEN/8, x10, x6, x7)
-
-inst_606:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x05db58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8005db58; op2val:0x243164;
-valaddr_reg:x9; val_offset:1166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1166*FLEN/8, x10, x6, x7)
-
-inst_607:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1168*FLEN/8, x10, x6, x7)
-
-inst_608:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1170*FLEN/8, x10, x6, x7)
-
-inst_609:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x046d8c and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x80046d8c;
-valaddr_reg:x9; val_offset:1172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1172*FLEN/8, x10, x6, x7)
-
-inst_610:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x046d8c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80046d8c; op2val:0x243164;
-valaddr_reg:x9; val_offset:1174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1174*FLEN/8, x10, x6, x7)
-
-inst_611:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1176*FLEN/8, x10, x6, x7)
-
-inst_612:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1178*FLEN/8, x10, x6, x7)
-
-inst_613:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0562e7 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x800562e7;
-valaddr_reg:x9; val_offset:1180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1180*FLEN/8, x10, x6, x7)
-
-inst_614:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0562e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800562e7; op2val:0x243164;
-valaddr_reg:x9; val_offset:1182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1182*FLEN/8, x10, x6, x7)
-
-inst_615:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1184*FLEN/8, x10, x6, x7)
-
-inst_616:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1186*FLEN/8, x10, x6, x7)
-
-inst_617:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005ca7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0350c8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5ca7; op2val:0x800350c8;
-valaddr_reg:x9; val_offset:1188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1188*FLEN/8, x10, x6, x7)
-
-inst_618:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0350c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005ca7 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800350c8; op2val:0x5ca7;
-valaddr_reg:x9; val_offset:1190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1190*FLEN/8, x10, x6, x7)
-
-inst_619:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005ca7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5ca7; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1192*FLEN/8, x10, x6, x7)
-
-inst_620:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005ca7 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x5ca7;
-valaddr_reg:x9; val_offset:1194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1194*FLEN/8, x10, x6, x7)
-
-inst_621:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1196*FLEN/8, x10, x6, x7)
-
-inst_622:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04aeea and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x8004aeea;
-valaddr_reg:x9; val_offset:1198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1198*FLEN/8, x10, x6, x7)
-
-inst_623:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04aeea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8004aeea; op2val:0x243164;
-valaddr_reg:x9; val_offset:1200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1200*FLEN/8, x10, x6, x7)
-
-inst_624:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1202*FLEN/8, x10, x6, x7)
-
-inst_625:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1204*FLEN/8, x10, x6, x7)
-
-inst_626:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x54b916 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4054b916; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1206*FLEN/8, x10, x6, x7)
-
-inst_627:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x54b916 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x4054b916;
-valaddr_reg:x9; val_offset:1208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1208*FLEN/8, x10, x6, x7)
-
-inst_628:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x80 and fm2 == 0x54b916 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x4054b916;
-valaddr_reg:x9; val_offset:1210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1210*FLEN/8, x10, x6, x7)
-
-inst_629:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1212*FLEN/8, x10, x6, x7)
-
-inst_630:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1214*FLEN/8, x10, x6, x7)
-
-inst_631:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1216*FLEN/8, x10, x6, x7)
-
-inst_632:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1218*FLEN/8, x10, x6, x7)
-
-inst_633:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1220*FLEN/8, x10, x6, x7)
-
-inst_634:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1222*FLEN/8, x10, x6, x7)
-
-inst_635:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1224*FLEN/8, x10, x6, x7)
-
-inst_636:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1226*FLEN/8, x10, x6, x7)
-
-inst_637:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1228*FLEN/8, x10, x6, x7)
-
-inst_638:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1230*FLEN/8, x10, x6, x7)
-
-inst_639:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1232*FLEN/8, x10, x6, x7)
-
-inst_640:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1234*FLEN/8, x10, x6, x7)
-
-inst_641:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1236*FLEN/8, x10, x6, x7)
-
-inst_642:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x6ce8a1 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dece8a1; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1238*FLEN/8, x10, x6, x7)
-
-inst_643:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0xfb and fm2 == 0x6ce8a1 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7dece8a1;
-valaddr_reg:x9; val_offset:1240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1240*FLEN/8, x10, x6, x7)
-
-inst_644:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1242*FLEN/8, x10, x6, x7)
-
-inst_645:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x6ce8a1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dece8a1; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1244*FLEN/8, x10, x6, x7)
-
-inst_646:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1246*FLEN/8, x10, x6, x7)
-
-inst_647:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1248*FLEN/8, x10, x6, x7)
-
-inst_648:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1250*FLEN/8, x10, x6, x7)
-
-inst_649:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1252*FLEN/8, x10, x6, x7)
-
-inst_650:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1254*FLEN/8, x10, x6, x7)
-
-inst_651:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1256*FLEN/8, x10, x6, x7)
-
-inst_652:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1258*FLEN/8, x10, x6, x7)
-
-inst_653:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044949 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x44949; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1260*FLEN/8, x10, x6, x7)
-
-inst_654:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x044949 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x44949;
-valaddr_reg:x9; val_offset:1262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1262*FLEN/8, x10, x6, x7)
-
-inst_655:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x253272;
-valaddr_reg:x9; val_offset:1264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1264*FLEN/8, x10, x6, x7)
-
-inst_656:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1266*FLEN/8, x10, x6, x7)
-
-inst_657:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1268*FLEN/8, x10, x6, x7)
-
-inst_658:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1270*FLEN/8, x10, x6, x7)
-
-inst_659:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1272*FLEN/8, x10, x6, x7)
-
-inst_660:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1274*FLEN/8, x10, x6, x7)
-
-inst_661:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1276*FLEN/8, x10, x6, x7)
-
-inst_662:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1278*FLEN/8, x10, x6, x7)
-
-inst_663:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1280*FLEN/8, x10, x6, x7)
-
-inst_664:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1282*FLEN/8, x10, x6, x7)
-
-inst_665:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1284*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_5)
-
-inst_666:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1286*FLEN/8, x10, x6, x7)
-
-inst_667:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1288*FLEN/8, x10, x6, x7)
-
-inst_668:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006dba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x6dba; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1290*FLEN/8, x10, x6, x7)
-
-inst_669:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006dba and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x6dba;
-valaddr_reg:x9; val_offset:1292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1292*FLEN/8, x10, x6, x7)
-
-inst_670:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006dba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x6dba; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1294*FLEN/8, x10, x6, x7)
-
-inst_671:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006dba and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x6dba;
-valaddr_reg:x9; val_offset:1296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1296*FLEN/8, x10, x6, x7)
-
-inst_672:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1298*FLEN/8, x10, x6, x7)
-
-inst_673:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1300*FLEN/8, x10, x6, x7)
-
-inst_674:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1302*FLEN/8, x10, x6, x7)
-
-inst_675:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x7becb0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x407becb0; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1304*FLEN/8, x10, x6, x7)
-
-inst_676:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x7becb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x407becb0;
-valaddr_reg:x9; val_offset:1306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1306*FLEN/8, x10, x6, x7)
-
-inst_677:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x80 and fm2 == 0x7becb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x407becb0;
-valaddr_reg:x9; val_offset:1308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1308*FLEN/8, x10, x6, x7)
-
-inst_678:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1310*FLEN/8, x10, x6, x7)
-
-inst_679:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1312*FLEN/8, x10, x6, x7)
-
-inst_680:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x253272;
-valaddr_reg:x9; val_offset:1314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1314*FLEN/8, x10, x6, x7)
-
-inst_681:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1316*FLEN/8, x10, x6, x7)
-
-inst_682:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1318*FLEN/8, x10, x6, x7)
-
-inst_683:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1320*FLEN/8, x10, x6, x7)
-
-inst_684:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1322*FLEN/8, x10, x6, x7)
-
-inst_685:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1324*FLEN/8, x10, x6, x7)
-
-inst_686:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4d97f8 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dcd97f8; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1326*FLEN/8, x10, x6, x7)
-
-inst_687:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4d97f8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7dcd97f8;
-valaddr_reg:x9; val_offset:1328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1328*FLEN/8, x10, x6, x7)
-
-inst_688:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1330*FLEN/8, x10, x6, x7)
-
-inst_689:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4d97f8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dcd97f8; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1332*FLEN/8, x10, x6, x7)
-
-inst_690:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1334*FLEN/8, x10, x6, x7)
-
-inst_691:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1336*FLEN/8, x10, x6, x7)
-
-inst_692:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1338*FLEN/8, x10, x6, x7)
-
-inst_693:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1340*FLEN/8, x10, x6, x7)
-
-inst_694:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03b83e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3b83e; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1342*FLEN/8, x10, x6, x7)
-
-inst_695:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03b83e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x3b83e;
-valaddr_reg:x9; val_offset:1344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1344*FLEN/8, x10, x6, x7)
-
-inst_696:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1346*FLEN/8, x10, x6, x7)
-
-inst_697:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x253272;
-valaddr_reg:x9; val_offset:1348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1348*FLEN/8, x10, x6, x7)
-
-inst_698:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1350*FLEN/8, x10, x6, x7)
-
-inst_699:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x253272;
-valaddr_reg:x9; val_offset:1352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1352*FLEN/8, x10, x6, x7)
-
-inst_700:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1354*FLEN/8, x10, x6, x7)
-
-inst_701:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x253272;
-valaddr_reg:x9; val_offset:1356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1356*FLEN/8, x10, x6, x7)
-
-inst_702:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1358*FLEN/8, x10, x6, x7)
-
-inst_703:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x253272;
-valaddr_reg:x9; val_offset:1360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1360*FLEN/8, x10, x6, x7)
-
-inst_704:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1362*FLEN/8, x10, x6, x7)
-
-inst_705:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x253272;
-valaddr_reg:x9; val_offset:1364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1364*FLEN/8, x10, x6, x7)
-
-inst_706:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1366*FLEN/8, x10, x6, x7)
-
-inst_707:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005f39 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5f39; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1368*FLEN/8, x10, x6, x7)
-
-inst_708:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005f39 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x5f39;
-valaddr_reg:x9; val_offset:1370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1370*FLEN/8, x10, x6, x7)
-
-inst_709:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005f39 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5f39; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1372*FLEN/8, x10, x6, x7)
-
-inst_710:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005f39 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x5f39;
-valaddr_reg:x9; val_offset:1374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1374*FLEN/8, x10, x6, x7)
-
-inst_711:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1376*FLEN/8, x10, x6, x7)
-
-inst_712:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x253272;
-valaddr_reg:x9; val_offset:1378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1378*FLEN/8, x10, x6, x7)
-
-inst_713:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1380*FLEN/8, x10, x6, x7)
-
-inst_714:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x5a9fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x405a9fe8; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1382*FLEN/8, x10, x6, x7)
-
-inst_715:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a9fe8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x405a9fe8;
-valaddr_reg:x9; val_offset:1384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1384*FLEN/8, x10, x6, x7)
-
-inst_716:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a9fe8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x405a9fe8;
-valaddr_reg:x9; val_offset:1386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1386*FLEN/8, x10, x6, x7)
-
-inst_717:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1388*FLEN/8, x10, x6, x7)
-
-inst_718:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1390*FLEN/8, x10, x6, x7)
-
-inst_719:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1392*FLEN/8, x10, x6, x7)
-
-inst_720:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1394*FLEN/8, x10, x6, x7)
-
-inst_721:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1396*FLEN/8, x10, x6, x7)
-
-inst_722:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1398*FLEN/8, x10, x6, x7)
-
-inst_723:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1400*FLEN/8, x10, x6, x7)
-
-inst_724:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1402*FLEN/8, x10, x6, x7)
-
-inst_725:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7fc1a6 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dffc1a6; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1404*FLEN/8, x10, x6, x7)
-
-inst_726:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x7fc1a6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7dffc1a6;
-valaddr_reg:x9; val_offset:1406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1406*FLEN/8, x10, x6, x7)
-
-inst_727:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1408*FLEN/8, x10, x6, x7)
-
-inst_728:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7fc1a6 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dffc1a6; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1410*FLEN/8, x10, x6, x7)
-
-inst_729:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1412*FLEN/8, x10, x6, x7)
-
-inst_730:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1414*FLEN/8, x10, x6, x7)
-
-inst_731:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1416*FLEN/8, x10, x6, x7)
-
-inst_732:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1418*FLEN/8, x10, x6, x7)
-
-inst_733:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a095 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4a095; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1420*FLEN/8, x10, x6, x7)
-
-inst_734:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x04a095 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x4a095;
-valaddr_reg:x9; val_offset:1422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1422*FLEN/8, x10, x6, x7)
-
-inst_735:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1424*FLEN/8, x10, x6, x7)
-
-inst_736:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1426*FLEN/8, x10, x6, x7)
-
-inst_737:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1428*FLEN/8, x10, x6, x7)
-
-inst_738:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1430*FLEN/8, x10, x6, x7)
-
-inst_739:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1432*FLEN/8, x10, x6, x7)
-
-inst_740:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1434*FLEN/8, x10, x6, x7)
-
-inst_741:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1436*FLEN/8, x10, x6, x7)
-
-inst_742:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1438*FLEN/8, x10, x6, x7)
-
-inst_743:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1440*FLEN/8, x10, x6, x7)
-
-inst_744:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007675 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7675; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1442*FLEN/8, x10, x6, x7)
-
-inst_745:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007675 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x7675;
-valaddr_reg:x9; val_offset:1444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1444*FLEN/8, x10, x6, x7)
-
-inst_746:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007675 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7675; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1446*FLEN/8, x10, x6, x7)
-
-inst_747:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007675 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7675;
-valaddr_reg:x9; val_offset:1448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1448*FLEN/8, x10, x6, x7)
-
-inst_748:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1450*FLEN/8, x10, x6, x7)
-
-inst_749:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1452*FLEN/8, x10, x6, x7)
-
-inst_750:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1454*FLEN/8, x10, x6, x7)
-
-inst_751:// fs1 == 0 and fe1 == 0x81 and fm1 == 0x07fbc3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4087fbc3; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1456*FLEN/8, x10, x6, x7)
-
-inst_752:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x07fbc3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x4087fbc3;
-valaddr_reg:x9; val_offset:1458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1458*FLEN/8, x10, x6, x7)
-
-inst_753:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x07fbc3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x4087fbc3;
-valaddr_reg:x9; val_offset:1460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1460*FLEN/8, x10, x6, x7)
-
-inst_754:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1462*FLEN/8, x10, x6, x7)
-
-inst_755:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1464*FLEN/8, x10, x6, x7)
-
-inst_756:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:1466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1466*FLEN/8, x10, x6, x7)
-
-inst_757:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1468*FLEN/8, x10, x6, x7)
-
-inst_758:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1470*FLEN/8, x10, x6, x7)
-
-inst_759:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1472*FLEN/8, x10, x6, x7)
-
-inst_760:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1474*FLEN/8, x10, x6, x7)
-
-inst_761:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1476*FLEN/8, x10, x6, x7)
-
-inst_762:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1478*FLEN/8, x10, x6, x7)
-
-inst_763:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1480*FLEN/8, x10, x6, x7)
-
-inst_764:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1482*FLEN/8, x10, x6, x7)
-
-inst_765:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1484*FLEN/8, x10, x6, x7)
-
-inst_766:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1486*FLEN/8, x10, x6, x7)
-
-inst_767:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d5c91 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d9d5c91; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1488*FLEN/8, x10, x6, x7)
-
-inst_768:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d5c91 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7d9d5c91;
-valaddr_reg:x9; val_offset:1490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1490*FLEN/8, x10, x6, x7)
-
-inst_769:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1492*FLEN/8, x10, x6, x7)
-
-inst_770:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d5c91 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d9d5c91; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1494*FLEN/8, x10, x6, x7)
-
-inst_771:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1496*FLEN/8, x10, x6, x7)
-
-inst_772:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1498*FLEN/8, x10, x6, x7)
-
-inst_773:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1500*FLEN/8, x10, x6, x7)
-
-inst_774:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1502*FLEN/8, x10, x6, x7)
-
-inst_775:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1504*FLEN/8, x10, x6, x7)
-
-inst_776:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1506*FLEN/8, x10, x6, x7)
-
-inst_777:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1508*FLEN/8, x10, x6, x7)
-
-inst_778:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02d8d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2d8d9; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1510*FLEN/8, x10, x6, x7)
-
-inst_779:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02d8d9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x2d8d9;
-valaddr_reg:x9; val_offset:1512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1512*FLEN/8, x10, x6, x7)
-
-inst_780:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1514*FLEN/8, x10, x6, x7)
-
-inst_781:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1516*FLEN/8, x10, x6, x7)
-
-inst_782:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1518*FLEN/8, x10, x6, x7)
-
-inst_783:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1520*FLEN/8, x10, x6, x7)
-
-inst_784:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1522*FLEN/8, x10, x6, x7)
-
-inst_785:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1524*FLEN/8, x10, x6, x7)
-
-inst_786:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1526*FLEN/8, x10, x6, x7)
-
-inst_787:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0048e2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x48e2; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1528*FLEN/8, x10, x6, x7)
-
-inst_788:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0048e2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x48e2;
-valaddr_reg:x9; val_offset:1530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1530*FLEN/8, x10, x6, x7)
-
-inst_789:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0048e2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x48e2; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1532*FLEN/8, x10, x6, x7)
-
-inst_790:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0048e2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x48e2;
-valaddr_reg:x9; val_offset:1534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1534*FLEN/8, x10, x6, x7)
-
-inst_791:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1536*FLEN/8, x10, x6, x7)
-
-inst_792:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1538*FLEN/8, x10, x6, x7)
-
-inst_793:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1540*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_6)
-
-inst_794:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x2755e6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x402755e6; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1542*FLEN/8, x10, x6, x7)
-
-inst_795:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2755e6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x402755e6;
-valaddr_reg:x9; val_offset:1544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1544*FLEN/8, x10, x6, x7)
-
-inst_796:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2755e6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x402755e6;
-valaddr_reg:x9; val_offset:1546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1546*FLEN/8, x10, x6, x7)
-
-inst_797:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1548*FLEN/8, x10, x6, x7)
-
-inst_798:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1550*FLEN/8, x10, x6, x7)
-
-inst_799:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1552*FLEN/8, x10, x6, x7)
-
-inst_800:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1554*FLEN/8, x10, x6, x7)
-
-inst_801:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1556*FLEN/8, x10, x6, x7)
-
-inst_802:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1558*FLEN/8, x10, x6, x7)
-
-inst_803:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1560*FLEN/8, x10, x6, x7)
-
-inst_804:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1562*FLEN/8, x10, x6, x7)
-
-inst_805:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x21db85 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe21db85; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1564*FLEN/8, x10, x6, x7)
-
-inst_806:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x21db85 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xfe21db85;
-valaddr_reg:x9; val_offset:1566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1566*FLEN/8, x10, x6, x7)
-
-inst_807:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1568*FLEN/8, x10, x6, x7)
-
-inst_808:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x21db85 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe21db85; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1570*FLEN/8, x10, x6, x7)
-
-inst_809:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1572*FLEN/8, x10, x6, x7)
-
-inst_810:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1574*FLEN/8, x10, x6, x7)
-
-inst_811:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1576*FLEN/8, x10, x6, x7)
-
-inst_812:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1578*FLEN/8, x10, x6, x7)
-
-inst_813:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x05db58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8005db58; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1580*FLEN/8, x10, x6, x7)
-
-inst_814:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x05db58 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x8005db58;
-valaddr_reg:x9; val_offset:1582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1582*FLEN/8, x10, x6, x7)
-
-inst_815:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1584*FLEN/8, x10, x6, x7)
-
-inst_816:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1586*FLEN/8, x10, x6, x7)
-
-inst_817:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1588*FLEN/8, x10, x6, x7)
-
-inst_818:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1590*FLEN/8, x10, x6, x7)
-
-inst_819:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1592*FLEN/8, x10, x6, x7)
-
-inst_820:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0095ef and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800095ef; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1594*FLEN/8, x10, x6, x7)
-
-inst_821:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0095ef and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x800095ef;
-valaddr_reg:x9; val_offset:1596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1596*FLEN/8, x10, x6, x7)
-
-inst_822:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0095ef and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800095ef; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1598*FLEN/8, x10, x6, x7)
-
-inst_823:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0095ef and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x800095ef;
-valaddr_reg:x9; val_offset:1600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1600*FLEN/8, x10, x6, x7)
-
-inst_824:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1602*FLEN/8, x10, x6, x7)
-
-inst_825:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1604*FLEN/8, x10, x6, x7)
-
-inst_826:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1606*FLEN/8, x10, x6, x7)
-
-inst_827:// fs1 == 1 and fe1 == 0x81 and fm1 == 0x2c1dce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc0ac1dce; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1608*FLEN/8, x10, x6, x7)
-
-inst_828:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x2c1dce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc0ac1dce;
-valaddr_reg:x9; val_offset:1610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1610*FLEN/8, x10, x6, x7)
-
-inst_829:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x2c1dce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xc0ac1dce;
-valaddr_reg:x9; val_offset:1612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1612*FLEN/8, x10, x6, x7)
-
-inst_830:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1614*FLEN/8, x10, x6, x7)
-
-inst_831:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1616*FLEN/8, x10, x6, x7)
-
-inst_832:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1618*FLEN/8, x10, x6, x7)
-
-inst_833:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1620*FLEN/8, x10, x6, x7)
-
-inst_834:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1622*FLEN/8, x10, x6, x7)
-
-inst_835:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1624*FLEN/8, x10, x6, x7)
-
-inst_836:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1626*FLEN/8, x10, x6, x7)
-
-inst_837:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1628*FLEN/8, x10, x6, x7)
-
-inst_838:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x74bcf0 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdf4bcf0; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1630*FLEN/8, x10, x6, x7)
-
-inst_839:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0xfb and fm2 == 0x74bcf0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xfdf4bcf0;
-valaddr_reg:x9; val_offset:1632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1632*FLEN/8, x10, x6, x7)
-
-inst_840:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1634*FLEN/8, x10, x6, x7)
-
-inst_841:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x74bcf0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdf4bcf0; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1636*FLEN/8, x10, x6, x7)
-
-inst_842:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1638*FLEN/8, x10, x6, x7)
-
-inst_843:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1640*FLEN/8, x10, x6, x7)
-
-inst_844:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1642*FLEN/8, x10, x6, x7)
-
-inst_845:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1644*FLEN/8, x10, x6, x7)
-
-inst_846:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x046d8c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80046d8c; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1646*FLEN/8, x10, x6, x7)
-
-inst_847:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x046d8c and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x80046d8c;
-valaddr_reg:x9; val_offset:1648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1648*FLEN/8, x10, x6, x7)
-
-inst_848:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1650*FLEN/8, x10, x6, x7)
-
-inst_849:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1652*FLEN/8, x10, x6, x7)
-
-inst_850:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1654*FLEN/8, x10, x6, x7)
-
-inst_851:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00715a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000715a; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1656*FLEN/8, x10, x6, x7)
-
-inst_852:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00715a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x8000715a;
-valaddr_reg:x9; val_offset:1658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1658*FLEN/8, x10, x6, x7)
-
-inst_853:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00715a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000715a; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1660*FLEN/8, x10, x6, x7)
-
-inst_854:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00715a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x8000715a;
-valaddr_reg:x9; val_offset:1662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1662*FLEN/8, x10, x6, x7)
-
-inst_855:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1664*FLEN/8, x10, x6, x7)
-
-inst_856:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1666*FLEN/8, x10, x6, x7)
-
-inst_857:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1668*FLEN/8, x10, x6, x7)
-
-inst_858:// fs1 == 1 and fe1 == 0x81 and fm1 == 0x022004 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc0822004; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1670*FLEN/8, x10, x6, x7)
-
-inst_859:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x022004 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc0822004;
-valaddr_reg:x9; val_offset:1672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1672*FLEN/8, x10, x6, x7)
-
-inst_860:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x81 and fm2 == 0x022004 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xc0822004;
-valaddr_reg:x9; val_offset:1674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1674*FLEN/8, x10, x6, x7)
-
-inst_861:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1676*FLEN/8, x10, x6, x7)
-
-inst_862:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1678*FLEN/8, x10, x6, x7)
-
-inst_863:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1680*FLEN/8, x10, x6, x7)
-
-inst_864:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1682*FLEN/8, x10, x6, x7)
-
-inst_865:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1684*FLEN/8, x10, x6, x7)
-
-inst_866:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1686*FLEN/8, x10, x6, x7)
-
-inst_867:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1688*FLEN/8, x10, x6, x7)
-
-inst_868:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1690*FLEN/8, x10, x6, x7)
-
-inst_869:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x14db11 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe14db11; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1692*FLEN/8, x10, x6, x7)
-
-inst_870:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0xfc and fm2 == 0x14db11 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xfe14db11;
-valaddr_reg:x9; val_offset:1694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1694*FLEN/8, x10, x6, x7)
-
-inst_871:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1696*FLEN/8, x10, x6, x7)
-
-inst_872:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x14db11 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe14db11; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1698*FLEN/8, x10, x6, x7)
-
-inst_873:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1700*FLEN/8, x10, x6, x7)
-
-inst_874:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1702*FLEN/8, x10, x6, x7)
-
-inst_875:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1704*FLEN/8, x10, x6, x7)
-
-inst_876:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1706*FLEN/8, x10, x6, x7)
-
-inst_877:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0562e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800562e7; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1708*FLEN/8, x10, x6, x7)
-
-inst_878:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0562e7 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x800562e7;
-valaddr_reg:x9; val_offset:1710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1710*FLEN/8, x10, x6, x7)
-
-inst_879:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1712*FLEN/8, x10, x6, x7)
-
-inst_880:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0089e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800089e3; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1714*FLEN/8, x10, x6, x7)
-
-inst_881:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0089e3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x800089e3;
-valaddr_reg:x9; val_offset:1716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1716*FLEN/8, x10, x6, x7)
-
-inst_882:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0089e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800089e3; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1718*FLEN/8, x10, x6, x7)
-
-inst_883:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0089e3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x800089e3;
-valaddr_reg:x9; val_offset:1720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1720*FLEN/8, x10, x6, x7)
-
-inst_884:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1722*FLEN/8, x10, x6, x7)
-
-inst_885:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1724*FLEN/8, x10, x6, x7)
-
-inst_886:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1726*FLEN/8, x10, x6, x7)
-
-inst_887:// fs1 == 1 and fe1 == 0x81 and fm1 == 0x1e4a63 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc09e4a63; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1728*FLEN/8, x10, x6, x7)
-
-inst_888:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1e4a63 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc09e4a63;
-valaddr_reg:x9; val_offset:1730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1730*FLEN/8, x10, x6, x7)
-
-inst_889:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1e4a63 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xc09e4a63;
-valaddr_reg:x9; val_offset:1732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1732*FLEN/8, x10, x6, x7)
-
-inst_890:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1734*FLEN/8, x10, x6, x7)
-
-inst_891:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1736*FLEN/8, x10, x6, x7)
-
-inst_892:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:1738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1738*FLEN/8, x10, x6, x7)
-
-inst_893:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1740*FLEN/8, x10, x6, x7)
-
-inst_894:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1742*FLEN/8, x10, x6, x7)
-
-inst_895:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1744*FLEN/8, x10, x6, x7)
-
-inst_896:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1746*FLEN/8, x10, x6, x7)
-
-inst_897:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1748*FLEN/8, x10, x6, x7)
-
-inst_898:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1750*FLEN/8, x10, x6, x7)
-
-inst_899:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1752*FLEN/8, x10, x6, x7)
-
-inst_900:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1754*FLEN/8, x10, x6, x7)
-
-inst_901:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1756*FLEN/8, x10, x6, x7)
-
-inst_902:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1758*FLEN/8, x10, x6, x7)
-
-inst_903:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x374171 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdb74171; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1760*FLEN/8, x10, x6, x7)
-
-inst_904:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x374171 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xfdb74171;
-valaddr_reg:x9; val_offset:1762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1762*FLEN/8, x10, x6, x7)
-
-inst_905:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1764*FLEN/8, x10, x6, x7)
-
-inst_906:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x374171 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdb74171; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1766*FLEN/8, x10, x6, x7)
-
-inst_907:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1768*FLEN/8, x10, x6, x7)
-
-inst_908:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1770*FLEN/8, x10, x6, x7)
-
-inst_909:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1772*FLEN/8, x10, x6, x7)
-
-inst_910:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1774*FLEN/8, x10, x6, x7)
-
-inst_911:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1776*FLEN/8, x10, x6, x7)
-
-inst_912:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1778*FLEN/8, x10, x6, x7)
-
-inst_913:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1780*FLEN/8, x10, x6, x7)
-
-inst_914:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0350c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800350c8; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1782*FLEN/8, x10, x6, x7)
-
-inst_915:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0350c8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x800350c8;
-valaddr_reg:x9; val_offset:1784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1784*FLEN/8, x10, x6, x7)
-
-inst_916:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1786*FLEN/8, x10, x6, x7)
-
-inst_917:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1788*FLEN/8, x10, x6, x7)
-
-inst_918:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1790*FLEN/8, x10, x6, x7)
-
-inst_919:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x253272;
-valaddr_reg:x9; val_offset:1792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1792*FLEN/8, x10, x6, x7)
-
-inst_920:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x253272;
-valaddr_reg:x9; val_offset:1794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1794*FLEN/8, x10, x6, x7)
-
-inst_921:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1796*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_7)
-
-inst_922:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1798*FLEN/8, x10, x6, x7)
-
-inst_923:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1800*FLEN/8, x10, x6, x7)
-
-inst_924:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1802*FLEN/8, x10, x6, x7)
-
-inst_925:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1804*FLEN/8, x10, x6, x7)
-
-inst_926:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1806*FLEN/8, x10, x6, x7)
-
-inst_927:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1808*FLEN/8, x10, x6, x7)
-
-inst_928:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1810*FLEN/8, x10, x6, x7)
-
-inst_929:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1812*FLEN/8, x10, x6, x7)
-
-inst_930:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1814*FLEN/8, x10, x6, x7)
-
-inst_931:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1816*FLEN/8, x10, x6, x7)
-
-inst_932:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0077e4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x800077e4;
-valaddr_reg:x9; val_offset:1818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1818*FLEN/8, x10, x6, x7)
-
-inst_933:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0077e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800077e4; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1820*FLEN/8, x10, x6, x7)
-
-inst_934:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1822*FLEN/8, x10, x6, x7)
-
-inst_935:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1824*FLEN/8, x10, x6, x7)
-
-inst_936:// fs1 == 1 and fe1 == 0x80 and fm1 == 0x42deee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc042deee; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1826*FLEN/8, x10, x6, x7)
-
-inst_937:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x42deee and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc042deee;
-valaddr_reg:x9; val_offset:1828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1828*FLEN/8, x10, x6, x7)
-
-inst_938:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x42deee and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xc042deee;
-valaddr_reg:x9; val_offset:1830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1830*FLEN/8, x10, x6, x7)
-
-inst_939:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1832*FLEN/8, x10, x6, x7)
-
-inst_940:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1834*FLEN/8, x10, x6, x7)
-
-inst_941:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1836*FLEN/8, x10, x6, x7)
-
-inst_942:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1838*FLEN/8, x10, x6, x7)
-
-inst_943:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1840*FLEN/8, x10, x6, x7)
-
-inst_944:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1842*FLEN/8, x10, x6, x7)
-
-inst_945:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1844*FLEN/8, x10, x6, x7)
-
-inst_946:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1846*FLEN/8, x10, x6, x7)
-
-inst_947:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x016ce1 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe016ce1; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1848*FLEN/8, x10, x6, x7)
-
-inst_948:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x016ce1 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xfe016ce1;
-valaddr_reg:x9; val_offset:1850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1850*FLEN/8, x10, x6, x7)
-
-inst_949:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1852*FLEN/8, x10, x6, x7)
-
-inst_950:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x016ce1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe016ce1; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1854*FLEN/8, x10, x6, x7)
-
-inst_951:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1856*FLEN/8, x10, x6, x7)
-
-inst_952:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1858*FLEN/8, x10, x6, x7)
-
-inst_953:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1860*FLEN/8, x10, x6, x7)
-
-inst_954:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1862*FLEN/8, x10, x6, x7)
-
-inst_955:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04aeea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8004aeea; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1864*FLEN/8, x10, x6, x7)
-
-inst_956:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04aeea and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x8004aeea;
-valaddr_reg:x9; val_offset:1866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1866*FLEN/8, x10, x6, x7)
-
-inst_957:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1868*FLEN/8, x10, x6, x7)
-
-inst_958:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0077e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800077e4; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1870*FLEN/8, x10, x6, x7)
-
-inst_959:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0077e4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x800077e4;
-valaddr_reg:x9; val_offset:1872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1872*FLEN/8, x10, x6, x7)
-
-inst_960:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1874*FLEN/8, x10, x6, x7)
-
-inst_961:// fs1 == 1 and fe1 == 0x81 and fm1 == 0x09a0ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc089a0ec; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1876*FLEN/8, x10, x6, x7)
-
-inst_962:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x09a0ec and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc089a0ec;
-valaddr_reg:x9; val_offset:1878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1878*FLEN/8, x10, x6, x7)
-
-inst_963:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x09a0ec and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xc089a0ec;
-valaddr_reg:x9; val_offset:1880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1880*FLEN/8, x10, x6, x7)
-
-inst_964:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1882*FLEN/8, x10, x6, x7)
-
-inst_965:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1884*FLEN/8, x10, x6, x7)
-
-inst_966:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1886*FLEN/8, x10, x6, x7)
-
-inst_967:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1888*FLEN/8, x10, x6, x7)
-
-inst_968:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1890*FLEN/8, x10, x6, x7)
-
-inst_969:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1892*FLEN/8, x10, x6, x7)
-
-inst_970:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1894*FLEN/8, x10, x6, x7)
-
-inst_971:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1896*FLEN/8, x10, x6, x7)
-
-inst_972:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1898*FLEN/8, x10, x6, x7)
-
-inst_973:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1900*FLEN/8, x10, x6, x7)
-
-inst_974:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1902*FLEN/8, x10, x6, x7)
-
-inst_975:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1904*FLEN/8, x10, x6, x7)
-
-inst_976:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1906*FLEN/8, x10, x6, x7)
-
-inst_977:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x253272;
-valaddr_reg:x9; val_offset:1908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1908*FLEN/8, x10, x6, x7)
-
-inst_978:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1910*FLEN/8, x10, x6, x7)
-
-inst_979:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1912*FLEN/8, x10, x6, x7)
-
-inst_980:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1914*FLEN/8, x10, x6, x7)
-
-inst_981:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1916*FLEN/8, x10, x6, x7)
-
-inst_982:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1918*FLEN/8, x10, x6, x7)
-
-inst_983:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1920*FLEN/8, x10, x6, x7)
-
-inst_984:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1922*FLEN/8, x10, x6, x7)
-
-inst_985:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1924*FLEN/8, x10, x6, x7)
-
-inst_986:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x1a917b;
-valaddr_reg:x9; val_offset:1926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1926*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-test_dataset_1:
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(2138705407,32,FLEN)
-NAN_BOXED(2138705407,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2437746,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2437746,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(3032532,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(3032532,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(1865853,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2135208886,32,FLEN)
-NAN_BOXED(2135208886,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(1865853,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2151321972,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2151321972,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(17411,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(17411,32,FLEN)
-NAN_BOXED(17411,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(17411,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1075586948,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1075586948,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(1075586948,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2105562406,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(2105562406,32,FLEN)
-NAN_BOXED(2105562406,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2105562406,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2105562406,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2105562406,32,FLEN)
-NAN_BOXED(2105562406,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(152165,32,FLEN)
-NAN_BOXED(2138705407,32,FLEN)
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-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2147790570,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2147514340,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2147514340,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3230245100,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3230245100,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(3230245100,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2437746,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3032532,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1865853,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2151321972,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_7:
-    .fill 130*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fmaxm_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fmaxm_b1-01.S
deleted file mode 100644
index 859aaa9bd..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fmaxm_b1-01.S
+++ /dev/null
@@ -1,5889 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:05:25 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmaxm.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmaxm.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fmaxm_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs2 == rd != rs1, rs1==f30, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f31; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rs2 == rd, rs1==f29, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f29; op2:f29; dest:f29; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f29, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f28; op2:f30; dest:f28; op1val:0x0; op2val:0x1;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f28, f28, f30, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f31, rs2==f28, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f31; op2:f28; dest:f30; op1val:0x0; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f30, f31, f28, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f26; op2:f26; dest:f27; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f27, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f27; op2:f25; dest:f26; op1val:0x0; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f26, f27, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f24; op2:f27; dest:f25; op1val:0x0; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f25, f24, f27, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f25; op2:f23; dest:f24; op1val:0x0; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f24, f25, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f22; op2:f24; dest:f23; op1val:0x0; op2val:0x800000;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f23, f22, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f23; op2:f21; dest:f22; op1val:0x0; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f22, f23, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x800001;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f21; op2:f19; dest:f20; op1val:0x0; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f20, f21, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f18; op2:f20; dest:f19; op1val:0x0; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f19; op2:f17; dest:f18; op1val:0x0; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f18, f19, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f16; op2:f18; dest:f17; op1val:0x0; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f17, f16, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f17; op2:f15; dest:f16; op1val:0x0; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f16, f17, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f15; op2:f13; dest:f14; op1val:0x0; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f14, f15, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f12; op2:f14; dest:f13; op1val:0x0; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f13; op2:f11; dest:f12; op1val:0x0; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f12, f13, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f10; op2:f12; dest:f11; op1val:0x0; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f11, f10, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f11; op2:f9; dest:f10; op1val:0x0; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f10, f11, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f9; op2:f7; dest:f8; op1val:0x0; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f8, f9, f7, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f6; op2:f8; dest:f7; op1val:0x80000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f7, rs2==f5, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f7; op2:f5; dest:f6; op1val:0x80000000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f6, f7, f5, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f4; op2:f6; dest:f5; op1val:0x80000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f5, f4, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f5, rs2==f3, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f5; op2:f3; dest:f4; op1val:0x80000000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f4, f5, f3, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f2; op2:f4; dest:f3; op1val:0x80000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f3, rs2==f1, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f3; op2:f1; dest:f2; op1val:0x80000000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f2, f3, f1, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f0; op2:f2; dest:f1; op1val:0x80000000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f1; op2:f30; dest:f31; op1val:0x80000000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f1, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f0; dest:f31; op1val:0x80000000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f0, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rd==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f0; op1val:0x80000000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:72*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:74*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:76*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:78*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:80*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:82*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:84*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:86*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:88*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:90*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:92*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:94*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x0;
-   valaddr_reg:x3; val_offset:96*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:98*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x1;
-   valaddr_reg:x3; val_offset:100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x2;
-   valaddr_reg:x3; val_offset:104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x800000;
-   valaddr_reg:x3; val_offset:112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x800001;
-   valaddr_reg:x3; val_offset:116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x0;
-   valaddr_reg:x3; val_offset:192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x1;
-   valaddr_reg:x3; val_offset:196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x2;
-   valaddr_reg:x3; val_offset:200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x800000;
-   valaddr_reg:x3; val_offset:208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x800001;
-   valaddr_reg:x3; val_offset:212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x0;
-   valaddr_reg:x3; val_offset:240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x1;
-   valaddr_reg:x3; val_offset:244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x2;
-   valaddr_reg:x3; val_offset:248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x800000;
-   valaddr_reg:x3; val_offset:256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x800001;
-   valaddr_reg:x3; val_offset:260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x0;
-   valaddr_reg:x3; val_offset:480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x1;
-   valaddr_reg:x3; val_offset:484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x2;
-   valaddr_reg:x3; val_offset:488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x0;
-   valaddr_reg:x3; val_offset:528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x1;
-   valaddr_reg:x3; val_offset:532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x2;
-   valaddr_reg:x3; val_offset:536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x800000;
-   valaddr_reg:x3; val_offset:544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x800001;
-   valaddr_reg:x3; val_offset:548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x0;
-   valaddr_reg:x3; val_offset:768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x1;
-   valaddr_reg:x3; val_offset:772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x2;
-   valaddr_reg:x3; val_offset:776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x0;
-   valaddr_reg:x3; val_offset:816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x1;
-   valaddr_reg:x3; val_offset:820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x2;
-   valaddr_reg:x3; val_offset:824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x0;
-   valaddr_reg:x3; val_offset:864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x1;
-   valaddr_reg:x3; val_offset:868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x2;
-   valaddr_reg:x3; val_offset:872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x0;
-   valaddr_reg:x3; val_offset:912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x1;
-   valaddr_reg:x3; val_offset:916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x2;
-   valaddr_reg:x3; val_offset:920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x800000;
-   valaddr_reg:x3; val_offset:928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x800001;
-   valaddr_reg:x3; val_offset:932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x0;
-   valaddr_reg:x3; val_offset:960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x1;
-   valaddr_reg:x3; val_offset:964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x2;
-   valaddr_reg:x3; val_offset:968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:990*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:992*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:994*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:996*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:998*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1000*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1002*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1004*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1006*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x0;
-   valaddr_reg:x3; val_offset:1008*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:1010*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x1;
-   valaddr_reg:x3; val_offset:1012*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:1014*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x2;
-   valaddr_reg:x3; val_offset:1016*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:1018*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:1020*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:1022*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x800000;
-   valaddr_reg:x3; val_offset:1024*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:1026*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x800001;
-   valaddr_reg:x3; val_offset:1028*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:1030*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1032*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1034*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:1036*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:1038*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:1040*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:1042*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:1044*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:1046*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1048*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1050*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1052*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1054*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1056*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:1058*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1060*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:1062*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1064*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:1066*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:1068*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:1070*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:1072*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:1074*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:1076*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:1078*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1080*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1082*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:1084*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:1086*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:1088*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:1090*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:1092*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:1094*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1096*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1098*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:1106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:1110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:1114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:1116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:1118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:1120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:1122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:1124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:1126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:1132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:1134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:1136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:1138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:1140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:1142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:1152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x2;
-   valaddr_reg:x3; val_offset:1154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
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-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
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-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
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-NAN_BOXED(2156221781,32,FLEN)
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-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
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-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
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-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
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-NAN_BOXED(2139095041,32,FLEN)
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-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
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-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
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-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
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-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
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-NAN_BOXED(8388608,32,FLEN)
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-NAN_BOXED(8388609,32,FLEN)
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-NAN_BOXED(1065353216,32,FLEN)
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-NAN_BOXED(1065353216,32,FLEN)
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-NAN_BOXED(1065353216,32,FLEN)
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-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
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-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 132*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fmaxm_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fmaxm_b19-01.S
deleted file mode 100644
index 31f8a00aa..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fmaxm_b19-01.S
+++ /dev/null
@@ -1,9704 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:05:25 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmaxm.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmaxm.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fmaxm_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs2 == rd != rs1, rs1==f30, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f31; dest:f31; op1val:0x7dce622b; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rs2 == rd, rs1==f29, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f29; op2:f29; dest:f29; op1val:0x7dce622b; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f29, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x183299 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f28; op2:f30; dest:f28; op1val:0x7f7fffff; op2val:0x7d183299;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f28, f28, f30, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f31, rs2==f28, rd==f30,fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f31; op2:f28; dest:f30; op1val:0x7d183299; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f30, f31, f28, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f26; op2:f26; dest:f27; op1val:0x7f7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f27, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f27; op2:f25; dest:f26; op1val:0x7dce622b; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f26, f27, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f24; op2:f27; dest:f25; op1val:0x7dce622b; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f25, f24, f27, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f25; op2:f23; dest:f24; op1val:0x7d902b16; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f24, f25, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f22; op2:f24; dest:f23; op1val:0x7dce622b; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f23, f22, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x6a2c24 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f23; op2:f21; dest:f22; op1val:0x7f7fffff; op2val:0x7d6a2c24;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f22, f23, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f20; op2:f22; dest:f21; op1val:0x7d6a2c24; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f21; op2:f19; dest:f20; op1val:0x7f7fffff; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f20, f21, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f18; op2:f20; dest:f19; op1val:0x7dce622b; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f19; op2:f17; dest:f18; op1val:0x7e2fb07b; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f18, f19, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f16; op2:f18; dest:f17; op1val:0x7dce622b; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f17, f16, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f17, rs2==f15, rd==f16,fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f17; op2:f15; dest:f16; op1val:0xfdea577e; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f16, f17, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f14; op2:f16; dest:f15; op1val:0x7dce622b; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x291dc8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f15; op2:f13; dest:f14; op1val:0x7f7fffff; op2val:0xfd291dc8;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f14, f15, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f12; op2:f14; dest:f13; op1val:0xfd291dc8; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f13; op2:f11; dest:f12; op1val:0x7f7fffff; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f12, f13, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f10; op2:f12; dest:f11; op1val:0x7dce622b; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f11, f10, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x153eee and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f11; op2:f9; dest:f10; op1val:0x7f7fffff; op2val:0xfd953eee;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f10, f11, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f8; op2:f10; dest:f9; op1val:0xfd953eee; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f9; op2:f7; dest:f8; op1val:0x7f7fffff; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f8, f9, f7, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f6; op2:f8; dest:f7; op1val:0x7dce622b; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f7, rs2==f5, rd==f6,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x1946c8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f7; op2:f5; dest:f6; op1val:0x7f7fffff; op2val:0xfd9946c8;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f6, f7, f5, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f4; op2:f6; dest:f5; op1val:0xfd9946c8; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f5, f4, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f5, rs2==f3, rd==f4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f5; op2:f3; dest:f4; op1val:0x7f7fffff; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f4, f5, f3, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f2; op2:f4; dest:f3; op1val:0x7dce622b; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f3, rs2==f1, rd==f2,fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f3; op2:f1; dest:f2; op1val:0xfd2820df; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f2, f3, f1, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f0; op2:f2; dest:f1; op1val:0x7dce622b; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x07167c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f1; op2:f30; dest:f31; op1val:0x255707; op2val:0x7e07167c;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f1, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f0,fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f0; dest:f31; op1val:0x7e07167c; op2val:0x255707;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f0, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rd==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f0; op1val:0x255707; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x255707;
-   valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x667e2a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x7de67e2a;
-   valaddr_reg:x3; val_offset:72*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x255707;
-   valaddr_reg:x3; val_offset:74*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:76*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:78*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x13d219 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x7e13d219;
-   valaddr_reg:x3; val_offset:80*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x255707;
-   valaddr_reg:x3; val_offset:82*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:84*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:86*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d8cd6 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x7d9d8cd6;
-   valaddr_reg:x3; val_offset:88*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x255707;
-   valaddr_reg:x3; val_offset:90*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:92*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:94*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x1f6f2f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x7e1f6f2f;
-   valaddr_reg:x3; val_offset:96*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x255707;
-   valaddr_reg:x3; val_offset:98*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03c146 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0xfe03c146;
-   valaddr_reg:x3; val_offset:104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x255707;
-   valaddr_reg:x3; val_offset:106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x157915 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0xfd157915;
-   valaddr_reg:x3; val_offset:112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x255707;
-   valaddr_reg:x3; val_offset:114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x48a6ca and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0xfdc8a6ca;
-   valaddr_reg:x3; val_offset:120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x255707;
-   valaddr_reg:x3; val_offset:122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x4500e4 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0xfd4500e4;
-   valaddr_reg:x3; val_offset:128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x255707;
-   valaddr_reg:x3; val_offset:130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2b7553 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0xfe2b7553;
-   valaddr_reg:x3; val_offset:136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x255707;
-   valaddr_reg:x3; val_offset:138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x5b76ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x405b76ec; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5b76ec and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x405b76ec;
-   valaddr_reg:x3; val_offset:146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5b76ec and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x405b76ec;
-   valaddr_reg:x3; val_offset:148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfa and fm2 == 0x183299 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7d183299;
-   valaddr_reg:x3; val_offset:154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3435dc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0x7f3435dc;
-   valaddr_reg:x3; val_offset:160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 0 and fe2 == 0xfa and fm2 == 0x183299 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0x7d183299;
-   valaddr_reg:x3; val_offset:162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x183299 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7d183299;
-   valaddr_reg:x3; val_offset:178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x522917 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0xfed22917;
-   valaddr_reg:x3; val_offset:196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 0 and fe2 == 0xfa and fm2 == 0x183299 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0x7d183299;
-   valaddr_reg:x3; val_offset:198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0dc4a8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xdc4a8;
-   valaddr_reg:x3; val_offset:206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0dc4a8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0xdc4a8;
-   valaddr_reg:x3; val_offset:210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44f00b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x7f44f00b;
-   valaddr_reg:x3; val_offset:222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0dc4a8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0xdc4a8;
-   valaddr_reg:x3; val_offset:224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0dc4a8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xdc4a8;
-   valaddr_reg:x3; val_offset:236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x3ad75a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0xfebad75a;
-   valaddr_reg:x3; val_offset:242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0dc4a8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0xdc4a8;
-   valaddr_reg:x3; val_offset:244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7ad07d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0xff7ad07d;
-   valaddr_reg:x3; val_offset:250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0dc4a8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0xdc4a8;
-   valaddr_reg:x3; val_offset:252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x76411d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0xfef6411d;
-   valaddr_reg:x3; val_offset:258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0dc4a8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0xdc4a8;
-   valaddr_reg:x3; val_offset:260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x21d824 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3fa1d824; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x21d824 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x3fa1d824;
-   valaddr_reg:x3; val_offset:272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x7f and fm2 == 0x21d824 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x3fa1d824;
-   valaddr_reg:x3; val_offset:274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3435dc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x7f3435dc;
-   valaddr_reg:x3; val_offset:282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 0 and fe2 == 0xfa and fm2 == 0x6a2c24 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0x7d6a2c24;
-   valaddr_reg:x3; val_offset:286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3435dc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0x7f3435dc;
-   valaddr_reg:x3; val_offset:288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 1 and fe2 == 0xfa and fm2 == 0x291dc8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0xfd291dc8;
-   valaddr_reg:x3; val_offset:302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3435dc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0x7f3435dc;
-   valaddr_reg:x3; val_offset:304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 1 and fe2 == 0xfb and fm2 == 0x153eee and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0xfd953eee;
-   valaddr_reg:x3; val_offset:310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3435dc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0x7f3435dc;
-   valaddr_reg:x3; val_offset:312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 1 and fe2 == 0xfb and fm2 == 0x1946c8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0xfd9946c8;
-   valaddr_reg:x3; val_offset:318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3435dc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0x7f3435dc;
-   valaddr_reg:x3; val_offset:320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x07167c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x7e07167c;
-   valaddr_reg:x3; val_offset:330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x667e2a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x7de67e2a;
-   valaddr_reg:x3; val_offset:340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x13d219 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x7e13d219;
-   valaddr_reg:x3; val_offset:348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d8cd6 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x7d9d8cd6;
-   valaddr_reg:x3; val_offset:356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x1f6f2f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x7e1f6f2f;
-   valaddr_reg:x3; val_offset:364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03c146 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0xfe03c146;
-   valaddr_reg:x3; val_offset:372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x157915 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0xfd157915;
-   valaddr_reg:x3; val_offset:380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x48a6ca and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0xfdc8a6ca;
-   valaddr_reg:x3; val_offset:388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x4500e4 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0xfd4500e4;
-   valaddr_reg:x3; val_offset:396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2b7553 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0xfe2b7553;
-   valaddr_reg:x3; val_offset:404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x194e59 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40194e59; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x194e59 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40194e59;
-   valaddr_reg:x3; val_offset:414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x194e59 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x40194e59;
-   valaddr_reg:x3; val_offset:416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfa and fm2 == 0x6a2c24 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7d6a2c24;
-   valaddr_reg:x3; val_offset:422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x6a2c24 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7d6a2c24;
-   valaddr_reg:x3; val_offset:438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x522917 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0xfed22917;
-   valaddr_reg:x3; val_offset:456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 0 and fe2 == 0xfa and fm2 == 0x6a2c24 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0x7d6a2c24;
-   valaddr_reg:x3; val_offset:458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x152f10 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x152f10;
-   valaddr_reg:x3; val_offset:466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x152f10 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x152f10;
-   valaddr_reg:x3; val_offset:470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44f00b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x7f44f00b;
-   valaddr_reg:x3; val_offset:482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x152f10 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0x152f10;
-   valaddr_reg:x3; val_offset:484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x152f10 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x152f10;
-   valaddr_reg:x3; val_offset:496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x3ad75a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0xfebad75a;
-   valaddr_reg:x3; val_offset:502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x152f10 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0x152f10;
-   valaddr_reg:x3; val_offset:504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7ad07d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0xff7ad07d;
-   valaddr_reg:x3; val_offset:510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x152f10 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0x152f10;
-   valaddr_reg:x3; val_offset:512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x76411d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0xfef6411d;
-   valaddr_reg:x3; val_offset:518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x152f10 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0x152f10;
-   valaddr_reg:x3; val_offset:520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x7903cc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3ff903cc; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7903cc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x3ff903cc;
-   valaddr_reg:x3; val_offset:532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7903cc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x3ff903cc;
-   valaddr_reg:x3; val_offset:534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x07167c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x7e07167c;
-   valaddr_reg:x3; val_offset:560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x667e2a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x7de67e2a;
-   valaddr_reg:x3; val_offset:570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x13d219 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x7e13d219;
-   valaddr_reg:x3; val_offset:578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d8cd6 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x7d9d8cd6;
-   valaddr_reg:x3; val_offset:586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x1f6f2f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x7e1f6f2f;
-   valaddr_reg:x3; val_offset:594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03c146 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0xfe03c146;
-   valaddr_reg:x3; val_offset:602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x157915 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0xfd157915;
-   valaddr_reg:x3; val_offset:610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x48a6ca and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0xfdc8a6ca;
-   valaddr_reg:x3; val_offset:618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x4500e4 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0xfd4500e4;
-   valaddr_reg:x3; val_offset:626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2b7553 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0xfe2b7553;
-   valaddr_reg:x3; val_offset:634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x3ad332 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40bad332; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3ad332 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40bad332;
-   valaddr_reg:x3; val_offset:644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3ad332 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x40bad332;
-   valaddr_reg:x3; val_offset:646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x291dc8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfd291dc8;
-   valaddr_reg:x3; val_offset:662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x153eee and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfd953eee;
-   valaddr_reg:x3; val_offset:670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x1946c8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfd9946c8;
-   valaddr_reg:x3; val_offset:678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x07167c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x7e07167c;
-   valaddr_reg:x3; val_offset:690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x667e2a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x7de67e2a;
-   valaddr_reg:x3; val_offset:700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x13d219 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x7e13d219;
-   valaddr_reg:x3; val_offset:708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d8cd6 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x7d9d8cd6;
-   valaddr_reg:x3; val_offset:716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x1f6f2f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x7e1f6f2f;
-   valaddr_reg:x3; val_offset:724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03c146 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0xfe03c146;
-   valaddr_reg:x3; val_offset:732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x157915 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0xfd157915;
-   valaddr_reg:x3; val_offset:740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x48a6ca and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0xfdc8a6ca;
-   valaddr_reg:x3; val_offset:748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x4500e4 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0xfd4500e4;
-   valaddr_reg:x3; val_offset:756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2b7553 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0xfe2b7553;
-   valaddr_reg:x3; val_offset:764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 1 and fe1 == 0x80 and fm1 == 0x7931e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc07931e5; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x7931e5 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc07931e5;
-   valaddr_reg:x3; val_offset:774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x7931e5 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0xc07931e5;
-   valaddr_reg:x3; val_offset:776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0xfa and fm2 == 0x291dc8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0xfd291dc8;
-   valaddr_reg:x3; val_offset:782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x522917 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0xfed22917;
-   valaddr_reg:x3; val_offset:808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x291dc8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0xfd291dc8;
-   valaddr_reg:x3; val_offset:810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f4c77 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x800f4c77;
-   valaddr_reg:x3; val_offset:818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f4c77 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x800f4c77;
-   valaddr_reg:x3; val_offset:822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44f00b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x7f44f00b;
-   valaddr_reg:x3; val_offset:834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f4c77 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0x800f4c77;
-   valaddr_reg:x3; val_offset:836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f4c77 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x800f4c77;
-   valaddr_reg:x3; val_offset:848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x3ad75a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0xfebad75a;
-   valaddr_reg:x3; val_offset:854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f4c77 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0x800f4c77;
-   valaddr_reg:x3; val_offset:856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7ad07d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0xff7ad07d;
-   valaddr_reg:x3; val_offset:862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f4c77 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0x800f4c77;
-   valaddr_reg:x3; val_offset:864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x76411d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0xfef6411d;
-   valaddr_reg:x3; val_offset:870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f4c77 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0x800f4c77;
-   valaddr_reg:x3; val_offset:872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x33d5d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbfb3d5d8; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x33d5d8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xbfb3d5d8;
-   valaddr_reg:x3; val_offset:884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0x7f and fm2 == 0x33d5d8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0xbfb3d5d8;
-   valaddr_reg:x3; val_offset:886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x153eee and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0xfd953eee;
-   valaddr_reg:x3; val_offset:892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 1 and fe2 == 0xfd and fm2 == 0x522917 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0xfed22917;
-   valaddr_reg:x3; val_offset:914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x153eee and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0xfd953eee;
-   valaddr_reg:x3; val_offset:916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0098 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x801b0098;
-   valaddr_reg:x3; val_offset:924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0098 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x801b0098;
-   valaddr_reg:x3; val_offset:928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44f00b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x7f44f00b;
-   valaddr_reg:x3; val_offset:940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0098 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0x801b0098;
-   valaddr_reg:x3; val_offset:942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0098 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x801b0098;
-   valaddr_reg:x3; val_offset:954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x3ad75a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0xfebad75a;
-   valaddr_reg:x3; val_offset:960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0098 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0x801b0098;
-   valaddr_reg:x3; val_offset:962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7ad07d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0xff7ad07d;
-   valaddr_reg:x3; val_offset:968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0098 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0x801b0098;
-   valaddr_reg:x3; val_offset:970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x76411d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0xfef6411d;
-   valaddr_reg:x3; val_offset:976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0098 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0x801b0098;
-   valaddr_reg:x3; val_offset:978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 1 and fe1 == 0x80 and fm1 == 0x1eb493 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc01eb493; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x1eb493 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc01eb493;
-   valaddr_reg:x3; val_offset:990*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x1eb493 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0xc01eb493;
-   valaddr_reg:x3; val_offset:992*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:994*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:996*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x1946c8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0xfd9946c8;
-   valaddr_reg:x3; val_offset:998*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1000*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1002*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1004*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1006*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1008*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1010*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1012*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1014*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x522917 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0xfed22917;
-   valaddr_reg:x3; val_offset:1016*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x1946c8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0xfd9946c8;
-   valaddr_reg:x3; val_offset:1018*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1020*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1022*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1024*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1bbb48 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x801bbb48;
-   valaddr_reg:x3; val_offset:1026*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1028*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1bbb48 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x801bbb48;
-   valaddr_reg:x3; val_offset:1030*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1032*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1034*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1036*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1038*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1040*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44f00b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x7f44f00b;
-   valaddr_reg:x3; val_offset:1042*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1bbb48 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0x801bbb48;
-   valaddr_reg:x3; val_offset:1044*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1046*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1048*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1050*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1052*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1054*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1bbb48 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x801bbb48;
-   valaddr_reg:x3; val_offset:1056*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1058*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1060*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x3ad75a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0xfebad75a;
-   valaddr_reg:x3; val_offset:1062*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1bbb48 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0x801bbb48;
-   valaddr_reg:x3; val_offset:1064*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1066*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1068*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7ad07d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0xff7ad07d;
-   valaddr_reg:x3; val_offset:1070*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1bbb48 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0x801bbb48;
-   valaddr_reg:x3; val_offset:1072*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1074*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1076*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x76411d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0xfef6411d;
-   valaddr_reg:x3; val_offset:1078*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1bbb48 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0x801bbb48;
-   valaddr_reg:x3; val_offset:1080*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1082*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1084*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1086*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1088*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 1 and fe1 == 0x80 and fm1 == 0x22fdd5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc022fdd5; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1090*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x22fdd5 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc022fdd5;
-   valaddr_reg:x3; val_offset:1092*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x22fdd5 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0xc022fdd5;
-   valaddr_reg:x3; val_offset:1094*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1096*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1098*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0xfd and fm2 == 0x522917 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0xfed22917;
-   valaddr_reg:x3; val_offset:1102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x07167c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x7e07167c;
-   valaddr_reg:x3; val_offset:1122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x667e2a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x7de67e2a;
-   valaddr_reg:x3; val_offset:1132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x13d219 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x7e13d219;
-   valaddr_reg:x3; val_offset:1140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d8cd6 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x7d9d8cd6;
-   valaddr_reg:x3; val_offset:1148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-
-inst_578:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x1f6f2f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x7e1f6f2f;
-   valaddr_reg:x3; val_offset:1156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1156*FLEN/8, x4, x1, x2)
-
-inst_579:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1158*FLEN/8, x4, x1, x2)
-
-inst_580:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1160*FLEN/8, x4, x1, x2)
-
-inst_581:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1162*FLEN/8, x4, x1, x2)
-
-inst_582:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03c146 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0xfe03c146;
-   valaddr_reg:x3; val_offset:1164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1164*FLEN/8, x4, x1, x2)
-
-inst_583:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1166*FLEN/8, x4, x1, x2)
-
-inst_584:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1168*FLEN/8, x4, x1, x2)
-
-inst_585:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1170*FLEN/8, x4, x1, x2)
-
-inst_586:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x157915 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0xfd157915;
-   valaddr_reg:x3; val_offset:1172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1172*FLEN/8, x4, x1, x2)
-
-inst_587:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1174*FLEN/8, x4, x1, x2)
-
-inst_588:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1176*FLEN/8, x4, x1, x2)
-
-inst_589:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1178*FLEN/8, x4, x1, x2)
-
-inst_590:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x48a6ca and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0xfdc8a6ca;
-   valaddr_reg:x3; val_offset:1180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1180*FLEN/8, x4, x1, x2)
-
-inst_591:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1182*FLEN/8, x4, x1, x2)
-
-inst_592:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1184*FLEN/8, x4, x1, x2)
-
-inst_593:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1186*FLEN/8, x4, x1, x2)
-
-inst_594:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x4500e4 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0xfd4500e4;
-   valaddr_reg:x3; val_offset:1188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1188*FLEN/8, x4, x1, x2)
-
-inst_595:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1190*FLEN/8, x4, x1, x2)
-
-inst_596:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1192*FLEN/8, x4, x1, x2)
-
-inst_597:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1194*FLEN/8, x4, x1, x2)
-
-inst_598:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2b7553 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0xfe2b7553;
-   valaddr_reg:x3; val_offset:1196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1196*FLEN/8, x4, x1, x2)
-
-inst_599:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1198*FLEN/8, x4, x1, x2)
-
-inst_600:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1200*FLEN/8, x4, x1, x2)
-
-inst_601:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1202*FLEN/8, x4, x1, x2)
-
-inst_602:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x32c8e8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbfb2c8e8; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1204*FLEN/8, x4, x1, x2)
-
-inst_603:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x32c8e8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xbfb2c8e8;
-   valaddr_reg:x3; val_offset:1206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1206*FLEN/8, x4, x1, x2)
-
-inst_604:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0x7f and fm2 == 0x32c8e8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0xbfb2c8e8;
-   valaddr_reg:x3; val_offset:1208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1208*FLEN/8, x4, x1, x2)
-
-inst_605:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1210*FLEN/8, x4, x1, x2)
-
-inst_606:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1212*FLEN/8, x4, x1, x2)
-
-inst_607:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0xfc and fm2 == 0x07167c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7e07167c;
-   valaddr_reg:x3; val_offset:1214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1214*FLEN/8, x4, x1, x2)
-
-inst_608:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1216*FLEN/8, x4, x1, x2)
-
-inst_609:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1218*FLEN/8, x4, x1, x2)
-
-inst_610:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1220*FLEN/8, x4, x1, x2)
-
-inst_611:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1222*FLEN/8, x4, x1, x2)
-
-inst_612:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1224*FLEN/8, x4, x1, x2)
-
-inst_613:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1226*FLEN/8, x4, x1, x2)
-
-inst_614:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1228*FLEN/8, x4, x1, x2)
-
-inst_615:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1230*FLEN/8, x4, x1, x2)
-
-inst_616:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1232*FLEN/8, x4, x1, x2)
-
-inst_617:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1234*FLEN/8, x4, x1, x2)
-
-inst_618:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1236*FLEN/8, x4, x1, x2)
-
-inst_619:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1238*FLEN/8, x4, x1, x2)
-
-inst_620:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1240*FLEN/8, x4, x1, x2)
-
-inst_621:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1242*FLEN/8, x4, x1, x2)
-
-inst_622:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1244*FLEN/8, x4, x1, x2)
-
-inst_623:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1246*FLEN/8, x4, x1, x2)
-
-inst_624:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1248*FLEN/8, x4, x1, x2)
-
-inst_625:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1250*FLEN/8, x4, x1, x2)
-
-inst_626:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1252*FLEN/8, x4, x1, x2)
-
-inst_627:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1254*FLEN/8, x4, x1, x2)
-
-inst_628:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1256*FLEN/8, x4, x1, x2)
-
-inst_629:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1258*FLEN/8, x4, x1, x2)
-
-inst_630:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1260*FLEN/8, x4, x1, x2)
-
-inst_631:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1262*FLEN/8, x4, x1, x2)
-
-inst_632:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1264*FLEN/8, x4, x1, x2)
-
-inst_633:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1266*FLEN/8, x4, x1, x2)
-
-inst_634:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1268*FLEN/8, x4, x1, x2)
-
-inst_635:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1270*FLEN/8, x4, x1, x2)
-
-inst_636:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1272*FLEN/8, x4, x1, x2)
-
-inst_637:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1274*FLEN/8, x4, x1, x2)
-
-inst_638:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1276*FLEN/8, x4, x1, x2)
-
-inst_639:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1278*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_6)
-
-inst_640:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1280*FLEN/8, x4, x1, x2)
-
-inst_641:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1282*FLEN/8, x4, x1, x2)
-
-inst_642:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x0fa668 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x408fa668; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1284*FLEN/8, x4, x1, x2)
-
-inst_643:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0fa668 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x408fa668;
-   valaddr_reg:x3; val_offset:1286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1286*FLEN/8, x4, x1, x2)
-
-inst_644:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0fa668 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x408fa668;
-   valaddr_reg:x3; val_offset:1288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1288*FLEN/8, x4, x1, x2)
-
-inst_645:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1290*FLEN/8, x4, x1, x2)
-
-inst_646:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1292*FLEN/8, x4, x1, x2)
-
-inst_647:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x667e2a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7de67e2a;
-   valaddr_reg:x3; val_offset:1294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1294*FLEN/8, x4, x1, x2)
-
-inst_648:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1296*FLEN/8, x4, x1, x2)
-
-inst_649:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1298*FLEN/8, x4, x1, x2)
-
-inst_650:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1300*FLEN/8, x4, x1, x2)
-
-inst_651:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1302*FLEN/8, x4, x1, x2)
-
-inst_652:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1304*FLEN/8, x4, x1, x2)
-
-inst_653:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1306*FLEN/8, x4, x1, x2)
-
-inst_654:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1308*FLEN/8, x4, x1, x2)
-
-inst_655:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1310*FLEN/8, x4, x1, x2)
-
-inst_656:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1312*FLEN/8, x4, x1, x2)
-
-inst_657:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1314*FLEN/8, x4, x1, x2)
-
-inst_658:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1316*FLEN/8, x4, x1, x2)
-
-inst_659:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1318*FLEN/8, x4, x1, x2)
-
-inst_660:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1320*FLEN/8, x4, x1, x2)
-
-inst_661:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1322*FLEN/8, x4, x1, x2)
-
-inst_662:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1324*FLEN/8, x4, x1, x2)
-
-inst_663:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1326*FLEN/8, x4, x1, x2)
-
-inst_664:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1328*FLEN/8, x4, x1, x2)
-
-inst_665:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1330*FLEN/8, x4, x1, x2)
-
-inst_666:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1332*FLEN/8, x4, x1, x2)
-
-inst_667:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1334*FLEN/8, x4, x1, x2)
-
-inst_668:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1336*FLEN/8, x4, x1, x2)
-
-inst_669:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1338*FLEN/8, x4, x1, x2)
-
-inst_670:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1340*FLEN/8, x4, x1, x2)
-
-inst_671:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1342*FLEN/8, x4, x1, x2)
-
-inst_672:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1344*FLEN/8, x4, x1, x2)
-
-inst_673:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1346*FLEN/8, x4, x1, x2)
-
-inst_674:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1348*FLEN/8, x4, x1, x2)
-
-inst_675:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1350*FLEN/8, x4, x1, x2)
-
-inst_676:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1352*FLEN/8, x4, x1, x2)
-
-inst_677:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1354*FLEN/8, x4, x1, x2)
-
-inst_678:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1356*FLEN/8, x4, x1, x2)
-
-inst_679:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1358*FLEN/8, x4, x1, x2)
-
-inst_680:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x751a1e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40751a1e; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1360*FLEN/8, x4, x1, x2)
-
-inst_681:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x751a1e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40751a1e;
-   valaddr_reg:x3; val_offset:1362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1362*FLEN/8, x4, x1, x2)
-
-inst_682:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x751a1e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x40751a1e;
-   valaddr_reg:x3; val_offset:1364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1364*FLEN/8, x4, x1, x2)
-
-inst_683:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1366*FLEN/8, x4, x1, x2)
-
-inst_684:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1368*FLEN/8, x4, x1, x2)
-
-inst_685:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x13d219 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7e13d219;
-   valaddr_reg:x3; val_offset:1370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1370*FLEN/8, x4, x1, x2)
-
-inst_686:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1372*FLEN/8, x4, x1, x2)
-
-inst_687:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1374*FLEN/8, x4, x1, x2)
-
-inst_688:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1376*FLEN/8, x4, x1, x2)
-
-inst_689:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1378*FLEN/8, x4, x1, x2)
-
-inst_690:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1380*FLEN/8, x4, x1, x2)
-
-inst_691:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1382*FLEN/8, x4, x1, x2)
-
-inst_692:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1384*FLEN/8, x4, x1, x2)
-
-inst_693:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1386*FLEN/8, x4, x1, x2)
-
-inst_694:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1388*FLEN/8, x4, x1, x2)
-
-inst_695:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1390*FLEN/8, x4, x1, x2)
-
-inst_696:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1392*FLEN/8, x4, x1, x2)
-
-inst_697:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1394*FLEN/8, x4, x1, x2)
-
-inst_698:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1396*FLEN/8, x4, x1, x2)
-
-inst_699:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1398*FLEN/8, x4, x1, x2)
-
-inst_700:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1400*FLEN/8, x4, x1, x2)
-
-inst_701:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1402*FLEN/8, x4, x1, x2)
-
-inst_702:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1404*FLEN/8, x4, x1, x2)
-
-inst_703:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1406*FLEN/8, x4, x1, x2)
-
-inst_704:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1408*FLEN/8, x4, x1, x2)
-
-inst_705:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1410*FLEN/8, x4, x1, x2)
-
-inst_706:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1412*FLEN/8, x4, x1, x2)
-
-inst_707:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1414*FLEN/8, x4, x1, x2)
-
-inst_708:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1416*FLEN/8, x4, x1, x2)
-
-inst_709:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1418*FLEN/8, x4, x1, x2)
-
-inst_710:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1420*FLEN/8, x4, x1, x2)
-
-inst_711:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1422*FLEN/8, x4, x1, x2)
-
-inst_712:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1424*FLEN/8, x4, x1, x2)
-
-inst_713:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1426*FLEN/8, x4, x1, x2)
-
-inst_714:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1428*FLEN/8, x4, x1, x2)
-
-inst_715:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1430*FLEN/8, x4, x1, x2)
-
-inst_716:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x1d309f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x409d309f; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1432*FLEN/8, x4, x1, x2)
-
-inst_717:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x1d309f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x409d309f;
-   valaddr_reg:x3; val_offset:1434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1434*FLEN/8, x4, x1, x2)
-
-inst_718:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0x81 and fm2 == 0x1d309f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x409d309f;
-   valaddr_reg:x3; val_offset:1436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1436*FLEN/8, x4, x1, x2)
-
-inst_719:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1438*FLEN/8, x4, x1, x2)
-
-inst_720:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1440*FLEN/8, x4, x1, x2)
-
-inst_721:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d8cd6 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7d9d8cd6;
-   valaddr_reg:x3; val_offset:1442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1442*FLEN/8, x4, x1, x2)
-
-inst_722:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1444*FLEN/8, x4, x1, x2)
-
-inst_723:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1446*FLEN/8, x4, x1, x2)
-
-inst_724:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1448*FLEN/8, x4, x1, x2)
-
-inst_725:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44f00b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7f44f00b;
-   valaddr_reg:x3; val_offset:1450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1450*FLEN/8, x4, x1, x2)
-
-inst_726:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1452*FLEN/8, x4, x1, x2)
-
-inst_727:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1454*FLEN/8, x4, x1, x2)
-
-inst_728:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1456*FLEN/8, x4, x1, x2)
-
-inst_729:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1458*FLEN/8, x4, x1, x2)
-
-inst_730:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1460*FLEN/8, x4, x1, x2)
-
-inst_731:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1462*FLEN/8, x4, x1, x2)
-
-inst_732:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1464*FLEN/8, x4, x1, x2)
-
-inst_733:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1466*FLEN/8, x4, x1, x2)
-
-inst_734:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1468*FLEN/8, x4, x1, x2)
-
-inst_735:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1470*FLEN/8, x4, x1, x2)
-
-inst_736:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1472*FLEN/8, x4, x1, x2)
-
-inst_737:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1474*FLEN/8, x4, x1, x2)
-
-inst_738:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1476*FLEN/8, x4, x1, x2)
-
-inst_739:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1478*FLEN/8, x4, x1, x2)
-
-inst_740:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1480*FLEN/8, x4, x1, x2)
-
-inst_741:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1482*FLEN/8, x4, x1, x2)
-
-inst_742:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1484*FLEN/8, x4, x1, x2)
-
-inst_743:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1486*FLEN/8, x4, x1, x2)
-
-inst_744:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1488*FLEN/8, x4, x1, x2)
-
-inst_745:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1490*FLEN/8, x4, x1, x2)
-
-inst_746:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1492*FLEN/8, x4, x1, x2)
-
-inst_747:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1494*FLEN/8, x4, x1, x2)
-
-inst_748:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1496*FLEN/8, x4, x1, x2)
-
-inst_749:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1498*FLEN/8, x4, x1, x2)
-
-inst_750:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1500*FLEN/8, x4, x1, x2)
-
-inst_751:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1502*FLEN/8, x4, x1, x2)
-
-inst_752:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1504*FLEN/8, x4, x1, x2)
-
-inst_753:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1506*FLEN/8, x4, x1, x2)
-
-inst_754:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1508*FLEN/8, x4, x1, x2)
-
-inst_755:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x27893a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4027893a; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1510*FLEN/8, x4, x1, x2)
-
-inst_756:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27893a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x4027893a;
-   valaddr_reg:x3; val_offset:1512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1512*FLEN/8, x4, x1, x2)
-
-inst_757:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27893a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x4027893a;
-   valaddr_reg:x3; val_offset:1514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1514*FLEN/8, x4, x1, x2)
-
-inst_758:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1516*FLEN/8, x4, x1, x2)
-
-inst_759:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1518*FLEN/8, x4, x1, x2)
-
-inst_760:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0xfc and fm2 == 0x1f6f2f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7e1f6f2f;
-   valaddr_reg:x3; val_offset:1520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1520*FLEN/8, x4, x1, x2)
-
-inst_761:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1522*FLEN/8, x4, x1, x2)
-
-inst_762:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1524*FLEN/8, x4, x1, x2)
-
-inst_763:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1526*FLEN/8, x4, x1, x2)
-
-inst_764:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1528*FLEN/8, x4, x1, x2)
-
-inst_765:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1530*FLEN/8, x4, x1, x2)
-
-inst_766:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1532*FLEN/8, x4, x1, x2)
-
-inst_767:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1534*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_7)
-
-inst_768:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1536*FLEN/8, x4, x1, x2)
-
-inst_769:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1538*FLEN/8, x4, x1, x2)
-
-inst_770:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1540*FLEN/8, x4, x1, x2)
-
-inst_771:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1542*FLEN/8, x4, x1, x2)
-
-inst_772:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1544*FLEN/8, x4, x1, x2)
-
-inst_773:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1546*FLEN/8, x4, x1, x2)
-
-inst_774:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1548*FLEN/8, x4, x1, x2)
-
-inst_775:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1550*FLEN/8, x4, x1, x2)
-
-inst_776:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1552*FLEN/8, x4, x1, x2)
-
-inst_777:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1554*FLEN/8, x4, x1, x2)
-
-inst_778:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1556*FLEN/8, x4, x1, x2)
-
-inst_779:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1558*FLEN/8, x4, x1, x2)
-
-inst_780:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1560*FLEN/8, x4, x1, x2)
-
-inst_781:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1562*FLEN/8, x4, x1, x2)
-
-inst_782:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1564*FLEN/8, x4, x1, x2)
-
-inst_783:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1566*FLEN/8, x4, x1, x2)
-
-inst_784:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1568*FLEN/8, x4, x1, x2)
-
-inst_785:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1570*FLEN/8, x4, x1, x2)
-
-inst_786:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1572*FLEN/8, x4, x1, x2)
-
-inst_787:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x298a26 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40a98a26; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1574*FLEN/8, x4, x1, x2)
-
-inst_788:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x298a26 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40a98a26;
-   valaddr_reg:x3; val_offset:1576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1576*FLEN/8, x4, x1, x2)
-
-inst_789:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x298a26 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x40a98a26;
-   valaddr_reg:x3; val_offset:1578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1578*FLEN/8, x4, x1, x2)
-
-inst_790:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1580*FLEN/8, x4, x1, x2)
-
-inst_791:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1582*FLEN/8, x4, x1, x2)
-
-inst_792:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03c146 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xfe03c146;
-   valaddr_reg:x3; val_offset:1584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1584*FLEN/8, x4, x1, x2)
-
-inst_793:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1586*FLEN/8, x4, x1, x2)
-
-inst_794:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1588*FLEN/8, x4, x1, x2)
-
-inst_795:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1590*FLEN/8, x4, x1, x2)
-
-inst_796:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1592*FLEN/8, x4, x1, x2)
-
-inst_797:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1594*FLEN/8, x4, x1, x2)
-
-inst_798:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1596*FLEN/8, x4, x1, x2)
-
-inst_799:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1598*FLEN/8, x4, x1, x2)
-
-inst_800:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1600*FLEN/8, x4, x1, x2)
-
-inst_801:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1602*FLEN/8, x4, x1, x2)
-
-inst_802:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1604*FLEN/8, x4, x1, x2)
-
-inst_803:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1606*FLEN/8, x4, x1, x2)
-
-inst_804:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1608*FLEN/8, x4, x1, x2)
-
-inst_805:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1610*FLEN/8, x4, x1, x2)
-
-inst_806:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1612*FLEN/8, x4, x1, x2)
-
-inst_807:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1614*FLEN/8, x4, x1, x2)
-
-inst_808:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1616*FLEN/8, x4, x1, x2)
-
-inst_809:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1618*FLEN/8, x4, x1, x2)
-
-inst_810:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1620*FLEN/8, x4, x1, x2)
-
-inst_811:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1622*FLEN/8, x4, x1, x2)
-
-inst_812:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1624*FLEN/8, x4, x1, x2)
-
-inst_813:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1626*FLEN/8, x4, x1, x2)
-
-inst_814:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1628*FLEN/8, x4, x1, x2)
-
-inst_815:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1630*FLEN/8, x4, x1, x2)
-
-inst_816:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1632*FLEN/8, x4, x1, x2)
-
-inst_817:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x0c1b1e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc08c1b1e; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1634*FLEN/8, x4, x1, x2)
-
-inst_818:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0c1b1e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc08c1b1e;
-   valaddr_reg:x3; val_offset:1636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1636*FLEN/8, x4, x1, x2)
-
-inst_819:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0c1b1e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xc08c1b1e;
-   valaddr_reg:x3; val_offset:1638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1638*FLEN/8, x4, x1, x2)
-
-inst_820:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1640*FLEN/8, x4, x1, x2)
-
-inst_821:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1642*FLEN/8, x4, x1, x2)
-
-inst_822:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x157915 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xfd157915;
-   valaddr_reg:x3; val_offset:1644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1644*FLEN/8, x4, x1, x2)
-
-inst_823:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1646*FLEN/8, x4, x1, x2)
-
-inst_824:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1648*FLEN/8, x4, x1, x2)
-
-inst_825:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1650*FLEN/8, x4, x1, x2)
-
-inst_826:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x3ad75a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xfebad75a;
-   valaddr_reg:x3; val_offset:1652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1652*FLEN/8, x4, x1, x2)
-
-inst_827:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1654*FLEN/8, x4, x1, x2)
-
-inst_828:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1656*FLEN/8, x4, x1, x2)
-
-inst_829:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1658*FLEN/8, x4, x1, x2)
-
-inst_830:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1660*FLEN/8, x4, x1, x2)
-
-inst_831:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1662*FLEN/8, x4, x1, x2)
-
-inst_832:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1664*FLEN/8, x4, x1, x2)
-
-inst_833:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1666*FLEN/8, x4, x1, x2)
-
-inst_834:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1668*FLEN/8, x4, x1, x2)
-
-inst_835:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1670*FLEN/8, x4, x1, x2)
-
-inst_836:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1672*FLEN/8, x4, x1, x2)
-
-inst_837:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1674*FLEN/8, x4, x1, x2)
-
-inst_838:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1676*FLEN/8, x4, x1, x2)
-
-inst_839:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1678*FLEN/8, x4, x1, x2)
-
-inst_840:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1680*FLEN/8, x4, x1, x2)
-
-inst_841:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1682*FLEN/8, x4, x1, x2)
-
-inst_842:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1684*FLEN/8, x4, x1, x2)
-
-inst_843:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1686*FLEN/8, x4, x1, x2)
-
-inst_844:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1688*FLEN/8, x4, x1, x2)
-
-inst_845:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1690*FLEN/8, x4, x1, x2)
-
-inst_846:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1692*FLEN/8, x4, x1, x2)
-
-inst_847:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1694*FLEN/8, x4, x1, x2)
-
-inst_848:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1696*FLEN/8, x4, x1, x2)
-
-inst_849:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1698*FLEN/8, x4, x1, x2)
-
-inst_850:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x1ef26a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf9ef26a; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1700*FLEN/8, x4, x1, x2)
-
-inst_851:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x1ef26a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xbf9ef26a;
-   valaddr_reg:x3; val_offset:1702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1702*FLEN/8, x4, x1, x2)
-
-inst_852:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0x7f and fm2 == 0x1ef26a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xbf9ef26a;
-   valaddr_reg:x3; val_offset:1704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1704*FLEN/8, x4, x1, x2)
-
-inst_853:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1706*FLEN/8, x4, x1, x2)
-
-inst_854:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1708*FLEN/8, x4, x1, x2)
-
-inst_855:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x48a6ca and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xfdc8a6ca;
-   valaddr_reg:x3; val_offset:1710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1710*FLEN/8, x4, x1, x2)
-
-inst_856:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1712*FLEN/8, x4, x1, x2)
-
-inst_857:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1714*FLEN/8, x4, x1, x2)
-
-inst_858:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1716*FLEN/8, x4, x1, x2)
-
-inst_859:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7ad07d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xff7ad07d;
-   valaddr_reg:x3; val_offset:1718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1718*FLEN/8, x4, x1, x2)
-
-inst_860:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1720*FLEN/8, x4, x1, x2)
-
-inst_861:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1722*FLEN/8, x4, x1, x2)
-
-inst_862:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1724*FLEN/8, x4, x1, x2)
-
-inst_863:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1726*FLEN/8, x4, x1, x2)
-
-inst_864:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1728*FLEN/8, x4, x1, x2)
-
-inst_865:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1730*FLEN/8, x4, x1, x2)
-
-inst_866:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1732*FLEN/8, x4, x1, x2)
-
-inst_867:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1734*FLEN/8, x4, x1, x2)
-
-inst_868:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1736*FLEN/8, x4, x1, x2)
-
-inst_869:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1738*FLEN/8, x4, x1, x2)
-
-inst_870:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1740*FLEN/8, x4, x1, x2)
-
-inst_871:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1742*FLEN/8, x4, x1, x2)
-
-inst_872:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1744*FLEN/8, x4, x1, x2)
-
-inst_873:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1746*FLEN/8, x4, x1, x2)
-
-inst_874:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1748*FLEN/8, x4, x1, x2)
-
-inst_875:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1750*FLEN/8, x4, x1, x2)
-
-inst_876:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1752*FLEN/8, x4, x1, x2)
-
-inst_877:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1754*FLEN/8, x4, x1, x2)
-
-inst_878:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1756*FLEN/8, x4, x1, x2)
-
-inst_879:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1758*FLEN/8, x4, x1, x2)
-
-inst_880:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1760*FLEN/8, x4, x1, x2)
-
-inst_881:
-// fs1 == 1 and fe1 == 0x80 and fm1 == 0x555e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc0555e8a; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1762*FLEN/8, x4, x1, x2)
-
-inst_882:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x555e8a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc0555e8a;
-   valaddr_reg:x3; val_offset:1764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1764*FLEN/8, x4, x1, x2)
-
-inst_883:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x555e8a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xc0555e8a;
-   valaddr_reg:x3; val_offset:1766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1766*FLEN/8, x4, x1, x2)
-
-inst_884:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1768*FLEN/8, x4, x1, x2)
-
-inst_885:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1770*FLEN/8, x4, x1, x2)
-
-inst_886:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x4500e4 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xfd4500e4;
-   valaddr_reg:x3; val_offset:1772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1772*FLEN/8, x4, x1, x2)
-
-inst_887:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1774*FLEN/8, x4, x1, x2)
-
-inst_888:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1776*FLEN/8, x4, x1, x2)
-
-inst_889:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1778*FLEN/8, x4, x1, x2)
-
-inst_890:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x76411d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xfef6411d;
-   valaddr_reg:x3; val_offset:1780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1780*FLEN/8, x4, x1, x2)
-
-inst_891:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1782*FLEN/8, x4, x1, x2)
-
-inst_892:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1784*FLEN/8, x4, x1, x2)
-
-inst_893:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1786*FLEN/8, x4, x1, x2)
-
-inst_894:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1788*FLEN/8, x4, x1, x2)
-
-inst_895:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1790*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_8)
-
-inst_896:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1792*FLEN/8, x4, x1, x2)
-
-inst_897:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1794*FLEN/8, x4, x1, x2)
-
-inst_898:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1796*FLEN/8, x4, x1, x2)
-
-inst_899:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1798*FLEN/8, x4, x1, x2)
-
-inst_900:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1800*FLEN/8, x4, x1, x2)
-
-inst_901:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1802*FLEN/8, x4, x1, x2)
-
-inst_902:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1804*FLEN/8, x4, x1, x2)
-
-inst_903:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1806*FLEN/8, x4, x1, x2)
-
-inst_904:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1808*FLEN/8, x4, x1, x2)
-
-inst_905:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1810*FLEN/8, x4, x1, x2)
-
-inst_906:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1812*FLEN/8, x4, x1, x2)
-
-inst_907:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1814*FLEN/8, x4, x1, x2)
-
-inst_908:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1816*FLEN/8, x4, x1, x2)
-
-inst_909:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1818*FLEN/8, x4, x1, x2)
-
-inst_910:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x517d72 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbfd17d72; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1820*FLEN/8, x4, x1, x2)
-
-inst_911:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x517d72 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xbfd17d72;
-   valaddr_reg:x3; val_offset:1822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1822*FLEN/8, x4, x1, x2)
-
-inst_912:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x517d72 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xbfd17d72;
-   valaddr_reg:x3; val_offset:1824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1824*FLEN/8, x4, x1, x2)
-
-inst_913:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1826*FLEN/8, x4, x1, x2)
-
-inst_914:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1828*FLEN/8, x4, x1, x2)
-
-inst_915:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2b7553 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xfe2b7553;
-   valaddr_reg:x3; val_offset:1830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1830*FLEN/8, x4, x1, x2)
-
-inst_916:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1832*FLEN/8, x4, x1, x2)
-
-inst_917:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1834*FLEN/8, x4, x1, x2)
-
-inst_918:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1836*FLEN/8, x4, x1, x2)
-
-inst_919:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1838*FLEN/8, x4, x1, x2)
-
-inst_920:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1840*FLEN/8, x4, x1, x2)
-
-inst_921:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1842*FLEN/8, x4, x1, x2)
-
-inst_922:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1844*FLEN/8, x4, x1, x2)
-
-inst_923:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1846*FLEN/8, x4, x1, x2)
-
-inst_924:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1848*FLEN/8, x4, x1, x2)
-
-inst_925:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1850*FLEN/8, x4, x1, x2)
-
-inst_926:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1852*FLEN/8, x4, x1, x2)
-
-inst_927:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1854*FLEN/8, x4, x1, x2)
-
-inst_928:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1856*FLEN/8, x4, x1, x2)
-
-inst_929:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1858*FLEN/8, x4, x1, x2)
-
-inst_930:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1860*FLEN/8, x4, x1, x2)
-
-inst_931:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1862*FLEN/8, x4, x1, x2)
-
-inst_932:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x365363 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc0b65363; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1864*FLEN/8, x4, x1, x2)
-
-inst_933:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x365363 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc0b65363;
-   valaddr_reg:x3; val_offset:1866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1866*FLEN/8, x4, x1, x2)
-
-inst_934:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0x81 and fm2 == 0x365363 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xc0b65363;
-   valaddr_reg:x3; val_offset:1868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1868*FLEN/8, x4, x1, x2)
-
-inst_935:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1870*FLEN/8, x4, x1, x2)
-
-inst_936:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1872*FLEN/8, x4, x1, x2)
-
-inst_937:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1874*FLEN/8, x4, x1, x2)
-
-inst_938:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1876*FLEN/8, x4, x1, x2)
-
-inst_939:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1878*FLEN/8, x4, x1, x2)
-
-inst_940:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1880*FLEN/8, x4, x1, x2)
-
-inst_941:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1882*FLEN/8, x4, x1, x2)
-
-inst_942:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1884*FLEN/8, x4, x1, x2)
-
-inst_943:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1886*FLEN/8, x4, x1, x2)
-
-inst_944:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1888*FLEN/8, x4, x1, x2)
-
-inst_945:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1890*FLEN/8, x4, x1, x2)
-
-inst_946:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1892*FLEN/8, x4, x1, x2)
-
-inst_947:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1894*FLEN/8, x4, x1, x2)
-
-inst_948:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1896*FLEN/8, x4, x1, x2)
-
-inst_949:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1898*FLEN/8, x4, x1, x2)
-
-inst_950:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1900*FLEN/8, x4, x1, x2)
-
-inst_951:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1902*FLEN/8, x4, x1, x2)
-
-inst_952:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1904*FLEN/8, x4, x1, x2)
-
-inst_953:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1906*FLEN/8, x4, x1, x2)
-
-inst_954:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1908*FLEN/8, x4, x1, x2)
-
-inst_955:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1910*FLEN/8, x4, x1, x2)
-
-inst_956:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1912*FLEN/8, x4, x1, x2)
-
-inst_957:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1914*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2104110116,32,FLEN)
-NAN_BOXED(2104110116,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
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-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3226820234,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3226820234,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(3226820234,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4249157860,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(4249157860,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(4277551389,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(4277551389,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(4249157860,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(4277551389,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(4249157860,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(4249157860,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(4277551389,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(4277551389,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(4277551389,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(4249157860,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3218177394,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3218177394,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(3218177394,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4264260947,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(4264260947,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(4264260947,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(4264260947,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(4264260947,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(4264260947,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3233174371,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3233174371,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(3233174371,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3203502,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2732978,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3505452,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1868089,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_7:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_8:
-    .fill 124*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fminm_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fminm_b1-01.S
deleted file mode 100644
index 48d3bab07..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fminm_b1-01.S
+++ /dev/null
@@ -1,5889 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:08:32 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fminm.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fminm.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fminm_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rd != rs2, rs1==f31, rs2==f30, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f31; op2:f30; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rs2 == rd, rs1==f29, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f29; op2:f29; dest:f29; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f29, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs2 == rd != rs1, rs1==f30, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f28; dest:f28; op1val:0x0; op2val:0x1;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f28, f30, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f28, rs2==f31, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f28; op2:f31; dest:f30; op1val:0x0; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f30, f28, f31, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f26; op2:f26; dest:f27; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f27, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f27; op2:f25; dest:f26; op1val:0x0; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f26, f27, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f24; op2:f27; dest:f25; op1val:0x0; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f25, f24, f27, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f25; op2:f23; dest:f24; op1val:0x0; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f24, f25, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f22; op2:f24; dest:f23; op1val:0x0; op2val:0x800000;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f23, f22, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f23; op2:f21; dest:f22; op1val:0x0; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f22, f23, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x800001;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f21; op2:f19; dest:f20; op1val:0x0; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f20, f21, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f18; op2:f20; dest:f19; op1val:0x0; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f19; op2:f17; dest:f18; op1val:0x0; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f18, f19, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f16; op2:f18; dest:f17; op1val:0x0; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f17, f16, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f17; op2:f15; dest:f16; op1val:0x0; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f16, f17, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f15; op2:f13; dest:f14; op1val:0x0; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f14, f15, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f12; op2:f14; dest:f13; op1val:0x0; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f13; op2:f11; dest:f12; op1val:0x0; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f12, f13, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f10; op2:f12; dest:f11; op1val:0x0; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f11, f10, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f11; op2:f9; dest:f10; op1val:0x0; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f10, f11, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f9; op2:f7; dest:f8; op1val:0x0; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f8, f9, f7, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f6; op2:f8; dest:f7; op1val:0x80000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f7, rs2==f5, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f7; op2:f5; dest:f6; op1val:0x80000000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f6, f7, f5, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f4; op2:f6; dest:f5; op1val:0x80000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f5, f4, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f5, rs2==f3, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f5; op2:f3; dest:f4; op1val:0x80000000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f4, f5, f3, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f2; op2:f4; dest:f3; op1val:0x80000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f3, rs2==f1, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f3; op2:f1; dest:f2; op1val:0x80000000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f2, f3, f1, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f0; op2:f2; dest:f1; op1val:0x80000000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f1; op2:f30; dest:f31; op1val:0x80000000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f1, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f0; dest:f31; op1val:0x80000000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f0, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rd==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f31; op2:f30; dest:f0; op1val:0x80000000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:72*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:74*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:76*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:78*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:80*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:82*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:84*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:86*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:88*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:90*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:92*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:94*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x0;
-   valaddr_reg:x3; val_offset:96*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:98*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x1;
-   valaddr_reg:x3; val_offset:100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x2;
-   valaddr_reg:x3; val_offset:104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x800000;
-   valaddr_reg:x3; val_offset:112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x800001;
-   valaddr_reg:x3; val_offset:116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x0;
-   valaddr_reg:x3; val_offset:192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x1;
-   valaddr_reg:x3; val_offset:196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x2;
-   valaddr_reg:x3; val_offset:200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x800000;
-   valaddr_reg:x3; val_offset:208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x800001;
-   valaddr_reg:x3; val_offset:212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x0;
-   valaddr_reg:x3; val_offset:240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x1;
-   valaddr_reg:x3; val_offset:244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x2;
-   valaddr_reg:x3; val_offset:248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x800000;
-   valaddr_reg:x3; val_offset:256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x800001;
-   valaddr_reg:x3; val_offset:260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x0;
-   valaddr_reg:x3; val_offset:480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x1;
-   valaddr_reg:x3; val_offset:484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x2;
-   valaddr_reg:x3; val_offset:488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x0;
-   valaddr_reg:x3; val_offset:528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x1;
-   valaddr_reg:x3; val_offset:532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x2;
-   valaddr_reg:x3; val_offset:536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x800000;
-   valaddr_reg:x3; val_offset:544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x800001;
-   valaddr_reg:x3; val_offset:548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x0;
-   valaddr_reg:x3; val_offset:768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x1;
-   valaddr_reg:x3; val_offset:772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x2;
-   valaddr_reg:x3; val_offset:776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x0;
-   valaddr_reg:x3; val_offset:816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x1;
-   valaddr_reg:x3; val_offset:820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x2;
-   valaddr_reg:x3; val_offset:824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x0;
-   valaddr_reg:x3; val_offset:864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x1;
-   valaddr_reg:x3; val_offset:868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x2;
-   valaddr_reg:x3; val_offset:872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x0;
-   valaddr_reg:x3; val_offset:912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x1;
-   valaddr_reg:x3; val_offset:916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x2;
-   valaddr_reg:x3; val_offset:920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x800000;
-   valaddr_reg:x3; val_offset:928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x800001;
-   valaddr_reg:x3; val_offset:932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x0;
-   valaddr_reg:x3; val_offset:960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x1;
-   valaddr_reg:x3; val_offset:964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x2;
-   valaddr_reg:x3; val_offset:968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:990*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:992*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:994*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:996*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:998*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1000*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1002*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1004*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1006*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x0;
-   valaddr_reg:x3; val_offset:1008*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:1010*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x1;
-   valaddr_reg:x3; val_offset:1012*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:1014*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x2;
-   valaddr_reg:x3; val_offset:1016*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:1018*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:1020*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:1022*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x800000;
-   valaddr_reg:x3; val_offset:1024*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:1026*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x800001;
-   valaddr_reg:x3; val_offset:1028*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:1030*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1032*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1034*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:1036*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:1038*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:1040*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:1042*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:1044*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:1046*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1048*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1050*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1052*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1054*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1056*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:1058*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1060*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:1062*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1064*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:1066*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:1068*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:1070*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:1072*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:1074*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:1076*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:1078*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1080*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1082*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:1084*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:1086*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:1088*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:1090*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:1092*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:1094*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1096*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1098*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:1106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:1110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:1114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:1116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:1118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:1120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:1122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:1124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:1126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:1132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:1134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:1136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:1138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:1140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:1142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:1152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x2;
-   valaddr_reg:x3; val_offset:1154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
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-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 132*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fminm_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fminm_b19-01.S
deleted file mode 100644
index b38976c18..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fminm_b19-01.S
+++ /dev/null
@@ -1,10074 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:08:32 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fminm.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fminm.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fminm_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rd != rs2, rs1==f31, rs2==f30, rd==f31,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f31; op2:f30; dest:f31; op1val:0x7f222105; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rs2 == rd, rs1==f29, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f29; op2:f29; dest:f29; op1val:0x7f222105; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f29, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs2 == rd != rs1, rs1==f30, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f28; dest:f28; op1val:0x7ec45459; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f28, f30, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f28, rs2==f31, rd==f30,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f28; op2:f31; dest:f30; op1val:0x7f222105; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f30, f28, f31, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f26; op2:f26; dest:f27; op1val:0x7eb70362; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f27, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f27; op2:f25; dest:f26; op1val:0x7f222105; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f26, f27, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f24; op2:f27; dest:f25; op1val:0x7d81b404; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f25, f24, f27, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x01b404 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f25; op2:f23; dest:f24; op1val:0x7f7fffff; op2val:0x7d81b404;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f24, f25, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f22; op2:f24; dest:f23; op1val:0x7d81b404; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f23, f22, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x01b404 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f23; op2:f21; dest:f22; op1val:0x7f222105; op2val:0x7d81b404;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f22, f23, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f20; op2:f22; dest:f21; op1val:0x7f222105; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f21; op2:f19; dest:f20; op1val:0x7f2eabd8; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f20, f21, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f18; op2:f20; dest:f19; op1val:0x7f222105; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f19; op2:f17; dest:f18; op1val:0x7d81b404; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f18, f19, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f18, rd==f17,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x01b404 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f16; op2:f18; dest:f17; op1val:0xff7fffff; op2val:0x7d81b404;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f17, f16, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f17; op2:f15; dest:f16; op1val:0x7d81b404; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f16, f17, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f14; op2:f16; dest:f15; op1val:0x7f222105; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f15, rs2==f13, rd==f14,fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f15; op2:f13; dest:f14; op1val:0xfee4815a; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f14, f15, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f12; op2:f14; dest:f13; op1val:0x7f222105; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f13, rs2==f11, rd==f12,fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f13; op2:f11; dest:f12; op1val:0xfe9ffb35; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f12, f13, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f10; op2:f12; dest:f11; op1val:0x7f222105; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f11, f10, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f11; op2:f9; dest:f10; op1val:0x7d81b404; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f10, f11, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f8; op2:f10; dest:f9; op1val:0x7f222105; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0xf7 and fm1 == 0x4f866d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f9; op2:f7; dest:f8; op1val:0x7bcf866d; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f8, f9, f7, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x4f866d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f6; op2:f8; dest:f7; op1val:0xff7fffff; op2val:0x7bcf866d;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f7, rs2==f5, rd==f6,fs1 == 0 and fe1 == 0xf7 and fm1 == 0x4f866d and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f7; op2:f5; dest:f6; op1val:0x7bcf866d; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f6, f7, f5, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f6, rd==f5,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x4f866d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f4; op2:f6; dest:f5; op1val:0x7f222105; op2val:0x7bcf866d;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f5, f4, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f5, rs2==f3, rd==f4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f5; op2:f3; dest:f4; op1val:0x7f222105; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f4, f5, f3, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f2; op2:f4; dest:f3; op1val:0x177770; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f3, rs2==f1, rd==f2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f3; op2:f1; dest:f2; op1val:0x7f39f704; op2val:0x177770;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f2, f3, f1, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f0; op2:f2; dest:f1; op1val:0x177770; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f1,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f1; op2:f30; dest:f31; op1val:0x7f222105; op2val:0x177770;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f1, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f0; dest:f31; op1val:0x7f222105; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f0, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rd==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f31; op2:f30; dest:f0; op1val:0x177770; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x177770;
-   valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:72*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:74*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:76*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:78*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:80*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:82*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:84*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:86*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x177770;
-   valaddr_reg:x3; val_offset:88*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:90*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:92*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:94*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:96*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x5b0376 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0xff5b0376;
-   valaddr_reg:x3; val_offset:98*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x177770;
-   valaddr_reg:x3; val_offset:100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0258be and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x258be; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0258be and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x258be;
-   valaddr_reg:x3; val_offset:112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0258be and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x258be; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0258be and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x258be;
-   valaddr_reg:x3; val_offset:116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x09ec91 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4009ec91; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09ec91 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x4009ec91;
-   valaddr_reg:x3; val_offset:122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09ec91 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x4009ec91;
-   valaddr_reg:x3; val_offset:124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x1d1047 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d1d1047; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x1d1047 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7d1d1047;
-   valaddr_reg:x3; val_offset:136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x1d1047 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d1d1047; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfa and fm2 == 0x1d1047 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x7d1d1047;
-   valaddr_reg:x3; val_offset:140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x1d1047 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d1d1047; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x1d1047 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7d1d1047;
-   valaddr_reg:x3; val_offset:150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x1d1047 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d1d1047; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x1d1047 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d1d1047; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 0 and fe1 == 0xf6 and fm1 == 0x7b4d3e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7b7b4d3e; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xf6 and fm2 == 0x7b4d3e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7b7b4d3e;
-   valaddr_reg:x3; val_offset:170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 0 and fe1 == 0xf6 and fm1 == 0x7b4d3e and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7b7b4d3e; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xf6 and fm2 == 0x7b4d3e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x7b7b4d3e;
-   valaddr_reg:x3; val_offset:174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0e3558 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0xe3558;
-   valaddr_reg:x3; val_offset:180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0e3558 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0xe3558;
-   valaddr_reg:x3; val_offset:184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0e3558 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xe3558;
-   valaddr_reg:x3; val_offset:190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0e3558 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xe3558;
-   valaddr_reg:x3; val_offset:210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x5b0376 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0xff5b0376;
-   valaddr_reg:x3; val_offset:220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0e3558 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0xe3558;
-   valaddr_reg:x3; val_offset:222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x016bbc and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x16bbc; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x016bbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x16bbc;
-   valaddr_reg:x3; val_offset:234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x016bbc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x16bbc; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x016bbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x16bbc;
-   valaddr_reg:x3; val_offset:238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x2704c6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3fa704c6; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2704c6 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x3fa704c6;
-   valaddr_reg:x3; val_offset:244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2704c6 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x3fa704c6;
-   valaddr_reg:x3; val_offset:246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x12691b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d12691b; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x12691b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7d12691b;
-   valaddr_reg:x3; val_offset:254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x12691b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d12691b; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfa and fm2 == 0x12691b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x7d12691b;
-   valaddr_reg:x3; val_offset:258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x12691b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d12691b; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x12691b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7d12691b;
-   valaddr_reg:x3; val_offset:268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x12691b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d12691b; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x12691b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d12691b; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 0 and fe1 == 0xf6 and fm1 == 0x6a41c5 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7b6a41c5; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xf6 and fm2 == 0x6a41c5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7b6a41c5;
-   valaddr_reg:x3; val_offset:288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0xf6 and fm1 == 0x6a41c5 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7b6a41c5; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xf6 and fm2 == 0x6a41c5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x7b6a41c5;
-   valaddr_reg:x3; val_offset:292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0d3ea3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0xd3ea3;
-   valaddr_reg:x3; val_offset:298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0d3ea3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0xd3ea3;
-   valaddr_reg:x3; val_offset:302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0d3ea3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xd3ea3;
-   valaddr_reg:x3; val_offset:308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0d3ea3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xd3ea3;
-   valaddr_reg:x3; val_offset:328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x5b0376 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0xff5b0376;
-   valaddr_reg:x3; val_offset:338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0d3ea3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0xd3ea3;
-   valaddr_reg:x3; val_offset:340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x015310 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x15310; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x015310 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x15310;
-   valaddr_reg:x3; val_offset:352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x015310 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x15310; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x015310 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x15310;
-   valaddr_reg:x3; val_offset:356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x1bb0c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f9bb0c0; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1bb0c0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x3f9bb0c0;
-   valaddr_reg:x3; val_offset:362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1bb0c0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x3f9bb0c0;
-   valaddr_reg:x3; val_offset:364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x0bbcad and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7d8bbcad;
-   valaddr_reg:x3; val_offset:384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0bbcad and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d8bbcad; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x36cde1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xfd36cde1;
-   valaddr_reg:x3; val_offset:396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x36cde1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd36cde1; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x7ff856 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xfcfff856;
-   valaddr_reg:x3; val_offset:404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7ff856 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfcfff856; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2d2942 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x043521 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7cad2942; op2val:0xfe043521;
-   valaddr_reg:x3; val_offset:416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x043521 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x2d2942 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe043521; op2val:0x7cad2942;
-   valaddr_reg:x3; val_offset:418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2d2942 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7cad2942; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x2d2942 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7cad2942;
-   valaddr_reg:x3; val_offset:422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x14c59d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x7d94c59d;
-   valaddr_reg:x3; val_offset:426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x14c59d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d94c59d; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0aa123 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x7e0aa123;
-   valaddr_reg:x3; val_offset:436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0aa123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0aa123; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x209de3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x7e209de3;
-   valaddr_reg:x3; val_offset:444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x209de3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e209de3; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x5abd82 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x7ddabd82;
-   valaddr_reg:x3; val_offset:452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5abd82 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ddabd82; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0f4d55 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x7e0f4d55;
-   valaddr_reg:x3; val_offset:460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0f4d55 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0f4d55; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03130e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0xfe03130e;
-   valaddr_reg:x3; val_offset:468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03130e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03130e; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x7671c2 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0xfdf671c2;
-   valaddr_reg:x3; val_offset:476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x7671c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdf671c2; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x2f35f8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0xfdaf35f8;
-   valaddr_reg:x3; val_offset:484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x2f35f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdaf35f8; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x048fde and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0xfe048fde;
-   valaddr_reg:x3; val_offset:492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x048fde and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe048fde; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x07d511 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2d09bb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d511; op2val:0xfe2d09bb;
-   valaddr_reg:x3; val_offset:500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2d09bb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07d511 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2d09bb; op2val:0x7d511;
-   valaddr_reg:x3; val_offset:502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x07d511 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d511; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07d511 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7d511;
-   valaddr_reg:x3; val_offset:506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x662bb0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40e62bb0; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x662bb0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40e62bb0;
-   valaddr_reg:x3; val_offset:512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x662bb0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x40e62bb0;
-   valaddr_reg:x3; val_offset:514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0bbcad and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d8bbcad; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x0bbcad and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x7d8bbcad;
-   valaddr_reg:x3; val_offset:522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0bbcad and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d8bbcad; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x0bbcad and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7d8bbcad;
-   valaddr_reg:x3; val_offset:528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0bbcad and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d8bbcad; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0bbcad and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d8bbcad; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 0 and fe1 == 0xf7 and fm1 == 0x5f9448 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7bdf9448; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x5f9448 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7bdf9448;
-   valaddr_reg:x3; val_offset:548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 0 and fe1 == 0xf7 and fm1 == 0x5f9448 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7bdf9448; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x5f9448 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x7bdf9448;
-   valaddr_reg:x3; val_offset:552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x19482d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0x19482d;
-   valaddr_reg:x3; val_offset:558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x19482d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x19482d;
-   valaddr_reg:x3; val_offset:562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x19482d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x19482d;
-   valaddr_reg:x3; val_offset:568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x19482d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x19482d;
-   valaddr_reg:x3; val_offset:588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x5b0376 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0xff5b0376;
-   valaddr_reg:x3; val_offset:598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x19482d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x19482d;
-   valaddr_reg:x3; val_offset:600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028737 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x28737; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x028737 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x28737;
-   valaddr_reg:x3; val_offset:612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028737 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x28737; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x028737 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x28737;
-   valaddr_reg:x3; val_offset:616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x149808 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40149808; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x149808 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40149808;
-   valaddr_reg:x3; val_offset:622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x149808 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x40149808;
-   valaddr_reg:x3; val_offset:624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x36cde1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfd36cde1;
-   valaddr_reg:x3; val_offset:648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x36cde1 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd36cde1; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x7ff856 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfcfff856;
-   valaddr_reg:x3; val_offset:656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7ff856 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfcfff856; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x14b67a and fs2 == 1 and fe2 == 0xfc and fm2 == 0x043521 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc94b67a; op2val:0xfe043521;
-   valaddr_reg:x3; val_offset:668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x043521 and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x14b67a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe043521; op2val:0xfc94b67a;
-   valaddr_reg:x3; val_offset:670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x14b67a and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc94b67a; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x14b67a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xfc94b67a;
-   valaddr_reg:x3; val_offset:674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x14c59d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x7d94c59d;
-   valaddr_reg:x3; val_offset:678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x14c59d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d94c59d; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0aa123 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x7e0aa123;
-   valaddr_reg:x3; val_offset:688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0aa123 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0aa123; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x209de3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x7e209de3;
-   valaddr_reg:x3; val_offset:696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x209de3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e209de3; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x5abd82 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x7ddabd82;
-   valaddr_reg:x3; val_offset:704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5abd82 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ddabd82; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0f4d55 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x7e0f4d55;
-   valaddr_reg:x3; val_offset:712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0f4d55 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0f4d55; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03130e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0xfe03130e;
-   valaddr_reg:x3; val_offset:720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03130e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03130e; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x7671c2 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0xfdf671c2;
-   valaddr_reg:x3; val_offset:728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x7671c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdf671c2; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x2f35f8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0xfdaf35f8;
-   valaddr_reg:x3; val_offset:736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x2f35f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdaf35f8; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x048fde and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0xfe048fde;
-   valaddr_reg:x3; val_offset:744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x048fde and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe048fde; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x06b9fa and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2d09bb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8006b9fa; op2val:0xfe2d09bb;
-   valaddr_reg:x3; val_offset:752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2d09bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x06b9fa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2d09bb; op2val:0x8006b9fa;
-   valaddr_reg:x3; val_offset:754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x06b9fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8006b9fa; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x06b9fa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x8006b9fa;
-   valaddr_reg:x3; val_offset:758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x45ac58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc0c5ac58; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x45ac58 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc0c5ac58;
-   valaddr_reg:x3; val_offset:764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x45ac58 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xc0c5ac58;
-   valaddr_reg:x3; val_offset:766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x36cde1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd36cde1; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0xfa and fm2 == 0x36cde1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xfd36cde1;
-   valaddr_reg:x3; val_offset:774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x36cde1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd36cde1; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x36cde1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd36cde1; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 1 and fe1 == 0xf7 and fm1 == 0x123e4e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfb923e4e; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xf7 and fm2 == 0x123e4e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfb923e4e;
-   valaddr_reg:x3; val_offset:792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 1 and fe1 == 0xf7 and fm1 == 0x123e4e and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfb923e4e; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0xf7 and fm2 == 0x123e4e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xfb923e4e;
-   valaddr_reg:x3; val_offset:796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108974 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0x80108974;
-   valaddr_reg:x3; val_offset:802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108974 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x80108974;
-   valaddr_reg:x3; val_offset:806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108974 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80108974;
-   valaddr_reg:x3; val_offset:812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108974 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80108974;
-   valaddr_reg:x3; val_offset:832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x5b0376 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0xff5b0376;
-   valaddr_reg:x3; val_offset:842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108974 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x80108974;
-   valaddr_reg:x3; val_offset:844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01a758 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8001a758; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a758 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x8001a758;
-   valaddr_reg:x3; val_offset:856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01a758 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8001a758; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a758 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x8001a758;
-   valaddr_reg:x3; val_offset:860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x42640b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbfc2640b; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x42640b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xbfc2640b;
-   valaddr_reg:x3; val_offset:866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x7f and fm2 == 0x42640b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xbfc2640b;
-   valaddr_reg:x3; val_offset:868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7ff856 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfcfff856; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x7ff856 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xfcfff856;
-   valaddr_reg:x3; val_offset:876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7ff856 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfcfff856; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7ff856 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfcfff856; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 1 and fe1 == 0xf6 and fm1 == 0x4cc6ab and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfb4cc6ab; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xf6 and fm2 == 0x4cc6ab and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfb4cc6ab;
-   valaddr_reg:x3; val_offset:890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 1 and fe1 == 0xf6 and fm1 == 0x4cc6ab and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfb4cc6ab; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0xf6 and fm2 == 0x4cc6ab and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xfb4cc6ab;
-   valaddr_reg:x3; val_offset:894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0b93ee and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0x800b93ee;
-   valaddr_reg:x3; val_offset:900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0b93ee and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x800b93ee;
-   valaddr_reg:x3; val_offset:904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0b93ee and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x800b93ee;
-   valaddr_reg:x3; val_offset:910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0b93ee and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x800b93ee;
-   valaddr_reg:x3; val_offset:930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 1 and fe2 == 0xfe and fm2 == 0x5b0376 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0xff5b0376;
-   valaddr_reg:x3; val_offset:940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0b93ee and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x800b93ee;
-   valaddr_reg:x3; val_offset:942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x012864 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80012864; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x012864 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80012864;
-   valaddr_reg:x3; val_offset:954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x012864 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80012864; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x012864 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x80012864;
-   valaddr_reg:x3; val_offset:958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0818d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf8818d6; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x0818d6 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xbf8818d6;
-   valaddr_reg:x3; val_offset:964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x0818d6 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xbf8818d6;
-   valaddr_reg:x3; val_offset:966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x1608ad and fs2 == 1 and fe2 == 0xfc and fm2 == 0x043521 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc9608ad; op2val:0xfe043521;
-   valaddr_reg:x3; val_offset:986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x043521 and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x1608ad and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe043521; op2val:0xfc9608ad;
-   valaddr_reg:x3; val_offset:988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x1608ad and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc9608ad; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:990*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x1608ad and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xfc9608ad;
-   valaddr_reg:x3; val_offset:992*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:994*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0xfb and fm2 == 0x14c59d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x7d94c59d;
-   valaddr_reg:x3; val_offset:996*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x14c59d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d94c59d; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:998*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1000*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1002*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1004*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0aa123 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x7e0aa123;
-   valaddr_reg:x3; val_offset:1006*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0aa123 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0aa123; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1008*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1010*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1012*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0xfc and fm2 == 0x209de3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x7e209de3;
-   valaddr_reg:x3; val_offset:1014*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x209de3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e209de3; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1016*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1018*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1020*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0xfb and fm2 == 0x5abd82 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x7ddabd82;
-   valaddr_reg:x3; val_offset:1022*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5abd82 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ddabd82; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1024*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1026*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1028*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0f4d55 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x7e0f4d55;
-   valaddr_reg:x3; val_offset:1030*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0f4d55 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0f4d55; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1032*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1034*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1036*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03130e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0xfe03130e;
-   valaddr_reg:x3; val_offset:1038*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03130e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03130e; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1040*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1042*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1044*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0xfb and fm2 == 0x7671c2 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0xfdf671c2;
-   valaddr_reg:x3; val_offset:1046*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x7671c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdf671c2; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1048*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1050*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1052*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0xfb and fm2 == 0x2f35f8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0xfdaf35f8;
-   valaddr_reg:x3; val_offset:1054*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x2f35f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdaf35f8; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1056*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1058*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1060*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0xfc and fm2 == 0x048fde and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0xfe048fde;
-   valaddr_reg:x3; val_offset:1062*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x048fde and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe048fde; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1064*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1066*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1068*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x06c946 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2d09bb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8006c946; op2val:0xfe2d09bb;
-   valaddr_reg:x3; val_offset:1070*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2d09bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x06c946 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2d09bb; op2val:0x8006c946;
-   valaddr_reg:x3; val_offset:1072*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x06c946 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8006c946; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1074*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x06c946 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x8006c946;
-   valaddr_reg:x3; val_offset:1076*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1078*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x476de3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc0c76de3; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1080*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x476de3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc0c76de3;
-   valaddr_reg:x3; val_offset:1082*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x476de3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xc0c76de3;
-   valaddr_reg:x3; val_offset:1084*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1086*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1088*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1090*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1092*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1094*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1096*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x043521 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe043521; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1098*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x043521 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xfe043521;
-   valaddr_reg:x3; val_offset:1100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x043521 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe043521; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x043521 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe043521; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x6e08fb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x7bee08fb;
-   valaddr_reg:x3; val_offset:1118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 0 and fe1 == 0xf7 and fm1 == 0x6e08fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7bee08fb; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0xf8 and fm2 == 0x5dce9f and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x7c5dce9f;
-   valaddr_reg:x3; val_offset:1128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x5dce9f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c5dce9f; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x007e4f and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x7c807e4f;
-   valaddr_reg:x3; val_offset:1136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x007e4f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c807e4f; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0xf8 and fm2 == 0x2efe01 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x7c2efe01;
-   valaddr_reg:x3; val_offset:1144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x2efe01 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c2efe01; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0xf8 and fm2 == 0x654888 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x7c654888;
-   valaddr_reg:x3; val_offset:1152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x654888 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c654888; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-
-inst_578:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1156*FLEN/8, x4, x1, x2)
-
-inst_579:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1158*FLEN/8, x4, x1, x2)
-
-inst_580:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x51b817 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0xfc51b817;
-   valaddr_reg:x3; val_offset:1160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1160*FLEN/8, x4, x1, x2)
-
-inst_581:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x51b817 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc51b817; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1162*FLEN/8, x4, x1, x2)
-
-inst_582:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1164*FLEN/8, x4, x1, x2)
-
-inst_583:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1166*FLEN/8, x4, x1, x2)
-
-inst_584:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x4527ce and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0xfc4527ce;
-   valaddr_reg:x3; val_offset:1168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1168*FLEN/8, x4, x1, x2)
-
-inst_585:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x4527ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc4527ce; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1170*FLEN/8, x4, x1, x2)
-
-inst_586:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1172*FLEN/8, x4, x1, x2)
-
-inst_587:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1174*FLEN/8, x4, x1, x2)
-
-inst_588:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x0c2b2c and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0xfc0c2b2c;
-   valaddr_reg:x3; val_offset:1176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1176*FLEN/8, x4, x1, x2)
-
-inst_589:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x0c2b2c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc0c2b2c; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1178*FLEN/8, x4, x1, x2)
-
-inst_590:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1180*FLEN/8, x4, x1, x2)
-
-inst_591:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1182*FLEN/8, x4, x1, x2)
-
-inst_592:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x541963 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0xfc541963;
-   valaddr_reg:x3; val_offset:1184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1184*FLEN/8, x4, x1, x2)
-
-inst_593:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x541963 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc541963; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1186*FLEN/8, x4, x1, x2)
-
-inst_594:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1188*FLEN/8, x4, x1, x2)
-
-inst_595:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1190*FLEN/8, x4, x1, x2)
-
-inst_596:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04c8af and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x0a6e2f and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8004c8af; op2val:0xfc8a6e2f;
-   valaddr_reg:x3; val_offset:1192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1192*FLEN/8, x4, x1, x2)
-
-inst_597:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x0a6e2f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04c8af and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc8a6e2f; op2val:0x8004c8af;
-   valaddr_reg:x3; val_offset:1194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1194*FLEN/8, x4, x1, x2)
-
-inst_598:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04c8af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8004c8af; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1196*FLEN/8, x4, x1, x2)
-
-inst_599:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04c8af and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x8004c8af;
-   valaddr_reg:x3; val_offset:1198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1198*FLEN/8, x4, x1, x2)
-
-inst_600:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1200*FLEN/8, x4, x1, x2)
-
-inst_601:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x0c9650 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc08c9650; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1202*FLEN/8, x4, x1, x2)
-
-inst_602:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0c9650 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc08c9650;
-   valaddr_reg:x3; val_offset:1204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1204*FLEN/8, x4, x1, x2)
-
-inst_603:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0c9650 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xc08c9650;
-   valaddr_reg:x3; val_offset:1206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1206*FLEN/8, x4, x1, x2)
-
-inst_604:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1208*FLEN/8, x4, x1, x2)
-
-inst_605:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1210*FLEN/8, x4, x1, x2)
-
-inst_606:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:1212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1212*FLEN/8, x4, x1, x2)
-
-inst_607:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1214*FLEN/8, x4, x1, x2)
-
-inst_608:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1216*FLEN/8, x4, x1, x2)
-
-inst_609:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1218*FLEN/8, x4, x1, x2)
-
-inst_610:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1220*FLEN/8, x4, x1, x2)
-
-inst_611:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1222*FLEN/8, x4, x1, x2)
-
-inst_612:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1224*FLEN/8, x4, x1, x2)
-
-inst_613:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x14c59d and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d94c59d; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1226*FLEN/8, x4, x1, x2)
-
-inst_614:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x14c59d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7d94c59d;
-   valaddr_reg:x3; val_offset:1228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1228*FLEN/8, x4, x1, x2)
-
-inst_615:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1230*FLEN/8, x4, x1, x2)
-
-inst_616:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1232*FLEN/8, x4, x1, x2)
-
-inst_617:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1234*FLEN/8, x4, x1, x2)
-
-inst_618:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x14c59d and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d94c59d; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1236*FLEN/8, x4, x1, x2)
-
-inst_619:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1238*FLEN/8, x4, x1, x2)
-
-inst_620:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1240*FLEN/8, x4, x1, x2)
-
-inst_621:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1242*FLEN/8, x4, x1, x2)
-
-inst_622:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1244*FLEN/8, x4, x1, x2)
-
-inst_623:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1246*FLEN/8, x4, x1, x2)
-
-inst_624:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x14c59d and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d94c59d; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1248*FLEN/8, x4, x1, x2)
-
-inst_625:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1250*FLEN/8, x4, x1, x2)
-
-inst_626:
-// fs1 == 0 and fe1 == 0xf7 and fm1 == 0x6e08fb and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7bee08fb; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1252*FLEN/8, x4, x1, x2)
-
-inst_627:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x6e08fb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7bee08fb;
-   valaddr_reg:x3; val_offset:1254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1254*FLEN/8, x4, x1, x2)
-
-inst_628:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1256*FLEN/8, x4, x1, x2)
-
-inst_629:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1258*FLEN/8, x4, x1, x2)
-
-inst_630:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1260*FLEN/8, x4, x1, x2)
-
-inst_631:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1262*FLEN/8, x4, x1, x2)
-
-inst_632:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1264*FLEN/8, x4, x1, x2)
-
-inst_633:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1266*FLEN/8, x4, x1, x2)
-
-inst_634:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1268*FLEN/8, x4, x1, x2)
-
-inst_635:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1270*FLEN/8, x4, x1, x2)
-
-inst_636:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1272*FLEN/8, x4, x1, x2)
-
-inst_637:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1274*FLEN/8, x4, x1, x2)
-
-inst_638:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1276*FLEN/8, x4, x1, x2)
-
-inst_639:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1278*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_6)
-
-inst_640:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1280*FLEN/8, x4, x1, x2)
-
-inst_641:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1282*FLEN/8, x4, x1, x2)
-
-inst_642:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1284*FLEN/8, x4, x1, x2)
-
-inst_643:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1286*FLEN/8, x4, x1, x2)
-
-inst_644:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1288*FLEN/8, x4, x1, x2)
-
-inst_645:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b110 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2b110; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1290*FLEN/8, x4, x1, x2)
-
-inst_646:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02b110 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x2b110;
-   valaddr_reg:x3; val_offset:1292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1292*FLEN/8, x4, x1, x2)
-
-inst_647:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b110 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2b110; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1294*FLEN/8, x4, x1, x2)
-
-inst_648:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02b110 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x2b110;
-   valaddr_reg:x3; val_offset:1296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1296*FLEN/8, x4, x1, x2)
-
-inst_649:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1298*FLEN/8, x4, x1, x2)
-
-inst_650:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x1e3392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x401e3392; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1300*FLEN/8, x4, x1, x2)
-
-inst_651:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1e3392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x401e3392;
-   valaddr_reg:x3; val_offset:1302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1302*FLEN/8, x4, x1, x2)
-
-inst_652:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1e3392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x401e3392;
-   valaddr_reg:x3; val_offset:1304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1304*FLEN/8, x4, x1, x2)
-
-inst_653:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1306*FLEN/8, x4, x1, x2)
-
-inst_654:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1308*FLEN/8, x4, x1, x2)
-
-inst_655:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1310*FLEN/8, x4, x1, x2)
-
-inst_656:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1312*FLEN/8, x4, x1, x2)
-
-inst_657:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1314*FLEN/8, x4, x1, x2)
-
-inst_658:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1316*FLEN/8, x4, x1, x2)
-
-inst_659:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0aa123 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0aa123; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1318*FLEN/8, x4, x1, x2)
-
-inst_660:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0aa123 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7e0aa123;
-   valaddr_reg:x3; val_offset:1320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1320*FLEN/8, x4, x1, x2)
-
-inst_661:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1322*FLEN/8, x4, x1, x2)
-
-inst_662:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1324*FLEN/8, x4, x1, x2)
-
-inst_663:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0aa123 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0aa123; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1326*FLEN/8, x4, x1, x2)
-
-inst_664:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1328*FLEN/8, x4, x1, x2)
-
-inst_665:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1330*FLEN/8, x4, x1, x2)
-
-inst_666:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1332*FLEN/8, x4, x1, x2)
-
-inst_667:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0aa123 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0aa123; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1334*FLEN/8, x4, x1, x2)
-
-inst_668:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1336*FLEN/8, x4, x1, x2)
-
-inst_669:
-// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x5dce9f and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c5dce9f; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1338*FLEN/8, x4, x1, x2)
-
-inst_670:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xf8 and fm2 == 0x5dce9f and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7c5dce9f;
-   valaddr_reg:x3; val_offset:1340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1340*FLEN/8, x4, x1, x2)
-
-inst_671:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1342*FLEN/8, x4, x1, x2)
-
-inst_672:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1344*FLEN/8, x4, x1, x2)
-
-inst_673:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1346*FLEN/8, x4, x1, x2)
-
-inst_674:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1348*FLEN/8, x4, x1, x2)
-
-inst_675:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1350*FLEN/8, x4, x1, x2)
-
-inst_676:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1352*FLEN/8, x4, x1, x2)
-
-inst_677:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1354*FLEN/8, x4, x1, x2)
-
-inst_678:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1356*FLEN/8, x4, x1, x2)
-
-inst_679:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1358*FLEN/8, x4, x1, x2)
-
-inst_680:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1360*FLEN/8, x4, x1, x2)
-
-inst_681:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1362*FLEN/8, x4, x1, x2)
-
-inst_682:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1364*FLEN/8, x4, x1, x2)
-
-inst_683:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1366*FLEN/8, x4, x1, x2)
-
-inst_684:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1368*FLEN/8, x4, x1, x2)
-
-inst_685:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1370*FLEN/8, x4, x1, x2)
-
-inst_686:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05042c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x5042c; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1372*FLEN/8, x4, x1, x2)
-
-inst_687:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05042c and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x5042c;
-   valaddr_reg:x3; val_offset:1374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1374*FLEN/8, x4, x1, x2)
-
-inst_688:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05042c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x5042c; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1376*FLEN/8, x4, x1, x2)
-
-inst_689:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05042c and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x5042c;
-   valaddr_reg:x3; val_offset:1378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1378*FLEN/8, x4, x1, x2)
-
-inst_690:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1380*FLEN/8, x4, x1, x2)
-
-inst_691:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x136a86 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40936a86; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1382*FLEN/8, x4, x1, x2)
-
-inst_692:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x136a86 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40936a86;
-   valaddr_reg:x3; val_offset:1384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1384*FLEN/8, x4, x1, x2)
-
-inst_693:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x136a86 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x40936a86;
-   valaddr_reg:x3; val_offset:1386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1386*FLEN/8, x4, x1, x2)
-
-inst_694:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1388*FLEN/8, x4, x1, x2)
-
-inst_695:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1390*FLEN/8, x4, x1, x2)
-
-inst_696:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1392*FLEN/8, x4, x1, x2)
-
-inst_697:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1394*FLEN/8, x4, x1, x2)
-
-inst_698:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1396*FLEN/8, x4, x1, x2)
-
-inst_699:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1398*FLEN/8, x4, x1, x2)
-
-inst_700:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x209de3 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e209de3; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1400*FLEN/8, x4, x1, x2)
-
-inst_701:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x209de3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7e209de3;
-   valaddr_reg:x3; val_offset:1402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1402*FLEN/8, x4, x1, x2)
-
-inst_702:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1404*FLEN/8, x4, x1, x2)
-
-inst_703:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1406*FLEN/8, x4, x1, x2)
-
-inst_704:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x209de3 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e209de3; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1408*FLEN/8, x4, x1, x2)
-
-inst_705:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1410*FLEN/8, x4, x1, x2)
-
-inst_706:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1412*FLEN/8, x4, x1, x2)
-
-inst_707:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1414*FLEN/8, x4, x1, x2)
-
-inst_708:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x209de3 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e209de3; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1416*FLEN/8, x4, x1, x2)
-
-inst_709:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1418*FLEN/8, x4, x1, x2)
-
-inst_710:
-// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x007e4f and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c807e4f; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1420*FLEN/8, x4, x1, x2)
-
-inst_711:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x007e4f and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7c807e4f;
-   valaddr_reg:x3; val_offset:1422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1422*FLEN/8, x4, x1, x2)
-
-inst_712:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1424*FLEN/8, x4, x1, x2)
-
-inst_713:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1426*FLEN/8, x4, x1, x2)
-
-inst_714:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1428*FLEN/8, x4, x1, x2)
-
-inst_715:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1430*FLEN/8, x4, x1, x2)
-
-inst_716:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1432*FLEN/8, x4, x1, x2)
-
-inst_717:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1434*FLEN/8, x4, x1, x2)
-
-inst_718:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1436*FLEN/8, x4, x1, x2)
-
-inst_719:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1438*FLEN/8, x4, x1, x2)
-
-inst_720:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1440*FLEN/8, x4, x1, x2)
-
-inst_721:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1442*FLEN/8, x4, x1, x2)
-
-inst_722:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1444*FLEN/8, x4, x1, x2)
-
-inst_723:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1446*FLEN/8, x4, x1, x2)
-
-inst_724:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1448*FLEN/8, x4, x1, x2)
-
-inst_725:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05cfda and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x5cfda; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1450*FLEN/8, x4, x1, x2)
-
-inst_726:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05cfda and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x5cfda;
-   valaddr_reg:x3; val_offset:1452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1452*FLEN/8, x4, x1, x2)
-
-inst_727:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05cfda and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x5cfda; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1454*FLEN/8, x4, x1, x2)
-
-inst_728:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05cfda and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x5cfda;
-   valaddr_reg:x3; val_offset:1456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1456*FLEN/8, x4, x1, x2)
-
-inst_729:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1458*FLEN/8, x4, x1, x2)
-
-inst_730:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x2acc0a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40aacc0a; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1460*FLEN/8, x4, x1, x2)
-
-inst_731:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x2acc0a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40aacc0a;
-   valaddr_reg:x3; val_offset:1462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1462*FLEN/8, x4, x1, x2)
-
-inst_732:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x2acc0a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x40aacc0a;
-   valaddr_reg:x3; val_offset:1464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1464*FLEN/8, x4, x1, x2)
-
-inst_733:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1466*FLEN/8, x4, x1, x2)
-
-inst_734:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1468*FLEN/8, x4, x1, x2)
-
-inst_735:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1470*FLEN/8, x4, x1, x2)
-
-inst_736:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1472*FLEN/8, x4, x1, x2)
-
-inst_737:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1474*FLEN/8, x4, x1, x2)
-
-inst_738:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1476*FLEN/8, x4, x1, x2)
-
-inst_739:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5abd82 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ddabd82; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1478*FLEN/8, x4, x1, x2)
-
-inst_740:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x5abd82 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7ddabd82;
-   valaddr_reg:x3; val_offset:1480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1480*FLEN/8, x4, x1, x2)
-
-inst_741:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1482*FLEN/8, x4, x1, x2)
-
-inst_742:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1484*FLEN/8, x4, x1, x2)
-
-inst_743:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5abd82 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ddabd82; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1486*FLEN/8, x4, x1, x2)
-
-inst_744:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1488*FLEN/8, x4, x1, x2)
-
-inst_745:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1490*FLEN/8, x4, x1, x2)
-
-inst_746:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1492*FLEN/8, x4, x1, x2)
-
-inst_747:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5abd82 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ddabd82; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1494*FLEN/8, x4, x1, x2)
-
-inst_748:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1496*FLEN/8, x4, x1, x2)
-
-inst_749:
-// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x2efe01 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c2efe01; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1498*FLEN/8, x4, x1, x2)
-
-inst_750:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xf8 and fm2 == 0x2efe01 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7c2efe01;
-   valaddr_reg:x3; val_offset:1500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1500*FLEN/8, x4, x1, x2)
-
-inst_751:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1502*FLEN/8, x4, x1, x2)
-
-inst_752:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1504*FLEN/8, x4, x1, x2)
-
-inst_753:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1506*FLEN/8, x4, x1, x2)
-
-inst_754:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1508*FLEN/8, x4, x1, x2)
-
-inst_755:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1510*FLEN/8, x4, x1, x2)
-
-inst_756:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1512*FLEN/8, x4, x1, x2)
-
-inst_757:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1514*FLEN/8, x4, x1, x2)
-
-inst_758:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1516*FLEN/8, x4, x1, x2)
-
-inst_759:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1518*FLEN/8, x4, x1, x2)
-
-inst_760:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1520*FLEN/8, x4, x1, x2)
-
-inst_761:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1522*FLEN/8, x4, x1, x2)
-
-inst_762:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f522 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f522; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1524*FLEN/8, x4, x1, x2)
-
-inst_763:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03f522 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x3f522;
-   valaddr_reg:x3; val_offset:1526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1526*FLEN/8, x4, x1, x2)
-
-inst_764:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f522 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f522; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1528*FLEN/8, x4, x1, x2)
-
-inst_765:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03f522 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x3f522;
-   valaddr_reg:x3; val_offset:1530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1530*FLEN/8, x4, x1, x2)
-
-inst_766:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1532*FLEN/8, x4, x1, x2)
-
-inst_767:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x689ac4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40689ac4; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1534*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_7)
-
-inst_768:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x689ac4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40689ac4;
-   valaddr_reg:x3; val_offset:1536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1536*FLEN/8, x4, x1, x2)
-
-inst_769:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x689ac4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x40689ac4;
-   valaddr_reg:x3; val_offset:1538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1538*FLEN/8, x4, x1, x2)
-
-inst_770:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1540*FLEN/8, x4, x1, x2)
-
-inst_771:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1542*FLEN/8, x4, x1, x2)
-
-inst_772:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1544*FLEN/8, x4, x1, x2)
-
-inst_773:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1546*FLEN/8, x4, x1, x2)
-
-inst_774:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1548*FLEN/8, x4, x1, x2)
-
-inst_775:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1550*FLEN/8, x4, x1, x2)
-
-inst_776:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0f4d55 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0f4d55; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1552*FLEN/8, x4, x1, x2)
-
-inst_777:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0f4d55 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7e0f4d55;
-   valaddr_reg:x3; val_offset:1554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1554*FLEN/8, x4, x1, x2)
-
-inst_778:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1556*FLEN/8, x4, x1, x2)
-
-inst_779:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1558*FLEN/8, x4, x1, x2)
-
-inst_780:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0f4d55 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0f4d55; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1560*FLEN/8, x4, x1, x2)
-
-inst_781:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1562*FLEN/8, x4, x1, x2)
-
-inst_782:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1564*FLEN/8, x4, x1, x2)
-
-inst_783:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1566*FLEN/8, x4, x1, x2)
-
-inst_784:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0f4d55 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0f4d55; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1568*FLEN/8, x4, x1, x2)
-
-inst_785:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1570*FLEN/8, x4, x1, x2)
-
-inst_786:
-// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x654888 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c654888; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1572*FLEN/8, x4, x1, x2)
-
-inst_787:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xf8 and fm2 == 0x654888 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7c654888;
-   valaddr_reg:x3; val_offset:1574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1574*FLEN/8, x4, x1, x2)
-
-inst_788:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1576*FLEN/8, x4, x1, x2)
-
-inst_789:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1578*FLEN/8, x4, x1, x2)
-
-inst_790:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1580*FLEN/8, x4, x1, x2)
-
-inst_791:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1582*FLEN/8, x4, x1, x2)
-
-inst_792:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1584*FLEN/8, x4, x1, x2)
-
-inst_793:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1586*FLEN/8, x4, x1, x2)
-
-inst_794:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1588*FLEN/8, x4, x1, x2)
-
-inst_795:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1590*FLEN/8, x4, x1, x2)
-
-inst_796:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1592*FLEN/8, x4, x1, x2)
-
-inst_797:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x052f75 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x52f75; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1594*FLEN/8, x4, x1, x2)
-
-inst_798:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x052f75 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x52f75;
-   valaddr_reg:x3; val_offset:1596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1596*FLEN/8, x4, x1, x2)
-
-inst_799:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x052f75 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x52f75; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1598*FLEN/8, x4, x1, x2)
-
-inst_800:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x052f75 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x52f75;
-   valaddr_reg:x3; val_offset:1600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1600*FLEN/8, x4, x1, x2)
-
-inst_801:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1602*FLEN/8, x4, x1, x2)
-
-inst_802:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x186289 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40986289; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1604*FLEN/8, x4, x1, x2)
-
-inst_803:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x186289 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40986289;
-   valaddr_reg:x3; val_offset:1606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1606*FLEN/8, x4, x1, x2)
-
-inst_804:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x186289 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x40986289;
-   valaddr_reg:x3; val_offset:1608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1608*FLEN/8, x4, x1, x2)
-
-inst_805:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1610*FLEN/8, x4, x1, x2)
-
-inst_806:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1612*FLEN/8, x4, x1, x2)
-
-inst_807:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1614*FLEN/8, x4, x1, x2)
-
-inst_808:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1616*FLEN/8, x4, x1, x2)
-
-inst_809:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1618*FLEN/8, x4, x1, x2)
-
-inst_810:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1620*FLEN/8, x4, x1, x2)
-
-inst_811:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03130e and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03130e; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1622*FLEN/8, x4, x1, x2)
-
-inst_812:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03130e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xfe03130e;
-   valaddr_reg:x3; val_offset:1624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1624*FLEN/8, x4, x1, x2)
-
-inst_813:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1626*FLEN/8, x4, x1, x2)
-
-inst_814:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1628*FLEN/8, x4, x1, x2)
-
-inst_815:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03130e and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03130e; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1630*FLEN/8, x4, x1, x2)
-
-inst_816:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1632*FLEN/8, x4, x1, x2)
-
-inst_817:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1634*FLEN/8, x4, x1, x2)
-
-inst_818:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1636*FLEN/8, x4, x1, x2)
-
-inst_819:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03130e and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03130e; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1638*FLEN/8, x4, x1, x2)
-
-inst_820:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1640*FLEN/8, x4, x1, x2)
-
-inst_821:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x51b817 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc51b817; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1642*FLEN/8, x4, x1, x2)
-
-inst_822:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x51b817 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xfc51b817;
-   valaddr_reg:x3; val_offset:1644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1644*FLEN/8, x4, x1, x2)
-
-inst_823:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1646*FLEN/8, x4, x1, x2)
-
-inst_824:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1648*FLEN/8, x4, x1, x2)
-
-inst_825:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1650*FLEN/8, x4, x1, x2)
-
-inst_826:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1652*FLEN/8, x4, x1, x2)
-
-inst_827:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1654*FLEN/8, x4, x1, x2)
-
-inst_828:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1656*FLEN/8, x4, x1, x2)
-
-inst_829:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1658*FLEN/8, x4, x1, x2)
-
-inst_830:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04be30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8004be30; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1660*FLEN/8, x4, x1, x2)
-
-inst_831:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04be30 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x8004be30;
-   valaddr_reg:x3; val_offset:1662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1662*FLEN/8, x4, x1, x2)
-
-inst_832:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04be30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8004be30; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1664*FLEN/8, x4, x1, x2)
-
-inst_833:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04be30 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x8004be30;
-   valaddr_reg:x3; val_offset:1666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1666*FLEN/8, x4, x1, x2)
-
-inst_834:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1668*FLEN/8, x4, x1, x2)
-
-inst_835:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x0b61db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc08b61db; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1670*FLEN/8, x4, x1, x2)
-
-inst_836:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0b61db and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc08b61db;
-   valaddr_reg:x3; val_offset:1672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1672*FLEN/8, x4, x1, x2)
-
-inst_837:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0b61db and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xc08b61db;
-   valaddr_reg:x3; val_offset:1674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1674*FLEN/8, x4, x1, x2)
-
-inst_838:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1676*FLEN/8, x4, x1, x2)
-
-inst_839:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1678*FLEN/8, x4, x1, x2)
-
-inst_840:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1680*FLEN/8, x4, x1, x2)
-
-inst_841:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1682*FLEN/8, x4, x1, x2)
-
-inst_842:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1684*FLEN/8, x4, x1, x2)
-
-inst_843:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1686*FLEN/8, x4, x1, x2)
-
-inst_844:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x7671c2 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdf671c2; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1688*FLEN/8, x4, x1, x2)
-
-inst_845:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x7671c2 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xfdf671c2;
-   valaddr_reg:x3; val_offset:1690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1690*FLEN/8, x4, x1, x2)
-
-inst_846:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1692*FLEN/8, x4, x1, x2)
-
-inst_847:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1694*FLEN/8, x4, x1, x2)
-
-inst_848:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x7671c2 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdf671c2; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1696*FLEN/8, x4, x1, x2)
-
-inst_849:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1698*FLEN/8, x4, x1, x2)
-
-inst_850:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1700*FLEN/8, x4, x1, x2)
-
-inst_851:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1702*FLEN/8, x4, x1, x2)
-
-inst_852:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x7671c2 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdf671c2; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1704*FLEN/8, x4, x1, x2)
-
-inst_853:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1706*FLEN/8, x4, x1, x2)
-
-inst_854:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x4527ce and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc4527ce; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1708*FLEN/8, x4, x1, x2)
-
-inst_855:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x4527ce and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xfc4527ce;
-   valaddr_reg:x3; val_offset:1710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1710*FLEN/8, x4, x1, x2)
-
-inst_856:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1712*FLEN/8, x4, x1, x2)
-
-inst_857:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1714*FLEN/8, x4, x1, x2)
-
-inst_858:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1716*FLEN/8, x4, x1, x2)
-
-inst_859:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1718*FLEN/8, x4, x1, x2)
-
-inst_860:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1720*FLEN/8, x4, x1, x2)
-
-inst_861:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x047573 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80047573; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1722*FLEN/8, x4, x1, x2)
-
-inst_862:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x047573 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x80047573;
-   valaddr_reg:x3; val_offset:1724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1724*FLEN/8, x4, x1, x2)
-
-inst_863:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x047573 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80047573; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1726*FLEN/8, x4, x1, x2)
-
-inst_864:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x047573 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x80047573;
-   valaddr_reg:x3; val_offset:1728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1728*FLEN/8, x4, x1, x2)
-
-inst_865:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1730*FLEN/8, x4, x1, x2)
-
-inst_866:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x030845 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc0830845; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1732*FLEN/8, x4, x1, x2)
-
-inst_867:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x030845 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc0830845;
-   valaddr_reg:x3; val_offset:1734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1734*FLEN/8, x4, x1, x2)
-
-inst_868:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x030845 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xc0830845;
-   valaddr_reg:x3; val_offset:1736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1736*FLEN/8, x4, x1, x2)
-
-inst_869:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1738*FLEN/8, x4, x1, x2)
-
-inst_870:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1740*FLEN/8, x4, x1, x2)
-
-inst_871:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x5b0376 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xff5b0376;
-   valaddr_reg:x3; val_offset:1742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1742*FLEN/8, x4, x1, x2)
-
-inst_872:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1744*FLEN/8, x4, x1, x2)
-
-inst_873:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1746*FLEN/8, x4, x1, x2)
-
-inst_874:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1748*FLEN/8, x4, x1, x2)
-
-inst_875:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1750*FLEN/8, x4, x1, x2)
-
-inst_876:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1752*FLEN/8, x4, x1, x2)
-
-inst_877:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1754*FLEN/8, x4, x1, x2)
-
-inst_878:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x2f35f8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdaf35f8; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1756*FLEN/8, x4, x1, x2)
-
-inst_879:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x2f35f8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xfdaf35f8;
-   valaddr_reg:x3; val_offset:1758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1758*FLEN/8, x4, x1, x2)
-
-inst_880:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1760*FLEN/8, x4, x1, x2)
-
-inst_881:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1762*FLEN/8, x4, x1, x2)
-
-inst_882:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1764*FLEN/8, x4, x1, x2)
-
-inst_883:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x2f35f8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdaf35f8; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1766*FLEN/8, x4, x1, x2)
-
-inst_884:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1768*FLEN/8, x4, x1, x2)
-
-inst_885:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1770*FLEN/8, x4, x1, x2)
-
-inst_886:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1772*FLEN/8, x4, x1, x2)
-
-inst_887:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1774*FLEN/8, x4, x1, x2)
-
-inst_888:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1776*FLEN/8, x4, x1, x2)
-
-inst_889:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x2f35f8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdaf35f8; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1778*FLEN/8, x4, x1, x2)
-
-inst_890:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1780*FLEN/8, x4, x1, x2)
-
-inst_891:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x0c2b2c and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc0c2b2c; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1782*FLEN/8, x4, x1, x2)
-
-inst_892:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x0c2b2c and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xfc0c2b2c;
-   valaddr_reg:x3; val_offset:1784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1784*FLEN/8, x4, x1, x2)
-
-inst_893:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1786*FLEN/8, x4, x1, x2)
-
-inst_894:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1788*FLEN/8, x4, x1, x2)
-
-inst_895:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1790*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_8)
-
-inst_896:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x032b85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80032b85; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1792*FLEN/8, x4, x1, x2)
-
-inst_897:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x032b85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x80032b85;
-   valaddr_reg:x3; val_offset:1794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1794*FLEN/8, x4, x1, x2)
-
-inst_898:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x032b85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80032b85; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1796*FLEN/8, x4, x1, x2)
-
-inst_899:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x032b85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x80032b85;
-   valaddr_reg:x3; val_offset:1798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1798*FLEN/8, x4, x1, x2)
-
-inst_900:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1800*FLEN/8, x4, x1, x2)
-
-inst_901:
-// fs1 == 1 and fe1 == 0x80 and fm1 == 0x3a50eb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc03a50eb; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1802*FLEN/8, x4, x1, x2)
-
-inst_902:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3a50eb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc03a50eb;
-   valaddr_reg:x3; val_offset:1804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1804*FLEN/8, x4, x1, x2)
-
-inst_903:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3a50eb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xc03a50eb;
-   valaddr_reg:x3; val_offset:1806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1806*FLEN/8, x4, x1, x2)
-
-inst_904:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1808*FLEN/8, x4, x1, x2)
-
-inst_905:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1810*FLEN/8, x4, x1, x2)
-
-inst_906:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1812*FLEN/8, x4, x1, x2)
-
-inst_907:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1814*FLEN/8, x4, x1, x2)
-
-inst_908:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1816*FLEN/8, x4, x1, x2)
-
-inst_909:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1818*FLEN/8, x4, x1, x2)
-
-inst_910:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x048fde and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe048fde; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1820*FLEN/8, x4, x1, x2)
-
-inst_911:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x048fde and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xfe048fde;
-   valaddr_reg:x3; val_offset:1822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1822*FLEN/8, x4, x1, x2)
-
-inst_912:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1824*FLEN/8, x4, x1, x2)
-
-inst_913:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1826*FLEN/8, x4, x1, x2)
-
-inst_914:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x048fde and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe048fde; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1828*FLEN/8, x4, x1, x2)
-
-inst_915:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1830*FLEN/8, x4, x1, x2)
-
-inst_916:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1832*FLEN/8, x4, x1, x2)
-
-inst_917:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1834*FLEN/8, x4, x1, x2)
-
-inst_918:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x048fde and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe048fde; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1836*FLEN/8, x4, x1, x2)
-
-inst_919:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1838*FLEN/8, x4, x1, x2)
-
-inst_920:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x541963 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc541963; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1840*FLEN/8, x4, x1, x2)
-
-inst_921:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x541963 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xfc541963;
-   valaddr_reg:x3; val_offset:1842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1842*FLEN/8, x4, x1, x2)
-
-inst_922:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1844*FLEN/8, x4, x1, x2)
-
-inst_923:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04cbf8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8004cbf8; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1846*FLEN/8, x4, x1, x2)
-
-inst_924:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04cbf8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x8004cbf8;
-   valaddr_reg:x3; val_offset:1848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1848*FLEN/8, x4, x1, x2)
-
-inst_925:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04cbf8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8004cbf8; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1850*FLEN/8, x4, x1, x2)
-
-inst_926:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04cbf8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x8004cbf8;
-   valaddr_reg:x3; val_offset:1852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1852*FLEN/8, x4, x1, x2)
-
-inst_927:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1854*FLEN/8, x4, x1, x2)
-
-inst_928:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x0cf6cd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc08cf6cd; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1856*FLEN/8, x4, x1, x2)
-
-inst_929:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0cf6cd and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc08cf6cd;
-   valaddr_reg:x3; val_offset:1858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1858*FLEN/8, x4, x1, x2)
-
-inst_930:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0cf6cd and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xc08cf6cd;
-   valaddr_reg:x3; val_offset:1860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1860*FLEN/8, x4, x1, x2)
-
-inst_931:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1862*FLEN/8, x4, x1, x2)
-
-inst_932:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1864*FLEN/8, x4, x1, x2)
-
-inst_933:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1866*FLEN/8, x4, x1, x2)
-
-inst_934:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1868*FLEN/8, x4, x1, x2)
-
-inst_935:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1870*FLEN/8, x4, x1, x2)
-
-inst_936:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1872*FLEN/8, x4, x1, x2)
-
-inst_937:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2d09bb and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2d09bb; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1874*FLEN/8, x4, x1, x2)
-
-inst_938:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2d09bb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xfe2d09bb;
-   valaddr_reg:x3; val_offset:1876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1876*FLEN/8, x4, x1, x2)
-
-inst_939:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1878*FLEN/8, x4, x1, x2)
-
-inst_940:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1880*FLEN/8, x4, x1, x2)
-
-inst_941:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2d09bb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2d09bb; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1882*FLEN/8, x4, x1, x2)
-
-inst_942:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1884*FLEN/8, x4, x1, x2)
-
-inst_943:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1886*FLEN/8, x4, x1, x2)
-
-inst_944:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1888*FLEN/8, x4, x1, x2)
-
-inst_945:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2d09bb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2d09bb; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1890*FLEN/8, x4, x1, x2)
-
-inst_946:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1892*FLEN/8, x4, x1, x2)
-
-inst_947:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x0a6e2f and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc8a6e2f; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1894*FLEN/8, x4, x1, x2)
-
-inst_948:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x0a6e2f and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xfc8a6e2f;
-   valaddr_reg:x3; val_offset:1896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1896*FLEN/8, x4, x1, x2)
-
-inst_949:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1898*FLEN/8, x4, x1, x2)
-
-inst_950:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1900*FLEN/8, x4, x1, x2)
-
-inst_951:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1902*FLEN/8, x4, x1, x2)
-
-inst_952:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1904*FLEN/8, x4, x1, x2)
-
-inst_953:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1906*FLEN/8, x4, x1, x2)
-
-inst_954:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1908*FLEN/8, x4, x1, x2)
-
-inst_955:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1910*FLEN/8, x4, x1, x2)
-
-inst_956:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1912*FLEN/8, x4, x1, x2)
-
-inst_957:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1914*FLEN/8, x4, x1, x2)
-
-inst_958:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1916*FLEN/8, x4, x1, x2)
-
-inst_959:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1918*FLEN/8, x4, x1, x2)
-
-inst_960:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1920*FLEN/8, x4, x1, x2)
-
-inst_961:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1922*FLEN/8, x4, x1, x2)
-
-inst_962:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1924*FLEN/8, x4, x1, x2)
-
-inst_963:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1926*FLEN/8, x4, x1, x2)
-
-inst_964:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1928*FLEN/8, x4, x1, x2)
-
-inst_965:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1930*FLEN/8, x4, x1, x2)
-
-inst_966:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1932*FLEN/8, x4, x1, x2)
-
-inst_967:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1934*FLEN/8, x4, x1, x2)
-
-inst_968:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1936*FLEN/8, x4, x1, x2)
-
-inst_969:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x38016d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc0b8016d; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1938*FLEN/8, x4, x1, x2)
-
-inst_970:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x38016d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc0b8016d;
-   valaddr_reg:x3; val_offset:1940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1940*FLEN/8, x4, x1, x2)
-
-inst_971:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0x81 and fm2 == 0x38016d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xc0b8016d;
-   valaddr_reg:x3; val_offset:1942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1942*FLEN/8, x4, x1, x2)
-
-inst_972:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1944*FLEN/8, x4, x1, x2)
-
-inst_973:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1946*FLEN/8, x4, x1, x2)
-
-inst_974:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1948*FLEN/8, x4, x1, x2)
-
-inst_975:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1950*FLEN/8, x4, x1, x2)
-
-inst_976:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1952*FLEN/8, x4, x1, x2)
-
-inst_977:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1954*FLEN/8, x4, x1, x2)
-
-inst_978:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1956*FLEN/8, x4, x1, x2)
-
-inst_979:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1958*FLEN/8, x4, x1, x2)
-
-inst_980:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1960*FLEN/8, x4, x1, x2)
-
-inst_981:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1962*FLEN/8, x4, x1, x2)
-
-inst_982:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1964*FLEN/8, x4, x1, x2)
-
-inst_983:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1966*FLEN/8, x4, x1, x2)
-
-inst_984:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1968*FLEN/8, x4, x1, x2)
-
-inst_985:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1970*FLEN/8, x4, x1, x2)
-
-inst_986:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1972*FLEN/8, x4, x1, x2)
-
-inst_987:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1974*FLEN/8, x4, x1, x2)
-
-inst_988:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1976*FLEN/8, x4, x1, x2)
-
-inst_989:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1978*FLEN/8, x4, x1, x2)
-
-inst_990:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1980*FLEN/8, x4, x1, x2)
-
-inst_991:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1982*FLEN/8, x4, x1, x2)
-
-inst_992:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1984*FLEN/8, x4, x1, x2)
-
-inst_993:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1986*FLEN/8, x4, x1, x2)
-
-inst_994:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1988*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2132943109,32,FLEN)
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-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4284154742,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(4284154742,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(4284154742,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2125923170,32,FLEN)
-NAN_BOXED(4284154742,32,FLEN)
-NAN_BOXED(2125923170,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(4256118264,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(4256118264,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2133765080,32,FLEN)
-NAN_BOXED(4284154742,32,FLEN)
-NAN_BOXED(2133765080,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(4256118264,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(4276388186,32,FLEN)
-NAN_BOXED(4284154742,32,FLEN)
-NAN_BOXED(4276388186,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(4271897397,32,FLEN)
-NAN_BOXED(4284154742,32,FLEN)
-NAN_BOXED(4271897397,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(4256118264,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(4228655916,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(4228655916,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2147691397,32,FLEN)
-NAN_BOXED(2151587109,32,FLEN)
-NAN_BOXED(2151587109,32,FLEN)
-NAN_BOXED(2147691397,32,FLEN)
-NAN_BOXED(2147691397,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2147691397,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3225047275,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3225047275,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(3225047275,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2125923170,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(4261711838,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(4261711838,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2133765080,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(4261711838,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(4276388186,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(4271897397,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(4261711838,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(4233369955,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(4233369955,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2147798008,32,FLEN)
-NAN_BOXED(2151587109,32,FLEN)
-NAN_BOXED(2151587109,32,FLEN)
-NAN_BOXED(2147798008,32,FLEN)
-NAN_BOXED(2147798008,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2147798008,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3230463693,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3230463693,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(3230463693,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2125923170,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(4264364475,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(4264364475,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2133765080,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(4264364475,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(4276388186,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(4271897397,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(4264364475,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(4236930607,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(4236930607,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(1764005,32,FLEN)
-NAN_BOXED(2151587109,32,FLEN)
-NAN_BOXED(1764005,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2151587109,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(3287489,32,FLEN)
-NAN_BOXED(2151587109,32,FLEN)
-NAN_BOXED(3287489,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(3808901,32,FLEN)
-NAN_BOXED(2151587109,32,FLEN)
-NAN_BOXED(3808901,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2593627,32,FLEN)
-NAN_BOXED(2151587109,32,FLEN)
-NAN_BOXED(2593627,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(3398297,32,FLEN)
-NAN_BOXED(2151587109,32,FLEN)
-NAN_BOXED(3398297,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2150591976,32,FLEN)
-NAN_BOXED(2151587109,32,FLEN)
-NAN_BOXED(2150591976,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2150405766,32,FLEN)
-NAN_BOXED(2151587109,32,FLEN)
-NAN_BOXED(2150405766,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2151587109,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2151587109,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3233284461,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3233284461,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(3233284461,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2125923170,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2133765080,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4276388186,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4271897397,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1764005,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3287489,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3808901,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2593627,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3398297,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2150591976,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2150405766,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2125923170,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_7:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_8:
-    .fill 198*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fround_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fround_b1-01.S
deleted file mode 100644
index 80b42df62..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/F_Zfa/src/fround_b1-01.S
+++ /dev/null
@@ -1,353 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:11:44 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fround.s.cgf \
- \
-//                  -- xlen 32  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fround.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fround_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fround_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f31, f30, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f29; dest:f29; op1val:0x80000000; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f29, f29, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f31; dest:f30; op1val:0x1; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f30, f31, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f28, f27, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f27, f28, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f25; dest:f26; op1val:0x807ffffe; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f26, f25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f26; dest:f25; op1val:0x7fffff; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f25, f26, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f23; dest:f24; op1val:0x807fffff; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f24, f23, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f23, f24, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f22, f21, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f22; dest:f21; op1val:0x800001; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f21, f22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f19; dest:f20; op1val:0x80855555; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f20, f19, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f20; dest:f19; op1val:0x7f7fffff; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f19, f20, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f17; dest:f18; op1val:0xff7fffff; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f18, f17, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f18; dest:f17; op1val:0x7f800000; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f17, f18, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f15; dest:f16; op1val:0xff800000; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f16, f15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f16; dest:f15; op1val:0x7fc00000; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f15, f16, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f13; dest:f14; op1val:0xffc00000; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f14, f13, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f14; dest:f13; op1val:0x7fc00001; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f13, f14, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f11; dest:f12; op1val:0xffc55555; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f12, f11, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f12; dest:f11; op1val:0x7f800001; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f11, f12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f9; dest:f10; op1val:0xffaaaaaa; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f10, f9, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f10; dest:f9; op1val:0x3f800000; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f9, f10, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f7; dest:f8; op1val:0xbf800000; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f8, f7, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f8, rd==f7,
-/* opcode: fround.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
-val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f7, f8, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f5, rd==f6,
-/* opcode: fround.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
-val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f6, f5, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f6, rd==f5,
-/* opcode: fround.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
-val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f5, f6, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rd==f4,
-/* opcode: fround.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
-val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f4, f3, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f4, rd==f3,
-/* opcode: fround.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
-val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f3, f4, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f1, rd==f2,
-/* opcode: fround.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
-val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f2, f1, dyn, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f2, rd==f1,
-/* opcode: fround.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
-val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f1, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f0,
-/* opcode: fround.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
-val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f31, f0, dyn, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rd==f0,
-/* opcode: fround.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
-val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f0, f31, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 66*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S
deleted file mode 100644
index 0caafa1c1..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b1-01.S
+++ /dev/null
@@ -1,320 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:56 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x8000000000000000; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x1; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x8000000000000001; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x2; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x8000000000000002; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0xfffffffffffff; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0x800fffffffffffff; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x10000000000000; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x8010000000000000; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x10000000000002; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x8010000000000002; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x7fefffffffffffff; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0xffefffffffffffff; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x7ff0000000000000; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0xfff0000000000000; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
-
-inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0x7ff8000000000000; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
-
-inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0xfff8000000000000; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
-
-inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0x7ff8000000000001; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
-
-inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0xfff8000000000001; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
-
-inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0x7ff0000000000001; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
-
-inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0xfff0000000000001; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
-
-inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0x3ff0000000000000; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
-
-inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0xbf80000000000000; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,
-/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
-
-inst_25:// rs1==f6, rd==x6,
-/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
-
-inst_26:// rs1==f5, rd==x5,
-/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,
-/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
-
-inst_28:// rs1==f3, rd==x3,
-/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
-
-inst_29:// rs1==f2, rd==x2,
-/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
-
-inst_30:// rs1==f1, rd==x1,
-/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
-
-inst_31:// rs1==f0, rd==x0,
-/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-test_dataset_1:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 10*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S
deleted file mode 100644
index d8b5fe24a..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b22-01.S
+++ /dev/null
@@ -1,383 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:56 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b22 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b22)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08577924770d3 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08577924770d3; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fd and fm1 == 0x93fdc7b89296c and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x3fd93fdc7b89296c; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 1 and fe1 == 0x3fe and fm1 == 0x766ba34c2da80 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0xbfe766ba34c2da80; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xd2d6b7dc59a3a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x3ffd2d6b7dc59a3a; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x400 and fm1 == 0xcf84ba749f9c5 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x400cf84ba749f9c5; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x401 and fm1 == 0x854a908ceac39 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x401854a908ceac39; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x402 and fm1 == 0x137a953e8eb43 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x402137a953e8eb43; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x403 and fm1 == 0xf3ebcf3d06f86 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0xc03f3ebcf3d06f86; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x404 and fm1 == 0x5c74eff1e5bef and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x4045c74eff1e5bef; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x405 and fm1 == 0xdc3386b9f15c4 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x405dc3386b9f15c4; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x406 and fm1 == 0x5ae6a9a6ab329 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x4065ae6a9a6ab329; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x407 and fm1 == 0x489b36bd7f503 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0xc07489b36bd7f503; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x408 and fm1 == 0x43277acca7f0d and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x40843277acca7f0d; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x409 and fm1 == 0xaf9492cb7362c and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x409af9492cb7362c; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x40a and fm1 == 0x5cd28a96ec2b3 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x40a5cd28a96ec2b3; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x40b and fm1 == 0xc491074f942cb and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0xc0bc491074f942cb; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
-
-inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x40c and fm1 == 0x3d480fb7f6f5d and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0xc0c3d480fb7f6f5d; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
-
-inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x40d and fm1 == 0x9d02f708cc1b6 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0x40d9d02f708cc1b6; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
-
-inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x40e and fm1 == 0x953b00b54aa22 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0x40e953b00b54aa22; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
-
-inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x40f and fm1 == 0x224c03c53d0e3 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0x40f224c03c53d0e3; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
-
-inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x410 and fm1 == 0xe8dacf0e58650 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0x410e8dacf0e58650; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
-
-inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x411 and fm1 == 0x5dbbb894deab4 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0xc115dbbb894deab4; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
-
-inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x412 and fm1 == 0x3d7c9e5f0307e and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0x4123d7c9e5f0307e; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
-
-inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x413 and fm1 == 0x8c8a1aaac3142 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0x4138c8a1aaac3142; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x414 and fm1 == 0x785036f9fb997 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0x414785036f9fb997; valaddr_reg:x8;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
-
-inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x415 and fm1 == 0x95a4da7298c66 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x41595a4da7298c66; valaddr_reg:x8;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
-
-inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x416 and fm1 == 0x807dad814d575 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x416807dad814d575; valaddr_reg:x8;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x417 and fm1 == 0x396bad798c9cf and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0xc17396bad798c9cf; valaddr_reg:x8;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
-
-inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x418 and fm1 == 0x3d06169b1dcbf and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x4183d06169b1dcbf; valaddr_reg:x8;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
-
-inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x419 and fm1 == 0x7f21608208d09 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x4197f21608208d09; valaddr_reg:x8;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
-
-inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x41a and fm1 == 0x9b4f3d167533a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0xc1a9b4f3d167533a; valaddr_reg:x8;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
-
-inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x41b and fm1 == 0x889261270dee2 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0xc1b889261270dee2; valaddr_reg:x8;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
-
-inst_32:// fs1 == 0 and fe1 == 0x41c and fm1 == 0x14b91dae98554 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x41c14b91dae98554; valaddr_reg:x8;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
-
-inst_33:// fs1 == 1 and fe1 == 0x41d and fm1 == 0x9136562694646 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xc1d9136562694646; valaddr_reg:x8;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
-
-inst_34:// fs1 == 1 and fe1 == 0x41e and fm1 == 0xe9b7e5fc9eba4 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xc1ee9b7e5fc9eba4; valaddr_reg:x8;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
-
-inst_35:// fs1 == 1 and fe1 == 0x41f and fm1 == 0x1ce80265039f6 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xc1f1ce80265039f6; valaddr_reg:x8;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
-
-inst_36:// fs1 == 0 and fe1 == 0x420 and fm1 == 0xc5ec6c6880007 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x420c5ec6c6880007; valaddr_reg:x8;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
-
-inst_37:// fs1 == 1 and fe1 == 0x421 and fm1 == 0x2a96d71097999 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xc212a96d71097999; valaddr_reg:x8;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
-
-inst_38:// fs1 == 0 and fe1 == 0x3ca and fm1 == 0x30e08ceb506f6 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ca30e08ceb506f6; valaddr_reg:x8;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
-
-inst_39:// fs1 == 0 and fe1 == 0x5ca and fm1 == 0xf871c6ee84270 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x5caf871c6ee84270; valaddr_reg:x8;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
-
-inst_40:// fs1 == 1 and fe1 == 0x41b and fm1 == 0x889261270dee2 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xc1b889261270dee2; valaddr_reg:x8;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(4593818368519663827,64,FLEN)
-NAN_BOXED(4600778710533613932,64,FLEN)
-NAN_BOXED(13828134130799532672,64,FLEN)
-NAN_BOXED(4610891533192108602,64,FLEN)
-NAN_BOXED(4615336721960794565,64,FLEN)
-NAN_BOXED(4618534502842412089,64,FLEN)
-NAN_BOXED(4621035893055613763,64,FLEN)
-NAN_BOXED(13852859960080232326,64,FLEN)
-NAN_BOXED(4631326933921979375,64,FLEN)
-NAN_BOXED(4638077838352651716,64,FLEN)
-NAN_BOXED(4640306763955614505,64,FLEN)
-NAN_BOXED(13867860556282066179,64,FLEN)
-NAN_BOXED(4648896204934643469,64,FLEN)
-NAN_BOXED(4655307257518962220,64,FLEN)
-NAN_BOXED(4658354964109640371,64,FLEN)
-NAN_BOXED(13888055685934564043,64,FLEN)
-NAN_BOXED(13890179326181076829,64,FLEN)
-NAN_BOXED(4672994990543913398,64,FLEN)
-NAN_BOXED(4677361703570418210,64,FLEN)
-NAN_BOXED(4679843370855813347,64,FLEN)
-NAN_BOXED(4687840036054730320,64,FLEN)
-NAN_BOXED(13913268222339967668,64,FLEN)
-NAN_BOXED(4693832498796310654,64,FLEN)
-NAN_BOXED(4699726807839813954,64,FLEN)
-test_dataset_1:
-NAN_BOXED(4703874585615907223,64,FLEN)
-NAN_BOXED(4708894174956063846,64,FLEN)
-NAN_BOXED(4713025646552733045,64,FLEN)
-NAN_BOXED(13939651000867015119,64,FLEN)
-NAN_BOXED(4720845951218080959,64,FLEN)
-NAN_BOXED(4726512510388178185,64,FLEN)
-NAN_BOXED(13954883879667454778,64,FLEN)
-NAN_BOXED(13959057841646001890,64,FLEN)
-NAN_BOXED(4738151372785550676,64,FLEN)
-NAN_BOXED(13968217045429995078,64,FLEN)
-NAN_BOXED(13974277660852480932,64,FLEN)
-NAN_BOXED(13975178168501287414,64,FLEN)
-NAN_BOXED(4759283114051108871,64,FLEN)
-NAN_BOXED(13984426080451787161,64,FLEN)
-NAN_BOXED(4369351494470010614,64,FLEN)
-NAN_BOXED(6678705328603284080,64,FLEN)
-NAN_BOXED(13959057841646001890,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 28*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S
deleted file mode 100644
index aff8f51be..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b23-01.S
+++ /dev/null
@@ -1,418 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:56 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b23 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b23)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43dffffffffffffc; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x43dffffffffffffc; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x43dffffffffffffc; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x43dffffffffffffc; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x43dffffffffffffc; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x43dffffffffffffd; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x43dffffffffffffd; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0x43dffffffffffffd; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x43dffffffffffffd; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x43dffffffffffffd; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x43dffffffffffffe; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x43dffffffffffffe; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x43dffffffffffffe; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x43dffffffffffffe; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x43dffffffffffffe; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0x43dfffffffffffff; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
-
-inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0x43dfffffffffffff; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
-
-inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0x43dfffffffffffff; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
-
-inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0x43dfffffffffffff; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
-
-inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0x43dfffffffffffff; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
-
-inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0x43e0000000000000; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
-
-inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0x43e0000000000000; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
-
-inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0x43e0000000000000; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
-
-inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0x43e0000000000000; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0x43e0000000000000; valaddr_reg:x8;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
-
-inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x43e0000000000001; valaddr_reg:x8;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
-
-inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x43e0000000000001; valaddr_reg:x8;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0x43e0000000000001; valaddr_reg:x8;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
-
-inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x43e0000000000001; valaddr_reg:x8;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
-
-inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x43e0000000000001; valaddr_reg:x8;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
-
-inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x43e0000000000002; valaddr_reg:x8;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
-
-inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x43e0000000000002; valaddr_reg:x8;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
-
-inst_32:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x8;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
-
-inst_33:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x8;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
-
-inst_34:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x8;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
-
-inst_35:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x8;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
-
-inst_36:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x8;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
-
-inst_37:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x8;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
-
-inst_38:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x8;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
-
-inst_39:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x8;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
-
-inst_40:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x8;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
-
-inst_41:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x8;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
-
-inst_42:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x8;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
-
-inst_43:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x8;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
-
-inst_44:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x8;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
-
-inst_45:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x8;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(4890909195324358652,64,FLEN)
-NAN_BOXED(4890909195324358652,64,FLEN)
-NAN_BOXED(4890909195324358652,64,FLEN)
-NAN_BOXED(4890909195324358652,64,FLEN)
-NAN_BOXED(4890909195324358652,64,FLEN)
-NAN_BOXED(4890909195324358653,64,FLEN)
-NAN_BOXED(4890909195324358653,64,FLEN)
-NAN_BOXED(4890909195324358653,64,FLEN)
-NAN_BOXED(4890909195324358653,64,FLEN)
-NAN_BOXED(4890909195324358653,64,FLEN)
-NAN_BOXED(4890909195324358654,64,FLEN)
-NAN_BOXED(4890909195324358654,64,FLEN)
-NAN_BOXED(4890909195324358654,64,FLEN)
-NAN_BOXED(4890909195324358654,64,FLEN)
-NAN_BOXED(4890909195324358654,64,FLEN)
-NAN_BOXED(4890909195324358655,64,FLEN)
-NAN_BOXED(4890909195324358655,64,FLEN)
-NAN_BOXED(4890909195324358655,64,FLEN)
-NAN_BOXED(4890909195324358655,64,FLEN)
-NAN_BOXED(4890909195324358655,64,FLEN)
-NAN_BOXED(4890909195324358656,64,FLEN)
-NAN_BOXED(4890909195324358656,64,FLEN)
-NAN_BOXED(4890909195324358656,64,FLEN)
-NAN_BOXED(4890909195324358656,64,FLEN)
-test_dataset_1:
-NAN_BOXED(4890909195324358656,64,FLEN)
-NAN_BOXED(4890909195324358657,64,FLEN)
-NAN_BOXED(4890909195324358657,64,FLEN)
-NAN_BOXED(4890909195324358657,64,FLEN)
-NAN_BOXED(4890909195324358657,64,FLEN)
-NAN_BOXED(4890909195324358657,64,FLEN)
-NAN_BOXED(4890909195324358658,64,FLEN)
-NAN_BOXED(4890909195324358658,64,FLEN)
-NAN_BOXED(4890909195324358658,64,FLEN)
-NAN_BOXED(4890909195324358658,64,FLEN)
-NAN_BOXED(4890909195324358658,64,FLEN)
-NAN_BOXED(4890909195324358659,64,FLEN)
-NAN_BOXED(4890909195324358659,64,FLEN)
-NAN_BOXED(4890909195324358659,64,FLEN)
-NAN_BOXED(4890909195324358659,64,FLEN)
-NAN_BOXED(4890909195324358659,64,FLEN)
-NAN_BOXED(4890909195324358660,64,FLEN)
-NAN_BOXED(4890909195324358660,64,FLEN)
-NAN_BOXED(4890909195324358660,64,FLEN)
-NAN_BOXED(4890909195324358660,64,FLEN)
-NAN_BOXED(4890909195324358660,64,FLEN)
-NAN_BOXED(4890909195324358658,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 38*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S
deleted file mode 100644
index 93b0a40be..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b24-01.S
+++ /dev/null
@@ -1,838 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:56 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b24 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b24)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfb999999999999a; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0xbfb999999999999a; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0xbfb999999999999a; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0xbfb999999999999a; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0xbfb999999999999a; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x3fefae147ae147ae; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x3fefae147ae147ae; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0x3fefae147ae147ae; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x3fefae147ae147ae; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x3fefae147ae147ae; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0xbfefae147ae147ae; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
-
-inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0xbfefae147ae147ae; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
-
-inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0xbfefae147ae147ae; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
-
-inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0xbfefae147ae147ae; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
-
-inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0xbfefae147ae147ae; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
-
-inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0xbf847ae147ae147b; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
-
-inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0xbf847ae147ae147b; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
-
-inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0xbf847ae147ae147b; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
-
-inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0xbf847ae147ae147b; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0xbf847ae147ae147b; valaddr_reg:x8;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
-
-inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x3feccccccccccccd; valaddr_reg:x8;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
-
-inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x3feccccccccccccd; valaddr_reg:x8;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0x3feccccccccccccd; valaddr_reg:x8;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
-
-inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x3feccccccccccccd; valaddr_reg:x8;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
-
-inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x3feccccccccccccd; valaddr_reg:x8;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
-
-inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x3ff199999999999a; valaddr_reg:x8;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
-
-inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x3ff199999999999a; valaddr_reg:x8;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
-
-inst_32:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x8;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
-
-inst_33:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x8;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
-
-inst_34:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x8;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
-
-inst_35:// fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3f847ae147ae147b; valaddr_reg:x8;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
-
-inst_36:// fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3f847ae147ae147b; valaddr_reg:x8;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
-
-inst_37:// fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3f847ae147ae147b; valaddr_reg:x8;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
-
-inst_38:// fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3f847ae147ae147b; valaddr_reg:x8;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
-
-inst_39:// fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3f847ae147ae147b; valaddr_reg:x8;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
-
-inst_40:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x8;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
-
-inst_41:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x8;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
-
-inst_42:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x8;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
-
-inst_43:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x8;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
-
-inst_44:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x8;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
-
-inst_45:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x8;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
-
-inst_46:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x8;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)
-
-inst_47:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x8;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)
-
-inst_48:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x8;
-val_offset:24*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)
-
-inst_49:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x8;
-val_offset:25*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)
-
-inst_50:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x8;
-val_offset:26*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)
-
-inst_51:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x8;
-val_offset:27*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)
-
-inst_52:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x8;
-val_offset:28*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)
-
-inst_53:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x8;
-val_offset:29*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)
-
-inst_54:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x8;
-val_offset:30*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)
-
-inst_55:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x8;
-val_offset:31*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)
-
-inst_56:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x8;
-val_offset:32*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)
-
-inst_57:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x8;
-val_offset:33*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)
-
-inst_58:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x8;
-val_offset:34*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)
-
-inst_59:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x8;
-val_offset:35*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)
-
-inst_60:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x8;
-val_offset:36*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)
-
-inst_61:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x8;
-val_offset:37*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)
-
-inst_62:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x8;
-val_offset:38*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)
-
-inst_63:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x8;
-val_offset:39*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)
-
-inst_64:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x8;
-val_offset:40*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)
-
-inst_65:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x8;
-val_offset:41*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)
-
-inst_66:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x8;
-val_offset:42*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)
-
-inst_67:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x8;
-val_offset:43*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)
-
-inst_68:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x8;
-val_offset:44*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)
-
-inst_69:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x8;
-val_offset:45*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)
-
-inst_70:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x8;
-val_offset:46*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)
-
-inst_71:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x8;
-val_offset:47*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)
-
-inst_72:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x8;
-val_offset:48*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)
-
-inst_73:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x8;
-val_offset:49*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)
-
-inst_74:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x8;
-val_offset:50*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)
-
-inst_75:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x8;
-val_offset:51*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)
-
-inst_76:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x8;
-val_offset:52*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)
-
-inst_77:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x8;
-val_offset:53*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)
-
-inst_78:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x8;
-val_offset:54*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)
-
-inst_79:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x8;
-val_offset:55*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)
-
-inst_80:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fec7ae147ae147b; valaddr_reg:x8;
-val_offset:56*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)
-
-inst_81:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fec7ae147ae147b; valaddr_reg:x8;
-val_offset:57*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 57*FLEN/8, x9, x5, x6,FLREG)
-
-inst_82:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fec7ae147ae147b; valaddr_reg:x8;
-val_offset:58*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 58*FLEN/8, x9, x5, x6,FLREG)
-
-inst_83:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fec7ae147ae147b; valaddr_reg:x8;
-val_offset:59*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 59*FLEN/8, x9, x5, x6,FLREG)
-
-inst_84:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fec7ae147ae147b; valaddr_reg:x8;
-val_offset:60*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 60*FLEN/8, x9, x5, x6,FLREG)
-
-inst_85:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fb999999999999a; valaddr_reg:x8;
-val_offset:61*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 61*FLEN/8, x9, x5, x6,FLREG)
-
-inst_86:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fb999999999999a; valaddr_reg:x8;
-val_offset:62*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 62*FLEN/8, x9, x5, x6,FLREG)
-
-inst_87:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fb999999999999a; valaddr_reg:x8;
-val_offset:63*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 63*FLEN/8, x9, x5, x6,FLREG)
-
-inst_88:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fb999999999999a; valaddr_reg:x8;
-val_offset:64*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 64*FLEN/8, x9, x5, x6,FLREG)
-
-inst_89:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fb999999999999a; valaddr_reg:x8;
-val_offset:65*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 65*FLEN/8, x9, x5, x6,FLREG)
-
-inst_90:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x8;
-val_offset:66*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 66*FLEN/8, x9, x5, x6,FLREG)
-
-inst_91:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x8;
-val_offset:67*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 67*FLEN/8, x9, x5, x6,FLREG)
-
-inst_92:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x8;
-val_offset:68*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 68*FLEN/8, x9, x5, x6,FLREG)
-
-inst_93:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x8;
-val_offset:69*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 69*FLEN/8, x9, x5, x6,FLREG)
-
-inst_94:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x8;
-val_offset:70*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 70*FLEN/8, x9, x5, x6,FLREG)
-
-inst_95:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x8;
-val_offset:71*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 71*FLEN/8, x9, x5, x6,FLREG)
-
-inst_96:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x8;
-val_offset:72*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 72*FLEN/8, x9, x5, x6,FLREG)
-
-inst_97:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x8;
-val_offset:73*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 73*FLEN/8, x9, x5, x6,FLREG)
-
-inst_98:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x8;
-val_offset:74*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 74*FLEN/8, x9, x5, x6,FLREG)
-
-inst_99:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x8;
-val_offset:75*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 75*FLEN/8, x9, x5, x6,FLREG)
-
-inst_100:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x8;
-val_offset:76*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 76*FLEN/8, x9, x5, x6,FLREG)
-
-inst_101:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x8;
-val_offset:77*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 77*FLEN/8, x9, x5, x6,FLREG)
-
-inst_102:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x8;
-val_offset:78*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 78*FLEN/8, x9, x5, x6,FLREG)
-
-inst_103:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x8;
-val_offset:79*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 79*FLEN/8, x9, x5, x6,FLREG)
-
-inst_104:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x8;
-val_offset:80*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 80*FLEN/8, x9, x5, x6,FLREG)
-
-inst_105:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x8;
-val_offset:81*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 81*FLEN/8, x9, x5, x6,FLREG)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(13815242216921733530,64,FLEN)
-NAN_BOXED(13815242216921733530,64,FLEN)
-NAN_BOXED(13815242216921733530,64,FLEN)
-NAN_BOXED(13815242216921733530,64,FLEN)
-NAN_BOXED(13815242216921733530,64,FLEN)
-NAN_BOXED(4607092346807469998,64,FLEN)
-NAN_BOXED(4607092346807469998,64,FLEN)
-NAN_BOXED(4607092346807469998,64,FLEN)
-NAN_BOXED(4607092346807469998,64,FLEN)
-NAN_BOXED(4607092346807469998,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13830464383662245806,64,FLEN)
-NAN_BOXED(13830464383662245806,64,FLEN)
-NAN_BOXED(13830464383662245806,64,FLEN)
-NAN_BOXED(13830464383662245806,64,FLEN)
-NAN_BOXED(13830464383662245806,64,FLEN)
-NAN_BOXED(13800290266158863483,64,FLEN)
-NAN_BOXED(13800290266158863483,64,FLEN)
-NAN_BOXED(13800290266158863483,64,FLEN)
-NAN_BOXED(13800290266158863483,64,FLEN)
-test_dataset_1:
-NAN_BOXED(13800290266158863483,64,FLEN)
-NAN_BOXED(4606281698874543309,64,FLEN)
-NAN_BOXED(4606281698874543309,64,FLEN)
-NAN_BOXED(4606281698874543309,64,FLEN)
-NAN_BOXED(4606281698874543309,64,FLEN)
-NAN_BOXED(4606281698874543309,64,FLEN)
-NAN_BOXED(4607632778762754458,64,FLEN)
-NAN_BOXED(4607632778762754458,64,FLEN)
-NAN_BOXED(4607632778762754458,64,FLEN)
-NAN_BOXED(4607632778762754458,64,FLEN)
-NAN_BOXED(4607632778762754458,64,FLEN)
-NAN_BOXED(4576918229304087675,64,FLEN)
-NAN_BOXED(4576918229304087675,64,FLEN)
-NAN_BOXED(4576918229304087675,64,FLEN)
-NAN_BOXED(4576918229304087675,64,FLEN)
-NAN_BOXED(4576918229304087675,64,FLEN)
-NAN_BOXED(4592590756007337001,64,FLEN)
-NAN_BOXED(4592590756007337001,64,FLEN)
-NAN_BOXED(4592590756007337001,64,FLEN)
-NAN_BOXED(4592590756007337001,64,FLEN)
-NAN_BOXED(4592590756007337001,64,FLEN)
-NAN_BOXED(4607677814759028163,64,FLEN)
-NAN_BOXED(4607677814759028163,64,FLEN)
-NAN_BOXED(4607677814759028163,64,FLEN)
-NAN_BOXED(4607677814759028163,64,FLEN)
-NAN_BOXED(4607677814759028163,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13831049851613803971,64,FLEN)
-NAN_BOXED(13831049851613803971,64,FLEN)
-NAN_BOXED(13831049851613803971,64,FLEN)
-NAN_BOXED(13831049851613803971,64,FLEN)
-NAN_BOXED(13831049851613803971,64,FLEN)
-NAN_BOXED(4607227454796291113,64,FLEN)
-NAN_BOXED(4607227454796291113,64,FLEN)
-NAN_BOXED(4607227454796291113,64,FLEN)
-NAN_BOXED(4607227454796291113,64,FLEN)
-NAN_BOXED(4607227454796291113,64,FLEN)
-NAN_BOXED(13829563663736771707,64,FLEN)
-NAN_BOXED(13829563663736771707,64,FLEN)
-NAN_BOXED(13829563663736771707,64,FLEN)
-NAN_BOXED(13829563663736771707,64,FLEN)
-NAN_BOXED(13829563663736771707,64,FLEN)
-NAN_BOXED(13830554455654793216,64,FLEN)
-NAN_BOXED(13830554455654793216,64,FLEN)
-NAN_BOXED(13830554455654793216,64,FLEN)
-NAN_BOXED(13830554455654793216,64,FLEN)
-NAN_BOXED(13830554455654793216,64,FLEN)
-NAN_BOXED(13815962792862112809,64,FLEN)
-NAN_BOXED(13815962792862112809,64,FLEN)
-NAN_BOXED(13815962792862112809,64,FLEN)
-NAN_BOXED(13815962792862112809,64,FLEN)
-NAN_BOXED(13815962792862112809,64,FLEN)
-NAN_BOXED(4606191626881995899,64,FLEN)
-NAN_BOXED(4606191626881995899,64,FLEN)
-NAN_BOXED(4606191626881995899,64,FLEN)
-NAN_BOXED(4606191626881995899,64,FLEN)
-NAN_BOXED(4606191626881995899,64,FLEN)
-NAN_BOXED(4591870180066957722,64,FLEN)
-NAN_BOXED(4591870180066957722,64,FLEN)
-NAN_BOXED(4591870180066957722,64,FLEN)
-NAN_BOXED(4591870180066957722,64,FLEN)
-NAN_BOXED(4591870180066957722,64,FLEN)
-NAN_BOXED(13830599491651066921,64,FLEN)
-NAN_BOXED(13830599491651066921,64,FLEN)
-NAN_BOXED(13830599491651066921,64,FLEN)
-NAN_BOXED(13830599491651066921,64,FLEN)
-NAN_BOXED(13830599491651066921,64,FLEN)
-NAN_BOXED(13831004815617530266,64,FLEN)
-NAN_BOXED(13831004815617530266,64,FLEN)
-NAN_BOXED(13831004815617530266,64,FLEN)
-NAN_BOXED(13831004815617530266,64,FLEN)
-NAN_BOXED(13831004815617530266,64,FLEN)
-NAN_BOXED(13829653735729319117,64,FLEN)
-NAN_BOXED(13829653735729319117,64,FLEN)
-NAN_BOXED(13829653735729319117,64,FLEN)
-NAN_BOXED(13829653735729319117,64,FLEN)
-NAN_BOXED(13829653735729319117,64,FLEN)
-NAN_BOXED(4607632778762754458,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 158*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S
deleted file mode 100644
index 26bee9643..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b27-01.S
+++ /dev/null
@@ -1,320 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:56 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b27 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b27)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x7ff0000000000001; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0xfff0000000000001; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x7ff4aaaaaaaaaaaa; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0xfff4aaaaaaaaaaaa; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x7ff8000000000001; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0xfff8000000000001; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x7ff and fm1 == 0xc000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x7ffc000000000001; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x7ff and fm1 == 0xc000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0xfffc000000000001; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
-
-inst_8:// rs1==f23, rd==x23,
-/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x0; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
-
-inst_9:// rs1==f22, rd==x22,
-/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
-
-inst_10:// rs1==f21, rd==x21,
-/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
-
-inst_11:// rs1==f20, rd==x20,
-/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
-
-inst_12:// rs1==f19, rd==x19,
-/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
-
-inst_13:// rs1==f18, rd==x18,
-/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
-
-inst_14:// rs1==f17, rd==x17,
-/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
-
-inst_15:// rs1==f16, rd==x16,
-/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
-
-inst_16:// rs1==f15, rd==x15,
-/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
-
-inst_17:// rs1==f14, rd==x14,
-/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
-
-inst_18:// rs1==f13, rd==x13,
-/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
-
-inst_19:// rs1==f12, rd==x12,
-/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
-
-inst_20:// rs1==f11, rd==x11,
-/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
-
-inst_21:// rs1==f10, rd==x10,
-/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
-
-inst_22:// rs1==f9, rd==x9,
-/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
-
-inst_23:// rs1==f8, rd==x8,
-/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,
-/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
-
-inst_25:// rs1==f6, rd==x6,
-/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
-
-inst_26:// rs1==f5, rd==x5,
-/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,
-/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
-
-inst_28:// rs1==f3, rd==x3,
-/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
-
-inst_29:// rs1==f2, rd==x2,
-/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
-
-inst_30:// rs1==f1, rd==x1,
-/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
-
-inst_31:// rs1==f0, rd==x0,
-/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9220181987118721706,64,FLEN)
-NAN_BOXED(18443554023973497514,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9222246136947933185,64,FLEN)
-NAN_BOXED(18445618173802708993,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-test_dataset_1:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 10*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b28-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b28-01.S
deleted file mode 100644
index ef021bc66..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b28-01.S
+++ /dev/null
@@ -1,320 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:56 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b28 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b28)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fe and fm1 == 0x248ee18215dfa and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x3fe248ee18215dfa; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x3ff0000000000000; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x3ff4000000000000; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x3ff8000000000000; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xc000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x3ffc000000000000; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x400 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x4000000000000000; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x400 and fm1 == 0x2000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0x4002000000000000; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x400 and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x4004000000000000; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x400 and fm1 == 0x6000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x4006000000000000; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x43c and fm1 == 0xb72eb13dc494a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x43cb72eb13dc494a; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x43e0000000000000; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x7ff0000000000000; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x7ff0000000000001; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x7ff8000000000001; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0x8000000000000000; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
-
-inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x3fd and fm1 == 0xb008d57e19f88 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0xbfdb008d57e19f88; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
-
-inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0xbf80000000000000; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
-
-inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x400 and fm1 == 0x6000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0xc006000000000000; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
-
-inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x400 and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0xc004000000000000; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
-
-inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x400 and fm1 == 0x2000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0xc002000000000000; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
-
-inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x400 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0xc000000000000000; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
-
-inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x3ff and fm1 == 0xc000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0xbffc000000000000; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
-
-inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0xbff8000000000000; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x4000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0xbff4000000000000; valaddr_reg:x8;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
-
-inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x43d and fm1 == 0x967a4ae26514c and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0xc3d967a4ae26514c; valaddr_reg:x8;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
-
-inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x43e and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0xc3e0000000000000; valaddr_reg:x8;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0xfff0000000000000; valaddr_reg:x8;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
-
-inst_28:// rs1==f3, rd==x3,
-/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
-
-inst_29:// rs1==f2, rd==x2,
-/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
-
-inst_30:// rs1==f1, rd==x1,
-/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
-
-inst_31:// rs1==f0, rd==x0,
-/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(4603321956570324474,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4608308318706860032,64,FLEN)
-NAN_BOXED(4609434218613702656,64,FLEN)
-NAN_BOXED(4610560118520545280,64,FLEN)
-NAN_BOXED(4611686018427387904,64,FLEN)
-NAN_BOXED(4612248968380809216,64,FLEN)
-NAN_BOXED(4612811918334230528,64,FLEN)
-NAN_BOXED(4613374868287651840,64,FLEN)
-NAN_BOXED(4885124574789519690,64,FLEN)
-NAN_BOXED(4890909195324358656,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(13824644088208662408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13836746905142427648,64,FLEN)
-NAN_BOXED(13836183955189006336,64,FLEN)
-NAN_BOXED(13835621005235585024,64,FLEN)
-NAN_BOXED(13835058055282163712,64,FLEN)
-NAN_BOXED(13833932155375321088,64,FLEN)
-NAN_BOXED(13832806255468478464,64,FLEN)
-test_dataset_1:
-NAN_BOXED(13831680355561635840,64,FLEN)
-NAN_BOXED(14112424864336204108,64,FLEN)
-NAN_BOXED(14114281232179134464,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 10*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b29-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b29-01.S
deleted file mode 100644
index b28fb700a..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fcvtmod.w.d_b29-01.S
+++ /dev/null
@@ -1,663 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:56 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b29 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b29)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b8698; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
-
-inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x3fc08574923b8698; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
-
-inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x3fc08574923b8698; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
-
-inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x3fc08574923b8698; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
-
-inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x3fc08574923b8698; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
-
-inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x3fc08574923b8699; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
-
-inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x3fc08574923b8699; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
-
-inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0x3fc08574923b8699; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
-
-inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x3fc08574923b8699; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
-
-inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x3fc08574923b8699; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
-
-inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x3fc08574923b869a; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
-
-inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x3fc08574923b869a; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
-
-inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x3fc08574923b869a; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
-
-inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x3fc08574923b869a; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
-
-inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x3fc08574923b869a; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
-
-inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0x3fc08574923b869b; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
-
-inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0x3fc08574923b869b; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
-
-inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0x3fc08574923b869b; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
-
-inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0x3fc08574923b869b; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
-
-inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0x3fc08574923b869b; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
-
-inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0x3fc08574923b869c; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
-
-inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0x3fc08574923b869c; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
-
-inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0x3fc08574923b869c; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
-
-inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0x3fc08574923b869c; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
-RVTEST_VALBASEUPD(x8,test_dataset_1)
-
-inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0x3fc08574923b869c; valaddr_reg:x8;
-val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
-
-inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x3fc08574923b869d; valaddr_reg:x8;
-val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
-
-inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x3fc08574923b869d; valaddr_reg:x8;
-val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
-RVTEST_SIGBASE(x5,signature_x5_0)
-
-inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0x3fc08574923b869d; valaddr_reg:x8;
-val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
-
-inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x3fc08574923b869d; valaddr_reg:x8;
-val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
-
-inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x3fc08574923b869d; valaddr_reg:x8;
-val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
-
-inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x3fc08574923b869e; valaddr_reg:x8;
-val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
-
-inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x3fc08574923b869e; valaddr_reg:x8;
-val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
-
-inst_32:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x8;
-val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
-
-inst_33:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x8;
-val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
-
-inst_34:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x8;
-val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
-
-inst_35:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x8;
-val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
-
-inst_36:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x8;
-val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
-
-inst_37:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x8;
-val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
-
-inst_38:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x8;
-val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
-
-inst_39:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x8;
-val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
-
-inst_40:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x8;
-val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
-
-inst_41:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x8;
-val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
-
-inst_42:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x8;
-val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
-
-inst_43:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x8;
-val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
-
-inst_44:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x8;
-val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
-
-inst_45:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x8;
-val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
-
-inst_46:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x8;
-val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)
-
-inst_47:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x8;
-val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)
-
-inst_48:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x8;
-val_offset:24*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)
-
-inst_49:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x8;
-val_offset:25*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)
-
-inst_50:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x8;
-val_offset:26*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)
-
-inst_51:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x8;
-val_offset:27*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)
-
-inst_52:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x8;
-val_offset:28*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)
-
-inst_53:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x8;
-val_offset:29*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)
-
-inst_54:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x8;
-val_offset:30*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)
-
-inst_55:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x8;
-val_offset:31*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)
-
-inst_56:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x8;
-val_offset:32*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)
-
-inst_57:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x8;
-val_offset:33*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)
-
-inst_58:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x8;
-val_offset:34*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)
-
-inst_59:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x8;
-val_offset:35*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)
-
-inst_60:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x8;
-val_offset:36*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)
-
-inst_61:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x8;
-val_offset:37*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)
-
-inst_62:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x8;
-val_offset:38*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)
-
-inst_63:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x8;
-val_offset:39*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)
-
-inst_64:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x8;
-val_offset:40*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)
-
-inst_65:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x8;
-val_offset:41*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)
-
-inst_66:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x8;
-val_offset:42*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)
-
-inst_67:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x8;
-val_offset:43*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)
-
-inst_68:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x8;
-val_offset:44*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)
-
-inst_69:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x8;
-val_offset:45*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)
-
-inst_70:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x8;
-val_offset:46*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)
-
-inst_71:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x8;
-val_offset:47*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)
-
-inst_72:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x8;
-val_offset:48*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)
-
-inst_73:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x8;
-val_offset:49*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)
-
-inst_74:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x8;
-val_offset:50*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)
-
-inst_75:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x8;
-val_offset:51*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:0*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)
-
-inst_76:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x8;
-val_offset:52*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)
-
-inst_77:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x40 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x8;
-val_offset:53*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:64*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)
-
-inst_78:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x60 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x8;
-val_offset:54*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:96*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)
-
-inst_79:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and  fcsr == 0x80 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x8;
-val_offset:55*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:128*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)
-
-inst_80:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and  fcsr == 0x20 and rm_val == 7   
-/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x8;
-val_offset:56*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
-fcsr_val:32*/
-TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(4593818355633981080,64,FLEN)
-NAN_BOXED(4593818355633981080,64,FLEN)
-NAN_BOXED(4593818355633981080,64,FLEN)
-NAN_BOXED(4593818355633981080,64,FLEN)
-NAN_BOXED(4593818355633981080,64,FLEN)
-NAN_BOXED(4593818355633981081,64,FLEN)
-NAN_BOXED(4593818355633981081,64,FLEN)
-NAN_BOXED(4593818355633981081,64,FLEN)
-NAN_BOXED(4593818355633981081,64,FLEN)
-NAN_BOXED(4593818355633981081,64,FLEN)
-NAN_BOXED(4593818355633981082,64,FLEN)
-NAN_BOXED(4593818355633981082,64,FLEN)
-NAN_BOXED(4593818355633981082,64,FLEN)
-NAN_BOXED(4593818355633981082,64,FLEN)
-NAN_BOXED(4593818355633981082,64,FLEN)
-NAN_BOXED(4593818355633981083,64,FLEN)
-NAN_BOXED(4593818355633981083,64,FLEN)
-NAN_BOXED(4593818355633981083,64,FLEN)
-NAN_BOXED(4593818355633981083,64,FLEN)
-NAN_BOXED(4593818355633981083,64,FLEN)
-NAN_BOXED(4593818355633981084,64,FLEN)
-NAN_BOXED(4593818355633981084,64,FLEN)
-NAN_BOXED(4593818355633981084,64,FLEN)
-NAN_BOXED(4593818355633981084,64,FLEN)
-test_dataset_1:
-NAN_BOXED(4593818355633981084,64,FLEN)
-NAN_BOXED(4593818355633981085,64,FLEN)
-NAN_BOXED(4593818355633981085,64,FLEN)
-NAN_BOXED(4593818355633981085,64,FLEN)
-NAN_BOXED(4593818355633981085,64,FLEN)
-NAN_BOXED(4593818355633981085,64,FLEN)
-NAN_BOXED(4593818355633981086,64,FLEN)
-NAN_BOXED(4593818355633981086,64,FLEN)
-NAN_BOXED(4593818355633981086,64,FLEN)
-NAN_BOXED(4593818355633981086,64,FLEN)
-NAN_BOXED(4593818355633981086,64,FLEN)
-NAN_BOXED(4593818355633981087,64,FLEN)
-NAN_BOXED(4593818355633981087,64,FLEN)
-NAN_BOXED(4593818355633981087,64,FLEN)
-NAN_BOXED(4593818355633981087,64,FLEN)
-NAN_BOXED(4593818355633981087,64,FLEN)
-NAN_BOXED(13817190392488756888,64,FLEN)
-NAN_BOXED(13817190392488756888,64,FLEN)
-NAN_BOXED(13817190392488756888,64,FLEN)
-NAN_BOXED(13817190392488756888,64,FLEN)
-NAN_BOXED(13817190392488756888,64,FLEN)
-NAN_BOXED(13817190392488756889,64,FLEN)
-NAN_BOXED(13817190392488756889,64,FLEN)
-NAN_BOXED(13817190392488756889,64,FLEN)
-NAN_BOXED(13817190392488756889,64,FLEN)
-NAN_BOXED(13817190392488756889,64,FLEN)
-NAN_BOXED(13817190392488756890,64,FLEN)
-NAN_BOXED(13817190392488756890,64,FLEN)
-NAN_BOXED(13817190392488756890,64,FLEN)
-NAN_BOXED(13817190392488756890,64,FLEN)
-NAN_BOXED(13817190392488756890,64,FLEN)
-NAN_BOXED(13817190392488756891,64,FLEN)
-NAN_BOXED(13817190392488756891,64,FLEN)
-NAN_BOXED(13817190392488756891,64,FLEN)
-NAN_BOXED(13817190392488756891,64,FLEN)
-NAN_BOXED(13817190392488756891,64,FLEN)
-NAN_BOXED(13817190392488756892,64,FLEN)
-NAN_BOXED(13817190392488756892,64,FLEN)
-NAN_BOXED(13817190392488756892,64,FLEN)
-NAN_BOXED(13817190392488756892,64,FLEN)
-NAN_BOXED(13817190392488756892,64,FLEN)
-NAN_BOXED(13817190392488756893,64,FLEN)
-NAN_BOXED(13817190392488756893,64,FLEN)
-NAN_BOXED(13817190392488756893,64,FLEN)
-NAN_BOXED(13817190392488756893,64,FLEN)
-NAN_BOXED(13817190392488756893,64,FLEN)
-NAN_BOXED(13817190392488756894,64,FLEN)
-NAN_BOXED(13817190392488756894,64,FLEN)
-NAN_BOXED(13817190392488756894,64,FLEN)
-NAN_BOXED(13817190392488756894,64,FLEN)
-NAN_BOXED(13817190392488756894,64,FLEN)
-NAN_BOXED(13817190392488756895,64,FLEN)
-NAN_BOXED(13817190392488756895,64,FLEN)
-NAN_BOXED(13817190392488756895,64,FLEN)
-NAN_BOXED(13817190392488756895,64,FLEN)
-NAN_BOXED(13817190392488756895,64,FLEN)
-NAN_BOXED(4593818355633981086,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 54*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x5_0:
-    .fill 108*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b1-01.S
deleted file mode 100644
index acabd9bca..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b1-01.S
+++ /dev/null
@@ -1,4740 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:15:02 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fleq.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fleq.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fleq.d_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fleq.d_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f29; op2:f29; dest:x30; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f30; op2:f31; dest:x29; op1val:0x0; op2val:0x1;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f28; op2:f27; dest:x28; op1val:0x0; op2val:0x8000000000000001;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f27; op2:f28; dest:x27; op1val:0x0; op2val:0x2;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f26; op2:f25; dest:x26; op1val:0x0; op2val:0x8000000000000002;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f25; op2:f26; dest:x25; op1val:0x0; op2val:0xfffffffffffff;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f24; op2:f23; dest:x24; op1val:0x0; op2val:0x800fffffffffffff;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f23; op2:f24; dest:x23; op1val:0x0; op2val:0x10000000000000;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f22; op2:f21; dest:x22; op1val:0x0; op2val:0x8010000000000000;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f21; op2:f22; dest:x21; op1val:0x0; op2val:0x10000000000002;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f20; op2:f19; dest:x20; op1val:0x0; op2val:0x8010000000000002;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f19; op2:f20; dest:x19; op1val:0x0; op2val:0x7fefffffffffffff;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f18; op2:f17; dest:x18; op1val:0x0; op2val:0xffefffffffffffff;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f17; op2:f18; dest:x17; op1val:0x0; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f16; op2:f15; dest:x16; op1val:0x0; op2val:0xfff0000000000000;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f15; op2:f16; dest:x15; op1val:0x0; op2val:0x7ff8000000000000;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f14; op2:f13; dest:x14; op1val:0x0; op2val:0xfff8000000000000;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f13; op2:f14; dest:x13; op1val:0x0; op2val:0x7ff8000000000001;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f12; op2:f11; dest:x12; op1val:0x0; op2val:0xfff8000000000001;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f11; op2:f12; dest:x11; op1val:0x0; op2val:0x7ff0000000000001;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f10; op2:f9; dest:x10; op1val:0x0; op2val:0xfff0000000000001;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f9; op2:f10; dest:x9; op1val:0x0; op2val:0x3ff0000000000000;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f8; op2:f7; dest:x8; op1val:0x0; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f7; op2:f8; dest:x7; op1val:0x8000000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f6; op2:f5; dest:x6; op1val:0x8000000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f5; op2:f6; dest:x5; op1val:0x8000000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f4; op2:f3; dest:x4; op1val:0x8000000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f3; op2:f4; dest:x3; op1val:0x8000000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f2; op2:f1; dest:x2; op1val:0x8000000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f1; op2:f2; dest:x1; op1val:0x8000000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f0; op2:f31; dest:x31; op1val:0x8000000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f0; dest:x31; op1val:0x8000000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x0; op1val:0x8000000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x0;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x1;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x2;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x0;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x1;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x2;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x0;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x1;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x2;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x0;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x1;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x2;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x0;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x1;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x2;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
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-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 80*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b19-01.S
deleted file mode 100644
index 9114da781..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fleq.d_b19-01.S
+++ /dev/null
@@ -1,8928 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:15:02 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fleq.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fleq.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fleq.d_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fleq.d_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x7fce759ff97b7507;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f29; op2:f29; dest:x30; op1val:0x7fce759ff97b7507; op2val:0x7fce759ff97b7507;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x004b878423be8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f30; op2:f31; dest:x29; op1val:0x7ff0000000000000; op2val:0x7fb004b878423be8;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x004b878423be8 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f28; op2:f27; dest:x28; op1val:0x7fb004b878423be8; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f27; op2:f28; dest:x27; op1val:0x7ff0000000000000; op2val:0x7fe405e69652cae2;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f26; op2:f25; dest:x26; op1val:0x7fce759ff97b7507; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f25; op2:f26; dest:x25; op1val:0x7fce759ff97b7507; op2val:0x7fd09941946801c5;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f24; op2:f23; dest:x24; op1val:0x7fd09941946801c5; op2val:0x7fce759ff97b7507;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f23; op2:f24; dest:x23; op1val:0x7fce759ff97b7507; op2val:0x7feac44ace32d282;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x569d571c24201 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f22; op2:f21; dest:x22; op1val:0x7ff0000000000000; op2val:0x7fb569d571c24201;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x569d571c24201 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f21; op2:f22; dest:x21; op1val:0x7fb569d571c24201; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f20; op2:f19; dest:x20; op1val:0x7ff0000000000000; op2val:0x7feac44ace32d282;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f19; op2:f20; dest:x19; op1val:0x7fce759ff97b7507; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x0409f707c3583 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f18; op2:f17; dest:x18; op1val:0x7ff0000000000000; op2val:0x7fb0409f707c3583;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x0409f707c3583 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f17; op2:f18; dest:x17; op1val:0x7fb0409f707c3583; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f16; op2:f15; dest:x16; op1val:0x7ff0000000000000; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f15; op2:f16; dest:x15; op1val:0x7fce759ff97b7507; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f14; op2:f13; dest:x14; op1val:0xffdd2b592ef4e4e6; op2val:0x7fce759ff97b7507;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f13; op2:f14; dest:x13; op1val:0x7fce759ff97b7507; op2val:0xffede7300593ddb7;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7ec266adcb15f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f12; op2:f11; dest:x12; op1val:0x7ff0000000000000; op2val:0xffb7ec266adcb15f;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7ec266adcb15f and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f11; op2:f12; dest:x11; op1val:0xffb7ec266adcb15f; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f10; op2:f9; dest:x10; op1val:0x7ff0000000000000; op2val:0xffede7300593ddb7;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f9; op2:f10; dest:x9; op1val:0x7fce759ff97b7507; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x399e37c2fb926 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f8; op2:f7; dest:x8; op1val:0x7ff0000000000000; op2val:0xffb399e37c2fb926;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x7fb and fm1 == 0x399e37c2fb926 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f7; op2:f8; dest:x7; op1val:0xffb399e37c2fb926; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f6; op2:f5; dest:x6; op1val:0x7ff0000000000000; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f5; op2:f6; dest:x5; op1val:0x7fce759ff97b7507; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f4; op2:f3; dest:x4; op1val:0xffe0c1b6ea69558e; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f3; op2:f4; dest:x3; op1val:0x7fce759ff97b7507; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f2; op2:f1; dest:x2; op1val:0xffc0e3e4312fc728; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f1; op2:f2; dest:x1; op1val:0x7fce759ff97b7507; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xd4e5c31a3975f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f0; op2:f31; dest:x31; op1val:0x3137cb6875068; op2val:0x7fdd4e5c31a3975f;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3137cb6875068 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f0; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0x3137cb6875068;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x0; op1val:0x3137cb6875068; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3137cb6875068 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x3137cb6875068;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x04ebfabda54d7 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x4dcb3b62b25ff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x4ebfabda54d7; op2val:0x7fc4dcb3b62b25ff;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x04ebfabda54d7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0x4ebfabda54d7;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x04ebfabda54d7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x4ebfabda54d7; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x04ebfabda54d7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x4ebfabda54d7;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xf8c50a18d0c04 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0x7fbf8c50a18d0c04;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xec2df2149240f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0x1ec2df2149240f;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xec2df2149240f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x1ec2df2149240f;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x43fe46d2b7ce6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0x7fb43fe46d2b7ce6;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xec2df2149240f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0x1ec2df2149240f;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x093dbe3aa0387 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0x7fb093dbe3aa0387;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xec2df2149240f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0x1ec2df2149240f;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xf6025caa2d205 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3137cb6875068; op2val:0xffdf6025caa2d205;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3137cb6875068 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0x3137cb6875068;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3137cb6875068; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x9bff6a8783cf3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3137cb6875068; op2val:0xffc9bff6a8783cf3;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3137cb6875068 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0x3137cb6875068;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3137cb6875068; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x0c90875ccb5d8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0xffb0c90875ccb5d8;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xec2df2149240f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0x1ec2df2149240f;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xae9e55abc765f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0xffbae9e55abc765f;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 0 and fe2 == 0x001 and fm2 == 0xec2df2149240f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0x1ec2df2149240f;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0x001 and fm1 == 0xec2df2149240f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ec2df2149240f; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x47f2e5cadc271 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3137cb6875068; op2val:0xffd47f2e5cadc271;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3137cb6875068 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0x3137cb6875068;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3137cb6875068; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x0;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 0 and fe1 == 0x401 and fm1 == 0x11c8af0ae0986 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x40111c8af0ae0986; op2val:0x0;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x401 and fm2 == 0x11c8af0ae0986 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x40111c8af0ae0986;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x401 and fm2 == 0x11c8af0ae0986 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x40111c8af0ae0986;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x004b878423be8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb004b878423be8; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x004b878423be8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x7fb004b878423be8;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x004b878423be8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb004b878423be8; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x004b878423be8 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb004b878423be8; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x004b878423be8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fb004b878423be8;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x004b878423be8 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb004b878423be8; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x004b878423be8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb004b878423be8; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x004b878423be8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb004b878423be8; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0cf11346ee18e and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xcf11346ee18e; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0cf11346ee18e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xcf11346ee18e;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0cf11346ee18e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xcf11346ee18e; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0cf11346ee18e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xcf11346ee18e;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x014b4eba4b028 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x14b4eba4b028; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x014b4eba4b028 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x14b4eba4b028;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x014b4eba4b028 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x14b4eba4b028; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x014b4eba4b028 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x14b4eba4b028;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x816ac0c54cf8a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x816ac0c54cf8a;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x816ac0c54cf8a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x816ac0c54cf8a;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x94fdd88765c1f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0x7fe94fdd88765c1f;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x816ac0c54cf8a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0x816ac0c54cf8a;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x4b8d2dc948469 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0x7fe4b8d2dc948469;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x816ac0c54cf8a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0x816ac0c54cf8a;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0cf11346ee18e and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xcf11346ee18e; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0cf11346ee18e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xcf11346ee18e;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0cf11346ee18e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xcf11346ee18e; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0cf11346ee18e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xcf11346ee18e; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x4fb4a933fe34f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0xffe4fb4a933fe34f;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x816ac0c54cf8a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0x816ac0c54cf8a;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x816ac0c54cf8a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x816ac0c54cf8a;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x816ac0c54cf8a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x816ac0c54cf8a; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0cf11346ee18e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xcf11346ee18e; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x0;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1ff65f57ff366 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff1ff65f57ff366; op2val:0x0;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x1ff65f57ff366 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff1ff65f57ff366;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x405e69652cae2 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x1ff65f57ff366 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe405e69652cae2; op2val:0x3ff1ff65f57ff366;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xd4e5c31a3975f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0x7fdd4e5c31a3975f;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x35a452e11324d and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0x35a452e11324d;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x35a452e11324d and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x35a452e11324d;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x055d3b7ce8508 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x4dcb3b62b25ff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x55d3b7ce8508; op2val:0x7fc4dcb3b62b25ff;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x055d3b7ce8508 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0x55d3b7ce8508;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x055d3b7ce8508 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x55d3b7ce8508; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x055d3b7ce8508 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x55d3b7ce8508;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xf8c50a18d0c04 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0x7fbf8c50a18d0c04;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x0c359e655fb81 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0x20c359e655fb81;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x0c359e655fb81 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x20c359e655fb81;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x43fe46d2b7ce6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0x7fb43fe46d2b7ce6;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x0c359e655fb81 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0x20c359e655fb81;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x093dbe3aa0387 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0x7fb093dbe3aa0387;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x0c359e655fb81 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0x20c359e655fb81;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xf6025caa2d205 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0xffdf6025caa2d205;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x35a452e11324d and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0x35a452e11324d;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x9bff6a8783cf3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0xffc9bff6a8783cf3;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x35a452e11324d and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0x35a452e11324d;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x0c90875ccb5d8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0xffb0c90875ccb5d8;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x0c359e655fb81 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0x20c359e655fb81;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xae9e55abc765f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0xffbae9e55abc765f;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 0 and fe2 == 0x002 and fm2 == 0x0c359e655fb81 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0x20c359e655fb81;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 0 and fe1 == 0x002 and fm1 == 0x0c359e655fb81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x20c359e655fb81; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x47f2e5cadc271 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0xffd47f2e5cadc271;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x35a452e11324d and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0x35a452e11324d;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x35a452e11324d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35a452e11324d; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x0;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 0 and fe1 == 0x401 and fm1 == 0x2a6496228606e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x4012a6496228606e; op2val:0x0;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x401 and fm2 == 0x2a6496228606e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x4012a6496228606e;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x09941946801c5 and fs2 == 0 and fe2 == 0x401 and fm2 == 0x2a6496228606e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fd09941946801c5; op2val:0x4012a6496228606e;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x569d571c24201 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb569d571c24201; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x569d571c24201 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x7fb569d571c24201;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x569d571c24201 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb569d571c24201; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x569d571c24201 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb569d571c24201; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x569d571c24201 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fb569d571c24201;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x569d571c24201 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb569d571c24201; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x569d571c24201 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb569d571c24201; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x569d571c24201 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb569d571c24201; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x114ce95016c16 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x114ce95016c16; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x114ce95016c16 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x114ce95016c16;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x114ce95016c16 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x114ce95016c16; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x114ce95016c16 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x114ce95016c16;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01bae4219be02 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1bae4219be02; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01bae4219be02 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x1bae4219be02;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01bae4219be02 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1bae4219be02; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01bae4219be02 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x1bae4219be02;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xad011d20e38de and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xad011d20e38de;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xad011d20e38de and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xad011d20e38de;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x94fdd88765c1f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0x7fe94fdd88765c1f;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xad011d20e38de and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0xad011d20e38de;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x4b8d2dc948469 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0x7fe4b8d2dc948469;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xad011d20e38de and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0xad011d20e38de;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x114ce95016c16 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x114ce95016c16; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x114ce95016c16 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x114ce95016c16;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x114ce95016c16 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x114ce95016c16; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x114ce95016c16 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x114ce95016c16; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x4fb4a933fe34f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0xffe4fb4a933fe34f;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xad011d20e38de and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0xad011d20e38de;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xad011d20e38de and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xad011d20e38de;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xad011d20e38de and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xad011d20e38de; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x114ce95016c16 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x114ce95016c16; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x0;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x80f28c9e9c76b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff80f28c9e9c76b; op2val:0x0;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x80f28c9e9c76b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff80f28c9e9c76b;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xac44ace32d282 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x80f28c9e9c76b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feac44ace32d282; op2val:0x3ff80f28c9e9c76b;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x0409f707c3583 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb0409f707c3583; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x0409f707c3583 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x7fb0409f707c3583;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x0409f707c3583 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb0409f707c3583; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x0409f707c3583 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb0409f707c3583; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x0409f707c3583 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fb0409f707c3583;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x0409f707c3583 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb0409f707c3583; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x0409f707c3583 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb0409f707c3583; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x0409f707c3583 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb0409f707c3583; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d2178c8e4bc2 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd2178c8e4bc2; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d2178c8e4bc2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xd2178c8e4bc2;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d2178c8e4bc2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd2178c8e4bc2; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d2178c8e4bc2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xd2178c8e4bc2;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x015025adb0793 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15025adb0793; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x015025adb0793 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x15025adb0793;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x015025adb0793 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15025adb0793; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x015025adb0793 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x15025adb0793;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x834eb7d8ef590 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x834eb7d8ef590;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x834eb7d8ef590 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x834eb7d8ef590;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x94fdd88765c1f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0x7fe94fdd88765c1f;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x834eb7d8ef590 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0x834eb7d8ef590;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x4b8d2dc948469 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0x7fe4b8d2dc948469;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x834eb7d8ef590 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0x834eb7d8ef590;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d2178c8e4bc2 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd2178c8e4bc2; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d2178c8e4bc2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xd2178c8e4bc2;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d2178c8e4bc2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd2178c8e4bc2; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d2178c8e4bc2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd2178c8e4bc2; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x4fb4a933fe34f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0xffe4fb4a933fe34f;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x834eb7d8ef590 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0x834eb7d8ef590;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x834eb7d8ef590 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x834eb7d8ef590;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x834eb7d8ef590 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x834eb7d8ef590; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d2178c8e4bc2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd2178c8e4bc2; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x0;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x242b3b0a4387a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff242b3b0a4387a; op2val:0x0;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x242b3b0a4387a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff242b3b0a4387a;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x450c74c9b42e4 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x242b3b0a4387a and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe450c74c9b42e4; op2val:0x3ff242b3b0a4387a;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7ec266adcb15f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffb7ec266adcb15f;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7ec266adcb15f and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb7ec266adcb15f; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x399e37c2fb926 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffb399e37c2fb926;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x399e37c2fb926 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb399e37c2fb926; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xd4e5c31a3975f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0x7fdd4e5c31a3975f;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e443bf91c5dd and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0x8005e443bf91c5dd;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e443bf91c5dd and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x8005e443bf91c5dd;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x096d393282d63 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x4dcb3b62b25ff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800096d393282d63; op2val:0x7fc4dcb3b62b25ff;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x096d393282d63 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0x800096d393282d63;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x096d393282d63 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800096d393282d63; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x096d393282d63 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x800096d393282d63;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xf8c50a18d0c04 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0x7fbf8c50a18d0c04;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd7552bdd8dd50 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0x802d7552bdd8dd50;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd7552bdd8dd50 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x802d7552bdd8dd50;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x43fe46d2b7ce6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0x7fb43fe46d2b7ce6;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd7552bdd8dd50 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0x802d7552bdd8dd50;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x093dbe3aa0387 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0x7fb093dbe3aa0387;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd7552bdd8dd50 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0x802d7552bdd8dd50;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xf6025caa2d205 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0xffdf6025caa2d205;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e443bf91c5dd and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0x8005e443bf91c5dd;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x9bff6a8783cf3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0xffc9bff6a8783cf3;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e443bf91c5dd and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0x8005e443bf91c5dd;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x0c90875ccb5d8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0xffb0c90875ccb5d8;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd7552bdd8dd50 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0x802d7552bdd8dd50;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xae9e55abc765f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0xffbae9e55abc765f;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd7552bdd8dd50 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0x802d7552bdd8dd50;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd7552bdd8dd50 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d7552bdd8dd50; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x47f2e5cadc271 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0xffd47f2e5cadc271;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e443bf91c5dd and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0x8005e443bf91c5dd;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e443bf91c5dd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e443bf91c5dd; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0x0;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 1 and fe1 == 0x402 and fm1 == 0x06300128a7be9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc0206300128a7be9; op2val:0x0;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x06300128a7be9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc0206300128a7be9;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2b592ef4e4e6 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x06300128a7be9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2b592ef4e4e6; op2val:0xc0206300128a7be9;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7ec266adcb15f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb7ec266adcb15f; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7ec266adcb15f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xffb7ec266adcb15f;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7ec266adcb15f and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb7ec266adcb15f; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7ec266adcb15f and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb7ec266adcb15f; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7ec266adcb15f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb7ec266adcb15f; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7ec266adcb15f and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb7ec266adcb15f; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1353dad8f9fcc and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001353dad8f9fcc; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1353dad8f9fcc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8001353dad8f9fcc;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1353dad8f9fcc and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001353dad8f9fcc; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1353dad8f9fcc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x8001353dad8f9fcc;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01eec915b2994 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001eec915b2994; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01eec915b2994 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x80001eec915b2994;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01eec915b2994 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001eec915b2994; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01eec915b2994 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x80001eec915b2994;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc1468c79c3df8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x800c1468c79c3df8;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc1468c79c3df8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x800c1468c79c3df8;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x94fdd88765c1f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0x7fe94fdd88765c1f;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc1468c79c3df8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0x800c1468c79c3df8;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x4b8d2dc948469 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0x7fe4b8d2dc948469;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc1468c79c3df8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0x800c1468c79c3df8;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1353dad8f9fcc and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001353dad8f9fcc; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1353dad8f9fcc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8001353dad8f9fcc;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1353dad8f9fcc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001353dad8f9fcc; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1353dad8f9fcc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001353dad8f9fcc; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x4fb4a933fe34f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0xffe4fb4a933fe34f;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc1468c79c3df8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0x800c1468c79c3df8;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc1468c79c3df8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x800c1468c79c3df8;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc1468c79c3df8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800c1468c79c3df8; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1353dad8f9fcc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001353dad8f9fcc; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0x0;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xae0d6ce341771 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbffae0d6ce341771; op2val:0x0;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xae0d6ce341771 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbffae0d6ce341771;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xde7300593ddb7 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xae0d6ce341771 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffede7300593ddb7; op2val:0xbffae0d6ce341771;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x399e37c2fb926 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb399e37c2fb926; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x399e37c2fb926 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xffb399e37c2fb926;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x399e37c2fb926 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb399e37c2fb926; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x399e37c2fb926 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb399e37c2fb926; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x399e37c2fb926 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb399e37c2fb926; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x399e37c2fb926 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb399e37c2fb926; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0fd6141352983 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000fd6141352983; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0fd6141352983 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000fd6141352983;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0fd6141352983 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000fd6141352983; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0fd6141352983 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x8000fd6141352983;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01956868550f3 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001956868550f3; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01956868550f3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x80001956868550f3;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01956868550f3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001956868550f3; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01956868550f3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x80001956868550f3;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x9e5cc8c139f1c and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8009e5cc8c139f1c;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x9e5cc8c139f1c and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x8009e5cc8c139f1c;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x94fdd88765c1f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0x7fe94fdd88765c1f;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x9e5cc8c139f1c and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0x8009e5cc8c139f1c;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x4b8d2dc948469 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0x7fe4b8d2dc948469;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x9e5cc8c139f1c and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0x8009e5cc8c139f1c;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0fd6141352983 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000fd6141352983; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0fd6141352983 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8000fd6141352983;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0fd6141352983 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000fd6141352983; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0fd6141352983 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000fd6141352983; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x4fb4a933fe34f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0xffe4fb4a933fe34f;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x9e5cc8c139f1c and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0x8009e5cc8c139f1c;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x9e5cc8c139f1c and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8009e5cc8c139f1c;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x9e5cc8c139f1c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8009e5cc8c139f1c; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0fd6141352983 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000fd6141352983; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0x0;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x605e3d372e471 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbff605e3d372e471; op2val:0x0;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x605e3d372e471 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbff605e3d372e471;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x8805c5b3ba76f and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x605e3d372e471 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe8805c5b3ba76f; op2val:0xbff605e3d372e471;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xd4e5c31a3975f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0x7fdd4e5c31a3975f;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6c4e25604ed00 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0x8006c4e25604ed00;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6c4e25604ed00 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x8006c4e25604ed00;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0ad49d566e480 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x4dcb3b62b25ff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000ad49d566e480; op2val:0x7fc4dcb3b62b25ff;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0ad49d566e480 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0x8000ad49d566e480;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0ad49d566e480 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000ad49d566e480; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0ad49d566e480 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x8000ad49d566e480;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xf8c50a18d0c04 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0x7fbf8c50a18d0c04;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0ec35d70c5080 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0x8030ec35d70c5080;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0ec35d70c5080 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x8030ec35d70c5080;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x43fe46d2b7ce6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0x7fb43fe46d2b7ce6;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0ec35d70c5080 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0x8030ec35d70c5080;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x093dbe3aa0387 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0x7fb093dbe3aa0387;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0ec35d70c5080 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0x8030ec35d70c5080;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xf6025caa2d205 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0xffdf6025caa2d205;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6c4e25604ed00 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0x8006c4e25604ed00;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x9bff6a8783cf3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0xffc9bff6a8783cf3;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6c4e25604ed00 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0x8006c4e25604ed00;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x0c90875ccb5d8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0xffb0c90875ccb5d8;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0ec35d70c5080 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0x8030ec35d70c5080;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xae9e55abc765f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0xffbae9e55abc765f;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0ec35d70c5080 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0x8030ec35d70c5080;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0ec35d70c5080 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030ec35d70c5080; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x47f2e5cadc271 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0xffd47f2e5cadc271;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6c4e25604ed00 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0x8006c4e25604ed00;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6c4e25604ed00 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006c4e25604ed00; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0x0;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0x402 and fm1 == 0x2d3be740985a9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc022d3be740985a9; op2val:0x0;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x2d3be740985a9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc022d3be740985a9;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0c1b6ea69558e and fs2 == 1 and fe2 == 0x402 and fm2 == 0x2d3be740985a9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0c1b6ea69558e; op2val:0xc022d3be740985a9;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xd4e5c31a3975f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0x7fdd4e5c31a3975f;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1b4ac2dd761b7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0x8001b4ac2dd761b7;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1b4ac2dd761b7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x8001b4ac2dd761b7;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x02baad1625692 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x4dcb3b62b25ff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80002baad1625692; op2val:0x7fc4dcb3b62b25ff;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x02baad1625692 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0x80002baad1625692;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x02baad1625692 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80002baad1625692; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x02baad1625692 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x80002baad1625692;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-
-inst_578:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1110*FLEN/8, x10, x6, x7)
-
-inst_579:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xf8c50a18d0c04 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0x7fbf8c50a18d0c04;
-valaddr_reg:x9; val_offset:1112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1112*FLEN/8, x10, x6, x7)
-
-inst_580:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x10eb9ca69d123 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0x80110eb9ca69d123;
-valaddr_reg:x9; val_offset:1114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1114*FLEN/8, x10, x6, x7)
-
-inst_581:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1116*FLEN/8, x10, x6, x7)
-
-inst_582:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x10eb9ca69d123 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x80110eb9ca69d123;
-valaddr_reg:x9; val_offset:1118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1118*FLEN/8, x10, x6, x7)
-
-inst_583:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1120*FLEN/8, x10, x6, x7)
-
-inst_584:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x43fe46d2b7ce6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0x7fb43fe46d2b7ce6;
-valaddr_reg:x9; val_offset:1122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1122*FLEN/8, x10, x6, x7)
-
-inst_585:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x10eb9ca69d123 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0x80110eb9ca69d123;
-valaddr_reg:x9; val_offset:1124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1124*FLEN/8, x10, x6, x7)
-
-inst_586:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1126*FLEN/8, x10, x6, x7)
-
-inst_587:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1128*FLEN/8, x10, x6, x7)
-
-inst_588:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x093dbe3aa0387 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0x7fb093dbe3aa0387;
-valaddr_reg:x9; val_offset:1130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1130*FLEN/8, x10, x6, x7)
-
-inst_589:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x10eb9ca69d123 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0x80110eb9ca69d123;
-valaddr_reg:x9; val_offset:1132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1132*FLEN/8, x10, x6, x7)
-
-inst_590:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1134*FLEN/8, x10, x6, x7)
-
-inst_591:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1136*FLEN/8, x10, x6, x7)
-
-inst_592:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xf6025caa2d205 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0xffdf6025caa2d205;
-valaddr_reg:x9; val_offset:1138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1138*FLEN/8, x10, x6, x7)
-
-inst_593:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1b4ac2dd761b7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0x8001b4ac2dd761b7;
-valaddr_reg:x9; val_offset:1140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1140*FLEN/8, x10, x6, x7)
-
-inst_594:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1142*FLEN/8, x10, x6, x7)
-
-inst_595:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1144*FLEN/8, x10, x6, x7)
-
-inst_596:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x9bff6a8783cf3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0xffc9bff6a8783cf3;
-valaddr_reg:x9; val_offset:1146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1146*FLEN/8, x10, x6, x7)
-
-inst_597:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1b4ac2dd761b7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0x8001b4ac2dd761b7;
-valaddr_reg:x9; val_offset:1148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1148*FLEN/8, x10, x6, x7)
-
-inst_598:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1150*FLEN/8, x10, x6, x7)
-
-inst_599:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1152*FLEN/8, x10, x6, x7)
-
-inst_600:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x0c90875ccb5d8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0xffb0c90875ccb5d8;
-valaddr_reg:x9; val_offset:1154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1154*FLEN/8, x10, x6, x7)
-
-inst_601:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x10eb9ca69d123 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0x80110eb9ca69d123;
-valaddr_reg:x9; val_offset:1156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1156*FLEN/8, x10, x6, x7)
-
-inst_602:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1158*FLEN/8, x10, x6, x7)
-
-inst_603:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1160*FLEN/8, x10, x6, x7)
-
-inst_604:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xae9e55abc765f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0xffbae9e55abc765f;
-valaddr_reg:x9; val_offset:1162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1162*FLEN/8, x10, x6, x7)
-
-inst_605:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 1 and fe2 == 0x001 and fm2 == 0x10eb9ca69d123 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0x80110eb9ca69d123;
-valaddr_reg:x9; val_offset:1164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1164*FLEN/8, x10, x6, x7)
-
-inst_606:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x10eb9ca69d123 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80110eb9ca69d123; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1166*FLEN/8, x10, x6, x7)
-
-inst_607:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1168*FLEN/8, x10, x6, x7)
-
-inst_608:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x47f2e5cadc271 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0xffd47f2e5cadc271;
-valaddr_reg:x9; val_offset:1170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1170*FLEN/8, x10, x6, x7)
-
-inst_609:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1b4ac2dd761b7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0x8001b4ac2dd761b7;
-valaddr_reg:x9; val_offset:1172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1172*FLEN/8, x10, x6, x7)
-
-inst_610:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1b4ac2dd761b7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8001b4ac2dd761b7; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1174*FLEN/8, x10, x6, x7)
-
-inst_611:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0x0;
-valaddr_reg:x9; val_offset:1176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1176*FLEN/8, x10, x6, x7)
-
-inst_612:// fs1 == 1 and fe1 == 0x400 and fm1 == 0x2fa24c650ac14 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc002fa24c650ac14; op2val:0x0;
-valaddr_reg:x9; val_offset:1178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1178*FLEN/8, x10, x6, x7)
-
-inst_613:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x2fa24c650ac14 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc002fa24c650ac14;
-valaddr_reg:x9; val_offset:1180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1180*FLEN/8, x10, x6, x7)
-
-inst_614:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x0e3e4312fc728 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x2fa24c650ac14 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc0e3e4312fc728; op2val:0xc002fa24c650ac14;
-valaddr_reg:x9; val_offset:1182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1182*FLEN/8, x10, x6, x7)
-
-inst_615:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1184*FLEN/8, x10, x6, x7)
-
-inst_616:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1186*FLEN/8, x10, x6, x7)
-
-inst_617:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xd4e5c31a3975f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x7fdd4e5c31a3975f;
-valaddr_reg:x9; val_offset:1188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1188*FLEN/8, x10, x6, x7)
-
-inst_618:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1190*FLEN/8, x10, x6, x7)
-
-inst_619:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1192*FLEN/8, x10, x6, x7)
-
-inst_620:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1194*FLEN/8, x10, x6, x7)
-
-inst_621:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1196*FLEN/8, x10, x6, x7)
-
-inst_622:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1198*FLEN/8, x10, x6, x7)
-
-inst_623:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1200*FLEN/8, x10, x6, x7)
-
-inst_624:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1202*FLEN/8, x10, x6, x7)
-
-inst_625:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1204*FLEN/8, x10, x6, x7)
-
-inst_626:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1206*FLEN/8, x10, x6, x7)
-
-inst_627:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1208*FLEN/8, x10, x6, x7)
-
-inst_628:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1210*FLEN/8, x10, x6, x7)
-
-inst_629:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1212*FLEN/8, x10, x6, x7)
-
-inst_630:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1214*FLEN/8, x10, x6, x7)
-
-inst_631:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1216*FLEN/8, x10, x6, x7)
-
-inst_632:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xd4e5c31a3975f and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdd4e5c31a3975f; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1218*FLEN/8, x10, x6, x7)
-
-inst_633:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1220*FLEN/8, x10, x6, x7)
-
-inst_634:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x097889c6218ac and fs2 == 0 and fe2 == 0x000 and fm2 == 0x21b5c662d267b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x97889c6218ac; op2val:0x21b5c662d267b;
-valaddr_reg:x9; val_offset:1222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1222*FLEN/8, x10, x6, x7)
-
-inst_635:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x097889c6218ac and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x97889c6218ac;
-valaddr_reg:x9; val_offset:1224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1224*FLEN/8, x10, x6, x7)
-
-inst_636:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x097889c6218ac and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x97889c6218ac; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1226*FLEN/8, x10, x6, x7)
-
-inst_637:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x097889c6218ac and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x97889c6218ac;
-valaddr_reg:x9; val_offset:1228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1228*FLEN/8, x10, x6, x7)
-
-inst_638:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1230*FLEN/8, x10, x6, x7)
-
-inst_639:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x197d0ed8b1e34 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0x197d0ed8b1e34;
-valaddr_reg:x9; val_offset:1232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1232*FLEN/8, x10, x6, x7)
-
-inst_640:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xd98ae8b28d198 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x2d98ae8b28d198;
-valaddr_reg:x9; val_offset:1234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1234*FLEN/8, x10, x6, x7)
-
-inst_641:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1236*FLEN/8, x10, x6, x7)
-
-inst_642:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xd98ae8b28d198 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x2d98ae8b28d198;
-valaddr_reg:x9; val_offset:1238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1238*FLEN/8, x10, x6, x7)
-
-inst_643:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1240*FLEN/8, x10, x6, x7)
-
-inst_644:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x105c326c5af30 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0x105c326c5af30;
-valaddr_reg:x9; val_offset:1242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1242*FLEN/8, x10, x6, x7)
-
-inst_645:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xd98ae8b28d198 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x2d98ae8b28d198;
-valaddr_reg:x9; val_offset:1244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1244*FLEN/8, x10, x6, x7)
-
-inst_646:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1246*FLEN/8, x10, x6, x7)
-
-inst_647:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1248*FLEN/8, x10, x6, x7)
-
-inst_648:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d64b86ad9094 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0xd64b86ad9094;
-valaddr_reg:x9; val_offset:1250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1250*FLEN/8, x10, x6, x7)
-
-inst_649:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xd98ae8b28d198 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x2d98ae8b28d198;
-valaddr_reg:x9; val_offset:1252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1252*FLEN/8, x10, x6, x7)
-
-inst_650:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1254*FLEN/8, x10, x6, x7)
-
-inst_651:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1256*FLEN/8, x10, x6, x7)
-
-inst_652:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1258*FLEN/8, x10, x6, x7)
-
-inst_653:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1260*FLEN/8, x10, x6, x7)
-
-inst_654:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1262*FLEN/8, x10, x6, x7)
-
-inst_655:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1264*FLEN/8, x10, x6, x7)
-
-inst_656:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d8fae5b11a26 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0x8000d8fae5b11a26;
-valaddr_reg:x9; val_offset:1266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1266*FLEN/8, x10, x6, x7)
-
-inst_657:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xd98ae8b28d198 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x2d98ae8b28d198;
-valaddr_reg:x9; val_offset:1268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1268*FLEN/8, x10, x6, x7)
-
-inst_658:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1270*FLEN/8, x10, x6, x7)
-
-inst_659:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1272*FLEN/8, x10, x6, x7)
-
-inst_660:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x15be852c0ecf4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0x80015be852c0ecf4;
-valaddr_reg:x9; val_offset:1274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1274*FLEN/8, x10, x6, x7)
-
-inst_661:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xd98ae8b28d198 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x2d98ae8b28d198;
-valaddr_reg:x9; val_offset:1276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1276*FLEN/8, x10, x6, x7)
-
-inst_662:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xd98ae8b28d198 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2d98ae8b28d198; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1278*FLEN/8, x10, x6, x7)
-
-inst_663:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1280*FLEN/8, x10, x6, x7)
-
-inst_664:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1282*FLEN/8, x10, x6, x7)
-
-inst_665:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x0;
-valaddr_reg:x9; val_offset:1284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1284*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_5)
-
-inst_666:// fs1 == 0 and fe1 == 0x402 and fm1 == 0x076ab4deeec91 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x402076ab4deeec91; op2val:0x0;
-valaddr_reg:x9; val_offset:1286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1286*FLEN/8, x10, x6, x7)
-
-inst_667:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x076ab4deeec91 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x402076ab4deeec91;
-valaddr_reg:x9; val_offset:1288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1288*FLEN/8, x10, x6, x7)
-
-inst_668:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x5eb561bd4f6b8 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x076ab4deeec91 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x5eb561bd4f6b8; op2val:0x402076ab4deeec91;
-valaddr_reg:x9; val_offset:1290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1290*FLEN/8, x10, x6, x7)
-
-inst_669:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1292*FLEN/8, x10, x6, x7)
-
-inst_670:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1294*FLEN/8, x10, x6, x7)
-
-inst_671:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x4dcb3b62b25ff and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x7fc4dcb3b62b25ff;
-valaddr_reg:x9; val_offset:1296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1296*FLEN/8, x10, x6, x7)
-
-inst_672:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1298*FLEN/8, x10, x6, x7)
-
-inst_673:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1300*FLEN/8, x10, x6, x7)
-
-inst_674:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1302*FLEN/8, x10, x6, x7)
-
-inst_675:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1304*FLEN/8, x10, x6, x7)
-
-inst_676:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1306*FLEN/8, x10, x6, x7)
-
-inst_677:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1308*FLEN/8, x10, x6, x7)
-
-inst_678:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1310*FLEN/8, x10, x6, x7)
-
-inst_679:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1312*FLEN/8, x10, x6, x7)
-
-inst_680:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1314*FLEN/8, x10, x6, x7)
-
-inst_681:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1316*FLEN/8, x10, x6, x7)
-
-inst_682:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1318*FLEN/8, x10, x6, x7)
-
-inst_683:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1320*FLEN/8, x10, x6, x7)
-
-inst_684:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1322*FLEN/8, x10, x6, x7)
-
-inst_685:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1324*FLEN/8, x10, x6, x7)
-
-inst_686:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x4dcb3b62b25ff and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fc4dcb3b62b25ff; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1326*FLEN/8, x10, x6, x7)
-
-inst_687:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1328*FLEN/8, x10, x6, x7)
-
-inst_688:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1330*FLEN/8, x10, x6, x7)
-
-inst_689:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x21b5c662d267b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x21b5c662d267b;
-valaddr_reg:x9; val_offset:1332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1332*FLEN/8, x10, x6, x7)
-
-inst_690:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1334*FLEN/8, x10, x6, x7)
-
-inst_691:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x028c817c11c9f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x28c817c11c9f;
-valaddr_reg:x9; val_offset:1336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1336*FLEN/8, x10, x6, x7)
-
-inst_692:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x028c817c11c9f and fs2 == 0 and fe2 == 0x001 and fm2 == 0x5119bfdc380d2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x28c817c11c9f; op2val:0x15119bfdc380d2;
-valaddr_reg:x9; val_offset:1338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1338*FLEN/8, x10, x6, x7)
-
-inst_693:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1340*FLEN/8, x10, x6, x7)
-
-inst_694:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x5119bfdc380d2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x15119bfdc380d2;
-valaddr_reg:x9; val_offset:1342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1342*FLEN/8, x10, x6, x7)
-
-inst_695:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1344*FLEN/8, x10, x6, x7)
-
-inst_696:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01a2d1d7a2b1e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x1a2d1d7a2b1e;
-valaddr_reg:x9; val_offset:1346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1346*FLEN/8, x10, x6, x7)
-
-inst_697:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01a2d1d7a2b1e and fs2 == 0 and fe2 == 0x001 and fm2 == 0x5119bfdc380d2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1a2d1d7a2b1e; op2val:0x15119bfdc380d2;
-valaddr_reg:x9; val_offset:1348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1348*FLEN/8, x10, x6, x7)
-
-inst_698:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1350*FLEN/8, x10, x6, x7)
-
-inst_699:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1352*FLEN/8, x10, x6, x7)
-
-inst_700:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0156df3de280f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x156df3de280f;
-valaddr_reg:x9; val_offset:1354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1354*FLEN/8, x10, x6, x7)
-
-inst_701:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0156df3de280f and fs2 == 0 and fe2 == 0x001 and fm2 == 0x5119bfdc380d2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x156df3de280f; op2val:0x15119bfdc380d2;
-valaddr_reg:x9; val_offset:1356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1356*FLEN/8, x10, x6, x7)
-
-inst_702:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1358*FLEN/8, x10, x6, x7)
-
-inst_703:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1360*FLEN/8, x10, x6, x7)
-
-inst_704:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0a23bfe815416 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x8000a23bfe815416;
-valaddr_reg:x9; val_offset:1362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1362*FLEN/8, x10, x6, x7)
-
-inst_705:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0a23bfe815416 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x21b5c662d267b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000a23bfe815416; op2val:0x21b5c662d267b;
-valaddr_reg:x9; val_offset:1364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1364*FLEN/8, x10, x6, x7)
-
-inst_706:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1366*FLEN/8, x10, x6, x7)
-
-inst_707:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1368*FLEN/8, x10, x6, x7)
-
-inst_708:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x042929a1b2ce1 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x800042929a1b2ce1;
-valaddr_reg:x9; val_offset:1370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1370*FLEN/8, x10, x6, x7)
-
-inst_709:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x042929a1b2ce1 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x21b5c662d267b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800042929a1b2ce1; op2val:0x21b5c662d267b;
-valaddr_reg:x9; val_offset:1372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1372*FLEN/8, x10, x6, x7)
-
-inst_710:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1374*FLEN/8, x10, x6, x7)
-
-inst_711:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1376*FLEN/8, x10, x6, x7)
-
-inst_712:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x015b2b091b5d1 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x800015b2b091b5d1;
-valaddr_reg:x9; val_offset:1378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1378*FLEN/8, x10, x6, x7)
-
-inst_713:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x015b2b091b5d1 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x5119bfdc380d2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800015b2b091b5d1; op2val:0x15119bfdc380d2;
-valaddr_reg:x9; val_offset:1380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1380*FLEN/8, x10, x6, x7)
-
-inst_714:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1382*FLEN/8, x10, x6, x7)
-
-inst_715:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1384*FLEN/8, x10, x6, x7)
-
-inst_716:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x022ca6eace47f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x800022ca6eace47f;
-valaddr_reg:x9; val_offset:1386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1386*FLEN/8, x10, x6, x7)
-
-inst_717:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x022ca6eace47f and fs2 == 0 and fe2 == 0x001 and fm2 == 0x5119bfdc380d2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800022ca6eace47f; op2val:0x15119bfdc380d2;
-valaddr_reg:x9; val_offset:1388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1388*FLEN/8, x10, x6, x7)
-
-inst_718:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x5119bfdc380d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x15119bfdc380d2; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1390*FLEN/8, x10, x6, x7)
-
-inst_719:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1392*FLEN/8, x10, x6, x7)
-
-inst_720:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x069fbb598d312 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x800069fbb598d312;
-valaddr_reg:x9; val_offset:1394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1394*FLEN/8, x10, x6, x7)
-
-inst_721:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x069fbb598d312 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x21b5c662d267b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800069fbb598d312; op2val:0x21b5c662d267b;
-valaddr_reg:x9; val_offset:1396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1396*FLEN/8, x10, x6, x7)
-
-inst_722:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x21b5c662d267b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x21b5c662d267b; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1398*FLEN/8, x10, x6, x7)
-
-inst_723:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x0;
-valaddr_reg:x9; val_offset:1400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1400*FLEN/8, x10, x6, x7)
-
-inst_724:// fs1 == 0 and fe1 == 0x400 and fm1 == 0x77096ee4d2f12 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x40077096ee4d2f12; op2val:0x0;
-valaddr_reg:x9; val_offset:1402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1402*FLEN/8, x10, x6, x7)
-
-inst_725:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x77096ee4d2f12 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x40077096ee4d2f12;
-valaddr_reg:x9; val_offset:1404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1404*FLEN/8, x10, x6, x7)
-
-inst_726:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x035efa3d150a6 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x77096ee4d2f12 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x35efa3d150a6; op2val:0x40077096ee4d2f12;
-valaddr_reg:x9; val_offset:1406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1406*FLEN/8, x10, x6, x7)
-
-inst_727:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1408*FLEN/8, x10, x6, x7)
-
-inst_728:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1410*FLEN/8, x10, x6, x7)
-
-inst_729:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xf8c50a18d0c04 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x7fbf8c50a18d0c04;
-valaddr_reg:x9; val_offset:1412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1412*FLEN/8, x10, x6, x7)
-
-inst_730:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1414*FLEN/8, x10, x6, x7)
-
-inst_731:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1416*FLEN/8, x10, x6, x7)
-
-inst_732:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1418*FLEN/8, x10, x6, x7)
-
-inst_733:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1420*FLEN/8, x10, x6, x7)
-
-inst_734:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1422*FLEN/8, x10, x6, x7)
-
-inst_735:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1424*FLEN/8, x10, x6, x7)
-
-inst_736:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1426*FLEN/8, x10, x6, x7)
-
-inst_737:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1428*FLEN/8, x10, x6, x7)
-
-inst_738:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1430*FLEN/8, x10, x6, x7)
-
-inst_739:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1432*FLEN/8, x10, x6, x7)
-
-inst_740:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1434*FLEN/8, x10, x6, x7)
-
-inst_741:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1436*FLEN/8, x10, x6, x7)
-
-inst_742:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1438*FLEN/8, x10, x6, x7)
-
-inst_743:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1440*FLEN/8, x10, x6, x7)
-
-inst_744:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xf8c50a18d0c04 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fbf8c50a18d0c04; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1442*FLEN/8, x10, x6, x7)
-
-inst_745:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1444*FLEN/8, x10, x6, x7)
-
-inst_746:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1446*FLEN/8, x10, x6, x7)
-
-inst_747:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x197d0ed8b1e34 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x197d0ed8b1e34;
-valaddr_reg:x9; val_offset:1448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1448*FLEN/8, x10, x6, x7)
-
-inst_748:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1450*FLEN/8, x10, x6, x7)
-
-inst_749:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x028c817c11c9f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x28c817c11c9f; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1452*FLEN/8, x10, x6, x7)
-
-inst_750:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x028c817c11c9f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x28c817c11c9f;
-valaddr_reg:x9; val_offset:1454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1454*FLEN/8, x10, x6, x7)
-
-inst_751:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1456*FLEN/8, x10, x6, x7)
-
-inst_752:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1458*FLEN/8, x10, x6, x7)
-
-inst_753:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1460*FLEN/8, x10, x6, x7)
-
-inst_754:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1462*FLEN/8, x10, x6, x7)
-
-inst_755:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1464*FLEN/8, x10, x6, x7)
-
-inst_756:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xfafb7b5426c47 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x802fafb7b5426c47;
-valaddr_reg:x9; val_offset:1466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1466*FLEN/8, x10, x6, x7)
-
-inst_757:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x197d0ed8b1e34 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0x197d0ed8b1e34;
-valaddr_reg:x9; val_offset:1468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1468*FLEN/8, x10, x6, x7)
-
-inst_758:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1470*FLEN/8, x10, x6, x7)
-
-inst_759:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1472*FLEN/8, x10, x6, x7)
-
-inst_760:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xa0144329d87cc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x801a0144329d87cc;
-valaddr_reg:x9; val_offset:1474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1474*FLEN/8, x10, x6, x7)
-
-inst_761:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 0 and fe2 == 0x000 and fm2 == 0x197d0ed8b1e34 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0x197d0ed8b1e34;
-valaddr_reg:x9; val_offset:1476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1476*FLEN/8, x10, x6, x7)
-
-inst_762:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1478*FLEN/8, x10, x6, x7)
-
-inst_763:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1480*FLEN/8, x10, x6, x7)
-
-inst_764:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1482*FLEN/8, x10, x6, x7)
-
-inst_765:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1484*FLEN/8, x10, x6, x7)
-
-inst_766:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1486*FLEN/8, x10, x6, x7)
-
-inst_767:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1488*FLEN/8, x10, x6, x7)
-
-inst_768:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x4b32977d93970 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x8024b32977d93970;
-valaddr_reg:x9; val_offset:1490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1490*FLEN/8, x10, x6, x7)
-
-inst_769:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x197d0ed8b1e34 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0x197d0ed8b1e34;
-valaddr_reg:x9; val_offset:1492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1492*FLEN/8, x10, x6, x7)
-
-inst_770:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x197d0ed8b1e34 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x197d0ed8b1e34; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1494*FLEN/8, x10, x6, x7)
-
-inst_771:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x0;
-valaddr_reg:x9; val_offset:1496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1496*FLEN/8, x10, x6, x7)
-
-inst_772:// fs1 == 0 and fe1 == 0x400 and fm1 == 0x1b91ae09e503b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x4001b91ae09e503b; op2val:0x0;
-valaddr_reg:x9; val_offset:1498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1498*FLEN/8, x10, x6, x7)
-
-inst_773:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x1b91ae09e503b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x4001b91ae09e503b;
-valaddr_reg:x9; val_offset:1500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1500*FLEN/8, x10, x6, x7)
-
-inst_774:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfee29476f2e06 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x1b91ae09e503b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfee29476f2e06; op2val:0x4001b91ae09e503b;
-valaddr_reg:x9; val_offset:1502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1502*FLEN/8, x10, x6, x7)
-
-inst_775:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1504*FLEN/8, x10, x6, x7)
-
-inst_776:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1506*FLEN/8, x10, x6, x7)
-
-inst_777:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x43fe46d2b7ce6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x7fb43fe46d2b7ce6;
-valaddr_reg:x9; val_offset:1508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1508*FLEN/8, x10, x6, x7)
-
-inst_778:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1510*FLEN/8, x10, x6, x7)
-
-inst_779:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1512*FLEN/8, x10, x6, x7)
-
-inst_780:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1514*FLEN/8, x10, x6, x7)
-
-inst_781:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x94fdd88765c1f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x7fe94fdd88765c1f;
-valaddr_reg:x9; val_offset:1516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1516*FLEN/8, x10, x6, x7)
-
-inst_782:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1518*FLEN/8, x10, x6, x7)
-
-inst_783:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1520*FLEN/8, x10, x6, x7)
-
-inst_784:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1522*FLEN/8, x10, x6, x7)
-
-inst_785:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1524*FLEN/8, x10, x6, x7)
-
-inst_786:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1526*FLEN/8, x10, x6, x7)
-
-inst_787:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1528*FLEN/8, x10, x6, x7)
-
-inst_788:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1530*FLEN/8, x10, x6, x7)
-
-inst_789:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1532*FLEN/8, x10, x6, x7)
-
-inst_790:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1534*FLEN/8, x10, x6, x7)
-
-inst_791:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1536*FLEN/8, x10, x6, x7)
-
-inst_792:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1538*FLEN/8, x10, x6, x7)
-
-inst_793:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x94fdd88765c1f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe94fdd88765c1f; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1540*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_6)
-
-inst_794:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1542*FLEN/8, x10, x6, x7)
-
-inst_795:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1544*FLEN/8, x10, x6, x7)
-
-inst_796:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1546*FLEN/8, x10, x6, x7)
-
-inst_797:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x43fe46d2b7ce6 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb43fe46d2b7ce6; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1548*FLEN/8, x10, x6, x7)
-
-inst_798:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1550*FLEN/8, x10, x6, x7)
-
-inst_799:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1552*FLEN/8, x10, x6, x7)
-
-inst_800:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x105c326c5af30 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x105c326c5af30;
-valaddr_reg:x9; val_offset:1554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1554*FLEN/8, x10, x6, x7)
-
-inst_801:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1556*FLEN/8, x10, x6, x7)
-
-inst_802:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01a2d1d7a2b1e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1a2d1d7a2b1e; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1558*FLEN/8, x10, x6, x7)
-
-inst_803:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01a2d1d7a2b1e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x1a2d1d7a2b1e;
-valaddr_reg:x9; val_offset:1560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1560*FLEN/8, x10, x6, x7)
-
-inst_804:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1562*FLEN/8, x10, x6, x7)
-
-inst_805:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1564*FLEN/8, x10, x6, x7)
-
-inst_806:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1566*FLEN/8, x10, x6, x7)
-
-inst_807:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xfafb7b5426c47 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x802fafb7b5426c47;
-valaddr_reg:x9; val_offset:1568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1568*FLEN/8, x10, x6, x7)
-
-inst_808:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x105c326c5af30 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0x105c326c5af30;
-valaddr_reg:x9; val_offset:1570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1570*FLEN/8, x10, x6, x7)
-
-inst_809:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1572*FLEN/8, x10, x6, x7)
-
-inst_810:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1574*FLEN/8, x10, x6, x7)
-
-inst_811:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xa0144329d87cc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x801a0144329d87cc;
-valaddr_reg:x9; val_offset:1576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1576*FLEN/8, x10, x6, x7)
-
-inst_812:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 0 and fe2 == 0x000 and fm2 == 0x105c326c5af30 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0x105c326c5af30;
-valaddr_reg:x9; val_offset:1578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1578*FLEN/8, x10, x6, x7)
-
-inst_813:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1580*FLEN/8, x10, x6, x7)
-
-inst_814:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1582*FLEN/8, x10, x6, x7)
-
-inst_815:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1584*FLEN/8, x10, x6, x7)
-
-inst_816:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1586*FLEN/8, x10, x6, x7)
-
-inst_817:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1588*FLEN/8, x10, x6, x7)
-
-inst_818:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1590*FLEN/8, x10, x6, x7)
-
-inst_819:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x4b32977d93970 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x8024b32977d93970;
-valaddr_reg:x9; val_offset:1592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1592*FLEN/8, x10, x6, x7)
-
-inst_820:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x105c326c5af30 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0x105c326c5af30;
-valaddr_reg:x9; val_offset:1594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1594*FLEN/8, x10, x6, x7)
-
-inst_821:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x105c326c5af30 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x105c326c5af30; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1596*FLEN/8, x10, x6, x7)
-
-inst_822:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x0;
-valaddr_reg:x9; val_offset:1598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1598*FLEN/8, x10, x6, x7)
-
-inst_823:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x6c0679d004e5b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff6c0679d004e5b; op2val:0x0;
-valaddr_reg:x9; val_offset:1600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1600*FLEN/8, x10, x6, x7)
-
-inst_824:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x6c0679d004e5b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff6c0679d004e5b;
-valaddr_reg:x9; val_offset:1602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1602*FLEN/8, x10, x6, x7)
-
-inst_825:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa399f83b8d7e3 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x6c0679d004e5b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xa399f83b8d7e3; op2val:0x3ff6c0679d004e5b;
-valaddr_reg:x9; val_offset:1604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1604*FLEN/8, x10, x6, x7)
-
-inst_826:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1606*FLEN/8, x10, x6, x7)
-
-inst_827:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1608*FLEN/8, x10, x6, x7)
-
-inst_828:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x093dbe3aa0387 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x7fb093dbe3aa0387;
-valaddr_reg:x9; val_offset:1610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1610*FLEN/8, x10, x6, x7)
-
-inst_829:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1612*FLEN/8, x10, x6, x7)
-
-inst_830:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1614*FLEN/8, x10, x6, x7)
-
-inst_831:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1616*FLEN/8, x10, x6, x7)
-
-inst_832:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x4b8d2dc948469 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x7fe4b8d2dc948469;
-valaddr_reg:x9; val_offset:1618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1618*FLEN/8, x10, x6, x7)
-
-inst_833:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1620*FLEN/8, x10, x6, x7)
-
-inst_834:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1622*FLEN/8, x10, x6, x7)
-
-inst_835:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1624*FLEN/8, x10, x6, x7)
-
-inst_836:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1626*FLEN/8, x10, x6, x7)
-
-inst_837:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1628*FLEN/8, x10, x6, x7)
-
-inst_838:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1630*FLEN/8, x10, x6, x7)
-
-inst_839:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1632*FLEN/8, x10, x6, x7)
-
-inst_840:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1634*FLEN/8, x10, x6, x7)
-
-inst_841:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1636*FLEN/8, x10, x6, x7)
-
-inst_842:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1638*FLEN/8, x10, x6, x7)
-
-inst_843:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1640*FLEN/8, x10, x6, x7)
-
-inst_844:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x4b8d2dc948469 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe4b8d2dc948469; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1642*FLEN/8, x10, x6, x7)
-
-inst_845:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1644*FLEN/8, x10, x6, x7)
-
-inst_846:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1646*FLEN/8, x10, x6, x7)
-
-inst_847:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1648*FLEN/8, x10, x6, x7)
-
-inst_848:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x093dbe3aa0387 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb093dbe3aa0387; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1650*FLEN/8, x10, x6, x7)
-
-inst_849:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1652*FLEN/8, x10, x6, x7)
-
-inst_850:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1654*FLEN/8, x10, x6, x7)
-
-inst_851:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d64b86ad9094 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0xd64b86ad9094;
-valaddr_reg:x9; val_offset:1656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1656*FLEN/8, x10, x6, x7)
-
-inst_852:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1658*FLEN/8, x10, x6, x7)
-
-inst_853:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0156df3de280f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x156df3de280f; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1660*FLEN/8, x10, x6, x7)
-
-inst_854:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0156df3de280f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x156df3de280f;
-valaddr_reg:x9; val_offset:1662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1662*FLEN/8, x10, x6, x7)
-
-inst_855:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1664*FLEN/8, x10, x6, x7)
-
-inst_856:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xfafb7b5426c47 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x802fafb7b5426c47;
-valaddr_reg:x9; val_offset:1666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1666*FLEN/8, x10, x6, x7)
-
-inst_857:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d64b86ad9094 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0xd64b86ad9094;
-valaddr_reg:x9; val_offset:1668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1668*FLEN/8, x10, x6, x7)
-
-inst_858:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1670*FLEN/8, x10, x6, x7)
-
-inst_859:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1672*FLEN/8, x10, x6, x7)
-
-inst_860:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xa0144329d87cc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x801a0144329d87cc;
-valaddr_reg:x9; val_offset:1674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1674*FLEN/8, x10, x6, x7)
-
-inst_861:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d64b86ad9094 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0xd64b86ad9094;
-valaddr_reg:x9; val_offset:1676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1676*FLEN/8, x10, x6, x7)
-
-inst_862:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1678*FLEN/8, x10, x6, x7)
-
-inst_863:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1680*FLEN/8, x10, x6, x7)
-
-inst_864:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1682*FLEN/8, x10, x6, x7)
-
-inst_865:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1684*FLEN/8, x10, x6, x7)
-
-inst_866:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1686*FLEN/8, x10, x6, x7)
-
-inst_867:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1688*FLEN/8, x10, x6, x7)
-
-inst_868:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x4b32977d93970 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x8024b32977d93970;
-valaddr_reg:x9; val_offset:1690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1690*FLEN/8, x10, x6, x7)
-
-inst_869:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0d64b86ad9094 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0xd64b86ad9094;
-valaddr_reg:x9; val_offset:1692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1692*FLEN/8, x10, x6, x7)
-
-inst_870:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0d64b86ad9094 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xd64b86ad9094; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1694*FLEN/8, x10, x6, x7)
-
-inst_871:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x0;
-valaddr_reg:x9; val_offset:1696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1696*FLEN/8, x10, x6, x7)
-
-inst_872:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x2a038f94d730b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff2a038f94d730b; op2val:0x0;
-valaddr_reg:x9; val_offset:1698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1698*FLEN/8, x10, x6, x7)
-
-inst_873:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x2a038f94d730b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff2a038f94d730b;
-valaddr_reg:x9; val_offset:1700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1700*FLEN/8, x10, x6, x7)
-
-inst_874:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x85ef342c7a5c9 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x2a038f94d730b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x85ef342c7a5c9; op2val:0x3ff2a038f94d730b;
-valaddr_reg:x9; val_offset:1702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1702*FLEN/8, x10, x6, x7)
-
-inst_875:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1704*FLEN/8, x10, x6, x7)
-
-inst_876:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1706*FLEN/8, x10, x6, x7)
-
-inst_877:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xf6025caa2d205 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xffdf6025caa2d205;
-valaddr_reg:x9; val_offset:1708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1708*FLEN/8, x10, x6, x7)
-
-inst_878:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1710*FLEN/8, x10, x6, x7)
-
-inst_879:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1712*FLEN/8, x10, x6, x7)
-
-inst_880:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1714*FLEN/8, x10, x6, x7)
-
-inst_881:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1716*FLEN/8, x10, x6, x7)
-
-inst_882:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1718*FLEN/8, x10, x6, x7)
-
-inst_883:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1720*FLEN/8, x10, x6, x7)
-
-inst_884:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1722*FLEN/8, x10, x6, x7)
-
-inst_885:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1724*FLEN/8, x10, x6, x7)
-
-inst_886:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1726*FLEN/8, x10, x6, x7)
-
-inst_887:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1728*FLEN/8, x10, x6, x7)
-
-inst_888:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1730*FLEN/8, x10, x6, x7)
-
-inst_889:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1732*FLEN/8, x10, x6, x7)
-
-inst_890:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1734*FLEN/8, x10, x6, x7)
-
-inst_891:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1736*FLEN/8, x10, x6, x7)
-
-inst_892:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xf6025caa2d205 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdf6025caa2d205; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1738*FLEN/8, x10, x6, x7)
-
-inst_893:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1740*FLEN/8, x10, x6, x7)
-
-inst_894:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0a23bfe815416 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000a23bfe815416; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1742*FLEN/8, x10, x6, x7)
-
-inst_895:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0a23bfe815416 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x8000a23bfe815416;
-valaddr_reg:x9; val_offset:1744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1744*FLEN/8, x10, x6, x7)
-
-inst_896:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1746*FLEN/8, x10, x6, x7)
-
-inst_897:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1748*FLEN/8, x10, x6, x7)
-
-inst_898:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x002 and fm2 == 0xfafb7b5426c47 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x802fafb7b5426c47;
-valaddr_reg:x9; val_offset:1750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1750*FLEN/8, x10, x6, x7)
-
-inst_899:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1752*FLEN/8, x10, x6, x7)
-
-inst_900:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1754*FLEN/8, x10, x6, x7)
-
-inst_901:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1756*FLEN/8, x10, x6, x7)
-
-inst_902:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1758*FLEN/8, x10, x6, x7)
-
-inst_903:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1760*FLEN/8, x10, x6, x7)
-
-inst_904:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1762*FLEN/8, x10, x6, x7)
-
-inst_905:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1764*FLEN/8, x10, x6, x7)
-
-inst_906:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d8fae5b11a26 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0x8000d8fae5b11a26;
-valaddr_reg:x9; val_offset:1766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1766*FLEN/8, x10, x6, x7)
-
-inst_907:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xfafb7b5426c47 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x802fafb7b5426c47;
-valaddr_reg:x9; val_offset:1768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1768*FLEN/8, x10, x6, x7)
-
-inst_908:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1770*FLEN/8, x10, x6, x7)
-
-inst_909:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1772*FLEN/8, x10, x6, x7)
-
-inst_910:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x15be852c0ecf4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0x80015be852c0ecf4;
-valaddr_reg:x9; val_offset:1774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1774*FLEN/8, x10, x6, x7)
-
-inst_911:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xfafb7b5426c47 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x802fafb7b5426c47;
-valaddr_reg:x9; val_offset:1776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1776*FLEN/8, x10, x6, x7)
-
-inst_912:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xfafb7b5426c47 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802fafb7b5426c47; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1778*FLEN/8, x10, x6, x7)
-
-inst_913:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1780*FLEN/8, x10, x6, x7)
-
-inst_914:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1782*FLEN/8, x10, x6, x7)
-
-inst_915:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0x0;
-valaddr_reg:x9; val_offset:1784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1784*FLEN/8, x10, x6, x7)
-
-inst_916:// fs1 == 1 and fe1 == 0x402 and fm1 == 0x1a04aee65a608 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc021a04aee65a608; op2val:0x0;
-valaddr_reg:x9; val_offset:1786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1786*FLEN/8, x10, x6, x7)
-
-inst_917:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x1a04aee65a608 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc021a04aee65a608;
-valaddr_reg:x9; val_offset:1788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1788*FLEN/8, x10, x6, x7)
-
-inst_918:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x65657f10d48db and fs2 == 1 and fe2 == 0x402 and fm2 == 0x1a04aee65a608 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80065657f10d48db; op2val:0xc021a04aee65a608;
-valaddr_reg:x9; val_offset:1790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1790*FLEN/8, x10, x6, x7)
-
-inst_919:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1792*FLEN/8, x10, x6, x7)
-
-inst_920:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1794*FLEN/8, x10, x6, x7)
-
-inst_921:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x9bff6a8783cf3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xffc9bff6a8783cf3;
-valaddr_reg:x9; val_offset:1796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1796*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_7)
-
-inst_922:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1798*FLEN/8, x10, x6, x7)
-
-inst_923:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1800*FLEN/8, x10, x6, x7)
-
-inst_924:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1802*FLEN/8, x10, x6, x7)
-
-inst_925:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1804*FLEN/8, x10, x6, x7)
-
-inst_926:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1806*FLEN/8, x10, x6, x7)
-
-inst_927:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1808*FLEN/8, x10, x6, x7)
-
-inst_928:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1810*FLEN/8, x10, x6, x7)
-
-inst_929:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1812*FLEN/8, x10, x6, x7)
-
-inst_930:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1814*FLEN/8, x10, x6, x7)
-
-inst_931:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1816*FLEN/8, x10, x6, x7)
-
-inst_932:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1818*FLEN/8, x10, x6, x7)
-
-inst_933:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1820*FLEN/8, x10, x6, x7)
-
-inst_934:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1822*FLEN/8, x10, x6, x7)
-
-inst_935:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1824*FLEN/8, x10, x6, x7)
-
-inst_936:// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x9bff6a8783cf3 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffc9bff6a8783cf3; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1826*FLEN/8, x10, x6, x7)
-
-inst_937:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1828*FLEN/8, x10, x6, x7)
-
-inst_938:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x042929a1b2ce1 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800042929a1b2ce1; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1830*FLEN/8, x10, x6, x7)
-
-inst_939:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x042929a1b2ce1 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x800042929a1b2ce1;
-valaddr_reg:x9; val_offset:1832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1832*FLEN/8, x10, x6, x7)
-
-inst_940:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1834*FLEN/8, x10, x6, x7)
-
-inst_941:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:1836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1836*FLEN/8, x10, x6, x7)
-
-inst_942:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xa0144329d87cc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x801a0144329d87cc;
-valaddr_reg:x9; val_offset:1838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1838*FLEN/8, x10, x6, x7)
-
-inst_943:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1840*FLEN/8, x10, x6, x7)
-
-inst_944:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:1842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1842*FLEN/8, x10, x6, x7)
-
-inst_945:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1844*FLEN/8, x10, x6, x7)
-
-inst_946:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:1846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1846*FLEN/8, x10, x6, x7)
-
-inst_947:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1848*FLEN/8, x10, x6, x7)
-
-inst_948:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d8fae5b11a26 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0x8000d8fae5b11a26;
-valaddr_reg:x9; val_offset:1850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1850*FLEN/8, x10, x6, x7)
-
-inst_949:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xa0144329d87cc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x801a0144329d87cc;
-valaddr_reg:x9; val_offset:1852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1852*FLEN/8, x10, x6, x7)
-
-inst_950:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1854*FLEN/8, x10, x6, x7)
-
-inst_951:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1856*FLEN/8, x10, x6, x7)
-
-inst_952:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x15be852c0ecf4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0x80015be852c0ecf4;
-valaddr_reg:x9; val_offset:1858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1858*FLEN/8, x10, x6, x7)
-
-inst_953:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xa0144329d87cc and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x801a0144329d87cc;
-valaddr_reg:x9; val_offset:1860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1860*FLEN/8, x10, x6, x7)
-
-inst_954:// fs1 == 1 and fe1 == 0x001 and fm1 == 0xa0144329d87cc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x801a0144329d87cc; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1862*FLEN/8, x10, x6, x7)
-
-inst_955:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1864*FLEN/8, x10, x6, x7)
-
-inst_956:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1866*FLEN/8, x10, x6, x7)
-
-inst_957:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0x0;
-valaddr_reg:x9; val_offset:1868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1868*FLEN/8, x10, x6, x7)
-
-inst_958:// fs1 == 1 and fe1 == 0x400 and fm1 == 0xcee7468323917 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc00cee7468323917; op2val:0x0;
-valaddr_reg:x9; val_offset:1870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1870*FLEN/8, x10, x6, x7)
-
-inst_959:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x400 and fm2 == 0xcee7468323917 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc00cee7468323917;
-valaddr_reg:x9; val_offset:1872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1872*FLEN/8, x10, x6, x7)
-
-inst_960:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x299ba050fc0c8 and fs2 == 1 and fe2 == 0x400 and fm2 == 0xcee7468323917 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800299ba050fc0c8; op2val:0xc00cee7468323917;
-valaddr_reg:x9; val_offset:1874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1874*FLEN/8, x10, x6, x7)
-
-inst_961:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1876*FLEN/8, x10, x6, x7)
-
-inst_962:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1878*FLEN/8, x10, x6, x7)
-
-inst_963:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x0c90875ccb5d8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xffb0c90875ccb5d8;
-valaddr_reg:x9; val_offset:1880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1880*FLEN/8, x10, x6, x7)
-
-inst_964:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1882*FLEN/8, x10, x6, x7)
-
-inst_965:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1884*FLEN/8, x10, x6, x7)
-
-inst_966:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1886*FLEN/8, x10, x6, x7)
-
-inst_967:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x4fb4a933fe34f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xffe4fb4a933fe34f;
-valaddr_reg:x9; val_offset:1888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1888*FLEN/8, x10, x6, x7)
-
-inst_968:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1890*FLEN/8, x10, x6, x7)
-
-inst_969:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1892*FLEN/8, x10, x6, x7)
-
-inst_970:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1894*FLEN/8, x10, x6, x7)
-
-inst_971:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1896*FLEN/8, x10, x6, x7)
-
-inst_972:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1898*FLEN/8, x10, x6, x7)
-
-inst_973:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1900*FLEN/8, x10, x6, x7)
-
-inst_974:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1902*FLEN/8, x10, x6, x7)
-
-inst_975:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1904*FLEN/8, x10, x6, x7)
-
-inst_976:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1906*FLEN/8, x10, x6, x7)
-
-inst_977:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1908*FLEN/8, x10, x6, x7)
-
-inst_978:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1910*FLEN/8, x10, x6, x7)
-
-inst_979:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x4fb4a933fe34f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe4fb4a933fe34f; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1912*FLEN/8, x10, x6, x7)
-
-inst_980:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1914*FLEN/8, x10, x6, x7)
-
-inst_981:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1916*FLEN/8, x10, x6, x7)
-
-inst_982:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1918*FLEN/8, x10, x6, x7)
-
-inst_983:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x0c90875ccb5d8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb0c90875ccb5d8; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1920*FLEN/8, x10, x6, x7)
-
-inst_984:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1922*FLEN/8, x10, x6, x7)
-
-inst_985:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1924*FLEN/8, x10, x6, x7)
-
-inst_986:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d8fae5b11a26 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x8000d8fae5b11a26;
-valaddr_reg:x9; val_offset:1926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1926*FLEN/8, x10, x6, x7)
-
-inst_987:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1928*FLEN/8, x10, x6, x7)
-
-inst_988:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x015b2b091b5d1 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800015b2b091b5d1; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:1930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1930*FLEN/8, x10, x6, x7)
-
-inst_989:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x015b2b091b5d1 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x800015b2b091b5d1;
-valaddr_reg:x9; val_offset:1932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1932*FLEN/8, x10, x6, x7)
-
-inst_990:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1934*FLEN/8, x10, x6, x7)
-
-inst_991:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:1936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1936*FLEN/8, x10, x6, x7)
-
-inst_992:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1938*FLEN/8, x10, x6, x7)
-
-inst_993:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:1940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1940*FLEN/8, x10, x6, x7)
-
-inst_994:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1942*FLEN/8, x10, x6, x7)
-
-inst_995:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:1944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1944*FLEN/8, x10, x6, x7)
-
-inst_996:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1946*FLEN/8, x10, x6, x7)
-
-inst_997:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x4b32977d93970 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x8024b32977d93970;
-valaddr_reg:x9; val_offset:1948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1948*FLEN/8, x10, x6, x7)
-
-inst_998:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d8fae5b11a26 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0x8000d8fae5b11a26;
-valaddr_reg:x9; val_offset:1950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1950*FLEN/8, x10, x6, x7)
-
-inst_999:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d8fae5b11a26 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d8fae5b11a26; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:1952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1952*FLEN/8, x10, x6, x7)
-
-inst_1000:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0x0;
-valaddr_reg:x9; val_offset:1954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1954*FLEN/8, x10, x6, x7)
-
-inst_1001:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x2dbf77d539bae and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbff2dbf77d539bae; op2val:0x0;
-valaddr_reg:x9; val_offset:1956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1956*FLEN/8, x10, x6, x7)
-
-inst_1002:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x2dbf77d539bae and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbff2dbf77d539bae;
-valaddr_reg:x9; val_offset:1958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1958*FLEN/8, x10, x6, x7)
-
-inst_1003:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x879ccf8eb0579 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x2dbf77d539bae and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800879ccf8eb0579; op2val:0xbff2dbf77d539bae;
-valaddr_reg:x9; val_offset:1960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1960*FLEN/8, x10, x6, x7)
-
-inst_1004:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1962*FLEN/8, x10, x6, x7)
-
-inst_1005:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:1964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1964*FLEN/8, x10, x6, x7)
-
-inst_1006:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xae9e55abc765f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xffbae9e55abc765f;
-valaddr_reg:x9; val_offset:1966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1966*FLEN/8, x10, x6, x7)
-
-inst_1007:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:1968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1968*FLEN/8, x10, x6, x7)
-
-inst_1008:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:1970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1970*FLEN/8, x10, x6, x7)
-
-inst_1009:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1972*FLEN/8, x10, x6, x7)
-
-inst_1010:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1974*FLEN/8, x10, x6, x7)
-
-inst_1011:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:1976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1976*FLEN/8, x10, x6, x7)
-
-inst_1012:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:1978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1978*FLEN/8, x10, x6, x7)
-
-inst_1013:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:1980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1980*FLEN/8, x10, x6, x7)
-
-inst_1014:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1982*FLEN/8, x10, x6, x7)
-
-inst_1015:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:1984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1984*FLEN/8, x10, x6, x7)
-
-inst_1016:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:1986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1986*FLEN/8, x10, x6, x7)
-
-inst_1017:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:1988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1988*FLEN/8, x10, x6, x7)
-
-inst_1018:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1990*FLEN/8, x10, x6, x7)
-
-inst_1019:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:1992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1992*FLEN/8, x10, x6, x7)
-
-inst_1020:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1994*FLEN/8, x10, x6, x7)
-
-inst_1021:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xae9e55abc765f and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbae9e55abc765f; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:1996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1996*FLEN/8, x10, x6, x7)
-
-inst_1022:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:1998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 1998*FLEN/8, x10, x6, x7)
-
-inst_1023:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:2000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2000*FLEN/8, x10, x6, x7)
-
-inst_1024:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x15be852c0ecf4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x80015be852c0ecf4;
-valaddr_reg:x9; val_offset:2002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2002*FLEN/8, x10, x6, x7)
-
-inst_1025:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:2004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2004*FLEN/8, x10, x6, x7)
-
-inst_1026:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x022ca6eace47f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800022ca6eace47f; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:2006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2006*FLEN/8, x10, x6, x7)
-
-inst_1027:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x022ca6eace47f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x800022ca6eace47f;
-valaddr_reg:x9; val_offset:2008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2008*FLEN/8, x10, x6, x7)
-
-inst_1028:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:2010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2010*FLEN/8, x10, x6, x7)
-
-inst_1029:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:2012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2012*FLEN/8, x10, x6, x7)
-
-inst_1030:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:2014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2014*FLEN/8, x10, x6, x7)
-
-inst_1031:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:2016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2016*FLEN/8, x10, x6, x7)
-
-inst_1032:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:2018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2018*FLEN/8, x10, x6, x7)
-
-inst_1033:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x4b32977d93970 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x8024b32977d93970;
-valaddr_reg:x9; val_offset:2020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2020*FLEN/8, x10, x6, x7)
-
-inst_1034:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x15be852c0ecf4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0x80015be852c0ecf4;
-valaddr_reg:x9; val_offset:2022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2022*FLEN/8, x10, x6, x7)
-
-inst_1035:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x15be852c0ecf4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80015be852c0ecf4; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:2024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2024*FLEN/8, x10, x6, x7)
-
-inst_1036:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0x0;
-valaddr_reg:x9; val_offset:2026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2026*FLEN/8, x10, x6, x7)
-
-inst_1037:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xe3d32f95a320d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbffe3d32f95a320d; op2val:0x0;
-valaddr_reg:x9; val_offset:2028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2028*FLEN/8, x10, x6, x7)
-
-inst_1038:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xe3d32f95a320d and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbffe3d32f95a320d;
-valaddr_reg:x9; val_offset:2030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2030*FLEN/8, x10, x6, x7)
-
-inst_1039:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd97133b894184 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xe3d32f95a320d and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d97133b894184; op2val:0xbffe3d32f95a320d;
-valaddr_reg:x9; val_offset:2032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2032*FLEN/8, x10, x6, x7)
-
-inst_1040:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:2034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2034*FLEN/8, x10, x6, x7)
-
-inst_1041:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:2036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2036*FLEN/8, x10, x6, x7)
-
-inst_1042:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x47f2e5cadc271 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xffd47f2e5cadc271;
-valaddr_reg:x9; val_offset:2038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2038*FLEN/8, x10, x6, x7)
-
-inst_1043:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:2040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2040*FLEN/8, x10, x6, x7)
-
-inst_1044:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:2042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2042*FLEN/8, x10, x6, x7)
-
-inst_1045:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:2044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2044*FLEN/8, x10, x6, x7)
-
-inst_1046:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:2046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2046*FLEN/8, x10, x6, x7)
-
-inst_1047:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:2048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2048*FLEN/8, x10, x6, x7)
-
-inst_1048:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:2050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2050*FLEN/8, x10, x6, x7)
-
-inst_1049:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:2052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2052*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_8)
-
-inst_1050:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:2054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2054*FLEN/8, x10, x6, x7)
-
-inst_1051:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:2056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2056*FLEN/8, x10, x6, x7)
-
-inst_1052:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:2058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2058*FLEN/8, x10, x6, x7)
-
-inst_1053:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:2060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2060*FLEN/8, x10, x6, x7)
-
-inst_1054:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:2062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2062*FLEN/8, x10, x6, x7)
-
-inst_1055:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:2064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2064*FLEN/8, x10, x6, x7)
-
-inst_1056:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:2066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2066*FLEN/8, x10, x6, x7)
-
-inst_1057:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x47f2e5cadc271 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd47f2e5cadc271; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:2068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2068*FLEN/8, x10, x6, x7)
-
-inst_1058:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:2070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2070*FLEN/8, x10, x6, x7)
-
-inst_1059:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x069fbb598d312 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800069fbb598d312; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:2072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2072*FLEN/8, x10, x6, x7)
-
-inst_1060:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x069fbb598d312 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x800069fbb598d312;
-valaddr_reg:x9; val_offset:2074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2074*FLEN/8, x10, x6, x7)
-
-inst_1061:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:2076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2076*FLEN/8, x10, x6, x7)
-
-inst_1062:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:2078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2078*FLEN/8, x10, x6, x7)
-
-inst_1063:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x4b32977d93970 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x8024b32977d93970;
-valaddr_reg:x9; val_offset:2080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2080*FLEN/8, x10, x6, x7)
-
-inst_1064:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:2082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2082*FLEN/8, x10, x6, x7)
-
-inst_1065:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:2084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2084*FLEN/8, x10, x6, x7)
-
-inst_1066:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:2086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2086*FLEN/8, x10, x6, x7)
-
-inst_1067:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:2088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2088*FLEN/8, x10, x6, x7)
-
-inst_1068:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:2090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2090*FLEN/8, x10, x6, x7)
-
-inst_1069:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:2092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2092*FLEN/8, x10, x6, x7)
-
-inst_1070:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:2094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2094*FLEN/8, x10, x6, x7)
-
-inst_1071:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x4b32977d93970 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8024b32977d93970; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:2096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2096*FLEN/8, x10, x6, x7)
-
-inst_1072:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0x0;
-valaddr_reg:x9; val_offset:2098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2098*FLEN/8, x10, x6, x7)
-
-inst_1073:// fs1 == 1 and fe1 == 0x401 and fm1 == 0x707836e56fe8b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc01707836e56fe8b; op2val:0x0;
-valaddr_reg:x9; val_offset:2100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2100*FLEN/8, x10, x6, x7)
-
-inst_1074:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x707836e56fe8b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc01707836e56fe8b;
-valaddr_reg:x9; val_offset:2102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2102*FLEN/8, x10, x6, x7)
-
-inst_1075:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x423d517f83eb0 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x707836e56fe8b and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800423d517f83eb0; op2val:0xc01707836e56fe8b;
-valaddr_reg:x9; val_offset:2104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2104*FLEN/8, x10, x6, x7)
-
-inst_1076:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xe759ff97b7507 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fce759ff97b7507;
-valaddr_reg:x9; val_offset:2106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2106*FLEN/8, x10, x6, x7)
-
-inst_1077:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x9; val_offset:2108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2108*FLEN/8, x10, x6, x7)
-
-inst_1078:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:2110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2110*FLEN/8, x10, x6, x7)
-
-inst_1079:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x09941946801c5 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fd09941946801c5;
-valaddr_reg:x9; val_offset:2112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2112*FLEN/8, x10, x6, x7)
-
-inst_1080:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xac44ace32d282 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7feac44ace32d282;
-valaddr_reg:x9; val_offset:2114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2114*FLEN/8, x10, x6, x7)
-
-inst_1081:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x450c74c9b42e4 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fe450c74c9b42e4;
-valaddr_reg:x9; val_offset:2116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2116*FLEN/8, x10, x6, x7)
-
-inst_1082:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2b592ef4e4e6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffdd2b592ef4e4e6;
-valaddr_reg:x9; val_offset:2118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2118*FLEN/8, x10, x6, x7)
-
-inst_1083:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xde7300593ddb7 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffede7300593ddb7;
-valaddr_reg:x9; val_offset:2120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2120*FLEN/8, x10, x6, x7)
-
-inst_1084:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x8805c5b3ba76f and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffe8805c5b3ba76f;
-valaddr_reg:x9; val_offset:2122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2122*FLEN/8, x10, x6, x7)
-
-inst_1085:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0c1b6ea69558e and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffe0c1b6ea69558e;
-valaddr_reg:x9; val_offset:2124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2124*FLEN/8, x10, x6, x7)
-
-inst_1086:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x0e3e4312fc728 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffc0e3e4312fc728;
-valaddr_reg:x9; val_offset:2126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2126*FLEN/8, x10, x6, x7)
-
-inst_1087:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:2128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2128*FLEN/8, x10, x6, x7)
-
-inst_1088:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x035efa3d150a6 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x35efa3d150a6;
-valaddr_reg:x9; val_offset:2130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2130*FLEN/8, x10, x6, x7)
-
-inst_1089:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfee29476f2e06 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xfee29476f2e06;
-valaddr_reg:x9; val_offset:2132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2132*FLEN/8, x10, x6, x7)
-
-inst_1090:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa399f83b8d7e3 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xa399f83b8d7e3;
-valaddr_reg:x9; val_offset:2134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2134*FLEN/8, x10, x6, x7)
-
-inst_1091:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x85ef342c7a5c9 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x85ef342c7a5c9;
-valaddr_reg:x9; val_offset:2136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2136*FLEN/8, x10, x6, x7)
-
-inst_1092:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x65657f10d48db and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x80065657f10d48db;
-valaddr_reg:x9; val_offset:2138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2138*FLEN/8, x10, x6, x7)
-
-inst_1093:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x299ba050fc0c8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800299ba050fc0c8;
-valaddr_reg:x9; val_offset:2140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2140*FLEN/8, x10, x6, x7)
-
-inst_1094:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x879ccf8eb0579 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800879ccf8eb0579;
-valaddr_reg:x9; val_offset:2142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2142*FLEN/8, x10, x6, x7)
-
-inst_1095:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd97133b894184 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800d97133b894184;
-valaddr_reg:x9; val_offset:2144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2144*FLEN/8, x10, x6, x7)
-
-inst_1096:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x423d517f83eb0 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800423d517f83eb0;
-valaddr_reg:x9; val_offset:2146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2146*FLEN/8, x10, x6, x7)
-
-inst_1097:// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xe759ff97b7507 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x405e69652cae2 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fce759ff97b7507; op2val:0x7fe405e69652cae2;
-valaddr_reg:x9; val_offset:2148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2148*FLEN/8, x10, x6, x7)
-
-inst_1098:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3137cb6875068 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x5eb561bd4f6b8 and  fcsr == 0  
-/* opcode: fleq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3137cb6875068; op2val:0x5eb561bd4f6b8;
-valaddr_reg:x9; val_offset:2150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.d, x31, f31, f30, 0, 0, x9, 2150*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
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-NAN_BOXED(9209427617965110535,64,FLEN)
-NAN_BOXED(18440129808424478575,64,FLEN)
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-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9210029744914432453,64,FLEN)
-NAN_BOXED(18427297996618888799,64,FLEN)
-NAN_BOXED(9210029744914432453,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9217395412933202562,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9215579554420835044,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(18436940111564563686,64,FLEN)
-NAN_BOXED(18427297996618888799,64,FLEN)
-NAN_BOXED(18436940111564563686,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(18441650242590072247,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(18440129808424478575,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(18437949865815790990,64,FLEN)
-NAN_BOXED(18427297996618888799,64,FLEN)
-NAN_BOXED(18437949865815790990,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(18428980244417333032,64,FLEN)
-NAN_BOXED(18427297996618888799,64,FLEN)
-NAN_BOXED(18428980244417333032,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(1666129950209720,64,FLEN)
-NAN_BOXED(9223754565210402036,64,FLEN)
-NAN_BOXED(1666129950209720,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9223754565210402036,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(59303361859750,64,FLEN)
-NAN_BOXED(9223410289690338431,64,FLEN)
-NAN_BOXED(59303361859750,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9223410289690338431,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9225155822421362907,64,FLEN)
-NAN_BOXED(9223754565210402036,64,FLEN)
-NAN_BOXED(9225155822421362907,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9224104011036082376,64,FLEN)
-NAN_BOXED(9223754565210402036,64,FLEN)
-NAN_BOXED(9224104011036082376,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9223754565210402036,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(9223754565210402036,64,FLEN)
-NAN_BOXED(9223754565210402036,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13834562394469839373,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13834562394469839373,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(13834562394469839373,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9209427617965110535,64,FLEN)
-NAN_BOXED(18434499011834397297,64,FLEN)
-NAN_BOXED(9209427617965110535,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(18434499011834397297,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9215497225429502690,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9210029744914432453,64,FLEN)
-NAN_BOXED(18434499011834397297,64,FLEN)
-NAN_BOXED(9210029744914432453,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9217395412933202562,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9215579554420835044,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(18436940111564563686,64,FLEN)
-NAN_BOXED(18434499011834397297,64,FLEN)
-NAN_BOXED(18436940111564563686,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(18441650242590072247,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(18440129808424478575,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(18437949865815790990,64,FLEN)
-NAN_BOXED(18434499011834397297,64,FLEN)
-NAN_BOXED(18437949865815790990,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(18428980244417333032,64,FLEN)
-NAN_BOXED(18434499011834397297,64,FLEN)
-NAN_BOXED(18428980244417333032,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(59303361859750,64,FLEN)
-NAN_BOXED(9223488566659175186,64,FLEN)
-NAN_BOXED(59303361859750,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9223488566659175186,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(4483985710198278,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(4483985710198278,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(2878107039619043,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(2878107039619043,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(2356198704129481,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(2356198704129481,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9225757757924902265,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(9225757757924902265,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9233702126702115184,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13841540240819814027,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13841540240819814027,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(13841540240819814027,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9209427617965110535,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9215497225429502690,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9210029744914432453,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9217395412933202562,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9215579554420835044,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18436940111564563686,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18441650242590072247,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18440129808424478575,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18437949865815790990,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18428980244417333032,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(1666129950209720,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(59303361859750,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(4483985710198278,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2878107039619043,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2356198704129481,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9225155822421362907,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9224104011036082376,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9225757757924902265,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9227197320411038084,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9224537334898769584,64,FLEN)
-NAN_BOXED(9209427617965110535,64,FLEN)
-NAN_BOXED(9215497225429502690,64,FLEN)
-NAN_BOXED(865851289325672,64,FLEN)
-NAN_BOXED(1666129950209720,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_7:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_8:
-    .fill 98*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b1-01.S
deleted file mode 100644
index 17e9a7e7a..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b1-01.S
+++ /dev/null
@@ -1,368 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:13:48 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fleq.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fleq.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fleq_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 == rs2, rs1==f31, rs2==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f31; op2:f31; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 != rs2, rs1==f30, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f30; op2:f29; dest:x30; op1val:0x0; op2val:0x80000000;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x30, f30, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f29, rs2==f30, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f29; op2:f30; dest:x29; op1val:0x0; op2val:0x1;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x29, f29, f30, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f28; op2:f27; dest:x28; op1val:0x0; op2val:0x80000001;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f27; op2:f28; dest:x27; op1val:0x0; op2val:0x2;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f26; op2:f25; dest:x26; op1val:0x0; op2val:0x807ffffe;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f25; op2:f26; dest:x25; op1val:0x0; op2val:0x7fffff;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f24; op2:f23; dest:x24; op1val:0x0; op2val:0x807fffff;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f23; op2:f24; dest:x23; op1val:0x0; op2val:0x800000;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f22; op2:f21; dest:x22; op1val:0x0; op2val:0x80800000;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f21; op2:f22; dest:x21; op1val:0x0; op2val:0x800001;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f20; op2:f19; dest:x20; op1val:0x0; op2val:0x80855555;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f19; op2:f20; dest:x19; op1val:0x0; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f18; op2:f17; dest:x18; op1val:0x0; op2val:0xff7fffff;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f17; op2:f18; dest:x17; op1val:0x0; op2val:0x7f800000;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f16; op2:f15; dest:x16; op1val:0x0; op2val:0xff800000;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f15; op2:f16; dest:x15; op1val:0x0; op2val:0x7fc00000;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f14; op2:f13; dest:x14; op1val:0x0; op2val:0xffc00000;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f13; op2:f14; dest:x13; op1val:0x0; op2val:0x7fc00001;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f12; op2:f11; dest:x12; op1val:0x0; op2val:0xffc55555;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f11; op2:f12; dest:x11; op1val:0x0; op2val:0x7f800001;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f10; op2:f9; dest:x10; op1val:0x0; op2val:0xffaaaaaa;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f9; op2:f10; dest:x9; op1val:0x0; op2val:0x3f800000;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f8; op2:f7; dest:x8; op1val:0x0; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f7; op2:f8; dest:x7; op1val:0x80000000; op2val:0x0;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f6; op2:f5; dest:x6; op1val:0x80000000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f5; op2:f6; dest:x5; op1val:0x80000000; op2val:0x1;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f4; op2:f3; dest:x4; op1val:0x80000000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f3; op2:f4; dest:x3; op1val:0x80000000; op2val:0x2;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f2; op2:f1; dest:x2; op1val:0x80000000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f1; op2:f2; dest:x1; op1val:0x80000000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f0; op2:f31; dest:x31; op1val:0x80000000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f31; op2:f0; dest:x31; op1val:0x80000000; op2val:0x800000;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x0; op1val:0x80000000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-test_dataset_1:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 16*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b19-01.S
deleted file mode 100644
index c9493db9b..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fleq_b19-01.S
+++ /dev/null
@@ -1,368 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:13:48 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fleq.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fleq.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fleq_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 == rs2, rs1==f31, rs2==f31, rd==x31,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f31; op2:f31; dest:x31; op1val:0x7e36c1bf; op2val:0x7e36c1bf;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 != rs2, rs1==f30, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f30; op2:f29; dest:x30; op1val:0x7e36c1bf; op2val:0x7ef046ce;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x30, f30, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f29, rs2==f30, rd==x29,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x4038a5 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f29; op2:f30; dest:x29; op1val:0x7f7fffff; op2val:0x7d4038a5;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x29, f29, f30, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0xfa and fm1 == 0x4038a5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f28; op2:f27; dest:x28; op1val:0x7d4038a5; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f27; op2:f28; dest:x27; op1val:0x7f7fffff; op2val:0x7ef046ce;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f26; op2:f25; dest:x26; op1val:0x7e36c1bf; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f25; op2:f26; dest:x25; op1val:0x7e36c1bf; op2val:0x7e472f12;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f24; op2:f23; dest:x24; op1val:0x7e472f12; op2val:0x7e36c1bf;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f23; op2:f24; dest:x23; op1val:0x7e36c1bf; op2val:0x7f2099c0;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x007b00 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f22; op2:f21; dest:x22; op1val:0x7f7fffff; op2val:0x7d807b00;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0xfb and fm1 == 0x007b00 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f21; op2:f22; dest:x21; op1val:0x7d807b00; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f20; op2:f19; dest:x20; op1val:0x7f7fffff; op2val:0x7f2099c0;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f19; op2:f20; dest:x19; op1val:0x7e36c1bf; op2val:0x7ef3c956;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x430778 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f18; op2:f17; dest:x18; op1val:0x7f7fffff; op2val:0x7d430778;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0xfa and fm1 == 0x430778 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f17; op2:f18; dest:x17; op1val:0x7d430778; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f16; op2:f15; dest:x16; op1val:0x7f7fffff; op2val:0x7ef3c956;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f15; op2:f16; dest:x15; op1val:0x7e36c1bf; op2val:0xfeaf0416;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x0c0345 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f14; op2:f13; dest:x14; op1val:0x7f7fffff; op2val:0xfd0c0345;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c0345 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f13; op2:f14; dest:x13; op1val:0xfd0c0345; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f12; op2:f11; dest:x12; op1val:0x7f7fffff; op2val:0xfeaf0416;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f11; op2:f12; dest:x11; op1val:0x7e36c1bf; op2val:0xff336b1f;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0f88e6 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f10; op2:f9; dest:x10; op1val:0x7f7fffff; op2val:0xfd8f88e6;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 1 and fe1 == 0xfb and fm1 == 0x0f88e6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f9; op2:f10; dest:x9; op1val:0xfd8f88e6; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f8; op2:f7; dest:x8; op1val:0x7f7fffff; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f7; op2:f8; dest:x7; op1val:0x7e36c1bf; op2val:0xff130229;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x6b36a9 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f6; op2:f5; dest:x6; op1val:0x7f7fffff; op2val:0xfd6b36a9;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0xfa and fm1 == 0x6b36a9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f5; op2:f6; dest:x5; op1val:0xfd6b36a9; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f4; op2:f3; dest:x4; op1val:0x7f7fffff; op2val:0xff130229;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f3; op2:f4; dest:x3; op1val:0x7e36c1bf; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x20dd41 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f2; op2:f1; dest:x2; op1val:0x7f7fffff; op2val:0xfd20dd41;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0xfa and fm1 == 0x20dd41 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f1; op2:f2; dest:x1; op1val:0xfd20dd41; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f0; op2:f31; dest:x31; op1val:0x7f7fffff; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f31; op2:f0; dest:x31; op1val:0x7e36c1bf; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x0; op1val:0xfdcaaeb1; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2101360805,32,FLEN)
-NAN_BOXED(2101360805,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2105572096,32,FLEN)
-NAN_BOXED(2105572096,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2101544824,32,FLEN)
-NAN_BOXED(2101544824,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4245422917,32,FLEN)
-NAN_BOXED(4245422917,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4254042342,32,FLEN)
-NAN_BOXED(4254042342,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-test_dataset_1:
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4251661993,32,FLEN)
-NAN_BOXED(4251661993,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4246789441,32,FLEN)
-NAN_BOXED(4246789441,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 16*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fli.d-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fli.d-01.S
deleted file mode 100644
index b670ebc23..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fli.d-01.S
+++ /dev/null
@@ -1,204 +0,0 @@
-// Copyright (c) 2023. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fli.d instruction
-// for the following ISA configurations:
-// * RV32ID_Zfa
-// * RV64ID_Zfa
-
-#include "model_test.h"
-#include "arch_test.h"
-
-RVTEST_ISA("RV32ID_Zfa,RV64ID_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-
-RVMODEL_BOOT
-
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fli.d)
-
-// Registers with a special purpose
-#define SIG_BASEREG x1
-#define FCSR_REG x2
-#define DATA_BASEREG x3
-
-// Initialize the FPU
-RVTEST_FP_ENABLE()
-// Prepare the DATA_BASEREG register
-RVTEST_VALBASEUPD(DATA_BASEREG, dataset_tc1)
-// Prepare the SIG_BASEREG register
-RVTEST_SIGBASE(SIG_BASEREG, signature_tc1)
-
-// FLI.D loads a pre-defined constant into a FP register.
-// FLI.D has the following inputs and outputs:
-// - input rs1: 5-bit immediate holding the constants ID
-// - output fld: FP register
-
-// TEST_CASE_FLI_D executes a FLI.D insn and stores the result in the sig
-// 1) the FCSR_OLD value will be store into FCSR using FCSR_REG
-// 2) fli.d is executed using FLD as dest register and FLI_CONST as constant
-// 3) The constents of FLD and FCSR are stored in the signature
-#define TEST_CASE_FLI_D(fld, fli_const, fcsr_old, fcsr_reg) \
-    li fcsr_reg, fcsr_old ;\
-    csrw fcsr, fcsr_reg   ;\
-    fli.d fld, fli_const  ;\
-    csrr fcsr_reg, fcsr   ;\
-    RVTEST_SIGUPD_F(SIG_BASEREG, fld, fcsr_reg) ;\
-
-// Below we have one instruction test per constant
-
-inst_0:
-TEST_CASE_FLI_D(f16, -0x1p+0, 0, FCSR_REG)
-
-inst_1:
-TEST_CASE_FLI_D(f17, min, 0, FCSR_REG)
-
-inst_2:
-TEST_CASE_FLI_D(f18, 0x1p-16, 0, FCSR_REG)
-
-inst_3:
-TEST_CASE_FLI_D(f19, 0x1p-15, 0, FCSR_REG)
-
-inst_4:
-TEST_CASE_FLI_D(f20, 0x1p-8, 0, FCSR_REG)
-
-inst_5:
-TEST_CASE_FLI_D(f21, 0x1p-7, 0, FCSR_REG)
-
-inst_6:
-TEST_CASE_FLI_D(f22, 0x1p-4, 0, FCSR_REG)
-
-inst_7:
-TEST_CASE_FLI_D(f23, 0x1p-3, 0, FCSR_REG)
-
-inst_8:
-TEST_CASE_FLI_D(f24, 0x1p-2, 0, FCSR_REG)
-
-inst_9:
-TEST_CASE_FLI_D(f25, 0x1.4p-2, 0, FCSR_REG)
-
-inst_10:
-TEST_CASE_FLI_D(f26, 0x1.8p-2, 0, FCSR_REG)
-
-inst_11:
-TEST_CASE_FLI_D(f27, 0x1.cp-2, 0, FCSR_REG)
-
-inst_12:
-TEST_CASE_FLI_D(f28, 0x1p-1, 0, FCSR_REG)
-
-inst_13:
-TEST_CASE_FLI_D(f29, 0x1.4p-1, 0, FCSR_REG)
-
-inst_14:
-TEST_CASE_FLI_D(f30, 0x1.8p-1, 0, FCSR_REG)
-
-inst_15:
-TEST_CASE_FLI_D(f31, 0x1.cp-1, 0, FCSR_REG)
-
-inst_16:
-TEST_CASE_FLI_D(f0, 0x1p0, 0, FCSR_REG)
-
-inst_17:
-TEST_CASE_FLI_D(f1, 0x1.4p+0, 0, FCSR_REG)
-
-inst_18:
-TEST_CASE_FLI_D(f2, 0x1.8p+0, 0, FCSR_REG)
-
-inst_19:
-TEST_CASE_FLI_D(f3, 0x1.cp+0, 0, FCSR_REG)
-
-inst_20:
-TEST_CASE_FLI_D(f4, 0x1p+1, 0, FCSR_REG)
-
-inst_21:
-TEST_CASE_FLI_D(f5, 0x1.4p+1, 0, FCSR_REG)
-
-inst_22:
-TEST_CASE_FLI_D(f6, 0x1.8p+1, 0, FCSR_REG)
-
-inst_23:
-TEST_CASE_FLI_D(f7, 0x1p+2, 0, FCSR_REG)
-
-inst_24:
-TEST_CASE_FLI_D(f8, 0x1p+3, 0, FCSR_REG)
-
-inst_25:
-TEST_CASE_FLI_D(f9, 0x1p+4, 0, FCSR_REG)
-
-inst_26:
-TEST_CASE_FLI_D(f10, 0x1p+7, 0, FCSR_REG)
-
-inst_27:
-TEST_CASE_FLI_D(f11, 0x1p+8, 0, FCSR_REG)
-
-inst_28:
-TEST_CASE_FLI_D(f12, 0x1p+15, 0, FCSR_REG)
-
-inst_29:
-TEST_CASE_FLI_D(f13, 0x1p+16, 0, FCSR_REG)
-
-inst_30:
-TEST_CASE_FLI_D(f14, inf, 0, FCSR_REG)
-
-inst_31:
-TEST_CASE_FLI_D(f15, nan, 0, FCSR_REG)
-
-#endif // TEST_CASE_1
-
-RVTEST_CODE_END
-
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.word 0xbabecafe // trapreg_sv
-.word 0xabecafeb // tramptbl_sv
-.word 0xbecafeba // mtvec_save
-.word 0xecafebab // mscratch_save
-dataset_tc1:
-/* empty */
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-signature_tc1:
-// We have 32 test cases and store for each test case:
-// - 32-bit FP register (fld)
-// - 32-bit FCSR content after the instruction
-    .fill 64*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-
-tsig_begin_canary:
-CANARY;
-tsig_begin_canary:
-CANARY;
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-tsig_end_canary:
-CANARY;
-tsig_end_canary:
-CANARY;
-
-#endif // rvtest_mtrap_routine
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif // rvtest_gpr_save
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b1-01.S
deleted file mode 100644
index 7da452337..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b1-01.S
+++ /dev/null
@@ -1,4740 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:13 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fltq.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fltq.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fltq.d_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fltq.d_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 == rs2, rs1==f31, rs2==f31, rd==x31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f31; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 != rs2, rs1==f30, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f30; op2:f29; dest:x30; op1val:0x0; op2val:0x8000000000000000;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x30, f30, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f29, rs2==f30, rd==x29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f29; op2:f30; dest:x29; op1val:0x0; op2val:0x1;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x29, f29, f30, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f28; op2:f27; dest:x28; op1val:0x0; op2val:0x8000000000000001;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f27; op2:f28; dest:x27; op1val:0x0; op2val:0x2;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f26; op2:f25; dest:x26; op1val:0x0; op2val:0x8000000000000002;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f25; op2:f26; dest:x25; op1val:0x0; op2val:0xfffffffffffff;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f24; op2:f23; dest:x24; op1val:0x0; op2val:0x800fffffffffffff;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f23; op2:f24; dest:x23; op1val:0x0; op2val:0x10000000000000;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f22; op2:f21; dest:x22; op1val:0x0; op2val:0x8010000000000000;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f21; op2:f22; dest:x21; op1val:0x0; op2val:0x10000000000002;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f20; op2:f19; dest:x20; op1val:0x0; op2val:0x8010000000000002;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f19; op2:f20; dest:x19; op1val:0x0; op2val:0x7fefffffffffffff;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f18; op2:f17; dest:x18; op1val:0x0; op2val:0xffefffffffffffff;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f17; op2:f18; dest:x17; op1val:0x0; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f16; op2:f15; dest:x16; op1val:0x0; op2val:0xfff0000000000000;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f15; op2:f16; dest:x15; op1val:0x0; op2val:0x7ff8000000000000;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f14; op2:f13; dest:x14; op1val:0x0; op2val:0xfff8000000000000;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f13; op2:f14; dest:x13; op1val:0x0; op2val:0x7ff8000000000001;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f12; op2:f11; dest:x12; op1val:0x0; op2val:0xfff8000000000001;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f11; op2:f12; dest:x11; op1val:0x0; op2val:0x7ff0000000000001;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f10; op2:f9; dest:x10; op1val:0x0; op2val:0xfff0000000000001;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f9; op2:f10; dest:x9; op1val:0x0; op2val:0x3ff0000000000000;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f8; op2:f7; dest:x8; op1val:0x0; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f7; op2:f8; dest:x7; op1val:0x8000000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f6; op2:f5; dest:x6; op1val:0x8000000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f5; op2:f6; dest:x5; op1val:0x8000000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f4; op2:f3; dest:x4; op1val:0x8000000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f3; op2:f4; dest:x3; op1val:0x8000000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f2; op2:f1; dest:x2; op1val:0x8000000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f1; op2:f2; dest:x1; op1val:0x8000000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f0; op2:f31; dest:x31; op1val:0x8000000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f0; dest:x31; op1val:0x8000000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x0; op1val:0x8000000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x0;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x1;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x2;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x0;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x1;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x2;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x0;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x1;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x2;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000002; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800fffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x0;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x1;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x2;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x10000000000002; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x0;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x1;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x2;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8010000000000002; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fefffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x0;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x1;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x2;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffefffffffffffff; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff8000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff8000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x0;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x1;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x2;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000001; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff0000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x0;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8000000000000000;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x1;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8000000000000001;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x2;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8000000000000002;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfffffffffffff;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x800fffffffffffff;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x10000000000000;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x10000000000002;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x8010000000000002;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7fefffffffffffff;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xffefffffffffffff;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff8000000000000;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff8000000000000;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff8000000000001;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff8000000000001;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x7ff0000000000001;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xfff0000000000001;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0x3ff0000000000000;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbf80000000000000; op2val:0xbf80000000000000;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000000000000000; op2val:0x8010000000000000;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
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-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 80*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b19-01.S
deleted file mode 100644
index 9818b1246..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fltq.d_b19-01.S
+++ /dev/null
@@ -1,9344 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:18:13 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fltq.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fltq.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fltq.d_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fltq.d_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 == rs2, rs1==f31, rs2==f31, rd==x31,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f31; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 != rs2, rs1==f30, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f30; op2:f29; dest:x30; op1val:0x7fee97d52f73d2ed; op2val:0x7feabc6824ad2440;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x30, f30, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f29, rs2==f30, rd==x29,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f29; op2:f30; dest:x29; op1val:0x7feabc6824ad2440; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x29, f29, f30, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f28; op2:f27; dest:x28; op1val:0x7fee97d52f73d2ed; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f27; op2:f28; dest:x27; op1val:0x7fe363e504d94fe2; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f26; op2:f25; dest:x26; op1val:0x7fee97d52f73d2ed; op2val:0x7fdb9017651b96db;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x879775929758a and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f25; op2:f26; dest:x25; op1val:0x7fb879775929758a; op2val:0x7ff0000000000000;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x879775929758a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f24; op2:f23; dest:x24; op1val:0x7ff0000000000000; op2val:0x7fb879775929758a;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x879775929758a and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f23; op2:f24; dest:x23; op1val:0x7fb879775929758a; op2val:0x7fdb9017651b96db;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x879775929758a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f22; op2:f21; dest:x22; op1val:0x7fee97d52f73d2ed; op2val:0x7fb879775929758a;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f21; op2:f22; dest:x21; op1val:0x7fee97d52f73d2ed; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f20; op2:f19; dest:x20; op1val:0x7fee61729d7cfd5e; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f19; op2:f20; dest:x19; op1val:0x7fee97d52f73d2ed; op2val:0xffaab65b09a91410;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x3945f7a87913c and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f18; op2:f17; dest:x18; op1val:0x7f83945f7a87913c; op2val:0xfff0000000000000;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x3945f7a87913c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f17; op2:f18; dest:x17; op1val:0xfff0000000000000; op2val:0x7f83945f7a87913c;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x3945f7a87913c and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f16; op2:f15; dest:x16; op1val:0x7f83945f7a87913c; op2val:0xffaab65b09a91410;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x3945f7a87913c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f15; op2:f16; dest:x15; op1val:0x7fee97d52f73d2ed; op2val:0x7f83945f7a87913c;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f14; op2:f13; dest:x14; op1val:0x7fee97d52f73d2ed; op2val:0xffd0e5de21873eea;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x879775929758a and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f13; op2:f14; dest:x13; op1val:0x7fb879775929758a; op2val:0xfff0000000000000;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x879775929758a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f12; op2:f11; dest:x12; op1val:0xfff0000000000000; op2val:0x7fb879775929758a;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x879775929758a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f11; op2:f12; dest:x11; op1val:0x7fb879775929758a; op2val:0xffd0e5de21873eea;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f10; op2:f9; dest:x10; op1val:0x7fee97d52f73d2ed; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x879775929758a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f9; op2:f10; dest:x9; op1val:0x7fb879775929758a; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f8; op2:f7; dest:x8; op1val:0x7fee97d52f73d2ed; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f7; op2:f8; dest:x7; op1val:0xffe3682ff4c90ae0; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f6; op2:f5; dest:x6; op1val:0x7fee97d52f73d2ed; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x879775929758a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f5; op2:f6; dest:x5; op1val:0x7fb879775929758a; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f4; op2:f3; dest:x4; op1val:0x7fee97d52f73d2ed; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 0 and fe1 == 0x000 and fm1 == 0x13c6071994562 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x6660e5465cd6d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f3; op2:f4; dest:x3; op1val:0x13c6071994562; op2val:0x7fe6660e5465cd6d;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x13c6071994562 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f2; op2:f1; dest:x2; op1val:0x7fe6660e5465cd6d; op2val:0x13c6071994562;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 0 and fe1 == 0x000 and fm1 == 0x13c6071994562 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f1; op2:f2; dest:x1; op1val:0x13c6071994562; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0x13c6071994562 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f0; op2:f31; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x13c6071994562;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f0; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xa86c4594097a9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x0; op1val:0xc5bc46ffcb5d2; op2val:0x7fea86c4594097a9;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc5bc46ffcb5d2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0xc5bc46ffcb5d2;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc5bc46ffcb5d2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0xc5bc46ffcb5d2;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x705262580c704 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x7fe705262580c704;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc5bc46ffcb5d2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0xc5bc46ffcb5d2;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xca304f80cbc99 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x7feca304f80cbc99;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc5bc46ffcb5d2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0xc5bc46ffcb5d2;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x13c6071994562 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x13c6071994562; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x13c6071994562 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x13c6071994562;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x13c6071994562 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x13c6071994562; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc5bc46ffcb5d2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xc5bc46ffcb5d2;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb672fe8c6e870 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0xffeb672fe8c6e870;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc5bc46ffcb5d2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0xc5bc46ffcb5d2;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01fa33e8f53bd and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x484bb4eb5b9d5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1fa33e8f53bd; op2val:0xffe484bb4eb5b9d5;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01fa33e8f53bd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x1fa33e8f53bd;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01fa33e8f53bd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1fa33e8f53bd; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01fa33e8f53bd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x1fa33e8f53bd;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xcfbb63d922c8f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0xffecfbb63d922c8f;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc5bc46ffcb5d2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0xc5bc46ffcb5d2;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x0;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xb7f9db1715774 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ffb7f9db1715774; op2val:0x0;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xb7f9db1715774 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ffb7f9db1715774;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xb7f9db1715774 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x3ffb7f9db1715774;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5638683bdb69a and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5638683bdb69a; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5638683bdb69a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7fb5638683bdb69a;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5638683bdb69a and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5638683bdb69a; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5638683bdb69a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x7fb5638683bdb69a;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x11c6b9c97c548 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f811c6b9c97c548; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x11c6b9c97c548 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7f811c6b9c97c548;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x11c6b9c97c548 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f811c6b9c97c548; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x11c6b9c97c548 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x7f811c6b9c97c548;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5638683bdb69a and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5638683bdb69a; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5638683bdb69a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fb5638683bdb69a;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5638683bdb69a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5638683bdb69a; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5638683bdb69a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5638683bdb69a; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5638683bdb69a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5638683bdb69a; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1147d0920addb and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x6660e5465cd6d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1147d0920addb; op2val:0x7fe6660e5465cd6d;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1147d0920addb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0x1147d0920addb;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1147d0920addb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1147d0920addb; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1147d0920addb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x1147d0920addb;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xa86c4594097a9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x7fea86c4594097a9;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xacce25b46ca92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0xacce25b46ca92;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xacce25b46ca92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xacce25b46ca92;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x705262580c704 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x7fe705262580c704;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xacce25b46ca92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0xacce25b46ca92;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xca304f80cbc99 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x7feca304f80cbc99;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xacce25b46ca92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0xacce25b46ca92;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1147d0920addb and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1147d0920addb; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1147d0920addb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x1147d0920addb;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1147d0920addb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1147d0920addb; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xacce25b46ca92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xacce25b46ca92;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb672fe8c6e870 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0xffeb672fe8c6e870;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xacce25b46ca92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0xacce25b46ca92;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01ba61a834496 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x484bb4eb5b9d5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ba61a834496; op2val:0xffe484bb4eb5b9d5;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01ba61a834496 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x1ba61a834496;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01ba61a834496 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1ba61a834496; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01ba61a834496 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x1ba61a834496;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xcfbb63d922c8f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0xffecfbb63d922c8f;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xacce25b46ca92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0xacce25b46ca92;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xacce25b46ca92 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xacce25b46ca92; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x0;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x80812523614ab and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff80812523614ab; op2val:0x0;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x80812523614ab and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff80812523614ab;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xabc6824ad2440 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x80812523614ab and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feabc6824ad2440; op2val:0x3ff80812523614ab;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xf063b3af54c9d and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7faf063b3af54c9d; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xf063b3af54c9d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7faf063b3af54c9d;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xf063b3af54c9d and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7faf063b3af54c9d; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xf063b3af54c9d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x7faf063b3af54c9d;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0x8d1c8fbf7707e and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f78d1c8fbf7707e; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0x8d1c8fbf7707e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7f78d1c8fbf7707e;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0x8d1c8fbf7707e and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f78d1c8fbf7707e; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0x8d1c8fbf7707e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x7f78d1c8fbf7707e;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xf063b3af54c9d and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7faf063b3af54c9d; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xf063b3af54c9d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7faf063b3af54c9d;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xf063b3af54c9d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7faf063b3af54c9d; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xf063b3af54c9d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7faf063b3af54c9d; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xf063b3af54c9d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7faf063b3af54c9d; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0c885d3ef4f92 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x6660e5465cd6d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc885d3ef4f92; op2val:0x7fe6660e5465cd6d;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0c885d3ef4f92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0xc885d3ef4f92;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0c885d3ef4f92 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc885d3ef4f92; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0c885d3ef4f92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xc885d3ef4f92;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xa86c4594097a9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x7fea86c4594097a9;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7d53a47591bb8 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0x7d53a47591bb8;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7d53a47591bb8 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x7d53a47591bb8;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x705262580c704 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x7fe705262580c704;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7d53a47591bb8 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0x7d53a47591bb8;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xca304f80cbc99 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x7feca304f80cbc99;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7d53a47591bb8 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0x7d53a47591bb8;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0c885d3ef4f92 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc885d3ef4f92; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0c885d3ef4f92 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xc885d3ef4f92;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0c885d3ef4f92 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc885d3ef4f92; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7d53a47591bb8 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7d53a47591bb8;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb672fe8c6e870 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0xffeb672fe8c6e870;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7d53a47591bb8 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0x7d53a47591bb8;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0140d61fe54c2 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x484bb4eb5b9d5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x140d61fe54c2; op2val:0xffe484bb4eb5b9d5;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0140d61fe54c2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x140d61fe54c2;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0140d61fe54c2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x140d61fe54c2; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0140d61fe54c2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x140d61fe54c2;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xcfbb63d922c8f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0xffecfbb63d922c8f;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7d53a47591bb8 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0x7d53a47591bb8;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7d53a47591bb8 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7d53a47591bb8; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x0;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x16dc795a2b73d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff16dc795a2b73d; op2val:0x0;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x16dc795a2b73d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff16dc795a2b73d;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x363e504d94fe2 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x16dc795a2b73d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe363e504d94fe2; op2val:0x3ff16dc795a2b73d;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x84df54aca644b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7fb84df54aca644b;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x84df54aca644b and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb84df54aca644b; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0x60cdf84161249 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0b1f8e609ac8a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fa60cdf84161249; op2val:0xffe0b1f8e609ac8a;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 0 and fe2 == 0x7fa and fm2 == 0x60cdf84161249 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0x7fa60cdf84161249;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0x60cdf84161249 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fa60cdf84161249; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x7fa and fm2 == 0x60cdf84161249 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x7fa60cdf84161249;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf0d1987a81166 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xffaf0d1987a81166;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf0d1987a81166 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaf0d1987a81166; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x59132cc0dc780 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x1eb3ea9eb0abd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x59132cc0dc780; op2val:0x7fb1eb3ea9eb0abd;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 0 and fe2 == 0x000 and fm2 == 0x59132cc0dc780 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0x59132cc0dc780;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x59132cc0dc780 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x59132cc0dc780; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x59132cc0dc780 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x59132cc0dc780;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5389d1433ac87 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x7fb5389d1433ac87;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x26a84eacd6c03 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x7fb26a84eacd6c03;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x6e8d0c67096e1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x7fb6e8d0c67096e1;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x59132cc0dc780 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x19e9f6802bcef and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x59132cc0dc780; op2val:0x7fe19e9f6802bcef;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 0 and fe2 == 0x000 and fm2 == 0x59132cc0dc780 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0x59132cc0dc780;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x59132cc0dc780 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x59132cc0dc780; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xcff30f3beb065 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0xffbcff30f3beb065;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x5ec2653d2538d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0xffb5ec2653d2538d;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xaaae5b42b9d01 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0xffbaaae5b42b9d01;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x08e851467c726 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x06a2f722afb11 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8e851467c726; op2val:0xffb06a2f722afb11;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x08e851467c726 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0x8e851467c726;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x08e851467c726 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8e851467c726; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x08e851467c726 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x8e851467c726;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x72fc4fe0e8a0c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0xffb72fc4fe0e8a0c;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 0 and fe2 == 0x002 and fm2 == 0xbd5fdfc44e580 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0x2bd5fdfc44e580;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 0 and fe1 == 0x002 and fm1 == 0xbd5fdfc44e580 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x2bd5fdfc44e580; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x0;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 0 and fe1 == 0x401 and fm1 == 0xef7eded580ce9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x401ef7eded580ce9; op2val:0x0;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x401 and fm2 == 0xef7eded580ce9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x401ef7eded580ce9;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xb9017651b96db and fs2 == 0 and fe2 == 0x401 and fm2 == 0xef7eded580ce9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fdb9017651b96db; op2val:0x401ef7eded580ce9;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x84df54aca644b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb84df54aca644b; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x84df54aca644b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x7fb84df54aca644b;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x3719108a1e9d6 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f83719108a1e9d6; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x3719108a1e9d6 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7f83719108a1e9d6;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x3719108a1e9d6 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f83719108a1e9d6; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x3719108a1e9d6 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x7f83719108a1e9d6;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x84df54aca644b and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb84df54aca644b; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x84df54aca644b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fb84df54aca644b;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x84df54aca644b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb84df54aca644b; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x84df54aca644b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb84df54aca644b; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x84df54aca644b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb84df54aca644b; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x13a2e0625c7c9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x6660e5465cd6d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x13a2e0625c7c9; op2val:0x7fe6660e5465cd6d;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x13a2e0625c7c9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0x13a2e0625c7c9;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x13a2e0625c7c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x13a2e0625c7c9; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x13a2e0625c7c9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x13a2e0625c7c9;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xa86c4594097a9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x7fea86c4594097a9;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc45cc3d79cddb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0xc45cc3d79cddb;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc45cc3d79cddb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xc45cc3d79cddb;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x705262580c704 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x7fe705262580c704;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc45cc3d79cddb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0xc45cc3d79cddb;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xca304f80cbc99 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x7feca304f80cbc99;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc45cc3d79cddb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0xc45cc3d79cddb;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x13a2e0625c7c9 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x13a2e0625c7c9; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x13a2e0625c7c9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x13a2e0625c7c9;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x13a2e0625c7c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x13a2e0625c7c9; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc45cc3d79cddb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xc45cc3d79cddb;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb672fe8c6e870 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0xffeb672fe8c6e870;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc45cc3d79cddb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0xc45cc3d79cddb;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01f6b009d60c7 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x484bb4eb5b9d5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1f6b009d60c7; op2val:0xffe484bb4eb5b9d5;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01f6b009d60c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x1f6b009d60c7;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01f6b009d60c7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1f6b009d60c7; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01f6b009d60c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x1f6b009d60c7;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xcfbb63d922c8f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0xffecfbb63d922c8f;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc45cc3d79cddb and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0xc45cc3d79cddb;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc45cc3d79cddb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc45cc3d79cddb; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x0;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xb4ebb70505c5a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ffb4ebb70505c5a; op2val:0x0;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xb4ebb70505c5a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ffb4ebb70505c5a;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe61729d7cfd5e and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xb4ebb70505c5a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee61729d7cfd5e; op2val:0x3ffb4ebb70505c5a;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0b1f8e609ac8a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xffe0b1f8e609ac8a;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0xb096368d864aa and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0xff9b096368d864aa;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0xb096368d864aa and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0b1f8e609ac8a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff9b096368d864aa; op2val:0xffe0b1f8e609ac8a;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x421ba72f8a718 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0xffa421ba72f8a718;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x421ba72f8a718 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0b1f8e609ac8a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffa421ba72f8a718; op2val:0xffe0b1f8e609ac8a;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0x8d7479fb9a785 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xff78d7479fb9a785;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0x8d7479fb9a785 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff78d7479fb9a785; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x7569006cfbae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0xffa7569006cfbae0;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x7569006cfbae0 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x0b1f8e609ac8a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffa7569006cfbae0; op2val:0xffe0b1f8e609ac8a;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0b1f8e609ac8a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe0b1f8e609ac8a; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6be865c2463a7 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xcab977644ddfc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006be865c2463a7; op2val:0x7f7cab977644ddfc;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xcab977644ddfc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6be865c2463a7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f7cab977644ddfc; op2val:0x8006be865c2463a7;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6be865c2463a7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006be865c2463a7; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6be865c2463a7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x8006be865c2463a7;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x0fa17435c8a06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x7f80fa17435c8a06;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x0fa17435c8a06 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f80fa17435c8a06; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xd773b1148acd1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x7f7d773b1148acd1;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xd773b1148acd1 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f7d773b1148acd1; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x253da385a124e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x7f8253da385a124e;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x253da385a124e and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f8253da385a124e; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6be865c2463a7 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xc30ff0cd12e4b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006be865c2463a7; op2val:0x7fac30ff0cd12e4b;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xc30ff0cd12e4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x6be865c2463a7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fac30ff0cd12e4b; op2val:0x8006be865c2463a7;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x6be865c2463a7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8006be865c2463a7; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x7328d8fcbc051 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0xff87328d8fcbc051;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x7328d8fcbc051 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff87328d8fcbc051; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x189b8430ea93d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0xff8189b8430ea93d;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x189b8430ea93d and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff8189b8430ea93d; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x555849022e400 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0xff8555849022e400;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x555849022e400 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff8555849022e400; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0aca70936d6c4 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0xa437f1d1191b5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000aca70936d6c4; op2val:0xff7a437f1d1191b5;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0xa437f1d1191b5 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0aca70936d6c4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff7a437f1d1191b5; op2val:0x8000aca70936d6c4;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0aca70936d6c4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000aca70936d6c4; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0aca70936d6c4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x8000aca70936d6c4;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x28c9d980ba1a3 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0xff828c9d980ba1a3;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x28c9d980ba1a3 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x0dc4fe65af923 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff828c9d980ba1a3; op2val:0x8030dc4fe65af923;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 1 and fe1 == 0x003 and fm1 == 0x0dc4fe65af923 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8030dc4fe65af923; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0x0;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 1 and fe1 == 0x402 and fm1 == 0x2c20e7e96fa8e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc022c20e7e96fa8e; op2val:0x0;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x2c20e7e96fa8e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc022c20e7e96fa8e;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xab65b09a91410 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x2c20e7e96fa8e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaab65b09a91410; op2val:0xc022c20e7e96fa8e;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0xb096368d864aa and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff9b096368d864aa; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0xb096368d864aa and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xff9b096368d864aa;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf0d1987a81166 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0xffaf0d1987a81166;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf0d1987a81166 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaf0d1987a81166; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x369be8c5e3b80 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x1eb3ea9eb0abd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800369be8c5e3b80; op2val:0x7fb1eb3ea9eb0abd;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x369be8c5e3b80 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0x800369be8c5e3b80;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x369be8c5e3b80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800369be8c5e3b80; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x000 and fm2 == 0x369be8c5e3b80 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x800369be8c5e3b80;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5389d1433ac87 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x7fb5389d1433ac87;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x26a84eacd6c03 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x7fb26a84eacd6c03;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x6e8d0c67096e1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x7fb6e8d0c67096e1;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x369be8c5e3b80 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x19e9f6802bcef and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800369be8c5e3b80; op2val:0x7fe19e9f6802bcef;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 1 and fe2 == 0x000 and fm2 == 0x369be8c5e3b80 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0x800369be8c5e3b80;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x369be8c5e3b80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800369be8c5e3b80; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xcff30f3beb065 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0xffbcff30f3beb065;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x5ec2653d2538d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0xffb5ec2653d2538d;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xaaae5b42b9d01 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0xffbaaae5b42b9d01;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0575fdad63926 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x06a2f722afb11 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000575fdad63926; op2val:0xffb06a2f722afb11;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0575fdad63926 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0x8000575fdad63926;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0575fdad63926 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000575fdad63926; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0575fdad63926 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x8000575fdad63926;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x72fc4fe0e8a0c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0xffb72fc4fe0e8a0c;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 1 and fe2 == 0x002 and fm2 == 0x110b8bdd7297e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0x802110b8bdd7297e;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x110b8bdd7297e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802110b8bdd7297e; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0x0;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 1 and fe1 == 0x401 and fm1 == 0x2fc5d39f551da and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc012fc5d39f551da; op2val:0x0;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x2fc5d39f551da and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc012fc5d39f551da;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0e5de21873eea and fs2 == 1 and fe2 == 0x401 and fm2 == 0x2fc5d39f551da and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd0e5de21873eea; op2val:0xc012fc5d39f551da;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x421ba72f8a718 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffa421ba72f8a718; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x421ba72f8a718 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xffa421ba72f8a718;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x51532237be62c and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x1eb3ea9eb0abd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80051532237be62c; op2val:0x7fb1eb3ea9eb0abd;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x51532237be62c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0x80051532237be62c;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x51532237be62c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80051532237be62c; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x000 and fm2 == 0x51532237be62c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x80051532237be62c;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5389d1433ac87 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x7fb5389d1433ac87;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x26a84eacd6c03 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x7fb26a84eacd6c03;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x6e8d0c67096e1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x7fb6e8d0c67096e1;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x51532237be62c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x19e9f6802bcef and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80051532237be62c; op2val:0x7fe19e9f6802bcef;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 1 and fe2 == 0x000 and fm2 == 0x51532237be62c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0x80051532237be62c;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x51532237be62c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80051532237be62c; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xcff30f3beb065 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0xffbcff30f3beb065;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x5ec2653d2538d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0xffb5ec2653d2538d;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xaaae5b42b9d01 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0xffbaaae5b42b9d01;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0821e9d25fd6b and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x06a2f722afb11 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000821e9d25fd6b; op2val:0xffb06a2f722afb11;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0821e9d25fd6b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0x8000821e9d25fd6b;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0821e9d25fd6b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000821e9d25fd6b; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0821e9d25fd6b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x8000821e9d25fd6b;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x72fc4fe0e8a0c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0xffb72fc4fe0e8a0c;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 1 and fe2 == 0x002 and fm2 == 0x969fab16b7edc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0x802969fab16b7edc;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 1 and fe1 == 0x002 and fm1 == 0x969fab16b7edc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802969fab16b7edc; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0x0;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 1 and fe1 == 0x401 and fm1 == 0xc4624671f2f0c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc01c4624671f2f0c; op2val:0x0;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0xc4624671f2f0c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc01c4624671f2f0c;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x92a290fb6d0de and fs2 == 1 and fe2 == 0x401 and fm2 == 0xc4624671f2f0c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffd92a290fb6d0de; op2val:0xc01c4624671f2f0c;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf0d1987a81166 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaf0d1987a81166; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf0d1987a81166 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xffaf0d1987a81166;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0x8d7479fb9a785 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff78d7479fb9a785; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0x8d7479fb9a785 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xff78d7479fb9a785;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf0d1987a81166 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaf0d1987a81166; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf0d1987a81166 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaf0d1987a81166; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf0d1987a81166 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffaf0d1987a81166; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c8b23887d51e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x6660e5465cd6d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000c8b23887d51e; op2val:0x7fe6660e5465cd6d;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0c8b23887d51e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0x8000c8b23887d51e;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c8b23887d51e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000c8b23887d51e; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0c8b23887d51e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x8000c8b23887d51e;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xa86c4594097a9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x7fea86c4594097a9;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7d6f6354e532b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0x8007d6f6354e532b;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7d6f6354e532b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x8007d6f6354e532b;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x705262580c704 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x7fe705262580c704;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7d6f6354e532b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0x8007d6f6354e532b;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xca304f80cbc99 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x7feca304f80cbc99;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7d6f6354e532b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0x8007d6f6354e532b;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-
-inst_578:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c8b23887d51e and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000c8b23887d51e; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1110*FLEN/8, x10, x6, x7)
-
-inst_579:// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0c8b23887d51e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7ff0000000000000; op2val:0x8000c8b23887d51e;
-valaddr_reg:x9; val_offset:1112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1112*FLEN/8, x10, x6, x7)
-
-inst_580:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c8b23887d51e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000c8b23887d51e; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1114*FLEN/8, x10, x6, x7)
-
-inst_581:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1116*FLEN/8, x10, x6, x7)
-
-inst_582:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1118*FLEN/8, x10, x6, x7)
-
-inst_583:// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7d6f6354e532b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xfff0000000000000; op2val:0x8007d6f6354e532b;
-valaddr_reg:x9; val_offset:1120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1120*FLEN/8, x10, x6, x7)
-
-inst_584:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1122*FLEN/8, x10, x6, x7)
-
-inst_585:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1124*FLEN/8, x10, x6, x7)
-
-inst_586:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb672fe8c6e870 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0xffeb672fe8c6e870;
-valaddr_reg:x9; val_offset:1126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1126*FLEN/8, x10, x6, x7)
-
-inst_587:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7d6f6354e532b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0x8007d6f6354e532b;
-valaddr_reg:x9; val_offset:1128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1128*FLEN/8, x10, x6, x7)
-
-inst_588:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1130*FLEN/8, x10, x6, x7)
-
-inst_589:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1132*FLEN/8, x10, x6, x7)
-
-inst_590:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1134*FLEN/8, x10, x6, x7)
-
-inst_591:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1136*FLEN/8, x10, x6, x7)
-
-inst_592:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01411d273fbb6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x484bb4eb5b9d5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001411d273fbb6; op2val:0xffe484bb4eb5b9d5;
-valaddr_reg:x9; val_offset:1138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1138*FLEN/8, x10, x6, x7)
-
-inst_593:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01411d273fbb6 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x80001411d273fbb6;
-valaddr_reg:x9; val_offset:1140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1140*FLEN/8, x10, x6, x7)
-
-inst_594:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01411d273fbb6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001411d273fbb6; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1142*FLEN/8, x10, x6, x7)
-
-inst_595:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01411d273fbb6 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x80001411d273fbb6;
-valaddr_reg:x9; val_offset:1144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1144*FLEN/8, x10, x6, x7)
-
-inst_596:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1146*FLEN/8, x10, x6, x7)
-
-inst_597:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xcfbb63d922c8f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0xffecfbb63d922c8f;
-valaddr_reg:x9; val_offset:1148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1148*FLEN/8, x10, x6, x7)
-
-inst_598:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7d6f6354e532b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0x8007d6f6354e532b;
-valaddr_reg:x9; val_offset:1150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1150*FLEN/8, x10, x6, x7)
-
-inst_599:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7d6f6354e532b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8007d6f6354e532b; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1152*FLEN/8, x10, x6, x7)
-
-inst_600:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0x0;
-valaddr_reg:x9; val_offset:1154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1154*FLEN/8, x10, x6, x7)
-
-inst_601:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x171a35c491d80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbff171a35c491d80; op2val:0x0;
-valaddr_reg:x9; val_offset:1156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1156*FLEN/8, x10, x6, x7)
-
-inst_602:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x171a35c491d80 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbff171a35c491d80;
-valaddr_reg:x9; val_offset:1158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1158*FLEN/8, x10, x6, x7)
-
-inst_603:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3682ff4c90ae0 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x171a35c491d80 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe3682ff4c90ae0; op2val:0xbff171a35c491d80;
-valaddr_reg:x9; val_offset:1160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1160*FLEN/8, x10, x6, x7)
-
-inst_604:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1162*FLEN/8, x10, x6, x7)
-
-inst_605:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1164*FLEN/8, x10, x6, x7)
-
-inst_606:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1166*FLEN/8, x10, x6, x7)
-
-inst_607:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1168*FLEN/8, x10, x6, x7)
-
-inst_608:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1170*FLEN/8, x10, x6, x7)
-
-inst_609:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1172*FLEN/8, x10, x6, x7)
-
-inst_610:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1174*FLEN/8, x10, x6, x7)
-
-inst_611:// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x7569006cfbae0 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffa7569006cfbae0; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1176*FLEN/8, x10, x6, x7)
-
-inst_612:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x7569006cfbae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xffa7569006cfbae0;
-valaddr_reg:x9; val_offset:1178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1178*FLEN/8, x10, x6, x7)
-
-inst_613:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1180*FLEN/8, x10, x6, x7)
-
-inst_614:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1182*FLEN/8, x10, x6, x7)
-
-inst_615:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e46ff3af089e and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x1eb3ea9eb0abd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e46ff3af089e; op2val:0x7fb1eb3ea9eb0abd;
-valaddr_reg:x9; val_offset:1184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1184*FLEN/8, x10, x6, x7)
-
-inst_616:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e46ff3af089e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0x8005e46ff3af089e;
-valaddr_reg:x9; val_offset:1186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1186*FLEN/8, x10, x6, x7)
-
-inst_617:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e46ff3af089e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e46ff3af089e; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1188*FLEN/8, x10, x6, x7)
-
-inst_618:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e46ff3af089e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x8005e46ff3af089e;
-valaddr_reg:x9; val_offset:1190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1190*FLEN/8, x10, x6, x7)
-
-inst_619:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1192*FLEN/8, x10, x6, x7)
-
-inst_620:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5389d1433ac87 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x7fb5389d1433ac87;
-valaddr_reg:x9; val_offset:1194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1194*FLEN/8, x10, x6, x7)
-
-inst_621:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1196*FLEN/8, x10, x6, x7)
-
-inst_622:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1198*FLEN/8, x10, x6, x7)
-
-inst_623:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1200*FLEN/8, x10, x6, x7)
-
-inst_624:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1202*FLEN/8, x10, x6, x7)
-
-inst_625:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x26a84eacd6c03 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x7fb26a84eacd6c03;
-valaddr_reg:x9; val_offset:1204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1204*FLEN/8, x10, x6, x7)
-
-inst_626:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1206*FLEN/8, x10, x6, x7)
-
-inst_627:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1208*FLEN/8, x10, x6, x7)
-
-inst_628:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1210*FLEN/8, x10, x6, x7)
-
-inst_629:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x6e8d0c67096e1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x7fb6e8d0c67096e1;
-valaddr_reg:x9; val_offset:1212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1212*FLEN/8, x10, x6, x7)
-
-inst_630:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1214*FLEN/8, x10, x6, x7)
-
-inst_631:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1216*FLEN/8, x10, x6, x7)
-
-inst_632:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1218*FLEN/8, x10, x6, x7)
-
-inst_633:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e46ff3af089e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x19e9f6802bcef and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e46ff3af089e; op2val:0x7fe19e9f6802bcef;
-valaddr_reg:x9; val_offset:1220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1220*FLEN/8, x10, x6, x7)
-
-inst_634:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 1 and fe2 == 0x000 and fm2 == 0x5e46ff3af089e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0x8005e46ff3af089e;
-valaddr_reg:x9; val_offset:1222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1222*FLEN/8, x10, x6, x7)
-
-inst_635:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x5e46ff3af089e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8005e46ff3af089e; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1224*FLEN/8, x10, x6, x7)
-
-inst_636:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1226*FLEN/8, x10, x6, x7)
-
-inst_637:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xcff30f3beb065 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0xffbcff30f3beb065;
-valaddr_reg:x9; val_offset:1228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1228*FLEN/8, x10, x6, x7)
-
-inst_638:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1230*FLEN/8, x10, x6, x7)
-
-inst_639:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1232*FLEN/8, x10, x6, x7)
-
-inst_640:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1234*FLEN/8, x10, x6, x7)
-
-inst_641:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x5ec2653d2538d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0xffb5ec2653d2538d;
-valaddr_reg:x9; val_offset:1236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1236*FLEN/8, x10, x6, x7)
-
-inst_642:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1238*FLEN/8, x10, x6, x7)
-
-inst_643:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1240*FLEN/8, x10, x6, x7)
-
-inst_644:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1242*FLEN/8, x10, x6, x7)
-
-inst_645:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xaaae5b42b9d01 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0xffbaaae5b42b9d01;
-valaddr_reg:x9; val_offset:1244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1244*FLEN/8, x10, x6, x7)
-
-inst_646:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1246*FLEN/8, x10, x6, x7)
-
-inst_647:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1248*FLEN/8, x10, x6, x7)
-
-inst_648:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1250*FLEN/8, x10, x6, x7)
-
-inst_649:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x096d7fec4b410 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x06a2f722afb11 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800096d7fec4b410; op2val:0xffb06a2f722afb11;
-valaddr_reg:x9; val_offset:1252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1252*FLEN/8, x10, x6, x7)
-
-inst_650:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x096d7fec4b410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0x800096d7fec4b410;
-valaddr_reg:x9; val_offset:1254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1254*FLEN/8, x10, x6, x7)
-
-inst_651:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x096d7fec4b410 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800096d7fec4b410; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1256*FLEN/8, x10, x6, x7)
-
-inst_652:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x096d7fec4b410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x800096d7fec4b410;
-valaddr_reg:x9; val_offset:1258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1258*FLEN/8, x10, x6, x7)
-
-inst_653:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1260*FLEN/8, x10, x6, x7)
-
-inst_654:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x72fc4fe0e8a0c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0xffb72fc4fe0e8a0c;
-valaddr_reg:x9; val_offset:1262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1262*FLEN/8, x10, x6, x7)
-
-inst_655:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 1 and fe2 == 0x002 and fm2 == 0xd762fc26b2b18 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0x802d762fc26b2b18;
-valaddr_reg:x9; val_offset:1264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1264*FLEN/8, x10, x6, x7)
-
-inst_656:// fs1 == 1 and fe1 == 0x002 and fm1 == 0xd762fc26b2b18 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x802d762fc26b2b18; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1266*FLEN/8, x10, x6, x7)
-
-inst_657:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0x0;
-valaddr_reg:x9; val_offset:1268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1268*FLEN/8, x10, x6, x7)
-
-inst_658:// fs1 == 1 and fe1 == 0x402 and fm1 == 0x0637b0487519a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc020637b0487519a; op2val:0x0;
-valaddr_reg:x9; val_offset:1270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1270*FLEN/8, x10, x6, x7)
-
-inst_659:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x0637b0487519a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc020637b0487519a;
-valaddr_reg:x9; val_offset:1272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1272*FLEN/8, x10, x6, x7)
-
-inst_660:// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xd2c340883a998 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x0637b0487519a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffdd2c340883a998; op2val:0xc020637b0487519a;
-valaddr_reg:x9; val_offset:1274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1274*FLEN/8, x10, x6, x7)
-
-inst_661:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1276*FLEN/8, x10, x6, x7)
-
-inst_662:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1278*FLEN/8, x10, x6, x7)
-
-inst_663:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x6660e5465cd6d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7fe6660e5465cd6d;
-valaddr_reg:x9; val_offset:1280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1280*FLEN/8, x10, x6, x7)
-
-inst_664:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1282*FLEN/8, x10, x6, x7)
-
-inst_665:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1284*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_5)
-
-inst_666:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1286*FLEN/8, x10, x6, x7)
-
-inst_667:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1288*FLEN/8, x10, x6, x7)
-
-inst_668:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1290*FLEN/8, x10, x6, x7)
-
-inst_669:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1292*FLEN/8, x10, x6, x7)
-
-inst_670:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1294*FLEN/8, x10, x6, x7)
-
-inst_671:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x1eb3ea9eb0abd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7fb1eb3ea9eb0abd;
-valaddr_reg:x9; val_offset:1296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1296*FLEN/8, x10, x6, x7)
-
-inst_672:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1298*FLEN/8, x10, x6, x7)
-
-inst_673:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1300*FLEN/8, x10, x6, x7)
-
-inst_674:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1302*FLEN/8, x10, x6, x7)
-
-inst_675:// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xcab977644ddfc and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f7cab977644ddfc; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1304*FLEN/8, x10, x6, x7)
-
-inst_676:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xcab977644ddfc and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x7f7cab977644ddfc;
-valaddr_reg:x9; val_offset:1306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1306*FLEN/8, x10, x6, x7)
-
-inst_677:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1308*FLEN/8, x10, x6, x7)
-
-inst_678:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1310*FLEN/8, x10, x6, x7)
-
-inst_679:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1312*FLEN/8, x10, x6, x7)
-
-inst_680:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1314*FLEN/8, x10, x6, x7)
-
-inst_681:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1316*FLEN/8, x10, x6, x7)
-
-inst_682:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x6660e5465cd6d and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe6660e5465cd6d; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1318*FLEN/8, x10, x6, x7)
-
-inst_683:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1320*FLEN/8, x10, x6, x7)
-
-inst_684:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x1eb3ea9eb0abd and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb1eb3ea9eb0abd; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1322*FLEN/8, x10, x6, x7)
-
-inst_685:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1324*FLEN/8, x10, x6, x7)
-
-inst_686:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1125252921dc7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x1125252921dc7;
-valaddr_reg:x9; val_offset:1326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1326*FLEN/8, x10, x6, x7)
-
-inst_687:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1125252921dc7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1125252921dc7; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1328*FLEN/8, x10, x6, x7)
-
-inst_688:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1330*FLEN/8, x10, x6, x7)
-
-inst_689:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1332*FLEN/8, x10, x6, x7)
-
-inst_690:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1334*FLEN/8, x10, x6, x7)
-
-inst_691:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0ee0fa88947a1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0xee0fa88947a1;
-valaddr_reg:x9; val_offset:1336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1336*FLEN/8, x10, x6, x7)
-
-inst_692:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0ee0fa88947a1 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xee0fa88947a1; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1338*FLEN/8, x10, x6, x7)
-
-inst_693:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1340*FLEN/8, x10, x6, x7)
-
-inst_694:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1342*FLEN/8, x10, x6, x7)
-
-inst_695:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x128254fc5a4fe and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x128254fc5a4fe;
-valaddr_reg:x9; val_offset:1344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1344*FLEN/8, x10, x6, x7)
-
-inst_696:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x128254fc5a4fe and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x128254fc5a4fe; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1346*FLEN/8, x10, x6, x7)
-
-inst_697:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1348*FLEN/8, x10, x6, x7)
-
-inst_698:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1350*FLEN/8, x10, x6, x7)
-
-inst_699:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1352*FLEN/8, x10, x6, x7)
-
-inst_700:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1354*FLEN/8, x10, x6, x7)
-
-inst_701:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x176d62053e9f2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x800176d62053e9f2;
-valaddr_reg:x9; val_offset:1356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1356*FLEN/8, x10, x6, x7)
-
-inst_702:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x176d62053e9f2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800176d62053e9f2; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1358*FLEN/8, x10, x6, x7)
-
-inst_703:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1360*FLEN/8, x10, x6, x7)
-
-inst_704:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1362*FLEN/8, x10, x6, x7)
-
-inst_705:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x11b63268cb80c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x80011b63268cb80c;
-valaddr_reg:x9; val_offset:1364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1364*FLEN/8, x10, x6, x7)
-
-inst_706:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11b63268cb80c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80011b63268cb80c; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1366*FLEN/8, x10, x6, x7)
-
-inst_707:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1368*FLEN/8, x10, x6, x7)
-
-inst_708:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1370*FLEN/8, x10, x6, x7)
-
-inst_709:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x158b9f3ccd07c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x800158b9f3ccd07c;
-valaddr_reg:x9; val_offset:1372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1372*FLEN/8, x10, x6, x7)
-
-inst_710:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x158b9f3ccd07c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800158b9f3ccd07c; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1374*FLEN/8, x10, x6, x7)
-
-inst_711:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1376*FLEN/8, x10, x6, x7)
-
-inst_712:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1378*FLEN/8, x10, x6, x7)
-
-inst_713:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01729d737e39f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d430d1d19325 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1729d737e39f; op2val:0x8000d430d1d19325;
-valaddr_reg:x9; val_offset:1380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1380*FLEN/8, x10, x6, x7)
-
-inst_714:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d430d1d19325 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01729d737e39f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d430d1d19325; op2val:0x1729d737e39f;
-valaddr_reg:x9; val_offset:1382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1382*FLEN/8, x10, x6, x7)
-
-inst_715:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01729d737e39f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1729d737e39f; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1384*FLEN/8, x10, x6, x7)
-
-inst_716:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01729d737e39f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x1729d737e39f;
-valaddr_reg:x9; val_offset:1386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1386*FLEN/8, x10, x6, x7)
-
-inst_717:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1388*FLEN/8, x10, x6, x7)
-
-inst_718:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x12bba85050ee4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x80012bba85050ee4;
-valaddr_reg:x9; val_offset:1390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1390*FLEN/8, x10, x6, x7)
-
-inst_719:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12bba85050ee4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x90c5811d4ea06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80012bba85050ee4; op2val:0x90c5811d4ea06;
-valaddr_reg:x9; val_offset:1392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1392*FLEN/8, x10, x6, x7)
-
-inst_720:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x90c5811d4ea06 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x90c5811d4ea06; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1394*FLEN/8, x10, x6, x7)
-
-inst_721:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x0;
-valaddr_reg:x9; val_offset:1396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1396*FLEN/8, x10, x6, x7)
-
-inst_722:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x422095a1629ee and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff422095a1629ee; op2val:0x0;
-valaddr_reg:x9; val_offset:1398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1398*FLEN/8, x10, x6, x7)
-
-inst_723:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x422095a1629ee and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff422095a1629ee;
-valaddr_reg:x9; val_offset:1400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1400*FLEN/8, x10, x6, x7)
-
-inst_724:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0e7a2682ee434 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x422095a1629ee and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xe7a2682ee434; op2val:0x3ff422095a1629ee;
-valaddr_reg:x9; val_offset:1402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1402*FLEN/8, x10, x6, x7)
-
-inst_725:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1404*FLEN/8, x10, x6, x7)
-
-inst_726:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1406*FLEN/8, x10, x6, x7)
-
-inst_727:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xa86c4594097a9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7fea86c4594097a9;
-valaddr_reg:x9; val_offset:1408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1408*FLEN/8, x10, x6, x7)
-
-inst_728:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1410*FLEN/8, x10, x6, x7)
-
-inst_729:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1412*FLEN/8, x10, x6, x7)
-
-inst_730:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1414*FLEN/8, x10, x6, x7)
-
-inst_731:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1416*FLEN/8, x10, x6, x7)
-
-inst_732:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1418*FLEN/8, x10, x6, x7)
-
-inst_733:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1420*FLEN/8, x10, x6, x7)
-
-inst_734:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1422*FLEN/8, x10, x6, x7)
-
-inst_735:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x5389d1433ac87 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7fb5389d1433ac87;
-valaddr_reg:x9; val_offset:1424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1424*FLEN/8, x10, x6, x7)
-
-inst_736:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1426*FLEN/8, x10, x6, x7)
-
-inst_737:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1428*FLEN/8, x10, x6, x7)
-
-inst_738:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1430*FLEN/8, x10, x6, x7)
-
-inst_739:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x0fa17435c8a06 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f80fa17435c8a06; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1432*FLEN/8, x10, x6, x7)
-
-inst_740:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x0fa17435c8a06 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x7f80fa17435c8a06;
-valaddr_reg:x9; val_offset:1434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1434*FLEN/8, x10, x6, x7)
-
-inst_741:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1436*FLEN/8, x10, x6, x7)
-
-inst_742:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1438*FLEN/8, x10, x6, x7)
-
-inst_743:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1440*FLEN/8, x10, x6, x7)
-
-inst_744:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1442*FLEN/8, x10, x6, x7)
-
-inst_745:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1444*FLEN/8, x10, x6, x7)
-
-inst_746:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xa86c4594097a9 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fea86c4594097a9; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1446*FLEN/8, x10, x6, x7)
-
-inst_747:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1448*FLEN/8, x10, x6, x7)
-
-inst_748:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x5389d1433ac87 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb5389d1433ac87; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1450*FLEN/8, x10, x6, x7)
-
-inst_749:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1452*FLEN/8, x10, x6, x7)
-
-inst_750:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1125252921dc7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1125252921dc7; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1454*FLEN/8, x10, x6, x7)
-
-inst_751:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1125252921dc7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x1125252921dc7;
-valaddr_reg:x9; val_offset:1456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1456*FLEN/8, x10, x6, x7)
-
-inst_752:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1458*FLEN/8, x10, x6, x7)
-
-inst_753:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1460*FLEN/8, x10, x6, x7)
-
-inst_754:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1462*FLEN/8, x10, x6, x7)
-
-inst_755:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1464*FLEN/8, x10, x6, x7)
-
-inst_756:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1466*FLEN/8, x10, x6, x7)
-
-inst_757:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1125252921dc7 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1125252921dc7; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1468*FLEN/8, x10, x6, x7)
-
-inst_758:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1125252921dc7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x1125252921dc7;
-valaddr_reg:x9; val_offset:1470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1470*FLEN/8, x10, x6, x7)
-
-inst_759:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1125252921dc7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1125252921dc7; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1472*FLEN/8, x10, x6, x7)
-
-inst_760:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1474*FLEN/8, x10, x6, x7)
-
-inst_761:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1476*FLEN/8, x10, x6, x7)
-
-inst_762:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1478*FLEN/8, x10, x6, x7)
-
-inst_763:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1480*FLEN/8, x10, x6, x7)
-
-inst_764:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1482*FLEN/8, x10, x6, x7)
-
-inst_765:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1484*FLEN/8, x10, x6, x7)
-
-inst_766:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1486*FLEN/8, x10, x6, x7)
-
-inst_767:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01b6ea1db6961 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1b6ea1db6961; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:1488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1488*FLEN/8, x10, x6, x7)
-
-inst_768:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01b6ea1db6961 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x1b6ea1db6961;
-valaddr_reg:x9; val_offset:1490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1490*FLEN/8, x10, x6, x7)
-
-inst_769:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01b6ea1db6961 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1b6ea1db6961; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1492*FLEN/8, x10, x6, x7)
-
-inst_770:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01b6ea1db6961 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x1b6ea1db6961;
-valaddr_reg:x9; val_offset:1494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1494*FLEN/8, x10, x6, x7)
-
-inst_771:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1496*FLEN/8, x10, x6, x7)
-
-inst_772:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1498*FLEN/8, x10, x6, x7)
-
-inst_773:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x0;
-valaddr_reg:x9; val_offset:1500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1500*FLEN/8, x10, x6, x7)
-
-inst_774:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x7d7db8b6fc61f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff7d7db8b6fc61f; op2val:0x0;
-valaddr_reg:x9; val_offset:1502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1502*FLEN/8, x10, x6, x7)
-
-inst_775:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x7d7db8b6fc61f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff7d7db8b6fc61f;
-valaddr_reg:x9; val_offset:1504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1504*FLEN/8, x10, x6, x7)
-
-inst_776:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xab73739b529c7 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x7d7db8b6fc61f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xab73739b529c7; op2val:0x3ff7d7db8b6fc61f;
-valaddr_reg:x9; val_offset:1506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1506*FLEN/8, x10, x6, x7)
-
-inst_777:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1508*FLEN/8, x10, x6, x7)
-
-inst_778:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1510*FLEN/8, x10, x6, x7)
-
-inst_779:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x705262580c704 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7fe705262580c704;
-valaddr_reg:x9; val_offset:1512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1512*FLEN/8, x10, x6, x7)
-
-inst_780:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1514*FLEN/8, x10, x6, x7)
-
-inst_781:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1516*FLEN/8, x10, x6, x7)
-
-inst_782:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1518*FLEN/8, x10, x6, x7)
-
-inst_783:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1520*FLEN/8, x10, x6, x7)
-
-inst_784:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1522*FLEN/8, x10, x6, x7)
-
-inst_785:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1524*FLEN/8, x10, x6, x7)
-
-inst_786:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1526*FLEN/8, x10, x6, x7)
-
-inst_787:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x26a84eacd6c03 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7fb26a84eacd6c03;
-valaddr_reg:x9; val_offset:1528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1528*FLEN/8, x10, x6, x7)
-
-inst_788:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1530*FLEN/8, x10, x6, x7)
-
-inst_789:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1532*FLEN/8, x10, x6, x7)
-
-inst_790:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1534*FLEN/8, x10, x6, x7)
-
-inst_791:// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xd773b1148acd1 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f7d773b1148acd1; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1536*FLEN/8, x10, x6, x7)
-
-inst_792:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xd773b1148acd1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x7f7d773b1148acd1;
-valaddr_reg:x9; val_offset:1538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1538*FLEN/8, x10, x6, x7)
-
-inst_793:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1540*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_6)
-
-inst_794:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1542*FLEN/8, x10, x6, x7)
-
-inst_795:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1544*FLEN/8, x10, x6, x7)
-
-inst_796:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1546*FLEN/8, x10, x6, x7)
-
-inst_797:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1548*FLEN/8, x10, x6, x7)
-
-inst_798:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x705262580c704 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe705262580c704; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1550*FLEN/8, x10, x6, x7)
-
-inst_799:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1552*FLEN/8, x10, x6, x7)
-
-inst_800:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x26a84eacd6c03 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb26a84eacd6c03; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1554*FLEN/8, x10, x6, x7)
-
-inst_801:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1556*FLEN/8, x10, x6, x7)
-
-inst_802:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0ee0fa88947a1 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xee0fa88947a1; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1558*FLEN/8, x10, x6, x7)
-
-inst_803:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0ee0fa88947a1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xee0fa88947a1;
-valaddr_reg:x9; val_offset:1560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1560*FLEN/8, x10, x6, x7)
-
-inst_804:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1562*FLEN/8, x10, x6, x7)
-
-inst_805:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1564*FLEN/8, x10, x6, x7)
-
-inst_806:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1566*FLEN/8, x10, x6, x7)
-
-inst_807:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0ee0fa88947a1 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xee0fa88947a1; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1568*FLEN/8, x10, x6, x7)
-
-inst_808:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0ee0fa88947a1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0xee0fa88947a1;
-valaddr_reg:x9; val_offset:1570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1570*FLEN/8, x10, x6, x7)
-
-inst_809:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0ee0fa88947a1 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xee0fa88947a1; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1572*FLEN/8, x10, x6, x7)
-
-inst_810:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1574*FLEN/8, x10, x6, x7)
-
-inst_811:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1576*FLEN/8, x10, x6, x7)
-
-inst_812:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1578*FLEN/8, x10, x6, x7)
-
-inst_813:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1580*FLEN/8, x10, x6, x7)
-
-inst_814:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1582*FLEN/8, x10, x6, x7)
-
-inst_815:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1584*FLEN/8, x10, x6, x7)
-
-inst_816:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1586*FLEN/8, x10, x6, x7)
-
-inst_817:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x017ce5da753f7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x17ce5da753f7; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:1588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1588*FLEN/8, x10, x6, x7)
-
-inst_818:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x017ce5da753f7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x17ce5da753f7;
-valaddr_reg:x9; val_offset:1590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1590*FLEN/8, x10, x6, x7)
-
-inst_819:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x017ce5da753f7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x17ce5da753f7; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1592*FLEN/8, x10, x6, x7)
-
-inst_820:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x017ce5da753f7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x17ce5da753f7;
-valaddr_reg:x9; val_offset:1594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1594*FLEN/8, x10, x6, x7)
-
-inst_821:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1596*FLEN/8, x10, x6, x7)
-
-inst_822:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1598*FLEN/8, x10, x6, x7)
-
-inst_823:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x0;
-valaddr_reg:x9; val_offset:1600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1600*FLEN/8, x10, x6, x7)
-
-inst_824:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x4b1096905e83e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff4b1096905e83e; op2val:0x0;
-valaddr_reg:x9; val_offset:1602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1602*FLEN/8, x10, x6, x7)
-
-inst_825:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x4b1096905e83e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff4b1096905e83e;
-valaddr_reg:x9; val_offset:1604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1604*FLEN/8, x10, x6, x7)
-
-inst_826:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x94c9c955ccc4c and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x4b1096905e83e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x94c9c955ccc4c; op2val:0x3ff4b1096905e83e;
-valaddr_reg:x9; val_offset:1606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1606*FLEN/8, x10, x6, x7)
-
-inst_827:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1608*FLEN/8, x10, x6, x7)
-
-inst_828:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1610*FLEN/8, x10, x6, x7)
-
-inst_829:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xca304f80cbc99 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7feca304f80cbc99;
-valaddr_reg:x9; val_offset:1612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1612*FLEN/8, x10, x6, x7)
-
-inst_830:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1614*FLEN/8, x10, x6, x7)
-
-inst_831:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1616*FLEN/8, x10, x6, x7)
-
-inst_832:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1618*FLEN/8, x10, x6, x7)
-
-inst_833:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1620*FLEN/8, x10, x6, x7)
-
-inst_834:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1622*FLEN/8, x10, x6, x7)
-
-inst_835:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1624*FLEN/8, x10, x6, x7)
-
-inst_836:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1626*FLEN/8, x10, x6, x7)
-
-inst_837:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x6e8d0c67096e1 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7fb6e8d0c67096e1;
-valaddr_reg:x9; val_offset:1628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1628*FLEN/8, x10, x6, x7)
-
-inst_838:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1630*FLEN/8, x10, x6, x7)
-
-inst_839:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1632*FLEN/8, x10, x6, x7)
-
-inst_840:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1634*FLEN/8, x10, x6, x7)
-
-inst_841:// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x253da385a124e and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7f8253da385a124e; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1636*FLEN/8, x10, x6, x7)
-
-inst_842:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x253da385a124e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x7f8253da385a124e;
-valaddr_reg:x9; val_offset:1638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1638*FLEN/8, x10, x6, x7)
-
-inst_843:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1640*FLEN/8, x10, x6, x7)
-
-inst_844:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1642*FLEN/8, x10, x6, x7)
-
-inst_845:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1644*FLEN/8, x10, x6, x7)
-
-inst_846:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1646*FLEN/8, x10, x6, x7)
-
-inst_847:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1648*FLEN/8, x10, x6, x7)
-
-inst_848:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xca304f80cbc99 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7feca304f80cbc99; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1650*FLEN/8, x10, x6, x7)
-
-inst_849:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1652*FLEN/8, x10, x6, x7)
-
-inst_850:// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x6e8d0c67096e1 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fb6e8d0c67096e1; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1654*FLEN/8, x10, x6, x7)
-
-inst_851:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1656*FLEN/8, x10, x6, x7)
-
-inst_852:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x128254fc5a4fe and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x128254fc5a4fe; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1658*FLEN/8, x10, x6, x7)
-
-inst_853:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x128254fc5a4fe and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x128254fc5a4fe;
-valaddr_reg:x9; val_offset:1660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1660*FLEN/8, x10, x6, x7)
-
-inst_854:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1662*FLEN/8, x10, x6, x7)
-
-inst_855:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x128254fc5a4fe and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x128254fc5a4fe; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1664*FLEN/8, x10, x6, x7)
-
-inst_856:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x128254fc5a4fe and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x128254fc5a4fe;
-valaddr_reg:x9; val_offset:1666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1666*FLEN/8, x10, x6, x7)
-
-inst_857:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x128254fc5a4fe and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x128254fc5a4fe; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1668*FLEN/8, x10, x6, x7)
-
-inst_858:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1670*FLEN/8, x10, x6, x7)
-
-inst_859:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1672*FLEN/8, x10, x6, x7)
-
-inst_860:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1674*FLEN/8, x10, x6, x7)
-
-inst_861:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1676*FLEN/8, x10, x6, x7)
-
-inst_862:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1678*FLEN/8, x10, x6, x7)
-
-inst_863:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1680*FLEN/8, x10, x6, x7)
-
-inst_864:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1682*FLEN/8, x10, x6, x7)
-
-inst_865:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01d9d54c6f6e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1d9d54c6f6e6; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:1684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1684*FLEN/8, x10, x6, x7)
-
-inst_866:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01d9d54c6f6e6 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x1d9d54c6f6e6;
-valaddr_reg:x9; val_offset:1686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1686*FLEN/8, x10, x6, x7)
-
-inst_867:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x01d9d54c6f6e6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x1d9d54c6f6e6; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1688*FLEN/8, x10, x6, x7)
-
-inst_868:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x01d9d54c6f6e6 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x1d9d54c6f6e6;
-valaddr_reg:x9; val_offset:1690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1690*FLEN/8, x10, x6, x7)
-
-inst_869:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1692*FLEN/8, x10, x6, x7)
-
-inst_870:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1694*FLEN/8, x10, x6, x7)
-
-inst_871:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x0;
-valaddr_reg:x9; val_offset:1696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1696*FLEN/8, x10, x6, x7)
-
-inst_872:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x9bd762d8a6627 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x3ff9bd762d8a6627; op2val:0x0;
-valaddr_reg:x9; val_offset:1698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1698*FLEN/8, x10, x6, x7)
-
-inst_873:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x9bd762d8a6627 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x3ff9bd762d8a6627;
-valaddr_reg:x9; val_offset:1700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1700*FLEN/8, x10, x6, x7)
-
-inst_874:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xb91751db871ea and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x9bd762d8a6627 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb91751db871ea; op2val:0x3ff9bd762d8a6627;
-valaddr_reg:x9; val_offset:1702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1702*FLEN/8, x10, x6, x7)
-
-inst_875:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1704*FLEN/8, x10, x6, x7)
-
-inst_876:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7ff0000000000000;
-valaddr_reg:x9; val_offset:1706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1706*FLEN/8, x10, x6, x7)
-
-inst_877:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1708*FLEN/8, x10, x6, x7)
-
-inst_878:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1710*FLEN/8, x10, x6, x7)
-
-inst_879:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1712*FLEN/8, x10, x6, x7)
-
-inst_880:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1714*FLEN/8, x10, x6, x7)
-
-inst_881:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1716*FLEN/8, x10, x6, x7)
-
-inst_882:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x19e9f6802bcef and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7fe19e9f6802bcef;
-valaddr_reg:x9; val_offset:1718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1718*FLEN/8, x10, x6, x7)
-
-inst_883:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1720*FLEN/8, x10, x6, x7)
-
-inst_884:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1722*FLEN/8, x10, x6, x7)
-
-inst_885:// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xc30ff0cd12e4b and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fac30ff0cd12e4b; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1724*FLEN/8, x10, x6, x7)
-
-inst_886:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xc30ff0cd12e4b and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x7fac30ff0cd12e4b;
-valaddr_reg:x9; val_offset:1726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1726*FLEN/8, x10, x6, x7)
-
-inst_887:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1728*FLEN/8, x10, x6, x7)
-
-inst_888:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1730*FLEN/8, x10, x6, x7)
-
-inst_889:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1732*FLEN/8, x10, x6, x7)
-
-inst_890:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1734*FLEN/8, x10, x6, x7)
-
-inst_891:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1736*FLEN/8, x10, x6, x7)
-
-inst_892:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1738*FLEN/8, x10, x6, x7)
-
-inst_893:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x19e9f6802bcef and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fe19e9f6802bcef; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1740*FLEN/8, x10, x6, x7)
-
-inst_894:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1742*FLEN/8, x10, x6, x7)
-
-inst_895:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:1744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1744*FLEN/8, x10, x6, x7)
-
-inst_896:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1746*FLEN/8, x10, x6, x7)
-
-inst_897:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1748*FLEN/8, x10, x6, x7)
-
-inst_898:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:1750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1750*FLEN/8, x10, x6, x7)
-
-inst_899:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1752*FLEN/8, x10, x6, x7)
-
-inst_900:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:1754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1754*FLEN/8, x10, x6, x7)
-
-inst_901:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1756*FLEN/8, x10, x6, x7)
-
-inst_902:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x176d62053e9f2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x800176d62053e9f2;
-valaddr_reg:x9; val_offset:1758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1758*FLEN/8, x10, x6, x7)
-
-inst_903:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x176d62053e9f2 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800176d62053e9f2; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1760*FLEN/8, x10, x6, x7)
-
-inst_904:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1762*FLEN/8, x10, x6, x7)
-
-inst_905:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1764*FLEN/8, x10, x6, x7)
-
-inst_906:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x11b63268cb80c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x80011b63268cb80c;
-valaddr_reg:x9; val_offset:1766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1766*FLEN/8, x10, x6, x7)
-
-inst_907:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11b63268cb80c and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80011b63268cb80c; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1768*FLEN/8, x10, x6, x7)
-
-inst_908:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1770*FLEN/8, x10, x6, x7)
-
-inst_909:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1772*FLEN/8, x10, x6, x7)
-
-inst_910:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x158b9f3ccd07c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x800158b9f3ccd07c;
-valaddr_reg:x9; val_offset:1774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1774*FLEN/8, x10, x6, x7)
-
-inst_911:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x158b9f3ccd07c and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800158b9f3ccd07c; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1776*FLEN/8, x10, x6, x7)
-
-inst_912:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1778*FLEN/8, x10, x6, x7)
-
-inst_913:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1780*FLEN/8, x10, x6, x7)
-
-inst_914:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0b63657b34e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d430d1d19325 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb63657b34e4c; op2val:0x8000d430d1d19325;
-valaddr_reg:x9; val_offset:1782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1782*FLEN/8, x10, x6, x7)
-
-inst_915:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d430d1d19325 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0b63657b34e4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d430d1d19325; op2val:0xb63657b34e4c;
-valaddr_reg:x9; val_offset:1784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1784*FLEN/8, x10, x6, x7)
-
-inst_916:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0b63657b34e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xb63657b34e4c; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1786*FLEN/8, x10, x6, x7)
-
-inst_917:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0b63657b34e4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0xb63657b34e4c;
-valaddr_reg:x9; val_offset:1788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1788*FLEN/8, x10, x6, x7)
-
-inst_918:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1790*FLEN/8, x10, x6, x7)
-
-inst_919:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x12bba85050ee4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x80012bba85050ee4;
-valaddr_reg:x9; val_offset:1792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1792*FLEN/8, x10, x6, x7)
-
-inst_920:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12bba85050ee4 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1cb4e9082a569 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80012bba85050ee4; op2val:0x31cb4e9082a569;
-valaddr_reg:x9; val_offset:1794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1794*FLEN/8, x10, x6, x7)
-
-inst_921:// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1cb4e9082a569 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x31cb4e9082a569; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1796*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_7)
-
-inst_922:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x0;
-valaddr_reg:x9; val_offset:1798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1798*FLEN/8, x10, x6, x7)
-
-inst_923:// fs1 == 0 and fe1 == 0x402 and fm1 == 0x3cbf277e6ba7f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x4023cbf277e6ba7f; op2val:0x0;
-valaddr_reg:x9; val_offset:1800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1800*FLEN/8, x10, x6, x7)
-
-inst_924:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x3cbf277e6ba7f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x4023cbf277e6ba7f;
-valaddr_reg:x9; val_offset:1802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1802*FLEN/8, x10, x6, x7)
-
-inst_925:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x71e1f6d010ef7 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x3cbf277e6ba7f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x71e1f6d010ef7; op2val:0x4023cbf277e6ba7f;
-valaddr_reg:x9; val_offset:1804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1804*FLEN/8, x10, x6, x7)
-
-inst_926:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1806*FLEN/8, x10, x6, x7)
-
-inst_927:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1808*FLEN/8, x10, x6, x7)
-
-inst_928:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1810*FLEN/8, x10, x6, x7)
-
-inst_929:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1812*FLEN/8, x10, x6, x7)
-
-inst_930:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1814*FLEN/8, x10, x6, x7)
-
-inst_931:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1816*FLEN/8, x10, x6, x7)
-
-inst_932:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1818*FLEN/8, x10, x6, x7)
-
-inst_933:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xcff30f3beb065 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xffbcff30f3beb065;
-valaddr_reg:x9; val_offset:1820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1820*FLEN/8, x10, x6, x7)
-
-inst_934:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1822*FLEN/8, x10, x6, x7)
-
-inst_935:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1824*FLEN/8, x10, x6, x7)
-
-inst_936:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x7328d8fcbc051 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff87328d8fcbc051; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1826*FLEN/8, x10, x6, x7)
-
-inst_937:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x7328d8fcbc051 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xff87328d8fcbc051;
-valaddr_reg:x9; val_offset:1828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1828*FLEN/8, x10, x6, x7)
-
-inst_938:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1830*FLEN/8, x10, x6, x7)
-
-inst_939:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1832*FLEN/8, x10, x6, x7)
-
-inst_940:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1834*FLEN/8, x10, x6, x7)
-
-inst_941:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1836*FLEN/8, x10, x6, x7)
-
-inst_942:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1838*FLEN/8, x10, x6, x7)
-
-inst_943:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1840*FLEN/8, x10, x6, x7)
-
-inst_944:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xcff30f3beb065 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbcff30f3beb065; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1842*FLEN/8, x10, x6, x7)
-
-inst_945:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1844*FLEN/8, x10, x6, x7)
-
-inst_946:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x176d62053e9f2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800176d62053e9f2; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1846*FLEN/8, x10, x6, x7)
-
-inst_947:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x176d62053e9f2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x800176d62053e9f2;
-valaddr_reg:x9; val_offset:1848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1848*FLEN/8, x10, x6, x7)
-
-inst_948:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1850*FLEN/8, x10, x6, x7)
-
-inst_949:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x176d62053e9f2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800176d62053e9f2; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1852*FLEN/8, x10, x6, x7)
-
-inst_950:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1854*FLEN/8, x10, x6, x7)
-
-inst_951:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1856*FLEN/8, x10, x6, x7)
-
-inst_952:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1858*FLEN/8, x10, x6, x7)
-
-inst_953:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1860*FLEN/8, x10, x6, x7)
-
-inst_954:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1862*FLEN/8, x10, x6, x7)
-
-inst_955:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0257bd0086432 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000257bd0086432; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:1864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1864*FLEN/8, x10, x6, x7)
-
-inst_956:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0257bd0086432 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x8000257bd0086432;
-valaddr_reg:x9; val_offset:1866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1866*FLEN/8, x10, x6, x7)
-
-inst_957:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0257bd0086432 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000257bd0086432; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1868*FLEN/8, x10, x6, x7)
-
-inst_958:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0257bd0086432 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x8000257bd0086432;
-valaddr_reg:x9; val_offset:1870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1870*FLEN/8, x10, x6, x7)
-
-inst_959:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1872*FLEN/8, x10, x6, x7)
-
-inst_960:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:1874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1874*FLEN/8, x10, x6, x7)
-
-inst_961:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0x0;
-valaddr_reg:x9; val_offset:1876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1876*FLEN/8, x10, x6, x7)
-
-inst_962:// fs1 == 1 and fe1 == 0x400 and fm1 == 0x04a31976bdb6f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc0004a31976bdb6f; op2val:0x0;
-valaddr_reg:x9; val_offset:1878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1878*FLEN/8, x10, x6, x7)
-
-inst_963:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x04a31976bdb6f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xc0004a31976bdb6f;
-valaddr_reg:x9; val_offset:1880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1880*FLEN/8, x10, x6, x7)
-
-inst_964:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xea45d43472379 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x04a31976bdb6f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800ea45d43472379; op2val:0xc0004a31976bdb6f;
-valaddr_reg:x9; val_offset:1882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1882*FLEN/8, x10, x6, x7)
-
-inst_965:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1884*FLEN/8, x10, x6, x7)
-
-inst_966:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1886*FLEN/8, x10, x6, x7)
-
-inst_967:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb672fe8c6e870 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xffeb672fe8c6e870;
-valaddr_reg:x9; val_offset:1888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1888*FLEN/8, x10, x6, x7)
-
-inst_968:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1890*FLEN/8, x10, x6, x7)
-
-inst_969:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1892*FLEN/8, x10, x6, x7)
-
-inst_970:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1894*FLEN/8, x10, x6, x7)
-
-inst_971:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1896*FLEN/8, x10, x6, x7)
-
-inst_972:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1898*FLEN/8, x10, x6, x7)
-
-inst_973:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1900*FLEN/8, x10, x6, x7)
-
-inst_974:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1902*FLEN/8, x10, x6, x7)
-
-inst_975:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x5ec2653d2538d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xffb5ec2653d2538d;
-valaddr_reg:x9; val_offset:1904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1904*FLEN/8, x10, x6, x7)
-
-inst_976:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1906*FLEN/8, x10, x6, x7)
-
-inst_977:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1908*FLEN/8, x10, x6, x7)
-
-inst_978:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1910*FLEN/8, x10, x6, x7)
-
-inst_979:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x189b8430ea93d and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff8189b8430ea93d; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1912*FLEN/8, x10, x6, x7)
-
-inst_980:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x189b8430ea93d and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xff8189b8430ea93d;
-valaddr_reg:x9; val_offset:1914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1914*FLEN/8, x10, x6, x7)
-
-inst_981:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1916*FLEN/8, x10, x6, x7)
-
-inst_982:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1918*FLEN/8, x10, x6, x7)
-
-inst_983:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1920*FLEN/8, x10, x6, x7)
-
-inst_984:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1922*FLEN/8, x10, x6, x7)
-
-inst_985:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1924*FLEN/8, x10, x6, x7)
-
-inst_986:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb672fe8c6e870 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffeb672fe8c6e870; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:1926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1926*FLEN/8, x10, x6, x7)
-
-inst_987:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1928*FLEN/8, x10, x6, x7)
-
-inst_988:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x5ec2653d2538d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb5ec2653d2538d; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:1930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1930*FLEN/8, x10, x6, x7)
-
-inst_989:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1932*FLEN/8, x10, x6, x7)
-
-inst_990:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11b63268cb80c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80011b63268cb80c; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:1934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1934*FLEN/8, x10, x6, x7)
-
-inst_991:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x11b63268cb80c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x80011b63268cb80c;
-valaddr_reg:x9; val_offset:1936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1936*FLEN/8, x10, x6, x7)
-
-inst_992:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1938*FLEN/8, x10, x6, x7)
-
-inst_993:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11b63268cb80c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80011b63268cb80c; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:1940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1940*FLEN/8, x10, x6, x7)
-
-inst_994:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1942*FLEN/8, x10, x6, x7)
-
-inst_995:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1944*FLEN/8, x10, x6, x7)
-
-inst_996:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1946*FLEN/8, x10, x6, x7)
-
-inst_997:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01c56b70e1268 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001c56b70e1268; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:1948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1948*FLEN/8, x10, x6, x7)
-
-inst_998:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01c56b70e1268 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x80001c56b70e1268;
-valaddr_reg:x9; val_offset:1950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1950*FLEN/8, x10, x6, x7)
-
-inst_999:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01c56b70e1268 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001c56b70e1268; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:1952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1952*FLEN/8, x10, x6, x7)
-
-inst_1000:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01c56b70e1268 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x80001c56b70e1268;
-valaddr_reg:x9; val_offset:1954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1954*FLEN/8, x10, x6, x7)
-
-inst_1001:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:1956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1956*FLEN/8, x10, x6, x7)
-
-inst_1002:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:1958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1958*FLEN/8, x10, x6, x7)
-
-inst_1003:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0x0;
-valaddr_reg:x9; val_offset:1960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1960*FLEN/8, x10, x6, x7)
-
-inst_1004:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8a193aec8d637 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbff8a193aec8d637; op2val:0x0;
-valaddr_reg:x9; val_offset:1962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1962*FLEN/8, x10, x6, x7)
-
-inst_1005:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x8a193aec8d637 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbff8a193aec8d637;
-valaddr_reg:x9; val_offset:1964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1964*FLEN/8, x10, x6, x7)
-
-inst_1006:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb11df817f3079 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x8a193aec8d637 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800b11df817f3079; op2val:0xbff8a193aec8d637;
-valaddr_reg:x9; val_offset:1966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1966*FLEN/8, x10, x6, x7)
-
-inst_1007:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:1968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1968*FLEN/8, x10, x6, x7)
-
-inst_1008:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xfff0000000000000;
-valaddr_reg:x9; val_offset:1970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1970*FLEN/8, x10, x6, x7)
-
-inst_1009:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:1972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1972*FLEN/8, x10, x6, x7)
-
-inst_1010:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:1974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1974*FLEN/8, x10, x6, x7)
-
-inst_1011:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:1976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1976*FLEN/8, x10, x6, x7)
-
-inst_1012:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1978*FLEN/8, x10, x6, x7)
-
-inst_1013:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:1980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1980*FLEN/8, x10, x6, x7)
-
-inst_1014:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xaaae5b42b9d01 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xffbaaae5b42b9d01;
-valaddr_reg:x9; val_offset:1982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1982*FLEN/8, x10, x6, x7)
-
-inst_1015:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:1984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1984*FLEN/8, x10, x6, x7)
-
-inst_1016:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1986*FLEN/8, x10, x6, x7)
-
-inst_1017:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x555849022e400 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff8555849022e400; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:1988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1988*FLEN/8, x10, x6, x7)
-
-inst_1018:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x555849022e400 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xff8555849022e400;
-valaddr_reg:x9; val_offset:1990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1990*FLEN/8, x10, x6, x7)
-
-inst_1019:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1992*FLEN/8, x10, x6, x7)
-
-inst_1020:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:1994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1994*FLEN/8, x10, x6, x7)
-
-inst_1021:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1996*FLEN/8, x10, x6, x7)
-
-inst_1022:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:1998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 1998*FLEN/8, x10, x6, x7)
-
-inst_1023:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:2000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2000*FLEN/8, x10, x6, x7)
-
-inst_1024:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:2002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2002*FLEN/8, x10, x6, x7)
-
-inst_1025:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xaaae5b42b9d01 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffbaaae5b42b9d01; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:2004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2004*FLEN/8, x10, x6, x7)
-
-inst_1026:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:2006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2006*FLEN/8, x10, x6, x7)
-
-inst_1027:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x158b9f3ccd07c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800158b9f3ccd07c; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:2008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2008*FLEN/8, x10, x6, x7)
-
-inst_1028:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x158b9f3ccd07c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x800158b9f3ccd07c;
-valaddr_reg:x9; val_offset:2010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2010*FLEN/8, x10, x6, x7)
-
-inst_1029:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:2012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2012*FLEN/8, x10, x6, x7)
-
-inst_1030:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x158b9f3ccd07c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800158b9f3ccd07c; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:2014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2014*FLEN/8, x10, x6, x7)
-
-inst_1031:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:2016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2016*FLEN/8, x10, x6, x7)
-
-inst_1032:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x02278fec7ae73 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80002278fec7ae73; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:2018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2018*FLEN/8, x10, x6, x7)
-
-inst_1033:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x02278fec7ae73 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x80002278fec7ae73;
-valaddr_reg:x9; val_offset:2020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2020*FLEN/8, x10, x6, x7)
-
-inst_1034:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x02278fec7ae73 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80002278fec7ae73; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:2022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2022*FLEN/8, x10, x6, x7)
-
-inst_1035:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x000 and fm2 == 0x02278fec7ae73 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x80002278fec7ae73;
-valaddr_reg:x9; val_offset:2024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2024*FLEN/8, x10, x6, x7)
-
-inst_1036:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:2026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2026*FLEN/8, x10, x6, x7)
-
-inst_1037:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:2028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2028*FLEN/8, x10, x6, x7)
-
-inst_1038:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0x0;
-valaddr_reg:x9; val_offset:2030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2030*FLEN/8, x10, x6, x7)
-
-inst_1039:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xdf66a9ea7fbe7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbffdf66a9ea7fbe7; op2val:0x0;
-valaddr_reg:x9; val_offset:2032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2032*FLEN/8, x10, x6, x7)
-
-inst_1040:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xdf66a9ea7fbe7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbffdf66a9ea7fbe7;
-valaddr_reg:x9; val_offset:2034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2034*FLEN/8, x10, x6, x7)
-
-inst_1041:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xd7743860024db and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xdf66a9ea7fbe7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800d7743860024db; op2val:0xbffdf66a9ea7fbe7;
-valaddr_reg:x9; val_offset:2036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2036*FLEN/8, x10, x6, x7)
-
-inst_1042:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:2038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2038*FLEN/8, x10, x6, x7)
-
-inst_1043:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:2040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2040*FLEN/8, x10, x6, x7)
-
-inst_1044:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x484bb4eb5b9d5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xffe484bb4eb5b9d5;
-valaddr_reg:x9; val_offset:2042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2042*FLEN/8, x10, x6, x7)
-
-inst_1045:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:2044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2044*FLEN/8, x10, x6, x7)
-
-inst_1046:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:2046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2046*FLEN/8, x10, x6, x7)
-
-inst_1047:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:2048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2048*FLEN/8, x10, x6, x7)
-
-inst_1048:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:2050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2050*FLEN/8, x10, x6, x7)
-
-inst_1049:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:2052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2052*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_8)
-
-inst_1050:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:2054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2054*FLEN/8, x10, x6, x7)
-
-inst_1051:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:2056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2056*FLEN/8, x10, x6, x7)
-
-inst_1052:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x06a2f722afb11 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xffb06a2f722afb11;
-valaddr_reg:x9; val_offset:2058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2058*FLEN/8, x10, x6, x7)
-
-inst_1053:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:2060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2060*FLEN/8, x10, x6, x7)
-
-inst_1054:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:2062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2062*FLEN/8, x10, x6, x7)
-
-inst_1055:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:2064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2064*FLEN/8, x10, x6, x7)
-
-inst_1056:// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0xa437f1d1191b5 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff7a437f1d1191b5; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:2066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2066*FLEN/8, x10, x6, x7)
-
-inst_1057:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0xa437f1d1191b5 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xff7a437f1d1191b5;
-valaddr_reg:x9; val_offset:2068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2068*FLEN/8, x10, x6, x7)
-
-inst_1058:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:2070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2070*FLEN/8, x10, x6, x7)
-
-inst_1059:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:2072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2072*FLEN/8, x10, x6, x7)
-
-inst_1060:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:2074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2074*FLEN/8, x10, x6, x7)
-
-inst_1061:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:2076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2076*FLEN/8, x10, x6, x7)
-
-inst_1062:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:2078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2078*FLEN/8, x10, x6, x7)
-
-inst_1063:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x484bb4eb5b9d5 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffe484bb4eb5b9d5; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:2080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2080*FLEN/8, x10, x6, x7)
-
-inst_1064:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:2082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2082*FLEN/8, x10, x6, x7)
-
-inst_1065:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x06a2f722afb11 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb06a2f722afb11; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:2084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2084*FLEN/8, x10, x6, x7)
-
-inst_1066:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:2086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2086*FLEN/8, x10, x6, x7)
-
-inst_1067:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d430d1d19325 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d430d1d19325; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:2088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2088*FLEN/8, x10, x6, x7)
-
-inst_1068:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0d430d1d19325 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x8000d430d1d19325;
-valaddr_reg:x9; val_offset:2090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2090*FLEN/8, x10, x6, x7)
-
-inst_1069:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:2092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2092*FLEN/8, x10, x6, x7)
-
-inst_1070:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:2094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2094*FLEN/8, x10, x6, x7)
-
-inst_1071:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:2096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2096*FLEN/8, x10, x6, x7)
-
-inst_1072:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:2098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2098*FLEN/8, x10, x6, x7)
-
-inst_1073:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:2100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2100*FLEN/8, x10, x6, x7)
-
-inst_1074:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:2102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2102*FLEN/8, x10, x6, x7)
-
-inst_1075:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:2104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2104*FLEN/8, x10, x6, x7)
-
-inst_1076:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:2106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2106*FLEN/8, x10, x6, x7)
-
-inst_1077:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0d430d1d19325 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000d430d1d19325; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:2108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2108*FLEN/8, x10, x6, x7)
-
-inst_1078:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:2110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2110*FLEN/8, x10, x6, x7)
-
-inst_1079:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:2112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2112*FLEN/8, x10, x6, x7)
-
-inst_1080:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:2114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2114*FLEN/8, x10, x6, x7)
-
-inst_1081:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:2116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2116*FLEN/8, x10, x6, x7)
-
-inst_1082:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:2118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2118*FLEN/8, x10, x6, x7)
-
-inst_1083:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:2120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2120*FLEN/8, x10, x6, x7)
-
-inst_1084:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:2122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2122*FLEN/8, x10, x6, x7)
-
-inst_1085:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01df90d4d4e4a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x80001df90d4d4e4a;
-valaddr_reg:x9; val_offset:2124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2124*FLEN/8, x10, x6, x7)
-
-inst_1086:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01df90d4d4e4a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x849e8322fbf77 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001df90d4d4e4a; op2val:0x800849e8322fbf77;
-valaddr_reg:x9; val_offset:2126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2126*FLEN/8, x10, x6, x7)
-
-inst_1087:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x849e8322fbf77 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800849e8322fbf77; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:2128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2128*FLEN/8, x10, x6, x7)
-
-inst_1088:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0x0;
-valaddr_reg:x9; val_offset:2130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2130*FLEN/8, x10, x6, x7)
-
-inst_1089:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x271665b532bfd and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbff271665b532bfd; op2val:0x0;
-valaddr_reg:x9; val_offset:2132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2132*FLEN/8, x10, x6, x7)
-
-inst_1090:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x271665b532bfd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbff271665b532bfd;
-valaddr_reg:x9; val_offset:2134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2134*FLEN/8, x10, x6, x7)
-
-inst_1091:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0153814fb5b84 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x271665b532bfd and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x8000153814fb5b84; op2val:0xbff271665b532bfd;
-valaddr_reg:x9; val_offset:2136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2136*FLEN/8, x10, x6, x7)
-
-inst_1092:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:2138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2138*FLEN/8, x10, x6, x7)
-
-inst_1093:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:2140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2140*FLEN/8, x10, x6, x7)
-
-inst_1094:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xcfbb63d922c8f and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xffecfbb63d922c8f;
-valaddr_reg:x9; val_offset:2142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2142*FLEN/8, x10, x6, x7)
-
-inst_1095:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:2144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2144*FLEN/8, x10, x6, x7)
-
-inst_1096:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:2146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2146*FLEN/8, x10, x6, x7)
-
-inst_1097:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:2148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2148*FLEN/8, x10, x6, x7)
-
-inst_1098:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:2150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2150*FLEN/8, x10, x6, x7)
-
-inst_1099:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:2152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2152*FLEN/8, x10, x6, x7)
-
-inst_1100:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:2154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2154*FLEN/8, x10, x6, x7)
-
-inst_1101:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:2156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2156*FLEN/8, x10, x6, x7)
-
-inst_1102:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x72fc4fe0e8a0c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xffb72fc4fe0e8a0c;
-valaddr_reg:x9; val_offset:2158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2158*FLEN/8, x10, x6, x7)
-
-inst_1103:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:2160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2160*FLEN/8, x10, x6, x7)
-
-inst_1104:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:2162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2162*FLEN/8, x10, x6, x7)
-
-inst_1105:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:2164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2164*FLEN/8, x10, x6, x7)
-
-inst_1106:// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x28c9d980ba1a3 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xff828c9d980ba1a3; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:2166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2166*FLEN/8, x10, x6, x7)
-
-inst_1107:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x28c9d980ba1a3 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xff828c9d980ba1a3;
-valaddr_reg:x9; val_offset:2168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2168*FLEN/8, x10, x6, x7)
-
-inst_1108:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:2170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2170*FLEN/8, x10, x6, x7)
-
-inst_1109:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:2172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2172*FLEN/8, x10, x6, x7)
-
-inst_1110:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:2174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2174*FLEN/8, x10, x6, x7)
-
-inst_1111:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:2176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2176*FLEN/8, x10, x6, x7)
-
-inst_1112:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:2178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2178*FLEN/8, x10, x6, x7)
-
-inst_1113:// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcfbb63d922c8f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffecfbb63d922c8f; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:2180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2180*FLEN/8, x10, x6, x7)
-
-inst_1114:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:2182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2182*FLEN/8, x10, x6, x7)
-
-inst_1115:// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x72fc4fe0e8a0c and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xffb72fc4fe0e8a0c; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:2184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2184*FLEN/8, x10, x6, x7)
-
-inst_1116:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:2186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2186*FLEN/8, x10, x6, x7)
-
-inst_1117:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12bba85050ee4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80012bba85050ee4; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:2188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2188*FLEN/8, x10, x6, x7)
-
-inst_1118:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x12bba85050ee4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x80012bba85050ee4;
-valaddr_reg:x9; val_offset:2190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2190*FLEN/8, x10, x6, x7)
-
-inst_1119:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:2192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2192*FLEN/8, x10, x6, x7)
-
-inst_1120:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12bba85050ee4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80012bba85050ee4; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:2194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2194*FLEN/8, x10, x6, x7)
-
-inst_1121:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:2196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2196*FLEN/8, x10, x6, x7)
-
-inst_1122:// fs1 == 1 and fe1 == 0x000 and fm1 == 0x01df90d4d4e4a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x80001df90d4d4e4a; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:2198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2198*FLEN/8, x10, x6, x7)
-
-inst_1123:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x01df90d4d4e4a and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x80001df90d4d4e4a;
-valaddr_reg:x9; val_offset:2200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2200*FLEN/8, x10, x6, x7)
-
-inst_1124:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0x0;
-valaddr_reg:x9; val_offset:2202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2202*FLEN/8, x10, x6, x7)
-
-inst_1125:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xa0d2ebbb9cec0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xbffa0d2ebbb9cec0; op2val:0x0;
-valaddr_reg:x9; val_offset:2204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2204*FLEN/8, x10, x6, x7)
-
-inst_1126:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xa0d2ebbb9cec0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xbffa0d2ebbb9cec0;
-valaddr_reg:x9; val_offset:2206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2206*FLEN/8, x10, x6, x7)
-
-inst_1127:// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbb549323294e4 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xa0d2ebbb9cec0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x800bb549323294e4; op2val:0xbffa0d2ebbb9cec0;
-valaddr_reg:x9; val_offset:2208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2208*FLEN/8, x10, x6, x7)
-
-inst_1128:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:2210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2210*FLEN/8, x10, x6, x7)
-
-inst_1129:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x9; val_offset:2212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2212*FLEN/8, x10, x6, x7)
-
-inst_1130:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xabc6824ad2440 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7feabc6824ad2440;
-valaddr_reg:x9; val_offset:2214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2214*FLEN/8, x10, x6, x7)
-
-inst_1131:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x363e504d94fe2 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fe363e504d94fe2;
-valaddr_reg:x9; val_offset:2216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2216*FLEN/8, x10, x6, x7)
-
-inst_1132:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xb9017651b96db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fdb9017651b96db;
-valaddr_reg:x9; val_offset:2218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2218*FLEN/8, x10, x6, x7)
-
-inst_1133:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe61729d7cfd5e and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x7fee61729d7cfd5e;
-valaddr_reg:x9; val_offset:2220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2220*FLEN/8, x10, x6, x7)
-
-inst_1134:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xab65b09a91410 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffaab65b09a91410;
-valaddr_reg:x9; val_offset:2222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2222*FLEN/8, x10, x6, x7)
-
-inst_1135:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0e5de21873eea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffd0e5de21873eea;
-valaddr_reg:x9; val_offset:2224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2224*FLEN/8, x10, x6, x7)
-
-inst_1136:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x92a290fb6d0de and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffd92a290fb6d0de;
-valaddr_reg:x9; val_offset:2226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2226*FLEN/8, x10, x6, x7)
-
-inst_1137:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x3682ff4c90ae0 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffe3682ff4c90ae0;
-valaddr_reg:x9; val_offset:2228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2228*FLEN/8, x10, x6, x7)
-
-inst_1138:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xd2c340883a998 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xffdd2c340883a998;
-valaddr_reg:x9; val_offset:2230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2230*FLEN/8, x10, x6, x7)
-
-inst_1139:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0e7a2682ee434 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xe7a2682ee434;
-valaddr_reg:x9; val_offset:2232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2232*FLEN/8, x10, x6, x7)
-
-inst_1140:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xab73739b529c7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xab73739b529c7;
-valaddr_reg:x9; val_offset:2234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2234*FLEN/8, x10, x6, x7)
-
-inst_1141:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x94c9c955ccc4c and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x94c9c955ccc4c;
-valaddr_reg:x9; val_offset:2236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2236*FLEN/8, x10, x6, x7)
-
-inst_1142:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xb91751db871ea and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0xb91751db871ea;
-valaddr_reg:x9; val_offset:2238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2238*FLEN/8, x10, x6, x7)
-
-inst_1143:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x71e1f6d010ef7 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x71e1f6d010ef7;
-valaddr_reg:x9; val_offset:2240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2240*FLEN/8, x10, x6, x7)
-
-inst_1144:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xea45d43472379 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800ea45d43472379;
-valaddr_reg:x9; val_offset:2242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2242*FLEN/8, x10, x6, x7)
-
-inst_1145:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb11df817f3079 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800b11df817f3079;
-valaddr_reg:x9; val_offset:2244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2244*FLEN/8, x10, x6, x7)
-
-inst_1146:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xd7743860024db and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800d7743860024db;
-valaddr_reg:x9; val_offset:2246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2246*FLEN/8, x10, x6, x7)
-
-inst_1147:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0153814fb5b84 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x8000153814fb5b84;
-valaddr_reg:x9; val_offset:2248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2248*FLEN/8, x10, x6, x7)
-
-inst_1148:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbb549323294e4 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x800bb549323294e4;
-valaddr_reg:x9; val_offset:2250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2250*FLEN/8, x10, x6, x7)
-
-inst_1149:// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe97d52f73d2ed and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe97d52f73d2ed and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0x7fee97d52f73d2ed; op2val:0x7fee97d52f73d2ed;
-valaddr_reg:x9; val_offset:2252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2252*FLEN/8, x10, x6, x7)
-
-inst_1150:// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc5bc46ffcb5d2 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xa86c4594097a9 and  fcsr == 0  
-/* opcode: fltq.d ; op1:f31; op2:f30; dest:x31; op1val:0xc5bc46ffcb5d2; op2val:0x7fea86c4594097a9;
-valaddr_reg:x9; val_offset:2254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.d, x31, f31, f30, 0, 0, x9, 2254*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
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-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(18438695854564510432,64,FLEN)
-NAN_BOXED(18439008714375936469,64,FLEN)
-NAN_BOXED(18438695854564510432,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(18436941051517446552,64,FLEN)
-NAN_BOXED(18424342827584125713,64,FLEN)
-NAN_BOXED(18436941051517446552,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(254684718621748,64,FLEN)
-NAN_BOXED(9223605342998467365,64,FLEN)
-NAN_BOXED(254684718621748,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(9223605342998467365,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(3016197586364871,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(3016197586364871,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(2617510194891852,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(2617510194891852,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(3256156939645418,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(3256156939645418,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(2003445158579959,64,FLEN)
-NAN_BOXED(9223605342998467365,64,FLEN)
-NAN_BOXED(2003445158579959,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(9227493406996374393,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(9227493406996374393,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(9226487913246568569,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(9226487913246568569,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(9227162343446684891,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(9227162343446684891,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(9223404992362008138,64,FLEN)
-NAN_BOXED(9223404992362008138,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(9225705098291691383,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13831242090040994813,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13831242090040994813,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(13831242090040994813,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(18441391334310947983,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18441391334310947983,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9217386742845088832,64,FLEN)
-NAN_BOXED(18441391334310947983,64,FLEN)
-NAN_BOXED(9217386742845088832,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9215319097810178018,64,FLEN)
-NAN_BOXED(18441391334310947983,64,FLEN)
-NAN_BOXED(9215319097810178018,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9213115892871435995,64,FLEN)
-NAN_BOXED(18426248923532134924,64,FLEN)
-NAN_BOXED(9213115892871435995,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18426248923532134924,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9218412632170364254,64,FLEN)
-NAN_BOXED(18441391334310947983,64,FLEN)
-NAN_BOXED(9218412632170364254,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18422737727832790032,64,FLEN)
-NAN_BOXED(18411432835132662179,64,FLEN)
-NAN_BOXED(18422737727832790032,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18411432835132662179,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18433486017035452138,64,FLEN)
-NAN_BOXED(18426248923532134924,64,FLEN)
-NAN_BOXED(18433486017035452138,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18435812905463501022,64,FLEN)
-NAN_BOXED(18426248923532134924,64,FLEN)
-NAN_BOXED(18435812905463501022,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18438695854564510432,64,FLEN)
-NAN_BOXED(18441391334310947983,64,FLEN)
-NAN_BOXED(18438695854564510432,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(18436941051517446552,64,FLEN)
-NAN_BOXED(18426248923532134924,64,FLEN)
-NAN_BOXED(18436941051517446552,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(254684718621748,64,FLEN)
-NAN_BOXED(9223701591927099108,64,FLEN)
-NAN_BOXED(254684718621748,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9223701591927099108,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(2003445158579959,64,FLEN)
-NAN_BOXED(9223701591927099108,64,FLEN)
-NAN_BOXED(2003445158579959,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(9223404992362008138,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9223404992362008138,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13833383699791072960,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13833383699791072960,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(13833383699791072960,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9217386742845088832,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9215319097810178018,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9213115892871435995,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9218412632170364254,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18422737727832790032,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18433486017035452138,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18435812905463501022,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18438695854564510432,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18436941051517446552,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(254684718621748,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(3016197586364871,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2617510194891852,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(3256156939645418,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2003445158579959,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9227493406996374393,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9226487913246568569,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9227162343446684891,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223395367469144964,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9226667587578008804,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(9218472429153932013,64,FLEN)
-NAN_BOXED(3478598971078098,64,FLEN)
-NAN_BOXED(9217327765236258729,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_7:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_8:
-    .fill 202*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b1-01.S
deleted file mode 100644
index 5d131ce8d..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b1-01.S
+++ /dev/null
@@ -1,368 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:17:01 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fltq.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fltq.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fltq_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 == rs2, rs1==f31, rs2==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f31; op2:f31; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 != rs2, rs1==f30, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f30; op2:f29; dest:x30; op1val:0x0; op2val:0x80000000;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x30, f30, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f29, rs2==f30, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f29; op2:f30; dest:x29; op1val:0x0; op2val:0x1;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x29, f29, f30, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f28; op2:f27; dest:x28; op1val:0x0; op2val:0x80000001;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f27; op2:f28; dest:x27; op1val:0x0; op2val:0x2;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f26; op2:f25; dest:x26; op1val:0x0; op2val:0x807ffffe;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f25; op2:f26; dest:x25; op1val:0x0; op2val:0x7fffff;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f24; op2:f23; dest:x24; op1val:0x0; op2val:0x807fffff;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f23; op2:f24; dest:x23; op1val:0x0; op2val:0x800000;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f22; op2:f21; dest:x22; op1val:0x0; op2val:0x80800000;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f21; op2:f22; dest:x21; op1val:0x0; op2val:0x800001;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f20; op2:f19; dest:x20; op1val:0x0; op2val:0x80855555;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f19; op2:f20; dest:x19; op1val:0x0; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f18; op2:f17; dest:x18; op1val:0x0; op2val:0xff7fffff;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f17; op2:f18; dest:x17; op1val:0x0; op2val:0x7f800000;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f16; op2:f15; dest:x16; op1val:0x0; op2val:0xff800000;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f15; op2:f16; dest:x15; op1val:0x0; op2val:0x7fc00000;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f14; op2:f13; dest:x14; op1val:0x0; op2val:0xffc00000;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f13; op2:f14; dest:x13; op1val:0x0; op2val:0x7fc00001;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f12; op2:f11; dest:x12; op1val:0x0; op2val:0xffc55555;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f11; op2:f12; dest:x11; op1val:0x0; op2val:0x7f800001;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f10; op2:f9; dest:x10; op1val:0x0; op2val:0xffaaaaaa;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f9; op2:f10; dest:x9; op1val:0x0; op2val:0x3f800000;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f8; op2:f7; dest:x8; op1val:0x0; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f7; op2:f8; dest:x7; op1val:0x80000000; op2val:0x0;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f6; op2:f5; dest:x6; op1val:0x80000000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f5; op2:f6; dest:x5; op1val:0x80000000; op2val:0x1;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f4; op2:f3; dest:x4; op1val:0x80000000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f3; op2:f4; dest:x3; op1val:0x80000000; op2val:0x2;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f2; op2:f1; dest:x2; op1val:0x80000000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f1; op2:f2; dest:x1; op1val:0x80000000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f0; op2:f31; dest:x31; op1val:0x80000000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f31; op2:f0; dest:x31; op1val:0x80000000; op2val:0x800000;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x0; op1val:0x80000000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-test_dataset_1:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 16*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b19-01.S
deleted file mode 100644
index ae6017762..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fltq_b19-01.S
+++ /dev/null
@@ -1,368 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:17:01 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fltq.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fltq.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fltq_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 == rs2, rs1==f31, rs2==f31, rd==x31,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f31; op2:f31; dest:x31; op1val:0x7f378efe; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 != rs2, rs1==f30, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f30; op2:f29; dest:x30; op1val:0x7f378efe; op2val:0x7f206a70;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x30, f30, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f29, rs2==f30, rd==x29,fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f29; op2:f30; dest:x29; op1val:0x7f206a70; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x29, f29, f30, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f28; op2:f27; dest:x28; op1val:0x7f378efe; op2val:0x7ee8aebb;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f27; op2:f28; dest:x27; op1val:0x7ee8aebb; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f26; op2:f25; dest:x26; op1val:0x7f378efe; op2val:0x7ea5608b;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f25; op2:f26; dest:x25; op1val:0x7ea5608b; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f24; op2:f23; dest:x24; op1val:0x7f378efe; op2val:0x7f3648af;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f23; op2:f24; dest:x23; op1val:0x7f3648af; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f22; op2:f21; dest:x22; op1val:0x7f378efe; op2val:0xfd204621;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f21; op2:f22; dest:x21; op1val:0x7d92d8cb; op2val:0xfec857aa;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfb and fm2 == 0x12d8cb and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f20; op2:f19; dest:x20; op1val:0xfec857aa; op2val:0x7d92d8cb;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f19; op2:f20; dest:x19; op1val:0x7d92d8cb; op2val:0xfd204621;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfb and fm2 == 0x12d8cb and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f18; op2:f17; dest:x18; op1val:0x7f378efe; op2val:0x7d92d8cb;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f17; op2:f18; dest:x17; op1val:0x7f378efe; op2val:0xfe4ac669;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f16; op2:f15; dest:x16; op1val:0x7d92d8cb; op2val:0xff7fffff;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x12d8cb and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f15; op2:f16; dest:x15; op1val:0xff7fffff; op2val:0x7d92d8cb;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f14; op2:f13; dest:x14; op1val:0x7d92d8cb; op2val:0xfe4ac669;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f13; op2:f14; dest:x13; op1val:0x7f378efe; op2val:0xfe96fcf5;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f12; op2:f11; dest:x12; op1val:0xfe96fcf5; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f11; op2:f12; dest:x11; op1val:0x7f378efe; op2val:0xfee8e23e;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f10; op2:f9; dest:x10; op1val:0xfee8e23e; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f9; op2:f10; dest:x9; op1val:0x7f378efe; op2val:0xfeaf0937;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f8; op2:f7; dest:x8; op1val:0xfeaf0937; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f7; op2:f8; dest:x7; op1val:0x7f378efe; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a825 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f6; op2:f5; dest:x6; op1val:0x2a825; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a825 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f5; op2:f6; dest:x5; op1val:0x7f7a0dff; op2val:0x2a825;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a825 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f4; op2:f3; dest:x4; op1val:0x2a825; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a825 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f3; op2:f4; dest:x3; op1val:0x7f378efe; op2val:0x2a825;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f2; op2:f1; dest:x2; op1val:0x7f378efe; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f1; op2:f2; dest:x1; op1val:0x1a917b; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f0; op2:f31; dest:x31; op1val:0x7f7fffff; op2val:0x1a917b;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f31; op2:f0; dest:x31; op1val:0x1a917b; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x0; op1val:0x7f378efe; op2val:0x1a917b;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-test_dataset_1:
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(2138705407,32,FLEN)
-NAN_BOXED(2138705407,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 16*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b1-01.S
deleted file mode 100644
index d5372876b..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b1-01.S
+++ /dev/null
@@ -1,5889 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:07:59 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmaxm.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmaxm.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fmaxm.d_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmaxm.d_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f30, rs2==f29, rd==f31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:0*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rd != rs2, rs1==f29, rs2==f31, rd==f29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f29; op2:f31; dest:f29; op1val:0x0; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:2*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f29, f29, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 == rs2 == rd, rs1==f28, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f28; op2:f28; dest:f28; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:4*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f28, f28, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs2 == rd != rs1, rs1==f31, rs2==f30, rd==f30,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f31; op2:f30; dest:f30; op1val:0x0; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:6*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f30, f31, f30, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f26; op2:f26; dest:f27; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:8*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f27, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f27; op2:f25; dest:f26; op1val:0x0; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:10*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f26, f27, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f24; op2:f27; dest:f25; op1val:0x0; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f25, f24, f27, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f25; op2:f23; dest:f24; op1val:0x0; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:14*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f24, f25, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f22; op2:f24; dest:f23; op1val:0x0; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:16*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f23, f22, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f23; op2:f21; dest:f22; op1val:0x0; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:18*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f22, f23, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:20*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f21; op2:f19; dest:f20; op1val:0x0; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:22*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f20, f21, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f18; op2:f20; dest:f19; op1val:0x0; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:24*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f19; op2:f17; dest:f18; op1val:0x0; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f18, f19, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f16; op2:f18; dest:f17; op1val:0x0; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:28*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f17, f16, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f17; op2:f15; dest:f16; op1val:0x0; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:30*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f16, f17, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:32*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f15; op2:f13; dest:f14; op1val:0x0; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:34*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f14, f15, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f12; op2:f14; dest:f13; op1val:0x0; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:36*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f13; op2:f11; dest:f12; op1val:0x0; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:38*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f12, f13, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f10; op2:f12; dest:f11; op1val:0x0; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:40*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f11, f10, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f11; op2:f9; dest:f10; op1val:0x0; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:42*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f10, f11, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:44*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f9; op2:f7; dest:f8; op1val:0x0; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:46*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f8, f9, f7, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f6; op2:f8; dest:f7; op1val:0x8000000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:48*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f7, rs2==f5, rd==f6,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f7; op2:f5; dest:f6; op1val:0x8000000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:50*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f6, f7, f5, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f4; op2:f6; dest:f5; op1val:0x8000000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:52*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f5, f4, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f5, rs2==f3, rd==f4,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f5; op2:f3; dest:f4; op1val:0x8000000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:54*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f4, f5, f3, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f2; op2:f4; dest:f3; op1val:0x8000000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:56*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f3, rs2==f1, rd==f2,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f3; op2:f1; dest:f2; op1val:0x8000000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:58*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f2, f3, f1, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f0; op2:f2; dest:f1; op1val:0x8000000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:60*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f1,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f1; op2:f30; dest:f31; op1val:0x8000000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:62*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f1, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f0; dest:f31; op1val:0x8000000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:64*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f0, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rd==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f31; op2:f30; dest:f0; op1val:0x8000000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:66*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:68*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:70*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:72*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:74*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:76*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:78*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:80*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:82*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:84*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:86*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:88*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:90*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:92*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:94*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x0;
-   valaddr_reg:x3; val_offset:96*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:98*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x1;
-   valaddr_reg:x3; val_offset:100*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:102*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x2;
-   valaddr_reg:x3; val_offset:104*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:106*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:108*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:110*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:112*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:114*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:116*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:118*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:120*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:122*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:124*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:126*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:128*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:130*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:132*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:134*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:136*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:138*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:140*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:142*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:144*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:146*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:148*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:150*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:152*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:154*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:156*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:158*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:160*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:162*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:164*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:166*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:168*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:170*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:172*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:174*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:176*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:178*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:180*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:182*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:184*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:186*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:188*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:190*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x0;
-   valaddr_reg:x3; val_offset:192*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:194*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x1;
-   valaddr_reg:x3; val_offset:196*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:198*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x2;
-   valaddr_reg:x3; val_offset:200*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:202*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:204*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:206*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:208*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:210*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:212*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:214*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:216*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:218*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:220*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:222*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:224*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:226*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:228*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:230*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:232*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:234*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:236*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:238*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x0;
-   valaddr_reg:x3; val_offset:240*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:242*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x1;
-   valaddr_reg:x3; val_offset:244*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:246*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x2;
-   valaddr_reg:x3; val_offset:248*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:250*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:252*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:254*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:256*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:258*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:260*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:262*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:264*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:266*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:268*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:270*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:272*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:274*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:276*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:278*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:280*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:282*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:284*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:286*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:288*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:290*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:292*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:294*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:296*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:298*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:300*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:302*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:304*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:306*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:308*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:310*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:312*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:314*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:316*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:318*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:320*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:322*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:324*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:326*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:328*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:330*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:332*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:334*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:336*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:338*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:340*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:342*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:344*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:346*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:348*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:350*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:352*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:354*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:356*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:358*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:360*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:362*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:364*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:366*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:368*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:370*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:372*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:374*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:376*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:378*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:380*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:382*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:384*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:386*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:388*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:390*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:392*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:394*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:396*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:398*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:400*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:402*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:404*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:406*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:408*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:410*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:412*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:414*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:416*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:418*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:420*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:422*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:424*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:426*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:428*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:430*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:432*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:434*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:436*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:438*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:440*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:442*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:444*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:446*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:448*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:450*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:452*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:454*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:456*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:458*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:460*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:462*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:464*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:466*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:468*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:470*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:472*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:474*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:476*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:478*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x0;
-   valaddr_reg:x3; val_offset:480*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:482*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x1;
-   valaddr_reg:x3; val_offset:484*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:486*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x2;
-   valaddr_reg:x3; val_offset:488*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:490*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:492*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:494*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:496*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:498*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:500*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:502*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:504*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:506*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:508*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:510*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:512*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:514*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:516*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:518*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:520*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:522*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:524*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:526*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x0;
-   valaddr_reg:x3; val_offset:528*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:530*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x1;
-   valaddr_reg:x3; val_offset:532*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:534*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x2;
-   valaddr_reg:x3; val_offset:536*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:538*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:540*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:542*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:544*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:546*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:548*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:550*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:552*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:554*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:556*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:558*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:560*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:562*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:564*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:566*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:568*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:570*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:572*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:574*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:576*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:578*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:580*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:582*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:584*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:586*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:588*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:590*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:592*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:594*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:596*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:598*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:600*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:602*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:604*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:606*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:608*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:610*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:612*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:614*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:616*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:618*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:620*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:622*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:624*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:626*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:628*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:630*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:632*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:634*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:636*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:638*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:640*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:642*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:644*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:646*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:648*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:650*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:652*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:654*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:656*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:658*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:660*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:662*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:664*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:666*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:668*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:670*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:672*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:674*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:676*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:678*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:680*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:682*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:684*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:686*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:688*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:690*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:692*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:694*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:696*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:698*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:700*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:702*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:704*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:706*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:708*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:710*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:712*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:714*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:716*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:718*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:720*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:722*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:724*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:726*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:728*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:730*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:732*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:734*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:736*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:738*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:740*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:742*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:744*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:746*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:748*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:750*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:752*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:754*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:756*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:758*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:760*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:762*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:764*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:766*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:768*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:770*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:772*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:774*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:776*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:778*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:780*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:782*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:784*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:786*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:788*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:790*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:792*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:794*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:796*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:798*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:800*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:802*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:804*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:806*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:808*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:810*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:812*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:814*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:816*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:818*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:820*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:822*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:824*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:826*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:828*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:830*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:832*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:834*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:836*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:838*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:840*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:842*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:844*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:846*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:848*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:850*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:852*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:854*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:856*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:858*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:860*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:862*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:864*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:866*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:868*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:870*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:872*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:874*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:876*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:878*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:880*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:882*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:884*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:886*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:888*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:890*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:892*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:894*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:896*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:898*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:900*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:902*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:904*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:906*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:908*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:910*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:912*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:914*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:916*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:918*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:920*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:922*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:924*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:926*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:928*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:930*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:932*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:934*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:936*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:938*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:940*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:942*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:944*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:946*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:948*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:950*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:952*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:954*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:956*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:958*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:960*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:962*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:964*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:966*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:968*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:970*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:972*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:974*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:976*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:978*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:980*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:982*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:984*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:986*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:988*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:990*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:992*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:994*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:996*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:998*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1000*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1002*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1004*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1006*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:1008*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:1010*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:1012*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:1014*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:1016*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:1018*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:1020*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:1022*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:1024*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:1026*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:1028*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:1030*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:1032*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:1034*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1036*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1038*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:1040*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:1042*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:1044*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:1046*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1048*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1050*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1052*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1054*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1056*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:1058*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1060*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:1062*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1064*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:1066*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:1068*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:1070*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:1072*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:1074*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:1076*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:1078*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:1080*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:1082*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1084*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1086*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:1088*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:1090*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:1092*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:1094*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1096*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1098*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1100*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1102*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1104*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:1106*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1108*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:1110*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1112*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:1114*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:1116*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:1118*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:1120*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:1122*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:1124*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:1126*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:1128*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:1130*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1132*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1134*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:1136*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:1138*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:1140*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:1142*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1144*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1146*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1148*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1150*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x1;
-   valaddr_reg:x3; val_offset:1152*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x2;
-   valaddr_reg:x3; val_offset:1154*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
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-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
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-NAN_BOXED(4503599627370498,64,FLEN)
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-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
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-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
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-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
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-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
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-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
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-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
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-NAN_BOXED(18442240474082181121,64,FLEN)
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-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
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-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
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-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
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-NAN_BOXED(4607182418800017408,64,FLEN)
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-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
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-NAN_BOXED(9218868437227405311,64,FLEN)
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-NAN_BOXED(18442240474082181119,64,FLEN)
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-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
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-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
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-NAN_BOXED(1,64,FLEN)
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-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
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-NAN_BOXED(9227875636482146304,64,FLEN)
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-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 132*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b19-01.S
deleted file mode 100644
index 8576f0bdf..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm.d_b19-01.S
+++ /dev/null
@@ -1,11279 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:07:59 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmaxm.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmaxm.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fmaxm.d_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmaxm.d_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f30, rs2==f29, rd==f31,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:0*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rd != rs2, rs1==f29, rs2==f31, rd==f29,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f29; op2:f31; dest:f29; op1val:0x7fc132d8f91b7583; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:2*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f29, f29, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 == rs2 == rd, rs1==f28, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f28; op2:f28; dest:f28; op1val:0x7fdfb5355e167379; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:4*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f28, f28, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs2 == rd != rs1, rs1==f31, rs2==f30, rd==f30,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f31; op2:f30; dest:f30; op1val:0x7fc132d8f91b7583; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:6*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f30, f31, f30, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f26; op2:f26; dest:f27; op1val:0x7fb8072e8f9c858f; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:8*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f27, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f27; op2:f25; dest:f26; op1val:0x7fc132d8f91b7583; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:10*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f26, f27, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x383adc274749d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f24; op2:f27; dest:f25; op1val:0x7ff0000000000000; op2val:0x7fb383adc274749d;
-   valaddr_reg:x3; val_offset:12*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f25, f24, f27, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f25; op2:f23; dest:f24; op1val:0x7fb383adc274749d; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:14*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f24, f25, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f22; op2:f24; dest:f23; op1val:0x7ff0000000000000; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:16*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f23, f22, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f23; op2:f21; dest:f22; op1val:0x7fc132d8f91b7583; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:18*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f22, f23, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f20; op2:f22; dest:f21; op1val:0x7fc132d8f91b7583; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:20*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f21; op2:f19; dest:f20; op1val:0x7fcd481499755d4b; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:22*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f20, f21, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f18; op2:f20; dest:f19; op1val:0x7fc132d8f91b7583; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:24*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f19, rs2==f17, rd==f18,fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f19; op2:f17; dest:f18; op1val:0xffc3874a9329ec20; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:26*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f18, f19, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f16; op2:f18; dest:f17; op1val:0x7fc132d8f91b7583; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:28*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f17, f16, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f17, rs2==f15, rd==f16,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f17; op2:f15; dest:f16; op1val:0xffe19dc4ea1c6bbe; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:30*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f16, f17, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f14; op2:f16; dest:f15; op1val:0x7fc132d8f91b7583; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:32*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x8dfd26d2431d6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f15; op2:f13; dest:f14; op1val:0x7ff0000000000000; op2val:0xffb8dfd26d2431d6;
-   valaddr_reg:x3; val_offset:34*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f14, f15, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f12; op2:f14; dest:f13; op1val:0xffb8dfd26d2431d6; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:36*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f13; op2:f11; dest:f12; op1val:0x7ff0000000000000; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:38*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f12, f13, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f10; op2:f12; dest:f11; op1val:0x7fc132d8f91b7583; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:40*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f11, f10, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x98bcc3a92c611 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f11; op2:f9; dest:f10; op1val:0x7ff0000000000000; op2val:0xffb98bcc3a92c611;
-   valaddr_reg:x3; val_offset:42*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f10, f11, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f8; op2:f10; dest:f9; op1val:0xffb98bcc3a92c611; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:44*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f9; op2:f7; dest:f8; op1val:0x7ff0000000000000; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:46*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f8, f9, f7, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f6; op2:f8; dest:f7; op1val:0x7fc132d8f91b7583; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:48*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f7, rs2==f5, rd==f6,fs1 == 0 and fe1 == 0x7f8 and fm1 == 0xb848e5b5f226b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x1836cb3e931a8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f7; op2:f5; dest:f6; op1val:0x7f8b848e5b5f226b; op2val:0xffe1836cb3e931a8;
-   valaddr_reg:x3; val_offset:50*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f6, f7, f5, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0xb848e5b5f226b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f4; op2:f6; dest:f5; op1val:0xffe1836cb3e931a8; op2val:0x7f8b848e5b5f226b;
-   valaddr_reg:x3; val_offset:52*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f5, f4, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f5, rs2==f3, rd==f4,fs1 == 0 and fe1 == 0x7f8 and fm1 == 0xb848e5b5f226b and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f5; op2:f3; dest:f4; op1val:0x7f8b848e5b5f226b; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:54*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f4, f5, f3, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0xb848e5b5f226b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f2; op2:f4; dest:f3; op1val:0x7fc132d8f91b7583; op2val:0x7f8b848e5b5f226b;
-   valaddr_reg:x3; val_offset:56*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f3, rs2==f1, rd==f2,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f3; op2:f1; dest:f2; op1val:0x7fc132d8f91b7583; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:58*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f2, f3, f1, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x833777722304f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f0; op2:f2; dest:f1; op1val:0x115e76ceed9d88; op2val:0x7fb833777722304f;
-   valaddr_reg:x3; val_offset:60*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f1,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f1; op2:f30; dest:f31; op1val:0x7fb833777722304f; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:62*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f1, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f0,fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f0; dest:f31; op1val:0x115e76ceed9d88; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:64*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f0, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rd==f0,fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f31; op2:f30; dest:f0; op1val:0x7fc132d8f91b7583; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:66*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:68*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x4a57d3f9bbb84 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0x7fb4a57d3f9bbb84;
-   valaddr_reg:x3; val_offset:70*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:72*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:74*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:76*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xa7b6d804df453 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0x7fba7b6d804df453;
-   valaddr_reg:x3; val_offset:78*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:80*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:82*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:84*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1bca57b17c2f4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x1a406f11e5bc4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1bca57b17c2f4; op2val:0x7fe1a406f11e5bc4;
-   valaddr_reg:x3; val_offset:86*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1bca57b17c2f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x1bca57b17c2f4;
-   valaddr_reg:x3; val_offset:88*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1bca57b17c2f4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1bca57b17c2f4; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:90*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1bca57b17c2f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x1bca57b17c2f4;
-   valaddr_reg:x3; val_offset:92*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:94*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xc900ea9c600e8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0x7fbc900ea9c600e8;
-   valaddr_reg:x3; val_offset:96*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:98*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:100*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:102*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x79a9d1edd4c29 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0xffb79a9d1edd4c29;
-   valaddr_reg:x3; val_offset:104*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:106*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:108*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:110*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1bca57b17c2f4 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0bc8069a0dddf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1bca57b17c2f4; op2val:0xffd0bc8069a0dddf;
-   valaddr_reg:x3; val_offset:112*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1bca57b17c2f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x1bca57b17c2f4;
-   valaddr_reg:x3; val_offset:114*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1bca57b17c2f4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1bca57b17c2f4; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:116*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:118*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x1f930d5b2a8f5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0xffb1f930d5b2a8f5;
-   valaddr_reg:x3; val_offset:120*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:122*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:124*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:126*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1bca57b17c2f4 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x60eeb556ce9ce and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1bca57b17c2f4; op2val:0xffd60eeb556ce9ce;
-   valaddr_reg:x3; val_offset:128*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1bca57b17c2f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x1bca57b17c2f4;
-   valaddr_reg:x3; val_offset:130*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1bca57b17c2f4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1bca57b17c2f4; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:132*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:134*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xeb781eb40c69d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0xffbeb781eb40c69d;
-   valaddr_reg:x3; val_offset:136*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x001 and fm2 == 0x15e76ceed9d88 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x115e76ceed9d88;
-   valaddr_reg:x3; val_offset:138*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x15e76ceed9d88 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x115e76ceed9d88; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:140*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x0;
-   valaddr_reg:x3; val_offset:142*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 0 and fe1 == 0x400 and fm1 == 0x352db02b86485 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x400352db02b86485; op2val:0x0;
-   valaddr_reg:x3; val_offset:144*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x352db02b86485 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x400352db02b86485;
-   valaddr_reg:x3; val_offset:146*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0x132d8f91b7583 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x352db02b86485 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fc132d8f91b7583; op2val:0x400352db02b86485;
-   valaddr_reg:x3; val_offset:148*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:150*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:152*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:154*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:156*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:158*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:160*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:162*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:164*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:166*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:168*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:170*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:172*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:174*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:176*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0x95dc44b45292d and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x1836cb3e931a8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fa95dc44b45292d; op2val:0xffe1836cb3e931a8;
-   valaddr_reg:x3; val_offset:178*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0x95dc44b45292d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0x7fa95dc44b45292d;
-   valaddr_reg:x3; val_offset:180*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0x95dc44b45292d and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fa95dc44b45292d; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:182*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0x95dc44b45292d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x7fa95dc44b45292d;
-   valaddr_reg:x3; val_offset:184*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:186*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x833777722304f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0x7fb833777722304f;
-   valaddr_reg:x3; val_offset:188*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:190*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:192*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:194*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:196*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x4a57d3f9bbb84 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0x7fb4a57d3f9bbb84;
-   valaddr_reg:x3; val_offset:198*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:200*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:202*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:204*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xa7b6d804df453 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0x7fba7b6d804df453;
-   valaddr_reg:x3; val_offset:206*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:208*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:210*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:212*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6678633536e0f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x1a406f11e5bc4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6678633536e0f; op2val:0x7fe1a406f11e5bc4;
-   valaddr_reg:x3; val_offset:214*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6678633536e0f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x6678633536e0f;
-   valaddr_reg:x3; val_offset:216*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6678633536e0f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6678633536e0f; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:218*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6678633536e0f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x6678633536e0f;
-   valaddr_reg:x3; val_offset:220*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:222*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xc900ea9c600e8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0x7fbc900ea9c600e8;
-   valaddr_reg:x3; val_offset:224*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:226*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:228*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:230*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x79a9d1edd4c29 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0xffb79a9d1edd4c29;
-   valaddr_reg:x3; val_offset:232*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:234*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:236*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:238*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6678633536e0f and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0bc8069a0dddf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6678633536e0f; op2val:0xffd0bc8069a0dddf;
-   valaddr_reg:x3; val_offset:240*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6678633536e0f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x6678633536e0f;
-   valaddr_reg:x3; val_offset:242*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6678633536e0f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6678633536e0f; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:244*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:246*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x1f930d5b2a8f5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0xffb1f930d5b2a8f5;
-   valaddr_reg:x3; val_offset:248*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:250*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:252*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:254*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6678633536e0f and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x60eeb556ce9ce and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6678633536e0f; op2val:0xffd60eeb556ce9ce;
-   valaddr_reg:x3; val_offset:256*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6678633536e0f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x6678633536e0f;
-   valaddr_reg:x3; val_offset:258*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6678633536e0f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6678633536e0f; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:260*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:262*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xeb781eb40c69d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0xffbeb781eb40c69d;
-   valaddr_reg:x3; val_offset:264*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x003 and fm2 == 0x002cf80509326 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x3002cf80509326;
-   valaddr_reg:x3; val_offset:266*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x002cf80509326 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3002cf80509326; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:268*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x0;
-   valaddr_reg:x3; val_offset:270*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 0 and fe1 == 0x402 and fm1 == 0x1d013feac5b5a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x4021d013feac5b5a; op2val:0x0;
-   valaddr_reg:x3; val_offset:272*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x1d013feac5b5a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x4021d013feac5b5a;
-   valaddr_reg:x3; val_offset:274*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x1d013feac5b5a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x4021d013feac5b5a;
-   valaddr_reg:x3; val_offset:276*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:278*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:280*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe08fa3383a6f3 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x383adc274749d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee08fa3383a6f3; op2val:0x7fb383adc274749d;
-   valaddr_reg:x3; val_offset:282*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe08fa3383a6f3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0x7fee08fa3383a6f3;
-   valaddr_reg:x3; val_offset:284*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe08fa3383a6f3 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee08fa3383a6f3; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:286*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe08fa3383a6f3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7fee08fa3383a6f3;
-   valaddr_reg:x3; val_offset:288*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:290*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:292*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:294*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:296*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:298*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:300*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:302*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe08fa3383a6f3 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x8dfd26d2431d6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee08fa3383a6f3; op2val:0xffb8dfd26d2431d6;
-   valaddr_reg:x3; val_offset:304*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe08fa3383a6f3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0x7fee08fa3383a6f3;
-   valaddr_reg:x3; val_offset:306*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe08fa3383a6f3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee08fa3383a6f3; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:308*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:310*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe08fa3383a6f3 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x98bcc3a92c611 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee08fa3383a6f3; op2val:0xffb98bcc3a92c611;
-   valaddr_reg:x3; val_offset:312*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe08fa3383a6f3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0x7fee08fa3383a6f3;
-   valaddr_reg:x3; val_offset:314*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe08fa3383a6f3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee08fa3383a6f3; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:316*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:318*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x338f20c7d37a6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x1836cb3e931a8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f8338f20c7d37a6; op2val:0xffe1836cb3e931a8;
-   valaddr_reg:x3; val_offset:320*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x338f20c7d37a6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0x7f8338f20c7d37a6;
-   valaddr_reg:x3; val_offset:322*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x338f20c7d37a6 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f8338f20c7d37a6; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:324*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x338f20c7d37a6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7f8338f20c7d37a6;
-   valaddr_reg:x3; val_offset:326*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:328*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x833777722304f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0x7fb833777722304f;
-   valaddr_reg:x3; val_offset:330*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:332*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:334*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:336*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:338*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x4a57d3f9bbb84 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0x7fb4a57d3f9bbb84;
-   valaddr_reg:x3; val_offset:340*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:342*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:344*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:346*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xa7b6d804df453 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0x7fba7b6d804df453;
-   valaddr_reg:x3; val_offset:348*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:350*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:352*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:354*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1369b1ce3b6b7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x1a406f11e5bc4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1369b1ce3b6b7; op2val:0x7fe1a406f11e5bc4;
-   valaddr_reg:x3; val_offset:356*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1369b1ce3b6b7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x1369b1ce3b6b7;
-   valaddr_reg:x3; val_offset:358*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1369b1ce3b6b7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1369b1ce3b6b7; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:360*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1369b1ce3b6b7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x1369b1ce3b6b7;
-   valaddr_reg:x3; val_offset:362*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:364*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xc900ea9c600e8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0x7fbc900ea9c600e8;
-   valaddr_reg:x3; val_offset:366*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:368*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:370*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:372*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x79a9d1edd4c29 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0xffb79a9d1edd4c29;
-   valaddr_reg:x3; val_offset:374*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:376*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:378*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:380*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1369b1ce3b6b7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0bc8069a0dddf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1369b1ce3b6b7; op2val:0xffd0bc8069a0dddf;
-   valaddr_reg:x3; val_offset:382*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1369b1ce3b6b7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x1369b1ce3b6b7;
-   valaddr_reg:x3; val_offset:384*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1369b1ce3b6b7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1369b1ce3b6b7; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:386*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:388*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x1f930d5b2a8f5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0xffb1f930d5b2a8f5;
-   valaddr_reg:x3; val_offset:390*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:392*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:394*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:396*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1369b1ce3b6b7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x60eeb556ce9ce and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1369b1ce3b6b7; op2val:0xffd60eeb556ce9ce;
-   valaddr_reg:x3; val_offset:398*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1369b1ce3b6b7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x1369b1ce3b6b7;
-   valaddr_reg:x3; val_offset:400*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1369b1ce3b6b7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1369b1ce3b6b7; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:402*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:404*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xeb781eb40c69d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0xffbeb781eb40c69d;
-   valaddr_reg:x3; val_offset:406*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc220f20e52329 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0xc220f20e52329;
-   valaddr_reg:x3; val_offset:408*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc220f20e52329 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc220f20e52329; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:410*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x0;
-   valaddr_reg:x3; val_offset:412*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xaff35fd55192c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ffaff35fd55192c; op2val:0x0;
-   valaddr_reg:x3; val_offset:414*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xaff35fd55192c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ffaff35fd55192c;
-   valaddr_reg:x3; val_offset:416*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xaff35fd55192c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x3ffaff35fd55192c;
-   valaddr_reg:x3; val_offset:418*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:420*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:422*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x383adc274749d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7fb383adc274749d;
-   valaddr_reg:x3; val_offset:424*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:426*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:428*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:430*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:432*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:434*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:436*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:438*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:440*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:442*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x383adc274749d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7fb383adc274749d;
-   valaddr_reg:x3; val_offset:444*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:446*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:448*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x383adc274749d and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb383adc274749d; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:450*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:452*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:454*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:456*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:458*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:460*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xf391603ed8761 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f7f391603ed8761; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:462*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xf391603ed8761 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7f7f391603ed8761;
-   valaddr_reg:x3; val_offset:464*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xf391603ed8761 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f7f391603ed8761; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:466*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xf391603ed8761 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7f7f391603ed8761;
-   valaddr_reg:x3; val_offset:468*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:470*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe405554eabc62 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0x7fee405554eabc62;
-   valaddr_reg:x3; val_offset:472*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe405554eabc62 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9da958592a6de and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee405554eabc62; op2val:0x9da958592a6de;
-   valaddr_reg:x3; val_offset:474*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:476*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9da958592a6de and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x9da958592a6de;
-   valaddr_reg:x3; val_offset:478*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:480*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x9cedc8f82aa65 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0x7fe9cedc8f82aa65;
-   valaddr_reg:x3; val_offset:482*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x9cedc8f82aa65 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9da958592a6de and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe9cedc8f82aa65; op2val:0x9da958592a6de;
-   valaddr_reg:x3; val_offset:484*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:486*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:488*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:490*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9da958592a6de and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x9da958592a6de;
-   valaddr_reg:x3; val_offset:492*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:494*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:496*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fc4226f510b0 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfc4226f510b0; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:498*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0fc4226f510b0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfc4226f510b0;
-   valaddr_reg:x3; val_offset:500*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fc4226f510b0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfc4226f510b0; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:502*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0fc4226f510b0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xfc4226f510b0;
-   valaddr_reg:x3; val_offset:504*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:506*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:508*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:510*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd814466949f33 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0xffed814466949f33;
-   valaddr_reg:x3; val_offset:512*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd814466949f33 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9da958592a6de and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed814466949f33; op2val:0x9da958592a6de;
-   valaddr_reg:x3; val_offset:514*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:516*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:518*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fc4226f510b0 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfc4226f510b0; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:520*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0fc4226f510b0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfc4226f510b0;
-   valaddr_reg:x3; val_offset:522*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fc4226f510b0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfc4226f510b0; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:524*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:526*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x6777d0b1f5332 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0xffe6777d0b1f5332;
-   valaddr_reg:x3; val_offset:528*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x6777d0b1f5332 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9da958592a6de and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe6777d0b1f5332; op2val:0x9da958592a6de;
-   valaddr_reg:x3; val_offset:530*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:532*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:534*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fc4226f510b0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfc4226f510b0; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:536*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:538*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:540*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9da958592a6de and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x9da958592a6de;
-   valaddr_reg:x3; val_offset:542*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9da958592a6de and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9da958592a6de; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:544*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x0;
-   valaddr_reg:x3; val_offset:546*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x5ecef9517d94f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff5ecef9517d94f; op2val:0x0;
-   valaddr_reg:x3; val_offset:548*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x5ecef9517d94f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ff5ecef9517d94f;
-   valaddr_reg:x3; val_offset:550*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x86499331191c4 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x5ecef9517d94f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe86499331191c4; op2val:0x3ff5ecef9517d94f;
-   valaddr_reg:x3; val_offset:552*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:554*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:556*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:558*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:560*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:562*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:564*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:566*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:568*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:570*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:572*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 0 and fe1 == 0x7f9 and fm1 == 0x76cdd4791176f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x1836cb3e931a8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f976cdd4791176f; op2val:0xffe1836cb3e931a8;
-   valaddr_reg:x3; val_offset:574*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7f9 and fm2 == 0x76cdd4791176f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0x7f976cdd4791176f;
-   valaddr_reg:x3; val_offset:576*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0x7f9 and fm1 == 0x76cdd4791176f and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f976cdd4791176f; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:578*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x7f9 and fm2 == 0x76cdd4791176f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x7f976cdd4791176f;
-   valaddr_reg:x3; val_offset:580*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:582*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x833777722304f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0x7fb833777722304f;
-   valaddr_reg:x3; val_offset:584*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:586*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:588*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:590*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:592*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x4a57d3f9bbb84 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0x7fb4a57d3f9bbb84;
-   valaddr_reg:x3; val_offset:594*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:596*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:598*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:600*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xa7b6d804df453 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0x7fba7b6d804df453;
-   valaddr_reg:x3; val_offset:602*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:604*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:606*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:608*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x2f508b3cddb2a and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x1a406f11e5bc4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2f508b3cddb2a; op2val:0x7fe1a406f11e5bc4;
-   valaddr_reg:x3; val_offset:610*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x2f508b3cddb2a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x2f508b3cddb2a;
-   valaddr_reg:x3; val_offset:612*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x2f508b3cddb2a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2f508b3cddb2a; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:614*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x2f508b3cddb2a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x2f508b3cddb2a;
-   valaddr_reg:x3; val_offset:616*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:618*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xc900ea9c600e8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0x7fbc900ea9c600e8;
-   valaddr_reg:x3; val_offset:620*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:622*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:624*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:626*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x79a9d1edd4c29 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0xffb79a9d1edd4c29;
-   valaddr_reg:x3; val_offset:628*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:630*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:632*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:634*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x2f508b3cddb2a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0bc8069a0dddf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2f508b3cddb2a; op2val:0xffd0bc8069a0dddf;
-   valaddr_reg:x3; val_offset:636*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x000 and fm2 == 0x2f508b3cddb2a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x2f508b3cddb2a;
-   valaddr_reg:x3; val_offset:638*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x2f508b3cddb2a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2f508b3cddb2a; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:640*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:642*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x1f930d5b2a8f5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0xffb1f930d5b2a8f5;
-   valaddr_reg:x3; val_offset:644*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:646*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:648*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:650*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x2f508b3cddb2a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x60eeb556ce9ce and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2f508b3cddb2a; op2val:0xffd60eeb556ce9ce;
-   valaddr_reg:x3; val_offset:652*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x000 and fm2 == 0x2f508b3cddb2a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x2f508b3cddb2a;
-   valaddr_reg:x3; val_offset:654*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x2f508b3cddb2a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2f508b3cddb2a; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:656*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:658*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xeb781eb40c69d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0xffbeb781eb40c69d;
-   valaddr_reg:x3; val_offset:660*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x001 and fm2 == 0xd9257060a8fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x1d9257060a8fa0;
-   valaddr_reg:x3; val_offset:662*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0xd9257060a8fa0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1d9257060a8fa0; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:664*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x0;
-   valaddr_reg:x3; val_offset:666*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 0 and fe1 == 0x401 and fm1 == 0x0732431031347 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x4010732431031347; op2val:0x0;
-   valaddr_reg:x3; val_offset:668*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x401 and fm2 == 0x0732431031347 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x4010732431031347;
-   valaddr_reg:x3; val_offset:670*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 0 and fe1 == 0x7fc and fm1 == 0xd481499755d4b and fs2 == 0 and fe2 == 0x401 and fm2 == 0x0732431031347 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fcd481499755d4b; op2val:0x4010732431031347;
-   valaddr_reg:x3; val_offset:672*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:674*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:676*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:678*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:680*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:682*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:684*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:686*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x8dfd26d2431d6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffb8dfd26d2431d6;
-   valaddr_reg:x3; val_offset:688*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:690*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:692*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:694*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x98bcc3a92c611 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffb98bcc3a92c611;
-   valaddr_reg:x3; val_offset:696*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:698*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:700*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:702*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0xf3eddb8431366 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x1836cb3e931a8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff8f3eddb8431366; op2val:0xffe1836cb3e931a8;
-   valaddr_reg:x3; val_offset:704*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0xf3eddb8431366 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0xff8f3eddb8431366;
-   valaddr_reg:x3; val_offset:706*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0xf3eddb8431366 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff8f3eddb8431366; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:708*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0xf3eddb8431366 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xff8f3eddb8431366;
-   valaddr_reg:x3; val_offset:710*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:712*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x833777722304f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0x7fb833777722304f;
-   valaddr_reg:x3; val_offset:714*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:716*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:718*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:720*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:722*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x4a57d3f9bbb84 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0x7fb4a57d3f9bbb84;
-   valaddr_reg:x3; val_offset:724*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:726*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:728*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:730*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xa7b6d804df453 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0x7fba7b6d804df453;
-   valaddr_reg:x3; val_offset:732*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:734*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:736*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:738*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1f8e1b3b91d2b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x1a406f11e5bc4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001f8e1b3b91d2b; op2val:0x7fe1a406f11e5bc4;
-   valaddr_reg:x3; val_offset:740*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1f8e1b3b91d2b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x8001f8e1b3b91d2b;
-   valaddr_reg:x3; val_offset:742*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1f8e1b3b91d2b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001f8e1b3b91d2b; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:744*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1f8e1b3b91d2b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x8001f8e1b3b91d2b;
-   valaddr_reg:x3; val_offset:746*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:748*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xc900ea9c600e8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0x7fbc900ea9c600e8;
-   valaddr_reg:x3; val_offset:750*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:752*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:754*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:756*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x79a9d1edd4c29 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0xffb79a9d1edd4c29;
-   valaddr_reg:x3; val_offset:758*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:760*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:762*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:764*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1f8e1b3b91d2b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0bc8069a0dddf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001f8e1b3b91d2b; op2val:0xffd0bc8069a0dddf;
-   valaddr_reg:x3; val_offset:766*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1f8e1b3b91d2b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x8001f8e1b3b91d2b;
-   valaddr_reg:x3; val_offset:768*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1f8e1b3b91d2b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001f8e1b3b91d2b; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:770*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:772*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x1f930d5b2a8f5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0xffb1f930d5b2a8f5;
-   valaddr_reg:x3; val_offset:774*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:776*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:778*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:780*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1f8e1b3b91d2b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x60eeb556ce9ce and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001f8e1b3b91d2b; op2val:0xffd60eeb556ce9ce;
-   valaddr_reg:x3; val_offset:782*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1f8e1b3b91d2b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x8001f8e1b3b91d2b;
-   valaddr_reg:x3; val_offset:784*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1f8e1b3b91d2b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001f8e1b3b91d2b; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:786*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:788*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xeb781eb40c69d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0xffbeb781eb40c69d;
-   valaddr_reg:x3; val_offset:790*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 1 and fe2 == 0x001 and fm2 == 0x3b8d1053b23ab and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x8013b8d1053b23ab;
-   valaddr_reg:x3; val_offset:792*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x3b8d1053b23ab and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8013b8d1053b23ab; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:794*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0x0;
-   valaddr_reg:x3; val_offset:796*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 1 and fe1 == 0x400 and fm1 == 0x5f0feaa8af2a4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc005f0feaa8af2a4; op2val:0x0;
-   valaddr_reg:x3; val_offset:798*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x5f0feaa8af2a4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc005f0feaa8af2a4;
-   valaddr_reg:x3; val_offset:800*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x3874a9329ec20 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x5f0feaa8af2a4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc3874a9329ec20; op2val:0xc005f0feaa8af2a4;
-   valaddr_reg:x3; val_offset:802*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:804*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:806*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:808*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:810*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:812*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:814*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc2fa17693df96 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x1836cb3e931a8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac2fa17693df96; op2val:0xffe1836cb3e931a8;
-   valaddr_reg:x3; val_offset:816*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc2fa17693df96 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0xffac2fa17693df96;
-   valaddr_reg:x3; val_offset:818*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc2fa17693df96 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac2fa17693df96; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:820*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc2fa17693df96 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xffac2fa17693df96;
-   valaddr_reg:x3; val_offset:822*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:824*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x833777722304f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0x7fb833777722304f;
-   valaddr_reg:x3; val_offset:826*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:828*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:830*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:832*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:834*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x4a57d3f9bbb84 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0x7fb4a57d3f9bbb84;
-   valaddr_reg:x3; val_offset:836*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:838*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:840*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:842*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xa7b6d804df453 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0x7fba7b6d804df453;
-   valaddr_reg:x3; val_offset:844*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:846*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:848*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:850*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71dc729cd4c0d and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x1a406f11e5bc4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071dc729cd4c0d; op2val:0x7fe1a406f11e5bc4;
-   valaddr_reg:x3; val_offset:852*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71dc729cd4c0d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x80071dc729cd4c0d;
-   valaddr_reg:x3; val_offset:854*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71dc729cd4c0d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071dc729cd4c0d; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:856*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71dc729cd4c0d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x80071dc729cd4c0d;
-   valaddr_reg:x3; val_offset:858*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:860*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xc900ea9c600e8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0x7fbc900ea9c600e8;
-   valaddr_reg:x3; val_offset:862*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:864*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:866*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:868*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x79a9d1edd4c29 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0xffb79a9d1edd4c29;
-   valaddr_reg:x3; val_offset:870*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:872*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:874*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:876*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71dc729cd4c0d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0bc8069a0dddf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071dc729cd4c0d; op2val:0xffd0bc8069a0dddf;
-   valaddr_reg:x3; val_offset:878*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71dc729cd4c0d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x80071dc729cd4c0d;
-   valaddr_reg:x3; val_offset:880*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71dc729cd4c0d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071dc729cd4c0d; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:882*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:884*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x1f930d5b2a8f5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0xffb1f930d5b2a8f5;
-   valaddr_reg:x3; val_offset:886*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:888*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:890*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:892*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71dc729cd4c0d and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x60eeb556ce9ce and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071dc729cd4c0d; op2val:0xffd60eeb556ce9ce;
-   valaddr_reg:x3; val_offset:894*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71dc729cd4c0d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x80071dc729cd4c0d;
-   valaddr_reg:x3; val_offset:896*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71dc729cd4c0d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071dc729cd4c0d; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:898*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:900*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xeb781eb40c69d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0xffbeb781eb40c69d;
-   valaddr_reg:x3; val_offset:902*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1ca71e8813e1f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x8031ca71e8813e1f;
-   valaddr_reg:x3; val_offset:904*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1ca71e8813e1f and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031ca71e8813e1f; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:906*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0x0;
-   valaddr_reg:x3; val_offset:908*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 1 and fe1 == 0x402 and fm1 == 0x3cafcfae8bc5f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc023cafcfae8bc5f; op2val:0x0;
-   valaddr_reg:x3; val_offset:910*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x3cafcfae8bc5f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc023cafcfae8bc5f;
-   valaddr_reg:x3; val_offset:912*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x19dc4ea1c6bbe and fs2 == 1 and fe2 == 0x402 and fm2 == 0x3cafcfae8bc5f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe19dc4ea1c6bbe; op2val:0xc023cafcfae8bc5f;
-   valaddr_reg:x3; val_offset:914*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:916*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:918*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x8dfd26d2431d6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xffb8dfd26d2431d6;
-   valaddr_reg:x3; val_offset:920*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:922*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:924*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:926*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:928*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:930*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:932*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:934*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:936*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:938*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:940*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x8dfd26d2431d6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb8dfd26d2431d6; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:942*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:944*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:946*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:948*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x3e641f0e9c178 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff83e641f0e9c178; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:950*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x3e641f0e9c178 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xff83e641f0e9c178;
-   valaddr_reg:x3; val_offset:952*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x3e641f0e9c178 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff83e641f0e9c178; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:954*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x3e641f0e9c178 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xff83e641f0e9c178;
-   valaddr_reg:x3; val_offset:956*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:958*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe405554eabc62 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0x7fee405554eabc62;
-   valaddr_reg:x3; val_offset:960*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe405554eabc62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc8f73c41dbdb6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee405554eabc62; op2val:0x800c8f73c41dbdb6;
-   valaddr_reg:x3; val_offset:962*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:964*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc8f73c41dbdb6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x800c8f73c41dbdb6;
-   valaddr_reg:x3; val_offset:966*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:968*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x9cedc8f82aa65 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0x7fe9cedc8f82aa65;
-   valaddr_reg:x3; val_offset:970*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x9cedc8f82aa65 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc8f73c41dbdb6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe9cedc8f82aa65; op2val:0x800c8f73c41dbdb6;
-   valaddr_reg:x3; val_offset:972*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:974*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:976*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:978*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc8f73c41dbdb6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x800c8f73c41dbdb6;
-   valaddr_reg:x3; val_offset:980*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:982*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:984*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1418b939c92f9 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001418b939c92f9; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:986*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1418b939c92f9 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8001418b939c92f9;
-   valaddr_reg:x3; val_offset:988*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1418b939c92f9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001418b939c92f9; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:990*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1418b939c92f9 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x8001418b939c92f9;
-   valaddr_reg:x3; val_offset:992*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:994*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:996*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:998*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd814466949f33 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0xffed814466949f33;
-   valaddr_reg:x3; val_offset:1000*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd814466949f33 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc8f73c41dbdb6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed814466949f33; op2val:0x800c8f73c41dbdb6;
-   valaddr_reg:x3; val_offset:1002*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1004*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1006*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1418b939c92f9 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001418b939c92f9; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1008*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1418b939c92f9 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8001418b939c92f9;
-   valaddr_reg:x3; val_offset:1010*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1418b939c92f9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001418b939c92f9; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1012*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1014*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x6777d0b1f5332 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0xffe6777d0b1f5332;
-   valaddr_reg:x3; val_offset:1016*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x6777d0b1f5332 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc8f73c41dbdb6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe6777d0b1f5332; op2val:0x800c8f73c41dbdb6;
-   valaddr_reg:x3; val_offset:1018*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1020*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1022*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1418b939c92f9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001418b939c92f9; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1024*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1026*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1028*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xc8f73c41dbdb6 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x800c8f73c41dbdb6;
-   valaddr_reg:x3; val_offset:1030*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xc8f73c41dbdb6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800c8f73c41dbdb6; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1032*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0x0;
-   valaddr_reg:x3; val_offset:1034*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xbf29e6067a411 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbffbf29e6067a411; op2val:0x0;
-   valaddr_reg:x3; val_offset:1036*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xbf29e6067a411 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbffbf29e6067a411;
-   valaddr_reg:x3; val_offset:1038*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xf17c7086d3e4c and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xbf29e6067a411 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffef17c7086d3e4c; op2val:0xbffbf29e6067a411;
-   valaddr_reg:x3; val_offset:1040*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1042*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1044*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x98bcc3a92c611 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xffb98bcc3a92c611;
-   valaddr_reg:x3; val_offset:1046*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1048*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1050*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1052*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1054*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1056*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1058*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1060*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1062*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1064*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1066*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x98bcc3a92c611 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb98bcc3a92c611; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1068*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1070*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x46fd69542380e and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff846fd69542380e; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1072*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x46fd69542380e and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xff846fd69542380e;
-   valaddr_reg:x3; val_offset:1074*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x46fd69542380e and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff846fd69542380e; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1076*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x46fd69542380e and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xff846fd69542380e;
-   valaddr_reg:x3; val_offset:1078*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1080*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe405554eabc62 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0x7fee405554eabc62;
-   valaddr_reg:x3; val_offset:1082*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe405554eabc62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xce64abc9e6d7c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee405554eabc62; op2val:0x800ce64abc9e6d7c;
-   valaddr_reg:x3; val_offset:1084*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1086*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xce64abc9e6d7c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x800ce64abc9e6d7c;
-   valaddr_reg:x3; val_offset:1088*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1090*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x9cedc8f82aa65 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0x7fe9cedc8f82aa65;
-   valaddr_reg:x3; val_offset:1092*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x9cedc8f82aa65 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xce64abc9e6d7c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe9cedc8f82aa65; op2val:0x800ce64abc9e6d7c;
-   valaddr_reg:x3; val_offset:1094*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1096*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1098*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1100*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xce64abc9e6d7c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x800ce64abc9e6d7c;
-   valaddr_reg:x3; val_offset:1102*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1104*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1106*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x14a3aac763e26 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80014a3aac763e26; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1108*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x14a3aac763e26 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x80014a3aac763e26;
-   valaddr_reg:x3; val_offset:1110*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x14a3aac763e26 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80014a3aac763e26; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1112*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x14a3aac763e26 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x80014a3aac763e26;
-   valaddr_reg:x3; val_offset:1114*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1116*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1118*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1120*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd814466949f33 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0xffed814466949f33;
-   valaddr_reg:x3; val_offset:1122*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd814466949f33 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xce64abc9e6d7c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed814466949f33; op2val:0x800ce64abc9e6d7c;
-   valaddr_reg:x3; val_offset:1124*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1126*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1128*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x14a3aac763e26 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80014a3aac763e26; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1130*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x14a3aac763e26 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x80014a3aac763e26;
-   valaddr_reg:x3; val_offset:1132*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x14a3aac763e26 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80014a3aac763e26; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1134*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1136*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x6777d0b1f5332 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0xffe6777d0b1f5332;
-   valaddr_reg:x3; val_offset:1138*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x6777d0b1f5332 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xce64abc9e6d7c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe6777d0b1f5332; op2val:0x800ce64abc9e6d7c;
-   valaddr_reg:x3; val_offset:1140*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1142*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1144*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x14a3aac763e26 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80014a3aac763e26; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1146*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1148*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1150*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xce64abc9e6d7c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x800ce64abc9e6d7c;
-   valaddr_reg:x3; val_offset:1152*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xce64abc9e6d7c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800ce64abc9e6d7c; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1154*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-
-inst_578:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0x0;
-   valaddr_reg:x3; val_offset:1156*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1156*FLEN/8, x4, x1, x2)
-
-inst_579:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xcb3d7eda95caf and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbffcb3d7eda95caf; op2val:0x0;
-   valaddr_reg:x3; val_offset:1158*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1158*FLEN/8, x4, x1, x2)
-
-inst_580:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xcb3d7eda95caf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbffcb3d7eda95caf;
-   valaddr_reg:x3; val_offset:1160*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1160*FLEN/8, x4, x1, x2)
-
-inst_581:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfeebf49377796 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xcb3d7eda95caf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefeebf49377796; op2val:0xbffcb3d7eda95caf;
-   valaddr_reg:x3; val_offset:1162*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1162*FLEN/8, x4, x1, x2)
-
-inst_582:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1164*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1164*FLEN/8, x4, x1, x2)
-
-inst_583:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1166*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1166*FLEN/8, x4, x1, x2)
-
-inst_584:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x1836cb3e931a8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xffe1836cb3e931a8;
-   valaddr_reg:x3; val_offset:1168*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1168*FLEN/8, x4, x1, x2)
-
-inst_585:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1170*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1170*FLEN/8, x4, x1, x2)
-
-inst_586:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1172*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1172*FLEN/8, x4, x1, x2)
-
-inst_587:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1174*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1174*FLEN/8, x4, x1, x2)
-
-inst_588:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1176*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1176*FLEN/8, x4, x1, x2)
-
-inst_589:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1178*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1178*FLEN/8, x4, x1, x2)
-
-inst_590:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1180*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1180*FLEN/8, x4, x1, x2)
-
-inst_591:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1182*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1182*FLEN/8, x4, x1, x2)
-
-inst_592:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1184*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1184*FLEN/8, x4, x1, x2)
-
-inst_593:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1186*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1186*FLEN/8, x4, x1, x2)
-
-inst_594:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1188*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1188*FLEN/8, x4, x1, x2)
-
-inst_595:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1190*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1190*FLEN/8, x4, x1, x2)
-
-inst_596:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1192*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1192*FLEN/8, x4, x1, x2)
-
-inst_597:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x1836cb3e931a8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe1836cb3e931a8; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1194*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1194*FLEN/8, x4, x1, x2)
-
-inst_598:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1196*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1196*FLEN/8, x4, x1, x2)
-
-inst_599:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1198*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1198*FLEN/8, x4, x1, x2)
-
-inst_600:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1200*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1200*FLEN/8, x4, x1, x2)
-
-inst_601:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x35c5f9281c03f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0x7f835c5f9281c03f;
-   valaddr_reg:x3; val_offset:1202*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1202*FLEN/8, x4, x1, x2)
-
-inst_602:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x35c5f9281c03f and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f835c5f9281c03f; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1204*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1204*FLEN/8, x4, x1, x2)
-
-inst_603:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1206*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1206*FLEN/8, x4, x1, x2)
-
-inst_604:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1208*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1208*FLEN/8, x4, x1, x2)
-
-inst_605:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1210*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1210*FLEN/8, x4, x1, x2)
-
-inst_606:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x0846432e2fc69 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0x7f80846432e2fc69;
-   valaddr_reg:x3; val_offset:1212*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1212*FLEN/8, x4, x1, x2)
-
-inst_607:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x0846432e2fc69 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f80846432e2fc69; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1214*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1214*FLEN/8, x4, x1, x2)
-
-inst_608:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1216*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1216*FLEN/8, x4, x1, x2)
-
-inst_609:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1218*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1218*FLEN/8, x4, x1, x2)
-
-inst_610:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x52f8acd0b29dc and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0x7f852f8acd0b29dc;
-   valaddr_reg:x3; val_offset:1220*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1220*FLEN/8, x4, x1, x2)
-
-inst_611:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x52f8acd0b29dc and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f852f8acd0b29dc; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1222*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1222*FLEN/8, x4, x1, x2)
-
-inst_612:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1224*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1224*FLEN/8, x4, x1, x2)
-
-inst_613:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1226*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1226*FLEN/8, x4, x1, x2)
-
-inst_614:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71322c1100041 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xc39a4b4fd5fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071322c1100041; op2val:0x7fac39a4b4fd5fa0;
-   valaddr_reg:x3; val_offset:1228*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1228*FLEN/8, x4, x1, x2)
-
-inst_615:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xc39a4b4fd5fa0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71322c1100041 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fac39a4b4fd5fa0; op2val:0x80071322c1100041;
-   valaddr_reg:x3; val_offset:1230*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1230*FLEN/8, x4, x1, x2)
-
-inst_616:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71322c1100041 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071322c1100041; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1232*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1232*FLEN/8, x4, x1, x2)
-
-inst_617:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71322c1100041 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x80071322c1100041;
-   valaddr_reg:x3; val_offset:1234*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1234*FLEN/8, x4, x1, x2)
-
-inst_618:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1236*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1236*FLEN/8, x4, x1, x2)
-
-inst_619:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x6d9a5549e6720 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0x7f86d9a5549e6720;
-   valaddr_reg:x3; val_offset:1238*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1238*FLEN/8, x4, x1, x2)
-
-inst_620:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x6d9a5549e6720 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f86d9a5549e6720; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1240*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1240*FLEN/8, x4, x1, x2)
-
-inst_621:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1242*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1242*FLEN/8, x4, x1, x2)
-
-inst_622:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1244*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1244*FLEN/8, x4, x1, x2)
-
-inst_623:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x2e2174be43ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0xff82e2174be43ced;
-   valaddr_reg:x3; val_offset:1246*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1246*FLEN/8, x4, x1, x2)
-
-inst_624:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x2e2174be43ced and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff82e2174be43ced; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1248*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1248*FLEN/8, x4, x1, x2)
-
-inst_625:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1250*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1250*FLEN/8, x4, x1, x2)
-
-inst_626:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1252*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1252*FLEN/8, x4, x1, x2)
-
-inst_627:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71322c1100041 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0xac733dc349632 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071322c1100041; op2val:0xff9ac733dc349632;
-   valaddr_reg:x3; val_offset:1254*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1254*FLEN/8, x4, x1, x2)
-
-inst_628:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0xac733dc349632 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71322c1100041 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff9ac733dc349632; op2val:0x80071322c1100041;
-   valaddr_reg:x3; val_offset:1256*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1256*FLEN/8, x4, x1, x2)
-
-inst_629:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71322c1100041 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071322c1100041; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1258*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1258*FLEN/8, x4, x1, x2)
-
-inst_630:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1260*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1260*FLEN/8, x4, x1, x2)
-
-inst_631:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0xcc1e7bc510e55 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0xff7cc1e7bc510e55;
-   valaddr_reg:x3; val_offset:1262*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1262*FLEN/8, x4, x1, x2)
-
-inst_632:
-// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0xcc1e7bc510e55 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff7cc1e7bc510e55; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1264*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1264*FLEN/8, x4, x1, x2)
-
-inst_633:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1266*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1266*FLEN/8, x4, x1, x2)
-
-inst_634:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1268*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1268*FLEN/8, x4, x1, x2)
-
-inst_635:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71322c1100041 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x1a5891123ee3f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071322c1100041; op2val:0xffa1a5891123ee3f;
-   valaddr_reg:x3; val_offset:1270*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1270*FLEN/8, x4, x1, x2)
-
-inst_636:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x1a5891123ee3f and fs2 == 1 and fe2 == 0x000 and fm2 == 0x71322c1100041 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffa1a5891123ee3f; op2val:0x80071322c1100041;
-   valaddr_reg:x3; val_offset:1272*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1272*FLEN/8, x4, x1, x2)
-
-inst_637:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x71322c1100041 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80071322c1100041; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1274*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1274*FLEN/8, x4, x1, x2)
-
-inst_638:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1276*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1276*FLEN/8, x4, x1, x2)
-
-inst_639:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x892ce55cd6bb0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0xff8892ce55cd6bb0;
-   valaddr_reg:x3; val_offset:1278*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1278*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_6)
-
-inst_640:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x892ce55cd6bb0 and fs2 == 1 and fe2 == 0x003 and fm2 == 0x1afd6e2a800a2 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff8892ce55cd6bb0; op2val:0x8031afd6e2a800a2;
-   valaddr_reg:x3; val_offset:1280*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1280*FLEN/8, x4, x1, x2)
-
-inst_641:
-// fs1 == 1 and fe1 == 0x003 and fm1 == 0x1afd6e2a800a2 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8031afd6e2a800a2; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1282*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1282*FLEN/8, x4, x1, x2)
-
-inst_642:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0x0;
-   valaddr_reg:x3; val_offset:1284*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1284*FLEN/8, x4, x1, x2)
-
-inst_643:
-// fs1 == 1 and fe1 == 0x402 and fm1 == 0x3ad6377363fb3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc023ad6377363fb3; op2val:0x0;
-   valaddr_reg:x3; val_offset:1286*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1286*FLEN/8, x4, x1, x2)
-
-inst_644:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x3ad6377363fb3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc023ad6377363fb3;
-   valaddr_reg:x3; val_offset:1288*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1288*FLEN/8, x4, x1, x2)
-
-inst_645:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xc057ab9751c40 and fs2 == 1 and fe2 == 0x402 and fm2 == 0x3ad6377363fb3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffac057ab9751c40; op2val:0xc023ad6377363fb3;
-   valaddr_reg:x3; val_offset:1290*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1290*FLEN/8, x4, x1, x2)
-
-inst_646:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1292*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1292*FLEN/8, x4, x1, x2)
-
-inst_647:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1294*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1294*FLEN/8, x4, x1, x2)
-
-inst_648:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x833777722304f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7fb833777722304f;
-   valaddr_reg:x3; val_offset:1296*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1296*FLEN/8, x4, x1, x2)
-
-inst_649:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1298*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1298*FLEN/8, x4, x1, x2)
-
-inst_650:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1300*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1300*FLEN/8, x4, x1, x2)
-
-inst_651:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1302*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1302*FLEN/8, x4, x1, x2)
-
-inst_652:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1304*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1304*FLEN/8, x4, x1, x2)
-
-inst_653:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1306*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1306*FLEN/8, x4, x1, x2)
-
-inst_654:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1308*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1308*FLEN/8, x4, x1, x2)
-
-inst_655:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe405554eabc62 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee405554eabc62; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1310*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1310*FLEN/8, x4, x1, x2)
-
-inst_656:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xe405554eabc62 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7fee405554eabc62;
-   valaddr_reg:x3; val_offset:1312*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1312*FLEN/8, x4, x1, x2)
-
-inst_657:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1314*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1314*FLEN/8, x4, x1, x2)
-
-inst_658:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1316*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1316*FLEN/8, x4, x1, x2)
-
-inst_659:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1318*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1318*FLEN/8, x4, x1, x2)
-
-inst_660:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1320*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1320*FLEN/8, x4, x1, x2)
-
-inst_661:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1322*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1322*FLEN/8, x4, x1, x2)
-
-inst_662:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x833777722304f and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb833777722304f; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1324*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1324*FLEN/8, x4, x1, x2)
-
-inst_663:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1326*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1326*FLEN/8, x4, x1, x2)
-
-inst_664:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe405554eabc62 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee405554eabc62; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1328*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1328*FLEN/8, x4, x1, x2)
-
-inst_665:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1330*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1330*FLEN/8, x4, x1, x2)
-
-inst_666:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xe405554eabc62 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fee405554eabc62; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1332*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1332*FLEN/8, x4, x1, x2)
-
-inst_667:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1334*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1334*FLEN/8, x4, x1, x2)
-
-inst_668:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x35c5f9281c03f and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f835c5f9281c03f; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1336*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1336*FLEN/8, x4, x1, x2)
-
-inst_669:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x35c5f9281c03f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7f835c5f9281c03f;
-   valaddr_reg:x3; val_offset:1338*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1338*FLEN/8, x4, x1, x2)
-
-inst_670:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1340*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1340*FLEN/8, x4, x1, x2)
-
-inst_671:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1342*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1342*FLEN/8, x4, x1, x2)
-
-inst_672:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1344*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1344*FLEN/8, x4, x1, x2)
-
-inst_673:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1346*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1346*FLEN/8, x4, x1, x2)
-
-inst_674:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1348*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1348*FLEN/8, x4, x1, x2)
-
-inst_675:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x138d792d007f4 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x138d792d007f4; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1350*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1350*FLEN/8, x4, x1, x2)
-
-inst_676:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x138d792d007f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x138d792d007f4;
-   valaddr_reg:x3; val_offset:1352*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1352*FLEN/8, x4, x1, x2)
-
-inst_677:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x138d792d007f4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x138d792d007f4; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1354*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1354*FLEN/8, x4, x1, x2)
-
-inst_678:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x138d792d007f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x138d792d007f4;
-   valaddr_reg:x3; val_offset:1356*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1356*FLEN/8, x4, x1, x2)
-
-inst_679:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1358*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1358*FLEN/8, x4, x1, x2)
-
-inst_680:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1360*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1360*FLEN/8, x4, x1, x2)
-
-inst_681:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1362*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1362*FLEN/8, x4, x1, x2)
-
-inst_682:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1364*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1364*FLEN/8, x4, x1, x2)
-
-inst_683:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1366*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1366*FLEN/8, x4, x1, x2)
-
-inst_684:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x138d792d007f4 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x138d792d007f4; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1368*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1368*FLEN/8, x4, x1, x2)
-
-inst_685:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x138d792d007f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x138d792d007f4;
-   valaddr_reg:x3; val_offset:1370*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1370*FLEN/8, x4, x1, x2)
-
-inst_686:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x138d792d007f4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x138d792d007f4; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1372*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1372*FLEN/8, x4, x1, x2)
-
-inst_687:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1374*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1374*FLEN/8, x4, x1, x2)
-
-inst_688:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1376*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1376*FLEN/8, x4, x1, x2)
-
-inst_689:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1378*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1378*FLEN/8, x4, x1, x2)
-
-inst_690:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x138d792d007f4 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x138d792d007f4; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:1380*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1380*FLEN/8, x4, x1, x2)
-
-inst_691:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x138d792d007f4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x138d792d007f4;
-   valaddr_reg:x3; val_offset:1382*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1382*FLEN/8, x4, x1, x2)
-
-inst_692:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x138d792d007f4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x138d792d007f4; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1384*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1384*FLEN/8, x4, x1, x2)
-
-inst_693:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1386*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1386*FLEN/8, x4, x1, x2)
-
-inst_694:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1388*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1388*FLEN/8, x4, x1, x2)
-
-inst_695:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x0;
-   valaddr_reg:x3; val_offset:1390*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1390*FLEN/8, x4, x1, x2)
-
-inst_696:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xb30f7a95c7e30 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ffb30f7a95c7e30; op2val:0x0;
-   valaddr_reg:x3; val_offset:1392*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1392*FLEN/8, x4, x1, x2)
-
-inst_697:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xb30f7a95c7e30 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ffb30f7a95c7e30;
-   valaddr_reg:x3; val_offset:1394*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1394*FLEN/8, x4, x1, x2)
-
-inst_698:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc386bbc204f89 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xb30f7a95c7e30 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc386bbc204f89; op2val:0x3ffb30f7a95c7e30;
-   valaddr_reg:x3; val_offset:1396*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1396*FLEN/8, x4, x1, x2)
-
-inst_699:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1398*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1398*FLEN/8, x4, x1, x2)
-
-inst_700:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1400*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1400*FLEN/8, x4, x1, x2)
-
-inst_701:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x4a57d3f9bbb84 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7fb4a57d3f9bbb84;
-   valaddr_reg:x3; val_offset:1402*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1402*FLEN/8, x4, x1, x2)
-
-inst_702:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1404*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1404*FLEN/8, x4, x1, x2)
-
-inst_703:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1406*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1406*FLEN/8, x4, x1, x2)
-
-inst_704:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1408*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1408*FLEN/8, x4, x1, x2)
-
-inst_705:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1410*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1410*FLEN/8, x4, x1, x2)
-
-inst_706:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1412*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1412*FLEN/8, x4, x1, x2)
-
-inst_707:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1414*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1414*FLEN/8, x4, x1, x2)
-
-inst_708:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x9cedc8f82aa65 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe9cedc8f82aa65; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1416*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1416*FLEN/8, x4, x1, x2)
-
-inst_709:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x9cedc8f82aa65 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7fe9cedc8f82aa65;
-   valaddr_reg:x3; val_offset:1418*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1418*FLEN/8, x4, x1, x2)
-
-inst_710:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1420*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1420*FLEN/8, x4, x1, x2)
-
-inst_711:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1422*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1422*FLEN/8, x4, x1, x2)
-
-inst_712:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1424*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1424*FLEN/8, x4, x1, x2)
-
-inst_713:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1426*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1426*FLEN/8, x4, x1, x2)
-
-inst_714:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1428*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1428*FLEN/8, x4, x1, x2)
-
-inst_715:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x4a57d3f9bbb84 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb4a57d3f9bbb84; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1430*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1430*FLEN/8, x4, x1, x2)
-
-inst_716:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1432*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1432*FLEN/8, x4, x1, x2)
-
-inst_717:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x9cedc8f82aa65 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe9cedc8f82aa65; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1434*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1434*FLEN/8, x4, x1, x2)
-
-inst_718:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1436*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1436*FLEN/8, x4, x1, x2)
-
-inst_719:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x9cedc8f82aa65 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe9cedc8f82aa65; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1438*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1438*FLEN/8, x4, x1, x2)
-
-inst_720:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1440*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1440*FLEN/8, x4, x1, x2)
-
-inst_721:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x0846432e2fc69 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f80846432e2fc69; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1442*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1442*FLEN/8, x4, x1, x2)
-
-inst_722:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x0846432e2fc69 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7f80846432e2fc69;
-   valaddr_reg:x3; val_offset:1444*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1444*FLEN/8, x4, x1, x2)
-
-inst_723:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1446*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1446*FLEN/8, x4, x1, x2)
-
-inst_724:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1448*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1448*FLEN/8, x4, x1, x2)
-
-inst_725:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1450*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1450*FLEN/8, x4, x1, x2)
-
-inst_726:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x10ae479ad094b and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10ae479ad094b; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1452*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1452*FLEN/8, x4, x1, x2)
-
-inst_727:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x10ae479ad094b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x10ae479ad094b;
-   valaddr_reg:x3; val_offset:1454*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1454*FLEN/8, x4, x1, x2)
-
-inst_728:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x10ae479ad094b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10ae479ad094b; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1456*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1456*FLEN/8, x4, x1, x2)
-
-inst_729:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x000 and fm2 == 0x10ae479ad094b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x10ae479ad094b;
-   valaddr_reg:x3; val_offset:1458*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1458*FLEN/8, x4, x1, x2)
-
-inst_730:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1460*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1460*FLEN/8, x4, x1, x2)
-
-inst_731:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1462*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1462*FLEN/8, x4, x1, x2)
-
-inst_732:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1464*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1464*FLEN/8, x4, x1, x2)
-
-inst_733:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1466*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1466*FLEN/8, x4, x1, x2)
-
-inst_734:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1468*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1468*FLEN/8, x4, x1, x2)
-
-inst_735:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x10ae479ad094b and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10ae479ad094b; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1470*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1470*FLEN/8, x4, x1, x2)
-
-inst_736:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x10ae479ad094b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x10ae479ad094b;
-   valaddr_reg:x3; val_offset:1472*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1472*FLEN/8, x4, x1, x2)
-
-inst_737:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x10ae479ad094b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10ae479ad094b; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1474*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1474*FLEN/8, x4, x1, x2)
-
-inst_738:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1476*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1476*FLEN/8, x4, x1, x2)
-
-inst_739:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1478*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1478*FLEN/8, x4, x1, x2)
-
-inst_740:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1480*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1480*FLEN/8, x4, x1, x2)
-
-inst_741:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x10ae479ad094b and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10ae479ad094b; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:1482*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1482*FLEN/8, x4, x1, x2)
-
-inst_742:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x10ae479ad094b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x10ae479ad094b;
-   valaddr_reg:x3; val_offset:1484*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1484*FLEN/8, x4, x1, x2)
-
-inst_743:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x10ae479ad094b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10ae479ad094b; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1486*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1486*FLEN/8, x4, x1, x2)
-
-inst_744:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1488*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1488*FLEN/8, x4, x1, x2)
-
-inst_745:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1490*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1490*FLEN/8, x4, x1, x2)
-
-inst_746:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x0;
-   valaddr_reg:x3; val_offset:1492*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1492*FLEN/8, x4, x1, x2)
-
-inst_747:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x7328e09ede5ed and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff7328e09ede5ed; op2val:0x0;
-   valaddr_reg:x3; val_offset:1494*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1494*FLEN/8, x4, x1, x2)
-
-inst_748:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x7328e09ede5ed and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ff7328e09ede5ed;
-   valaddr_reg:x3; val_offset:1496*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1496*FLEN/8, x4, x1, x2)
-
-inst_749:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xa6cecc0c25ced and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x7328e09ede5ed and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xa6cecc0c25ced; op2val:0x3ff7328e09ede5ed;
-   valaddr_reg:x3; val_offset:1498*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1498*FLEN/8, x4, x1, x2)
-
-inst_750:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1500*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1500*FLEN/8, x4, x1, x2)
-
-inst_751:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1502*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1502*FLEN/8, x4, x1, x2)
-
-inst_752:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xa7b6d804df453 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7fba7b6d804df453;
-   valaddr_reg:x3; val_offset:1504*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1504*FLEN/8, x4, x1, x2)
-
-inst_753:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1506*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1506*FLEN/8, x4, x1, x2)
-
-inst_754:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1508*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1508*FLEN/8, x4, x1, x2)
-
-inst_755:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1510*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1510*FLEN/8, x4, x1, x2)
-
-inst_756:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1512*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1512*FLEN/8, x4, x1, x2)
-
-inst_757:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1514*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1514*FLEN/8, x4, x1, x2)
-
-inst_758:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1516*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1516*FLEN/8, x4, x1, x2)
-
-inst_759:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1518*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1518*FLEN/8, x4, x1, x2)
-
-inst_760:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1520*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1520*FLEN/8, x4, x1, x2)
-
-inst_761:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1522*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1522*FLEN/8, x4, x1, x2)
-
-inst_762:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1524*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1524*FLEN/8, x4, x1, x2)
-
-inst_763:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1526*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1526*FLEN/8, x4, x1, x2)
-
-inst_764:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1528*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1528*FLEN/8, x4, x1, x2)
-
-inst_765:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xa7b6d804df453 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fba7b6d804df453; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1530*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1530*FLEN/8, x4, x1, x2)
-
-inst_766:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1532*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1532*FLEN/8, x4, x1, x2)
-
-inst_767:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1534*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1534*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_7)
-
-inst_768:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1536*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1536*FLEN/8, x4, x1, x2)
-
-inst_769:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x52f8acd0b29dc and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f852f8acd0b29dc; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1538*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1538*FLEN/8, x4, x1, x2)
-
-inst_770:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x52f8acd0b29dc and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7f852f8acd0b29dc;
-   valaddr_reg:x3; val_offset:1540*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1540*FLEN/8, x4, x1, x2)
-
-inst_771:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1542*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1542*FLEN/8, x4, x1, x2)
-
-inst_772:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1565452ad8ee7 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1565452ad8ee7; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1544*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1544*FLEN/8, x4, x1, x2)
-
-inst_773:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1565452ad8ee7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x1565452ad8ee7;
-   valaddr_reg:x3; val_offset:1546*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1546*FLEN/8, x4, x1, x2)
-
-inst_774:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1565452ad8ee7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1565452ad8ee7; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1548*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1548*FLEN/8, x4, x1, x2)
-
-inst_775:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1565452ad8ee7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x1565452ad8ee7;
-   valaddr_reg:x3; val_offset:1550*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1550*FLEN/8, x4, x1, x2)
-
-inst_776:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1552*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1552*FLEN/8, x4, x1, x2)
-
-inst_777:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1554*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1554*FLEN/8, x4, x1, x2)
-
-inst_778:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1556*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1556*FLEN/8, x4, x1, x2)
-
-inst_779:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1558*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1558*FLEN/8, x4, x1, x2)
-
-inst_780:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1560*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1560*FLEN/8, x4, x1, x2)
-
-inst_781:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1565452ad8ee7 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1565452ad8ee7; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1562*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1562*FLEN/8, x4, x1, x2)
-
-inst_782:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1565452ad8ee7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x1565452ad8ee7;
-   valaddr_reg:x3; val_offset:1564*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1564*FLEN/8, x4, x1, x2)
-
-inst_783:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1565452ad8ee7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1565452ad8ee7; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1566*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1566*FLEN/8, x4, x1, x2)
-
-inst_784:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1568*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1568*FLEN/8, x4, x1, x2)
-
-inst_785:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1570*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1570*FLEN/8, x4, x1, x2)
-
-inst_786:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1572*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1572*FLEN/8, x4, x1, x2)
-
-inst_787:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1565452ad8ee7 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1565452ad8ee7; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:1574*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1574*FLEN/8, x4, x1, x2)
-
-inst_788:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1565452ad8ee7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x1565452ad8ee7;
-   valaddr_reg:x3; val_offset:1576*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1576*FLEN/8, x4, x1, x2)
-
-inst_789:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1565452ad8ee7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1565452ad8ee7; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1578*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1578*FLEN/8, x4, x1, x2)
-
-inst_790:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1580*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1580*FLEN/8, x4, x1, x2)
-
-inst_791:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1582*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1582*FLEN/8, x4, x1, x2)
-
-inst_792:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x0;
-   valaddr_reg:x3; val_offset:1584*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1584*FLEN/8, x4, x1, x2)
-
-inst_793:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xdc114e9aa78bb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ffdc114e9aa78bb; op2val:0x0;
-   valaddr_reg:x3; val_offset:1586*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1586*FLEN/8, x4, x1, x2)
-
-inst_794:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xdc114e9aa78bb and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ffdc114e9aa78bb;
-   valaddr_reg:x3; val_offset:1588*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1588*FLEN/8, x4, x1, x2)
-
-inst_795:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xd5f4b3ac79504 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xdc114e9aa78bb and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xd5f4b3ac79504; op2val:0x3ffdc114e9aa78bb;
-   valaddr_reg:x3; val_offset:1590*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1590*FLEN/8, x4, x1, x2)
-
-inst_796:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1592*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1592*FLEN/8, x4, x1, x2)
-
-inst_797:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1594*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1594*FLEN/8, x4, x1, x2)
-
-inst_798:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x1a406f11e5bc4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7fe1a406f11e5bc4;
-   valaddr_reg:x3; val_offset:1596*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1596*FLEN/8, x4, x1, x2)
-
-inst_799:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1598*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1598*FLEN/8, x4, x1, x2)
-
-inst_800:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1600*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1600*FLEN/8, x4, x1, x2)
-
-inst_801:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1602*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1602*FLEN/8, x4, x1, x2)
-
-inst_802:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1604*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1604*FLEN/8, x4, x1, x2)
-
-inst_803:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1606*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1606*FLEN/8, x4, x1, x2)
-
-inst_804:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1608*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1608*FLEN/8, x4, x1, x2)
-
-inst_805:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1610*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1610*FLEN/8, x4, x1, x2)
-
-inst_806:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1612*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1612*FLEN/8, x4, x1, x2)
-
-inst_807:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1614*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1614*FLEN/8, x4, x1, x2)
-
-inst_808:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1616*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1616*FLEN/8, x4, x1, x2)
-
-inst_809:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1618*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1618*FLEN/8, x4, x1, x2)
-
-inst_810:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1620*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1620*FLEN/8, x4, x1, x2)
-
-inst_811:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x1a406f11e5bc4 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe1a406f11e5bc4; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1622*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1622*FLEN/8, x4, x1, x2)
-
-inst_812:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1624*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1624*FLEN/8, x4, x1, x2)
-
-inst_813:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1626*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1626*FLEN/8, x4, x1, x2)
-
-inst_814:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1628*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1628*FLEN/8, x4, x1, x2)
-
-inst_815:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xc39a4b4fd5fa0 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fac39a4b4fd5fa0; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1630*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1630*FLEN/8, x4, x1, x2)
-
-inst_816:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xc39a4b4fd5fa0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x7fac39a4b4fd5fa0;
-   valaddr_reg:x3; val_offset:1632*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1632*FLEN/8, x4, x1, x2)
-
-inst_817:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1634*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1634*FLEN/8, x4, x1, x2)
-
-inst_818:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1636*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1636*FLEN/8, x4, x1, x2)
-
-inst_819:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1638*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1638*FLEN/8, x4, x1, x2)
-
-inst_820:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1640*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1640*FLEN/8, x4, x1, x2)
-
-inst_821:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1642*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1642*FLEN/8, x4, x1, x2)
-
-inst_822:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1644*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1644*FLEN/8, x4, x1, x2)
-
-inst_823:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1646*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1646*FLEN/8, x4, x1, x2)
-
-inst_824:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1648*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1648*FLEN/8, x4, x1, x2)
-
-inst_825:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x171398510409d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x171398510409d;
-   valaddr_reg:x3; val_offset:1650*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1650*FLEN/8, x4, x1, x2)
-
-inst_826:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x171398510409d and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x171398510409d; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1652*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1652*FLEN/8, x4, x1, x2)
-
-inst_827:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1654*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1654*FLEN/8, x4, x1, x2)
-
-inst_828:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1656*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1656*FLEN/8, x4, x1, x2)
-
-inst_829:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1311fac939004 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x8001311fac939004;
-   valaddr_reg:x3; val_offset:1658*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1658*FLEN/8, x4, x1, x2)
-
-inst_830:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1311fac939004 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001311fac939004; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1660*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1660*FLEN/8, x4, x1, x2)
-
-inst_831:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1662*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1662*FLEN/8, x4, x1, x2)
-
-inst_832:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1664*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1664*FLEN/8, x4, x1, x2)
-
-inst_833:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1666*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1666*FLEN/8, x4, x1, x2)
-
-inst_834:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1668*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1668*FLEN/8, x4, x1, x2)
-
-inst_835:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0e856af141964 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x8000e856af141964;
-   valaddr_reg:x3; val_offset:1670*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1670*FLEN/8, x4, x1, x2)
-
-inst_836:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0e856af141964 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000e856af141964; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1672*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1672*FLEN/8, x4, x1, x2)
-
-inst_837:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1674*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1674*FLEN/8, x4, x1, x2)
-
-inst_838:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1676*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1676*FLEN/8, x4, x1, x2)
-
-inst_839:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1678*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1678*FLEN/8, x4, x1, x2)
-
-inst_840:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1680*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1680*FLEN/8, x4, x1, x2)
-
-inst_841:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x18d1201fedb6b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x80018d1201fedb6b;
-   valaddr_reg:x3; val_offset:1682*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1682*FLEN/8, x4, x1, x2)
-
-inst_842:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x18d1201fedb6b and fs2 == 0 and fe2 == 0x003 and fm2 == 0x1d0c3ce54e734 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80018d1201fedb6b; op2val:0x31d0c3ce54e734;
-   valaddr_reg:x3; val_offset:1684*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1684*FLEN/8, x4, x1, x2)
-
-inst_843:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x1d0c3ce54e734 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x31d0c3ce54e734; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1686*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1686*FLEN/8, x4, x1, x2)
-
-inst_844:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x0;
-   valaddr_reg:x3; val_offset:1688*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1688*FLEN/8, x4, x1, x2)
-
-inst_845:
-// fs1 == 0 and fe1 == 0x402 and fm1 == 0x3d204f37ca317 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x4023d204f37ca317; op2val:0x0;
-   valaddr_reg:x3; val_offset:1690*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1690*FLEN/8, x4, x1, x2)
-
-inst_846:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x3d204f37ca317 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x4023d204f37ca317;
-   valaddr_reg:x3; val_offset:1692*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1692*FLEN/8, x4, x1, x2)
-
-inst_847:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x7204e52885c7b and fs2 == 0 and fe2 == 0x402 and fm2 == 0x3d204f37ca317 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7204e52885c7b; op2val:0x4023d204f37ca317;
-   valaddr_reg:x3; val_offset:1694*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1694*FLEN/8, x4, x1, x2)
-
-inst_848:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1696*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1696*FLEN/8, x4, x1, x2)
-
-inst_849:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1698*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1698*FLEN/8, x4, x1, x2)
-
-inst_850:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xc900ea9c600e8 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7fbc900ea9c600e8;
-   valaddr_reg:x3; val_offset:1700*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1700*FLEN/8, x4, x1, x2)
-
-inst_851:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1702*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1702*FLEN/8, x4, x1, x2)
-
-inst_852:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1704*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1704*FLEN/8, x4, x1, x2)
-
-inst_853:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1706*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1706*FLEN/8, x4, x1, x2)
-
-inst_854:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1708*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1708*FLEN/8, x4, x1, x2)
-
-inst_855:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1710*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1710*FLEN/8, x4, x1, x2)
-
-inst_856:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1712*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1712*FLEN/8, x4, x1, x2)
-
-inst_857:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1714*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1714*FLEN/8, x4, x1, x2)
-
-inst_858:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1716*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1716*FLEN/8, x4, x1, x2)
-
-inst_859:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1718*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1718*FLEN/8, x4, x1, x2)
-
-inst_860:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1720*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1720*FLEN/8, x4, x1, x2)
-
-inst_861:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1722*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1722*FLEN/8, x4, x1, x2)
-
-inst_862:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1724*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1724*FLEN/8, x4, x1, x2)
-
-inst_863:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xc900ea9c600e8 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbc900ea9c600e8; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1726*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1726*FLEN/8, x4, x1, x2)
-
-inst_864:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1728*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1728*FLEN/8, x4, x1, x2)
-
-inst_865:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1730*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1730*FLEN/8, x4, x1, x2)
-
-inst_866:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1732*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1732*FLEN/8, x4, x1, x2)
-
-inst_867:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x6d9a5549e6720 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f86d9a5549e6720; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1734*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1734*FLEN/8, x4, x1, x2)
-
-inst_868:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x6d9a5549e6720 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7f86d9a5549e6720;
-   valaddr_reg:x3; val_offset:1736*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1736*FLEN/8, x4, x1, x2)
-
-inst_869:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1738*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1738*FLEN/8, x4, x1, x2)
-
-inst_870:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x171398510409d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x171398510409d; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1740*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1740*FLEN/8, x4, x1, x2)
-
-inst_871:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x171398510409d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x171398510409d;
-   valaddr_reg:x3; val_offset:1742*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1742*FLEN/8, x4, x1, x2)
-
-inst_872:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1744*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1744*FLEN/8, x4, x1, x2)
-
-inst_873:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1746*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1746*FLEN/8, x4, x1, x2)
-
-inst_874:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1748*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1748*FLEN/8, x4, x1, x2)
-
-inst_875:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x171398510409d and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x171398510409d; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1750*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1750*FLEN/8, x4, x1, x2)
-
-inst_876:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x171398510409d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x171398510409d;
-   valaddr_reg:x3; val_offset:1752*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1752*FLEN/8, x4, x1, x2)
-
-inst_877:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x171398510409d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x171398510409d; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1754*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1754*FLEN/8, x4, x1, x2)
-
-inst_878:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1756*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1756*FLEN/8, x4, x1, x2)
-
-inst_879:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1758*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1758*FLEN/8, x4, x1, x2)
-
-inst_880:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1760*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1760*FLEN/8, x4, x1, x2)
-
-inst_881:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x171398510409d and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x171398510409d; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:1762*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1762*FLEN/8, x4, x1, x2)
-
-inst_882:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x171398510409d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x171398510409d;
-   valaddr_reg:x3; val_offset:1764*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1764*FLEN/8, x4, x1, x2)
-
-inst_883:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x171398510409d and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x171398510409d; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1766*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1766*FLEN/8, x4, x1, x2)
-
-inst_884:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1768*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1768*FLEN/8, x4, x1, x2)
-
-inst_885:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1770*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1770*FLEN/8, x4, x1, x2)
-
-inst_886:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x0;
-   valaddr_reg:x3; val_offset:1772*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1772*FLEN/8, x4, x1, x2)
-
-inst_887:
-// fs1 == 0 and fe1 == 0x400 and fm1 == 0x00bc2d04a6fc5 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x40000bc2d04a6fc5; op2val:0x0;
-   valaddr_reg:x3; val_offset:1774*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1774*FLEN/8, x4, x1, x2)
-
-inst_888:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x00bc2d04a6fc5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x40000bc2d04a6fc5;
-   valaddr_reg:x3; val_offset:1776*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1776*FLEN/8, x4, x1, x2)
-
-inst_889:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe6c3f32a28622 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x00bc2d04a6fc5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe6c3f32a28622; op2val:0x40000bc2d04a6fc5;
-   valaddr_reg:x3; val_offset:1778*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1778*FLEN/8, x4, x1, x2)
-
-inst_890:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1780*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1780*FLEN/8, x4, x1, x2)
-
-inst_891:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1782*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1782*FLEN/8, x4, x1, x2)
-
-inst_892:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x79a9d1edd4c29 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xffb79a9d1edd4c29;
-   valaddr_reg:x3; val_offset:1784*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1784*FLEN/8, x4, x1, x2)
-
-inst_893:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1786*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1786*FLEN/8, x4, x1, x2)
-
-inst_894:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1788*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1788*FLEN/8, x4, x1, x2)
-
-inst_895:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1790*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1790*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_8)
-
-inst_896:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1792*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1792*FLEN/8, x4, x1, x2)
-
-inst_897:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1794*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1794*FLEN/8, x4, x1, x2)
-
-inst_898:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1796*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1796*FLEN/8, x4, x1, x2)
-
-inst_899:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd814466949f33 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed814466949f33; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1798*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1798*FLEN/8, x4, x1, x2)
-
-inst_900:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd814466949f33 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xffed814466949f33;
-   valaddr_reg:x3; val_offset:1800*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1800*FLEN/8, x4, x1, x2)
-
-inst_901:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1802*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1802*FLEN/8, x4, x1, x2)
-
-inst_902:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1804*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1804*FLEN/8, x4, x1, x2)
-
-inst_903:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1806*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1806*FLEN/8, x4, x1, x2)
-
-inst_904:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1808*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1808*FLEN/8, x4, x1, x2)
-
-inst_905:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1810*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1810*FLEN/8, x4, x1, x2)
-
-inst_906:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x79a9d1edd4c29 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb79a9d1edd4c29; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1812*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1812*FLEN/8, x4, x1, x2)
-
-inst_907:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1814*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1814*FLEN/8, x4, x1, x2)
-
-inst_908:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd814466949f33 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed814466949f33; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1816*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1816*FLEN/8, x4, x1, x2)
-
-inst_909:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1818*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1818*FLEN/8, x4, x1, x2)
-
-inst_910:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd814466949f33 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed814466949f33; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1820*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1820*FLEN/8, x4, x1, x2)
-
-inst_911:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1822*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1822*FLEN/8, x4, x1, x2)
-
-inst_912:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x2e2174be43ced and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff82e2174be43ced; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1824*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1824*FLEN/8, x4, x1, x2)
-
-inst_913:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x2e2174be43ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xff82e2174be43ced;
-   valaddr_reg:x3; val_offset:1826*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1826*FLEN/8, x4, x1, x2)
-
-inst_914:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1828*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1828*FLEN/8, x4, x1, x2)
-
-inst_915:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1311fac939004 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001311fac939004; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:1830*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1830*FLEN/8, x4, x1, x2)
-
-inst_916:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1311fac939004 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x8001311fac939004;
-   valaddr_reg:x3; val_offset:1832*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1832*FLEN/8, x4, x1, x2)
-
-inst_917:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1834*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1834*FLEN/8, x4, x1, x2)
-
-inst_918:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1311fac939004 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001311fac939004; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1836*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1836*FLEN/8, x4, x1, x2)
-
-inst_919:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1311fac939004 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x8001311fac939004;
-   valaddr_reg:x3; val_offset:1838*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1838*FLEN/8, x4, x1, x2)
-
-inst_920:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1311fac939004 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001311fac939004; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1840*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1840*FLEN/8, x4, x1, x2)
-
-inst_921:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1842*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1842*FLEN/8, x4, x1, x2)
-
-inst_922:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1844*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1844*FLEN/8, x4, x1, x2)
-
-inst_923:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1846*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1846*FLEN/8, x4, x1, x2)
-
-inst_924:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1311fac939004 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001311fac939004; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:1848*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1848*FLEN/8, x4, x1, x2)
-
-inst_925:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x1311fac939004 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x8001311fac939004;
-   valaddr_reg:x3; val_offset:1850*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1850*FLEN/8, x4, x1, x2)
-
-inst_926:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x1311fac939004 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8001311fac939004; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1852*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1852*FLEN/8, x4, x1, x2)
-
-inst_927:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1854*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1854*FLEN/8, x4, x1, x2)
-
-inst_928:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1856*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1856*FLEN/8, x4, x1, x2)
-
-inst_929:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0x0;
-   valaddr_reg:x3; val_offset:1858*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1858*FLEN/8, x4, x1, x2)
-
-inst_930:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xa853a7101cfb4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbffa853a7101cfb4; op2val:0x0;
-   valaddr_reg:x3; val_offset:1860*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1860*FLEN/8, x4, x1, x2)
-
-inst_931:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xa853a7101cfb4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbffa853a7101cfb4;
-   valaddr_reg:x3; val_offset:1862*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1862*FLEN/8, x4, x1, x2)
-
-inst_932:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbeb3cbdc3a029 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xa853a7101cfb4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800beb3cbdc3a029; op2val:0xbffa853a7101cfb4;
-   valaddr_reg:x3; val_offset:1864*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1864*FLEN/8, x4, x1, x2)
-
-inst_933:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1866*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1866*FLEN/8, x4, x1, x2)
-
-inst_934:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1868*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1868*FLEN/8, x4, x1, x2)
-
-inst_935:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x0bc8069a0dddf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xffd0bc8069a0dddf;
-   valaddr_reg:x3; val_offset:1870*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1870*FLEN/8, x4, x1, x2)
-
-inst_936:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1872*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1872*FLEN/8, x4, x1, x2)
-
-inst_937:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1874*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1874*FLEN/8, x4, x1, x2)
-
-inst_938:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1876*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1876*FLEN/8, x4, x1, x2)
-
-inst_939:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1878*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1878*FLEN/8, x4, x1, x2)
-
-inst_940:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1880*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1880*FLEN/8, x4, x1, x2)
-
-inst_941:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1882*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1882*FLEN/8, x4, x1, x2)
-
-inst_942:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1884*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1884*FLEN/8, x4, x1, x2)
-
-inst_943:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1886*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1886*FLEN/8, x4, x1, x2)
-
-inst_944:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1888*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1888*FLEN/8, x4, x1, x2)
-
-inst_945:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1890*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1890*FLEN/8, x4, x1, x2)
-
-inst_946:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1892*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1892*FLEN/8, x4, x1, x2)
-
-inst_947:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1894*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1894*FLEN/8, x4, x1, x2)
-
-inst_948:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0bc8069a0dddf and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd0bc8069a0dddf; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1896*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1896*FLEN/8, x4, x1, x2)
-
-inst_949:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1898*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1898*FLEN/8, x4, x1, x2)
-
-inst_950:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1900*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1900*FLEN/8, x4, x1, x2)
-
-inst_951:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1902*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1902*FLEN/8, x4, x1, x2)
-
-inst_952:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0xac733dc349632 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff9ac733dc349632; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:1904*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1904*FLEN/8, x4, x1, x2)
-
-inst_953:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0xac733dc349632 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xff9ac733dc349632;
-   valaddr_reg:x3; val_offset:1906*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1906*FLEN/8, x4, x1, x2)
-
-inst_954:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1908*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1908*FLEN/8, x4, x1, x2)
-
-inst_955:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:1910*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1910*FLEN/8, x4, x1, x2)
-
-inst_956:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1912*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1912*FLEN/8, x4, x1, x2)
-
-inst_957:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1914*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1914*FLEN/8, x4, x1, x2)
-
-inst_958:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:1916*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1916*FLEN/8, x4, x1, x2)
-
-inst_959:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1918*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1918*FLEN/8, x4, x1, x2)
-
-inst_960:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:1920*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1920*FLEN/8, x4, x1, x2)
-
-inst_961:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1922*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1922*FLEN/8, x4, x1, x2)
-
-inst_962:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:1924*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1924*FLEN/8, x4, x1, x2)
-
-inst_963:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1926*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1926*FLEN/8, x4, x1, x2)
-
-inst_964:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:1928*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1928*FLEN/8, x4, x1, x2)
-
-inst_965:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1930*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1930*FLEN/8, x4, x1, x2)
-
-inst_966:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0e856af141964 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x8000e856af141964;
-   valaddr_reg:x3; val_offset:1932*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1932*FLEN/8, x4, x1, x2)
-
-inst_967:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0e856af141964 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000e856af141964; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1934*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1934*FLEN/8, x4, x1, x2)
-
-inst_968:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1936*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1936*FLEN/8, x4, x1, x2)
-
-inst_969:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:1938*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1938*FLEN/8, x4, x1, x2)
-
-inst_970:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:1940*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1940*FLEN/8, x4, x1, x2)
-
-inst_971:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1942*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1942*FLEN/8, x4, x1, x2)
-
-inst_972:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x18d1201fedb6b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x80018d1201fedb6b;
-   valaddr_reg:x3; val_offset:1944*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1944*FLEN/8, x4, x1, x2)
-
-inst_973:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x18d1201fedb6b and fs2 == 1 and fe2 == 0x002 and fm2 == 0x0e6f21de6840b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80018d1201fedb6b; op2val:0x8020e6f21de6840b;
-   valaddr_reg:x3; val_offset:1946*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1946*FLEN/8, x4, x1, x2)
-
-inst_974:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x0e6f21de6840b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8020e6f21de6840b; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:1948*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1948*FLEN/8, x4, x1, x2)
-
-inst_975:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0x0;
-   valaddr_reg:x3; val_offset:1950*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1950*FLEN/8, x4, x1, x2)
-
-inst_976:
-// fs1 == 1 and fe1 == 0x401 and fm1 == 0x2cde30fb81e08 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc012cde30fb81e08; op2val:0x0;
-   valaddr_reg:x3; val_offset:1952*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1952*FLEN/8, x4, x1, x2)
-
-inst_977:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x2cde30fb81e08 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc012cde30fb81e08;
-   valaddr_reg:x3; val_offset:1954*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1954*FLEN/8, x4, x1, x2)
-
-inst_978:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x361639f9480cf and fs2 == 1 and fe2 == 0x401 and fm2 == 0x2cde30fb81e08 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800361639f9480cf; op2val:0xc012cde30fb81e08;
-   valaddr_reg:x3; val_offset:1956*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1956*FLEN/8, x4, x1, x2)
-
-inst_979:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1958*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1958*FLEN/8, x4, x1, x2)
-
-inst_980:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:1960*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1960*FLEN/8, x4, x1, x2)
-
-inst_981:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x1f930d5b2a8f5 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xffb1f930d5b2a8f5;
-   valaddr_reg:x3; val_offset:1962*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1962*FLEN/8, x4, x1, x2)
-
-inst_982:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:1964*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1964*FLEN/8, x4, x1, x2)
-
-inst_983:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1966*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1966*FLEN/8, x4, x1, x2)
-
-inst_984:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:1968*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1968*FLEN/8, x4, x1, x2)
-
-inst_985:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1970*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1970*FLEN/8, x4, x1, x2)
-
-inst_986:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:1972*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1972*FLEN/8, x4, x1, x2)
-
-inst_987:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1974*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1974*FLEN/8, x4, x1, x2)
-
-inst_988:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x6777d0b1f5332 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe6777d0b1f5332; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:1976*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1976*FLEN/8, x4, x1, x2)
-
-inst_989:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x6777d0b1f5332 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xffe6777d0b1f5332;
-   valaddr_reg:x3; val_offset:1978*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1978*FLEN/8, x4, x1, x2)
-
-inst_990:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1980*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1980*FLEN/8, x4, x1, x2)
-
-inst_991:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:1982*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1982*FLEN/8, x4, x1, x2)
-
-inst_992:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1984*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1984*FLEN/8, x4, x1, x2)
-
-inst_993:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:1986*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1986*FLEN/8, x4, x1, x2)
-
-inst_994:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1988*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1988*FLEN/8, x4, x1, x2)
-
-inst_995:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x1f930d5b2a8f5 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb1f930d5b2a8f5; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:1990*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1990*FLEN/8, x4, x1, x2)
-
-inst_996:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1992*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1992*FLEN/8, x4, x1, x2)
-
-inst_997:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x6777d0b1f5332 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe6777d0b1f5332; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:1994*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1994*FLEN/8, x4, x1, x2)
-
-inst_998:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1996*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1996*FLEN/8, x4, x1, x2)
-
-inst_999:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x6777d0b1f5332 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe6777d0b1f5332; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:1998*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 1998*FLEN/8, x4, x1, x2)
-
-inst_1000:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:2000*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2000*FLEN/8, x4, x1, x2)
-
-inst_1001:
-// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0xcc1e7bc510e55 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff7cc1e7bc510e55; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:2002*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2002*FLEN/8, x4, x1, x2)
-
-inst_1002:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0xcc1e7bc510e55 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xff7cc1e7bc510e55;
-   valaddr_reg:x3; val_offset:2004*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2004*FLEN/8, x4, x1, x2)
-
-inst_1003:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:2006*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2006*FLEN/8, x4, x1, x2)
-
-inst_1004:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0e856af141964 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000e856af141964; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:2008*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2008*FLEN/8, x4, x1, x2)
-
-inst_1005:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0e856af141964 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x8000e856af141964;
-   valaddr_reg:x3; val_offset:2010*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2010*FLEN/8, x4, x1, x2)
-
-inst_1006:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:2012*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2012*FLEN/8, x4, x1, x2)
-
-inst_1007:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0e856af141964 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000e856af141964; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:2014*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2014*FLEN/8, x4, x1, x2)
-
-inst_1008:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:2016*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2016*FLEN/8, x4, x1, x2)
-
-inst_1009:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0e856af141964 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000e856af141964; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:2018*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2018*FLEN/8, x4, x1, x2)
-
-inst_1010:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0e856af141964 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x8000e856af141964;
-   valaddr_reg:x3; val_offset:2020*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2020*FLEN/8, x4, x1, x2)
-
-inst_1011:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0e856af141964 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000e856af141964; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:2022*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2022*FLEN/8, x4, x1, x2)
-
-inst_1012:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:2024*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2024*FLEN/8, x4, x1, x2)
-
-inst_1013:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:2026*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2026*FLEN/8, x4, x1, x2)
-
-inst_1014:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0x0;
-   valaddr_reg:x3; val_offset:2028*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2028*FLEN/8, x4, x1, x2)
-
-inst_1015:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x431b4a598252a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbff431b4a598252a; op2val:0x0;
-   valaddr_reg:x3; val_offset:2030*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2030*FLEN/8, x4, x1, x2)
-
-inst_1016:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x431b4a598252a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbff431b4a598252a;
-   valaddr_reg:x3; val_offset:2032*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2032*FLEN/8, x4, x1, x2)
-
-inst_1017:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x91362d6c8fde3 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x431b4a598252a and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80091362d6c8fde3; op2val:0xbff431b4a598252a;
-   valaddr_reg:x3; val_offset:2034*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2034*FLEN/8, x4, x1, x2)
-
-inst_1018:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:2036*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2036*FLEN/8, x4, x1, x2)
-
-inst_1019:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:2038*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2038*FLEN/8, x4, x1, x2)
-
-inst_1020:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0x60eeb556ce9ce and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xffd60eeb556ce9ce;
-   valaddr_reg:x3; val_offset:2040*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2040*FLEN/8, x4, x1, x2)
-
-inst_1021:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:2042*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2042*FLEN/8, x4, x1, x2)
-
-inst_1022:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:2044*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2044*FLEN/8, x4, x1, x2)
-
-inst_1023:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:2046*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2046*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_9)
-
-inst_1024:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:2048*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2048*FLEN/8, x4, x1, x2)
-
-inst_1025:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:2050*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2050*FLEN/8, x4, x1, x2)
-
-inst_1026:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:2052*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2052*FLEN/8, x4, x1, x2)
-
-inst_1027:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:2054*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2054*FLEN/8, x4, x1, x2)
-
-inst_1028:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:2056*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2056*FLEN/8, x4, x1, x2)
-
-inst_1029:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:2058*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2058*FLEN/8, x4, x1, x2)
-
-inst_1030:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:2060*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2060*FLEN/8, x4, x1, x2)
-
-inst_1031:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:2062*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2062*FLEN/8, x4, x1, x2)
-
-inst_1032:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:2064*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2064*FLEN/8, x4, x1, x2)
-
-inst_1033:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0x60eeb556ce9ce and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffd60eeb556ce9ce; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:2066*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2066*FLEN/8, x4, x1, x2)
-
-inst_1034:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:2068*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2068*FLEN/8, x4, x1, x2)
-
-inst_1035:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:2070*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2070*FLEN/8, x4, x1, x2)
-
-inst_1036:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:2072*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2072*FLEN/8, x4, x1, x2)
-
-inst_1037:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x1a5891123ee3f and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffa1a5891123ee3f; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:2074*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2074*FLEN/8, x4, x1, x2)
-
-inst_1038:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x1a5891123ee3f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xffa1a5891123ee3f;
-   valaddr_reg:x3; val_offset:2076*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2076*FLEN/8, x4, x1, x2)
-
-inst_1039:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:2078*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2078*FLEN/8, x4, x1, x2)
-
-inst_1040:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:2080*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2080*FLEN/8, x4, x1, x2)
-
-inst_1041:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:2082*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2082*FLEN/8, x4, x1, x2)
-
-inst_1042:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:2084*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2084*FLEN/8, x4, x1, x2)
-
-inst_1043:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:2086*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2086*FLEN/8, x4, x1, x2)
-
-inst_1044:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:2088*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2088*FLEN/8, x4, x1, x2)
-
-inst_1045:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:2090*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2090*FLEN/8, x4, x1, x2)
-
-inst_1046:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:2092*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2092*FLEN/8, x4, x1, x2)
-
-inst_1047:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:2094*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2094*FLEN/8, x4, x1, x2)
-
-inst_1048:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:2096*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2096*FLEN/8, x4, x1, x2)
-
-inst_1049:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:2098*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2098*FLEN/8, x4, x1, x2)
-
-inst_1050:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:2100*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2100*FLEN/8, x4, x1, x2)
-
-inst_1051:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:2102*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2102*FLEN/8, x4, x1, x2)
-
-inst_1052:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:2104*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2104*FLEN/8, x4, x1, x2)
-
-inst_1053:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x18d1201fedb6b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x80018d1201fedb6b;
-   valaddr_reg:x3; val_offset:2106*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2106*FLEN/8, x4, x1, x2)
-
-inst_1054:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x18d1201fedb6b and fs2 == 1 and fe2 == 0x002 and fm2 == 0x646dc31fb5314 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80018d1201fedb6b; op2val:0x802646dc31fb5314;
-   valaddr_reg:x3; val_offset:2108*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2108*FLEN/8, x4, x1, x2)
-
-inst_1055:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0x646dc31fb5314 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802646dc31fb5314; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:2110*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2110*FLEN/8, x4, x1, x2)
-
-inst_1056:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0x0;
-   valaddr_reg:x3; val_offset:2112*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2112*FLEN/8, x4, x1, x2)
-
-inst_1057:
-// fs1 == 1 and fe1 == 0x401 and fm1 == 0x8c8a47b3dd237 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc018c8a47b3dd237; op2val:0x0;
-   valaddr_reg:x3; val_offset:2114*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2114*FLEN/8, x4, x1, x2)
-
-inst_1058:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x8c8a47b3dd237 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc018c8a47b3dd237;
-   valaddr_reg:x3; val_offset:2116*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2116*FLEN/8, x4, x1, x2)
-
-inst_1059:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x4749270657704 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x8c8a47b3dd237 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8004749270657704; op2val:0xc018c8a47b3dd237;
-   valaddr_reg:x3; val_offset:2118*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2118*FLEN/8, x4, x1, x2)
-
-inst_1060:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:2120*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2120*FLEN/8, x4, x1, x2)
-
-inst_1061:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:2122*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2122*FLEN/8, x4, x1, x2)
-
-inst_1062:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xeb781eb40c69d and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xffbeb781eb40c69d;
-   valaddr_reg:x3; val_offset:2124*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2124*FLEN/8, x4, x1, x2)
-
-inst_1063:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:2126*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2126*FLEN/8, x4, x1, x2)
-
-inst_1064:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:2128*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2128*FLEN/8, x4, x1, x2)
-
-inst_1065:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:2130*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2130*FLEN/8, x4, x1, x2)
-
-inst_1066:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:2132*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2132*FLEN/8, x4, x1, x2)
-
-inst_1067:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:2134*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2134*FLEN/8, x4, x1, x2)
-
-inst_1068:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:2136*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2136*FLEN/8, x4, x1, x2)
-
-inst_1069:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:2138*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2138*FLEN/8, x4, x1, x2)
-
-inst_1070:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:2140*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2140*FLEN/8, x4, x1, x2)
-
-inst_1071:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:2142*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2142*FLEN/8, x4, x1, x2)
-
-inst_1072:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:2144*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2144*FLEN/8, x4, x1, x2)
-
-inst_1073:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:2146*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2146*FLEN/8, x4, x1, x2)
-
-inst_1074:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:2148*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2148*FLEN/8, x4, x1, x2)
-
-inst_1075:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xeb781eb40c69d and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbeb781eb40c69d; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:2150*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2150*FLEN/8, x4, x1, x2)
-
-inst_1076:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:2152*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2152*FLEN/8, x4, x1, x2)
-
-inst_1077:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:2154*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2154*FLEN/8, x4, x1, x2)
-
-inst_1078:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:2156*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2156*FLEN/8, x4, x1, x2)
-
-inst_1079:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x892ce55cd6bb0 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff8892ce55cd6bb0; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:2158*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2158*FLEN/8, x4, x1, x2)
-
-inst_1080:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x892ce55cd6bb0 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xff8892ce55cd6bb0;
-   valaddr_reg:x3; val_offset:2160*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2160*FLEN/8, x4, x1, x2)
-
-inst_1081:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:2162*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2162*FLEN/8, x4, x1, x2)
-
-inst_1082:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x18d1201fedb6b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80018d1201fedb6b; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:2164*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2164*FLEN/8, x4, x1, x2)
-
-inst_1083:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x18d1201fedb6b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x80018d1201fedb6b;
-   valaddr_reg:x3; val_offset:2166*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2166*FLEN/8, x4, x1, x2)
-
-inst_1084:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:2168*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2168*FLEN/8, x4, x1, x2)
-
-inst_1085:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x18d1201fedb6b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80018d1201fedb6b; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:2170*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2170*FLEN/8, x4, x1, x2)
-
-inst_1086:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:2172*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2172*FLEN/8, x4, x1, x2)
-
-inst_1087:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x18d1201fedb6b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80018d1201fedb6b; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:2174*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2174*FLEN/8, x4, x1, x2)
-
-inst_1088:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0x0;
-   valaddr_reg:x3; val_offset:2176*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2176*FLEN/8, x4, x1, x2)
-
-inst_1089:
-// fs1 == 1 and fe1 == 0x400 and fm1 == 0x1418de01443c7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc001418de01443c7; op2val:0x0;
-   valaddr_reg:x3; val_offset:2178*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2178*FLEN/8, x4, x1, x2)
-
-inst_1090:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x1418de01443c7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc001418de01443c7;
-   valaddr_reg:x3; val_offset:2180*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2180*FLEN/8, x4, x1, x2)
-
-inst_1091:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xf82b413f49232 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x1418de01443c7 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800f82b413f49232; op2val:0xc001418de01443c7;
-   valaddr_reg:x3; val_offset:2182*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2182*FLEN/8, x4, x1, x2)
-
-inst_1092:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:2184*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2184*FLEN/8, x4, x1, x2)
-
-inst_1093:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:2186*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2186*FLEN/8, x4, x1, x2)
-
-inst_1094:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfb5355e167379 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fdfb5355e167379;
-   valaddr_reg:x3; val_offset:2188*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2188*FLEN/8, x4, x1, x2)
-
-inst_1095:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8072e8f9c858f and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fb8072e8f9c858f;
-   valaddr_reg:x3; val_offset:2190*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2190*FLEN/8, x4, x1, x2)
-
-inst_1096:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x86499331191c4 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fe86499331191c4;
-   valaddr_reg:x3; val_offset:2192*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2192*FLEN/8, x4, x1, x2)
-
-inst_1097:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0xd481499755d4b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fcd481499755d4b;
-   valaddr_reg:x3; val_offset:2194*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2194*FLEN/8, x4, x1, x2)
-
-inst_1098:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x3874a9329ec20 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffc3874a9329ec20;
-   valaddr_reg:x3; val_offset:2196*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2196*FLEN/8, x4, x1, x2)
-
-inst_1099:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x19dc4ea1c6bbe and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffe19dc4ea1c6bbe;
-   valaddr_reg:x3; val_offset:2198*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2198*FLEN/8, x4, x1, x2)
-
-inst_1100:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xf17c7086d3e4c and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffef17c7086d3e4c;
-   valaddr_reg:x3; val_offset:2200*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2200*FLEN/8, x4, x1, x2)
-
-inst_1101:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfeebf49377796 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffefeebf49377796;
-   valaddr_reg:x3; val_offset:2202*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2202*FLEN/8, x4, x1, x2)
-
-inst_1102:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xc057ab9751c40 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffac057ab9751c40;
-   valaddr_reg:x3; val_offset:2204*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2204*FLEN/8, x4, x1, x2)
-
-inst_1103:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc386bbc204f89 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc386bbc204f89;
-   valaddr_reg:x3; val_offset:2206*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2206*FLEN/8, x4, x1, x2)
-
-inst_1104:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xa6cecc0c25ced and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xa6cecc0c25ced;
-   valaddr_reg:x3; val_offset:2208*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2208*FLEN/8, x4, x1, x2)
-
-inst_1105:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xd5f4b3ac79504 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xd5f4b3ac79504;
-   valaddr_reg:x3; val_offset:2210*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2210*FLEN/8, x4, x1, x2)
-
-inst_1106:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x7204e52885c7b and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7204e52885c7b;
-   valaddr_reg:x3; val_offset:2212*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2212*FLEN/8, x4, x1, x2)
-
-inst_1107:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe6c3f32a28622 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xe6c3f32a28622;
-   valaddr_reg:x3; val_offset:2214*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2214*FLEN/8, x4, x1, x2)
-
-inst_1108:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbeb3cbdc3a029 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x800beb3cbdc3a029;
-   valaddr_reg:x3; val_offset:2216*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2216*FLEN/8, x4, x1, x2)
-
-inst_1109:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x361639f9480cf and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x800361639f9480cf;
-   valaddr_reg:x3; val_offset:2218*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2218*FLEN/8, x4, x1, x2)
-
-inst_1110:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x91362d6c8fde3 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x80091362d6c8fde3;
-   valaddr_reg:x3; val_offset:2220*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2220*FLEN/8, x4, x1, x2)
-
-inst_1111:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x4749270657704 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x8004749270657704;
-   valaddr_reg:x3; val_offset:2222*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2222*FLEN/8, x4, x1, x2)
-
-inst_1112:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xf82b413f49232 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x800f82b413f49232;
-   valaddr_reg:x3; val_offset:2224*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2224*FLEN/8, x4, x1, x2)
-
-inst_1113:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xfb5355e167379 and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fdfb5355e167379; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:2226*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2226*FLEN/8, x4, x1, x2)
-
-inst_1114:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8072e8f9c858f and fs2 == 0 and fe2 == 0x7fc and fm2 == 0x132d8f91b7583 and  fcsr == 0  
-/* opcode: fmaxm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8072e8f9c858f; op2val:0x7fc132d8f91b7583;
-   valaddr_reg:x3; val_offset:2228*FLEN/8;  fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.d, f31, f30, f29, 0, 0, x3, 2228*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
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-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(9209096066353683787,64,FLEN)
-NAN_BOXED(18434938528601008590,64,FLEN)
-NAN_BOXED(9209096066353683787,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(18429722854496529440,64,FLEN)
-NAN_BOXED(18434938528601008590,64,FLEN)
-NAN_BOXED(18429722854496529440,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(18438191818498403262,64,FLEN)
-NAN_BOXED(18434938528601008590,64,FLEN)
-NAN_BOXED(18438191818498403262,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(18441985142712778316,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(18442221504440006550,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(18423106200321465408,64,FLEN)
-NAN_BOXED(18420185959038709311,64,FLEN)
-NAN_BOXED(18423106200321465408,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(18420185959038709311,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(3439735089418121,64,FLEN)
-NAN_BOXED(9234145997515084564,64,FLEN)
-NAN_BOXED(3439735089418121,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(9234145997515084564,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(2934513869151469,64,FLEN)
-NAN_BOXED(9234145997515084564,64,FLEN)
-NAN_BOXED(2934513869151469,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(3763951410582788,64,FLEN)
-NAN_BOXED(9234145997515084564,64,FLEN)
-NAN_BOXED(3763951410582788,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(4059668362200610,64,FLEN)
-NAN_BOXED(9234145997515084564,64,FLEN)
-NAN_BOXED(4059668362200610,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(9226726907712872489,64,FLEN)
-NAN_BOXED(9234145997515084564,64,FLEN)
-NAN_BOXED(9226726907712872489,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(9225926626876390883,64,FLEN)
-NAN_BOXED(9234145997515084564,64,FLEN)
-NAN_BOXED(9225926626876390883,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9234145997515084564,64,FLEN)
-NAN_BOXED(9223808620313893739,64,FLEN)
-NAN_BOXED(9223808620313893739,64,FLEN)
-NAN_BOXED(9234145997515084564,64,FLEN)
-NAN_BOXED(9234145997515084564,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13842034063491060279,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13842034063491060279,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(13842034063491060279,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9205695020795655555,64,FLEN)
-NAN_BOXED(18428368493872203421,64,FLEN)
-NAN_BOXED(9205695020795655555,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18428368493872203421,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9214282603439747961,64,FLEN)
-NAN_BOXED(18428368493872203421,64,FLEN)
-NAN_BOXED(9214282603439747961,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9203113735090898319,64,FLEN)
-NAN_BOXED(18428368493872203421,64,FLEN)
-NAN_BOXED(9203113735090898319,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9216727246563283396,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9209096066353683787,64,FLEN)
-NAN_BOXED(18428368493872203421,64,FLEN)
-NAN_BOXED(9209096066353683787,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18429722854496529440,64,FLEN)
-NAN_BOXED(18428368493872203421,64,FLEN)
-NAN_BOXED(18429722854496529440,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18438191818498403262,64,FLEN)
-NAN_BOXED(18428368493872203421,64,FLEN)
-NAN_BOXED(18438191818498403262,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18441985142712778316,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18442221504440006550,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18423106200321465408,64,FLEN)
-NAN_BOXED(18413128491404716976,64,FLEN)
-NAN_BOXED(18423106200321465408,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(18413128491404716976,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(2005845601180795,64,FLEN)
-NAN_BOXED(9223808620313893739,64,FLEN)
-NAN_BOXED(2005845601180795,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9223808620313893739,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9224323542291873999,64,FLEN)
-NAN_BOXED(9223808620313893739,64,FLEN)
-NAN_BOXED(9224323542291873999,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(9223808620313893739,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13835411607864492999,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13835411607864492999,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(13835411607864492999,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9205695020795655555,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9214282603439747961,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9203113735090898319,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9216727246563283396,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9209096066353683787,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18429722854496529440,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18438191818498403262,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18441985142712778316,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18442221504440006550,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18423106200321465408,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(3439735089418121,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2934513869151469,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(3763951410582788,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(2005845601180795,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(4059668362200610,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9226726907712872489,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9224323542291873999,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9225926626876390883,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9224626109061363460,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9227737871445955122,64,FLEN)
-NAN_BOXED(9214282603439747961,64,FLEN)
-NAN_BOXED(9205695020795655555,64,FLEN)
-NAN_BOXED(9203113735090898319,64,FLEN)
-NAN_BOXED(9205695020795655555,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_7:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_8:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_9:
-    .fill 182*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b1-01.S
deleted file mode 100644
index 16d793919..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b1-01.S
+++ /dev/null
@@ -1,429 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:06:50 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmaxm.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmaxm.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fmaxm_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rd != rs2, rs1==f31, rs2==f30, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f29; op1val:0x0; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f29, f30, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 == rs2 == rd, rs1==f28, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f28; op2:f28; dest:f28; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f28, f28, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f29, rs2==f31, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f29; op2:f31; dest:f30; op1val:0x0; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f30, f29, f31, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f26; op2:f26; dest:f27; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f27, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f27; op2:f25; dest:f26; op1val:0x0; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f26, f27, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f24; op2:f27; dest:f25; op1val:0x0; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f25, f24, f27, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f25; op2:f23; dest:f24; op1val:0x0; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f24, f25, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f22; op2:f24; dest:f23; op1val:0x0; op2val:0x800000;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f23, f22, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f23; op2:f21; dest:f22; op1val:0x0; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f22, f23, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x800001;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f21; op2:f19; dest:f20; op1val:0x0; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f20, f21, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f18; op2:f20; dest:f19; op1val:0x0; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f19; op2:f17; dest:f18; op1val:0x0; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f18, f19, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f16; op2:f18; dest:f17; op1val:0x0; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f17, f16, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f17; op2:f15; dest:f16; op1val:0x0; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f16, f17, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f15; op2:f13; dest:f14; op1val:0x0; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f14, f15, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f12; op2:f14; dest:f13; op1val:0x0; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f13; op2:f11; dest:f12; op1val:0x0; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f12, f13, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f10; op2:f12; dest:f11; op1val:0x0; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f11, f10, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f11; op2:f9; dest:f10; op1val:0x0; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f10, f11, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f9; op2:f7; dest:f8; op1val:0x0; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f8, f9, f7, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f6; op2:f8; dest:f7; op1val:0x80000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f7, rs2==f5, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f7; op2:f5; dest:f6; op1val:0x80000000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f6, f7, f5, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f4; op2:f6; dest:f5; op1val:0x80000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f5, f4, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f5, rs2==f3, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f5; op2:f3; dest:f4; op1val:0x80000000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f4, f5, f3, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f2; op2:f4; dest:f3; op1val:0x80000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f3, rs2==f1, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f3; op2:f1; dest:f2; op1val:0x80000000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f2, f3, f1, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f0; op2:f2; dest:f1; op1val:0x80000000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f1; op2:f30; dest:f31; op1val:0x80000000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f1, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f30; op2:f0; dest:f31; op1val:0x80000000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f0, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rd==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f0; op1val:0x80000000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 68*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b19-01.S
deleted file mode 100644
index 76e66430a..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fmaxm_b19-01.S
+++ /dev/null
@@ -1,429 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:06:50 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmaxm.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmaxm.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fmaxm_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rd != rs2, rs1==f31, rs2==f30, rd==f31,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f31; op1val:0x7dce622b; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f29; op1val:0x7dce622b; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f29, f30, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 == rs2 == rd, rs1==f28, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x183299 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f28; op2:f28; dest:f28; op1val:0x7f7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f28, f28, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f29, rs2==f31, rd==f30,fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f29; op2:f31; dest:f30; op1val:0x7d183299; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f30, f29, f31, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f26; op2:f26; dest:f27; op1val:0x7f7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f27, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f27; op2:f25; dest:f26; op1val:0x7dce622b; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f26, f27, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f24; op2:f27; dest:f25; op1val:0x7dce622b; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f25, f24, f27, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f25; op2:f23; dest:f24; op1val:0x7d902b16; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f24, f25, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f22; op2:f24; dest:f23; op1val:0x7dce622b; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f23, f22, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x6a2c24 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f23; op2:f21; dest:f22; op1val:0x7f7fffff; op2val:0x7d6a2c24;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f22, f23, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f20; op2:f22; dest:f21; op1val:0x7d6a2c24; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f21; op2:f19; dest:f20; op1val:0x7f7fffff; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f20, f21, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f18; op2:f20; dest:f19; op1val:0x7dce622b; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f19; op2:f17; dest:f18; op1val:0x7e2fb07b; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f18, f19, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f16; op2:f18; dest:f17; op1val:0x7dce622b; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f17, f16, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f17, rs2==f15, rd==f16,fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f17; op2:f15; dest:f16; op1val:0xfdea577e; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f16, f17, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f14; op2:f16; dest:f15; op1val:0x7dce622b; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x291dc8 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f15; op2:f13; dest:f14; op1val:0x7f7fffff; op2val:0xfd291dc8;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f14, f15, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f12; op2:f14; dest:f13; op1val:0xfd291dc8; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f13; op2:f11; dest:f12; op1val:0x7f7fffff; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f12, f13, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f10; op2:f12; dest:f11; op1val:0x7dce622b; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f11, f10, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x153eee and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f11; op2:f9; dest:f10; op1val:0x7f7fffff; op2val:0xfd953eee;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f10, f11, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f8; op2:f10; dest:f9; op1val:0xfd953eee; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f9; op2:f7; dest:f8; op1val:0x7f7fffff; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f8, f9, f7, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f6; op2:f8; dest:f7; op1val:0x7dce622b; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f7, rs2==f5, rd==f6,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x1946c8 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f7; op2:f5; dest:f6; op1val:0x7f7fffff; op2val:0xfd9946c8;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f6, f7, f5, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f4; op2:f6; dest:f5; op1val:0xfd9946c8; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f5, f4, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f5, rs2==f3, rd==f4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f5; op2:f3; dest:f4; op1val:0x7f7fffff; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f4, f5, f3, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f2; op2:f4; dest:f3; op1val:0x7dce622b; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f3, rs2==f1, rd==f2,fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f3; op2:f1; dest:f2; op1val:0xfd2820df; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f2, f3, f1, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f0; op2:f2; dest:f1; op1val:0x7dce622b; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x07167c and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f1; op2:f30; dest:f31; op1val:0x255707; op2val:0x7e07167c;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f1, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f0,fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f30; op2:f0; dest:f31; op1val:0x7e07167c; op2val:0x255707;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f0, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rd==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f0; op1val:0x255707; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2104110116,32,FLEN)
-NAN_BOXED(2104110116,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4247330248,32,FLEN)
-NAN_BOXED(4247330248,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4254416622,32,FLEN)
-NAN_BOXED(4254416622,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4254680776,32,FLEN)
-NAN_BOXED(4254680776,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(3203502,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2114393724,32,FLEN)
-NAN_BOXED(2114393724,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(3203502,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 68*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b1-01.S
deleted file mode 100644
index 18eddd5b5..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b1-01.S
+++ /dev/null
@@ -1,5889 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:11:12 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fminm.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fminm.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fminm.d_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fminm.d_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f30, rs2==f29, rd==f31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rs2 != rd, rs1==f31, rs2==f31, rd==f30,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f31; op2:f31; dest:f30; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f30, f31, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs2 == rd != rs1, rs1==f29, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f29; op2:f28; dest:f28; op1val:0x0; op2val:0x1;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f28, f29, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 == rs2 == rd, rs1==f27, rs2==f27, rd==f27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f27; op2:f27; dest:f27; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f27, f27, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rd != rs2, rs1==f26, rs2==f30, rd==f26,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f26; op2:f30; dest:f26; op1val:0x0; op2val:0x2;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f26, f26, f30, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f28, rs2==f26, rd==f29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f28; op2:f26; dest:f29; op1val:0x0; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f29, f28, f26, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f23, rd==f25,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f24; op2:f23; dest:f25; op1val:0x0; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f25, f24, f23, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f23, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f23; op2:f25; dest:f24; op1val:0x0; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f24, f23, f25, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f25, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f25; op2:f24; dest:f23; op1val:0x0; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f23, f25, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rs2==f20, rd==f22,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f21; op2:f20; dest:f22; op1val:0x0; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f22, f21, f20, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f22, rs2==f21, rd==f20,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f22; op2:f21; dest:f20; op1val:0x0; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f20, f22, f21, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f17, rd==f19,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f18; op2:f17; dest:f19; op1val:0x0; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f19, f18, f17, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f17, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f17; op2:f19; dest:f18; op1val:0x0; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f18, f17, f19, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f19, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f19; op2:f18; dest:f17; op1val:0x0; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f17, f19, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rs2==f14, rd==f16,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f15; op2:f14; dest:f16; op1val:0x0; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f16, f15, f14, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f16, rs2==f15, rd==f14,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f16; op2:f15; dest:f14; op1val:0x0; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f14, f16, f15, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f11, rd==f13,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f12; op2:f11; dest:f13; op1val:0x0; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f13, f12, f11, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f11, rs2==f13, rd==f12,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f11; op2:f13; dest:f12; op1val:0x0; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f12, f11, f13, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f13, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f13; op2:f12; dest:f11; op1val:0x0; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f11, f13, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rs2==f8, rd==f10,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f9; op2:f8; dest:f10; op1val:0x0; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f10, f9, f8, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f10, rs2==f9, rd==f8,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f10; op2:f9; dest:f8; op1val:0x0; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f8, f10, f9, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f5, rd==f7,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f6; op2:f5; dest:f7; op1val:0x8000000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f7, f6, f5, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f5, rs2==f7, rd==f6,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f5; op2:f7; dest:f6; op1val:0x8000000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f6, f5, f7, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f7, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f7; op2:f6; dest:f5; op1val:0x8000000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f5, f7, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rs2==f2, rd==f4,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f3; op2:f2; dest:f4; op1val:0x8000000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f4, f3, f2, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f2; op2:f4; dest:f3; op1val:0x8000000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f4, rs2==f3, rd==f2,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f4; op2:f3; dest:f2; op1val:0x8000000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f2, f4, f3, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f1,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f1; op2:f30; dest:f31; op1val:0x8000000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f1, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f0; op2:f30; dest:f31; op1val:0x8000000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f0, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f1,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f1; dest:f31; op1val:0x8000000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f1, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rs2==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f0; dest:f31; op1val:0x8000000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f0, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// rd==f1,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f31; op2:f30; dest:f1; op1val:0x8000000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f1, f31, f30, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// rd==f0,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f31; op2:f30; dest:f0; op1val:0x8000000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f0, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:72*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:74*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:76*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:78*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:80*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:82*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:84*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:86*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:88*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:90*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:92*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:94*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x0;
-   valaddr_reg:x3; val_offset:96*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:98*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x1;
-   valaddr_reg:x3; val_offset:100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x2;
-   valaddr_reg:x3; val_offset:104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x0;
-   valaddr_reg:x3; val_offset:192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x1;
-   valaddr_reg:x3; val_offset:196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x2;
-   valaddr_reg:x3; val_offset:200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x0;
-   valaddr_reg:x3; val_offset:240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x1;
-   valaddr_reg:x3; val_offset:244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x2;
-   valaddr_reg:x3; val_offset:248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000000000000002; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x0;
-   valaddr_reg:x3; val_offset:480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x1;
-   valaddr_reg:x3; val_offset:484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x2;
-   valaddr_reg:x3; val_offset:488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x10000000000002; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x0;
-   valaddr_reg:x3; val_offset:528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x1;
-   valaddr_reg:x3; val_offset:532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x2;
-   valaddr_reg:x3; val_offset:536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8010000000000002; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fefffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefffffffffffff; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff8000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff8000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:990*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:992*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:994*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:996*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:998*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1000*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1002*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1004*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1006*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:1008*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:1010*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:1012*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:1014*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:1016*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:1018*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:1020*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:1022*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:1024*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:1026*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:1028*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:1030*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:1032*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:1034*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1036*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1038*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:1040*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:1042*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:1044*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:1046*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1048*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1050*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1052*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000001; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1054*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1056*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:1058*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1060*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:1062*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1064*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:1066*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:1068*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:1070*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:1072*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:1074*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:1076*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:1078*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:1080*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:1082*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1084*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1086*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:1088*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:1090*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:1092*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:1094*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1096*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1098*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff0000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:1106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:1110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8000000000000002;
-   valaddr_reg:x3; val_offset:1114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfffffffffffff;
-   valaddr_reg:x3; val_offset:1116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x800fffffffffffff;
-   valaddr_reg:x3; val_offset:1118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x10000000000000;
-   valaddr_reg:x3; val_offset:1120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8010000000000000;
-   valaddr_reg:x3; val_offset:1122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x10000000000002;
-   valaddr_reg:x3; val_offset:1124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x0000000000002 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x8010000000000002;
-   valaddr_reg:x3; val_offset:1126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7fefffffffffffff;
-   valaddr_reg:x3; val_offset:1128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xfffffffffffff and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xffefffffffffffff;
-   valaddr_reg:x3; val_offset:1130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff8000000000000;
-   valaddr_reg:x3; val_offset:1136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff8000000000000;
-   valaddr_reg:x3; val_offset:1138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff8000000000001;
-   valaddr_reg:x3; val_offset:1140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x8000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff8000000000001;
-   valaddr_reg:x3; val_offset:1142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x7ff0000000000001;
-   valaddr_reg:x3; val_offset:1144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xfff0000000000001;
-   valaddr_reg:x3; val_offset:1146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0x3ff0000000000000;
-   valaddr_reg:x3; val_offset:1148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3f8 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbf80000000000000; op2val:0xbf80000000000000;
-   valaddr_reg:x3; val_offset:1150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x8000000000000000;
-   valaddr_reg:x3; val_offset:1152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0000000000001 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x8000000000000001;
-   valaddr_reg:x3; val_offset:1154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
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-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 132*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b19-01.S
deleted file mode 100644
index 557890ecf..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fminm.d_b19-01.S
+++ /dev/null
@@ -1,11109 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:11:12 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fminm.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fminm.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fminm.d_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fminm.d_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f30, rs2==f29, rd==f31,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rs2 != rd, rs1==f31, rs2==f31, rd==f30,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f31; op2:f31; dest:f30; op1val:0x7feb0580f98a7dbd; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f30, f31, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs2 == rd != rs1, rs1==f29, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f29; op2:f28; dest:f28; op1val:0x7fb59e00c7a1fe31; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f28, f29, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 == rs2 == rd, rs1==f27, rs2==f27, rd==f27,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x59e00c7a1fe31 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f27; op2:f27; dest:f27; op1val:0x7ff0000000000000; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f27, f27, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rd != rs2, rs1==f26, rs2==f30, rd==f26,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f26; op2:f30; dest:f26; op1val:0x7fb59e00c7a1fe31; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f26, f26, f30, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f28, rs2==f26, rd==f29,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x59e00c7a1fe31 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f28; op2:f26; dest:f29; op1val:0x7feb0580f98a7dbd; op2val:0x7fb59e00c7a1fe31;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f29, f28, f26, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f23, rd==f25,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f24; op2:f23; dest:f25; op1val:0x7feb0580f98a7dbd; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f25, f24, f23, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f23, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f23; op2:f25; dest:f24; op1val:0x7fb59e00c7a1fe31; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f24, f23, f25, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f25, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f25; op2:f24; dest:f23; op1val:0x7feb0580f98a7dbd; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f23, f25, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rs2==f20, rd==f22,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f21; op2:f20; dest:f22; op1val:0x7fb59e00c7a1fe31; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f22, f21, f20, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f20; op2:f22; dest:f21; op1val:0x7feb0580f98a7dbd; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f22, rs2==f21, rd==f20,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f22; op2:f21; dest:f20; op1val:0x7fed1ca42e21585b; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f20, f22, f21, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f17, rd==f19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f18; op2:f17; dest:f19; op1val:0x7feb0580f98a7dbd; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f19, f18, f17, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f17, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f17; op2:f19; dest:f18; op1val:0x7fb59e00c7a1fe31; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f18, f17, f19, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f19, rs2==f18, rd==f17,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x59e00c7a1fe31 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f19; op2:f18; dest:f17; op1val:0xfff0000000000000; op2val:0x7fb59e00c7a1fe31;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f17, f19, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rs2==f14, rd==f16,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f15; op2:f14; dest:f16; op1val:0x7fb59e00c7a1fe31; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f16, f15, f14, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f14; op2:f16; dest:f15; op1val:0x7feb0580f98a7dbd; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f16, rs2==f15, rd==f14,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f16; op2:f15; dest:f14; op1val:0xffe30ac79053ba62; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f14, f16, f15, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f11, rd==f13,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f12; op2:f11; dest:f13; op1val:0x7feb0580f98a7dbd; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f13, f12, f11, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f11, rs2==f13, rd==f12,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f11; op2:f13; dest:f12; op1val:0x7fb59e00c7a1fe31; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f12, f11, f13, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f13, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f13; op2:f12; dest:f11; op1val:0x7feb0580f98a7dbd; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f11, f13, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rs2==f8, rd==f10,fs1 == 0 and fe1 == 0x7fb and fm1 == 0x59e00c7a1fe31 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f9; op2:f8; dest:f10; op1val:0x7fb59e00c7a1fe31; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f10, f9, f8, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f8; op2:f10; dest:f9; op1val:0x7feb0580f98a7dbd; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f10, rs2==f9, rd==f8,fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x14b33d2e7fe8d and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f10; op2:f9; dest:f8; op1val:0x7f814b33d2e7fe8d; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f8, f10, f9, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f5, rd==f7,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x14b33d2e7fe8d and  fcsr == 0  
-/* opcode: fminm.d ; op1:f6; op2:f5; dest:f7; op1val:0xfff0000000000000; op2val:0x7f814b33d2e7fe8d;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f7, f6, f5, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f5, rs2==f7, rd==f6,fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x14b33d2e7fe8d and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f5; op2:f7; dest:f6; op1val:0x7f814b33d2e7fe8d; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f6, f5, f7, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f7, rs2==f6, rd==f5,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x14b33d2e7fe8d and  fcsr == 0  
-/* opcode: fminm.d ; op1:f7; op2:f6; dest:f5; op1val:0x7feb0580f98a7dbd; op2val:0x7f814b33d2e7fe8d;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f5, f7, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rs2==f2, rd==f4,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f3; op2:f2; dest:f4; op1val:0x7feb0580f98a7dbd; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f4, f3, f2, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x000 and fm1 == 0x11770f6c9c8eb and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f2; op2:f4; dest:f3; op1val:0x11770f6c9c8eb; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f4, rs2==f3, rd==f2,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x11770f6c9c8eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f4; op2:f3; dest:f2; op1val:0x7ff0000000000000; op2val:0x11770f6c9c8eb;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f2, f4, f3, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f1,fs1 == 0 and fe1 == 0x000 and fm1 == 0x11770f6c9c8eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f1; op2:f30; dest:f31; op1val:0x11770f6c9c8eb; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f1, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f0,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0x11770f6c9c8eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f0; op2:f30; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x11770f6c9c8eb;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f0, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f1,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f1; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f1, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rs2==f0,fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xf0b5e103c0954 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f0; dest:f31; op1val:0xaea69a3e1d929; op2val:0x7fef0b5e103c0954;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f0, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// rd==f1,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xf0b5e103c0954 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f31; op2:f30; dest:f1; op1val:0x7fef0b5e103c0954; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f1, f31, f30, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// rd==f0,fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f31; op2:f30; dest:f0; op1val:0xaea69a3e1d929; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f0, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:72*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:74*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:76*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:78*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:80*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:82*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x87dfc3c4343fa and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0x7fe87dfc3c4343fa;
-   valaddr_reg:x3; val_offset:84*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x87dfc3c4343fa and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe87dfc3c4343fa; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:86*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:88*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:90*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:92*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:94*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd5a40c379c682 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0xffed5a40c379c682;
-   valaddr_reg:x3; val_offset:96*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd5a40c379c682 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed5a40c379c682; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:98*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb9818fe1eccda and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0xffeb9818fe1eccda;
-   valaddr_reg:x3; val_offset:104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb9818fe1eccda and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffeb9818fe1eccda; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x39e41023e1389 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0xffe39e41023e1389;
-   valaddr_reg:x3; val_offset:112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x39e41023e1389 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe39e41023e1389; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xdaf87e09a11da and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0xffedaf87e09a11da;
-   valaddr_reg:x3; val_offset:120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xdaf87e09a11da and fs2 == 0 and fe2 == 0x000 and fm2 == 0xaea69a3e1d929 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffedaf87e09a11da; op2val:0xaea69a3e1d929;
-   valaddr_reg:x3; val_offset:122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xaea69a3e1d929 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xaea69a3e1d929; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x11770f6c9c8eb and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x11770f6c9c8eb; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x11770f6c9c8eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x11770f6c9c8eb;
-   valaddr_reg:x3; val_offset:130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x11770f6c9c8eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x11770f6c9c8eb; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x0;
-   valaddr_reg:x3; val_offset:134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x849c649169268 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff849c649169268; op2val:0x0;
-   valaddr_reg:x3; val_offset:136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x849c649169268 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ff849c649169268;
-   valaddr_reg:x3; val_offset:138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x849c649169268 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x3ff849c649169268;
-   valaddr_reg:x3; val_offset:140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x74a1cf1b446af and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7fb74a1cf1b446af;
-   valaddr_reg:x3; val_offset:160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xe77a5b3b92a36 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xffae77a5b3b92a36;
-   valaddr_reg:x3; val_offset:172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xa2d6149828b3c and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x608daef2c2520 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7faa2d6149828b3c; op2val:0xffc608daef2c2520;
-   valaddr_reg:x3; val_offset:188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xa2d6149828b3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0x7faa2d6149828b3c;
-   valaddr_reg:x3; val_offset:190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xa2d6149828b3c and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7faa2d6149828b3c; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xa2d6149828b3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x7faa2d6149828b3c;
-   valaddr_reg:x3; val_offset:194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x69bf113fe2b81 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x0a8686b58e06e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x69bf113fe2b81; op2val:0x7fe0a8686b58e06e;
-   valaddr_reg:x3; val_offset:198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x69bf113fe2b81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x69bf113fe2b81;
-   valaddr_reg:x3; val_offset:200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x69bf113fe2b81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x69bf113fe2b81; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x69bf113fe2b81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x69bf113fe2b81;
-   valaddr_reg:x3; val_offset:204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8d5e4d9c9a110 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x7fb8d5e4d9c9a110;
-   valaddr_reg:x3; val_offset:208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xcc6497dd9aeac and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x7fbcc6497dd9aeac;
-   valaddr_reg:x3; val_offset:218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x397fcfd029cc8 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x7fb397fcfd029cc8;
-   valaddr_reg:x3; val_offset:226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x9ac314c1e5de7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x7fb9ac314c1e5de7;
-   valaddr_reg:x3; val_offset:234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x77b6702c7d202 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0xffb77b6702c7d202;
-   valaddr_reg:x3; val_offset:242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x6134731b23d7b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0xffb6134731b23d7b;
-   valaddr_reg:x3; val_offset:250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf639b36c9b8db and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0xffaf639b36c9b8db;
-   valaddr_reg:x3; val_offset:258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7bf9fe6e1a7e1 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0xffb7bf9fe6e1a7e1;
-   valaddr_reg:x3; val_offset:266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x085dab1fb6cc3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x3085dab1fb6cc3;
-   valaddr_reg:x3; val_offset:268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x085dab1fb6cc3 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3085dab1fb6cc3; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x69bf113fe2b81 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xefff2c6cde040 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x69bf113fe2b81; op2val:0xffbefff2c6cde040;
-   valaddr_reg:x3; val_offset:274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x69bf113fe2b81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x69bf113fe2b81;
-   valaddr_reg:x3; val_offset:276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x69bf113fe2b81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x69bf113fe2b81; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x0;
-   valaddr_reg:x3; val_offset:280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 0 and fe1 == 0x402 and fm1 == 0x261de7cadff67 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x402261de7cadff67; op2val:0x0;
-   valaddr_reg:x3; val_offset:282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x261de7cadff67 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x402261de7cadff67;
-   valaddr_reg:x3; val_offset:284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x261de7cadff67 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe05c5ccdf19706; op2val:0x402261de7cadff67;
-   valaddr_reg:x3; val_offset:286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0x866da024aa0c9 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x608daef2c2520 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fa866da024aa0c9; op2val:0xffc608daef2c2520;
-   valaddr_reg:x3; val_offset:316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 0 and fe2 == 0x7fa and fm2 == 0x866da024aa0c9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0x7fa866da024aa0c9;
-   valaddr_reg:x3; val_offset:318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0x866da024aa0c9 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fa866da024aa0c9; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x7fa and fm2 == 0x866da024aa0c9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x7fa866da024aa0c9;
-   valaddr_reg:x3; val_offset:322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6292f14fe32c9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x0a8686b58e06e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6292f14fe32c9; op2val:0x7fe0a8686b58e06e;
-   valaddr_reg:x3; val_offset:326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6292f14fe32c9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x6292f14fe32c9;
-   valaddr_reg:x3; val_offset:328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6292f14fe32c9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6292f14fe32c9; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6292f14fe32c9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x6292f14fe32c9;
-   valaddr_reg:x3; val_offset:332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8d5e4d9c9a110 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x7fb8d5e4d9c9a110;
-   valaddr_reg:x3; val_offset:336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xcc6497dd9aeac and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x7fbcc6497dd9aeac;
-   valaddr_reg:x3; val_offset:346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x397fcfd029cc8 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x7fb397fcfd029cc8;
-   valaddr_reg:x3; val_offset:354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x9ac314c1e5de7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x7fb9ac314c1e5de7;
-   valaddr_reg:x3; val_offset:362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x77b6702c7d202 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0xffb77b6702c7d202;
-   valaddr_reg:x3; val_offset:370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x6134731b23d7b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0xffb6134731b23d7b;
-   valaddr_reg:x3; val_offset:378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf639b36c9b8db and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0xffaf639b36c9b8db;
-   valaddr_reg:x3; val_offset:386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7bf9fe6e1a7e1 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0xffb7bf9fe6e1a7e1;
-   valaddr_reg:x3; val_offset:394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 0 and fe2 == 0x002 and fm2 == 0xecdeb68f6fdee and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x2ecdeb68f6fdee;
-   valaddr_reg:x3; val_offset:396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0xecdeb68f6fdee and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x2ecdeb68f6fdee; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6292f14fe32c9 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xefff2c6cde040 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6292f14fe32c9; op2val:0xffbefff2c6cde040;
-   valaddr_reg:x3; val_offset:402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6292f14fe32c9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x6292f14fe32c9;
-   valaddr_reg:x3; val_offset:404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6292f14fe32c9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6292f14fe32c9; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x0;
-   valaddr_reg:x3; val_offset:408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0x402 and fm1 == 0x122b0391ed653 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x402122b0391ed653; op2val:0x0;
-   valaddr_reg:x3; val_offset:410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x122b0391ed653 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x402122b0391ed653;
-   valaddr_reg:x3; val_offset:412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x402 and fm2 == 0x122b0391ed653 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fde809082dd48fb; op2val:0x402122b0391ed653;
-   valaddr_reg:x3; val_offset:414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 0 and fe1 == 0x7f9 and fm1 == 0xcdc35c1c9eb3f and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x608daef2c2520 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f9cdc35c1c9eb3f; op2val:0xffc608daef2c2520;
-   valaddr_reg:x3; val_offset:440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 0 and fe2 == 0x7f9 and fm2 == 0xcdc35c1c9eb3f and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0x7f9cdc35c1c9eb3f;
-   valaddr_reg:x3; val_offset:442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 0 and fe1 == 0x7f9 and fm1 == 0xcdc35c1c9eb3f and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f9cdc35c1c9eb3f; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x7f9 and fm2 == 0xcdc35c1c9eb3f and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x7f9cdc35c1c9eb3f;
-   valaddr_reg:x3; val_offset:446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3a4acd3b9460c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x0a8686b58e06e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3a4acd3b9460c; op2val:0x7fe0a8686b58e06e;
-   valaddr_reg:x3; val_offset:450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3a4acd3b9460c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x3a4acd3b9460c;
-   valaddr_reg:x3; val_offset:452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3a4acd3b9460c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3a4acd3b9460c; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3a4acd3b9460c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x3a4acd3b9460c;
-   valaddr_reg:x3; val_offset:456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8d5e4d9c9a110 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x7fb8d5e4d9c9a110;
-   valaddr_reg:x3; val_offset:460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xcc6497dd9aeac and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x7fbcc6497dd9aeac;
-   valaddr_reg:x3; val_offset:470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x397fcfd029cc8 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x7fb397fcfd029cc8;
-   valaddr_reg:x3; val_offset:478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x9ac314c1e5de7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x7fb9ac314c1e5de7;
-   valaddr_reg:x3; val_offset:486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x77b6702c7d202 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0xffb77b6702c7d202;
-   valaddr_reg:x3; val_offset:494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x6134731b23d7b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0xffb6134731b23d7b;
-   valaddr_reg:x3; val_offset:502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf639b36c9b8db and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0xffaf639b36c9b8db;
-   valaddr_reg:x3; val_offset:510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7bf9fe6e1a7e1 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0xffb7bf9fe6e1a7e1;
-   valaddr_reg:x3; val_offset:518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 0 and fe2 == 0x002 and fm2 == 0x23760229e5e3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x223760229e5e3c;
-   valaddr_reg:x3; val_offset:520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 0 and fe1 == 0x002 and fm1 == 0x23760229e5e3c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x223760229e5e3c; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3a4acd3b9460c and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xefff2c6cde040 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3a4acd3b9460c; op2val:0xffbefff2c6cde040;
-   valaddr_reg:x3; val_offset:526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x3a4acd3b9460c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x3a4acd3b9460c;
-   valaddr_reg:x3; val_offset:528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x3a4acd3b9460c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3a4acd3b9460c; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x0;
-   valaddr_reg:x3; val_offset:532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 0 and fe1 == 0x401 and fm1 == 0x4442d6ffe75f4 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x4014442d6ffe75f4; op2val:0x0;
-   valaddr_reg:x3; val_offset:534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x401 and fm2 == 0x4442d6ffe75f4 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x4014442d6ffe75f4;
-   valaddr_reg:x3; val_offset:536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 0 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x401 and fm2 == 0x4442d6ffe75f4 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fd209a1991e3307; op2val:0x4014442d6ffe75f4;
-   valaddr_reg:x3; val_offset:538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x74a1cf1b446af and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x7fb74a1cf1b446af;
-   valaddr_reg:x3; val_offset:546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x74a1cf1b446af and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7fb74a1cf1b446af;
-   valaddr_reg:x3; val_offset:560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x74a1cf1b446af and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb74a1cf1b446af; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x2a1b0c15d0559 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f82a1b0c15d0559; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x2a1b0c15d0559 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7f82a1b0c15d0559;
-   valaddr_reg:x3; val_offset:580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x2a1b0c15d0559 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f82a1b0c15d0559; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x2a1b0c15d0559 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x7f82a1b0c15d0559;
-   valaddr_reg:x3; val_offset:584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x12d0f0ec06819 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x12d0f0ec06819; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x12d0f0ec06819 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x12d0f0ec06819;
-   valaddr_reg:x3; val_offset:590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x12d0f0ec06819 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x12d0f0ec06819; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x12d0f0ec06819 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x12d0f0ec06819;
-   valaddr_reg:x3; val_offset:594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xf0b5e103c0954 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x7fef0b5e103c0954;
-   valaddr_reg:x3; val_offset:598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xf0b5e103c0954 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fef0b5e103c0954; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x87dfc3c4343fa and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x7fe87dfc3c4343fa;
-   valaddr_reg:x3; val_offset:616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x87dfc3c4343fa and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe87dfc3c4343fa; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd5a40c379c682 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0xffed5a40c379c682;
-   valaddr_reg:x3; val_offset:628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd5a40c379c682 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed5a40c379c682; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb9818fe1eccda and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0xffeb9818fe1eccda;
-   valaddr_reg:x3; val_offset:636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb9818fe1eccda and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffeb9818fe1eccda; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x39e41023e1389 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0xffe39e41023e1389;
-   valaddr_reg:x3; val_offset:644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x39e41023e1389 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe39e41023e1389; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xdaf87e09a11da and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0xffedaf87e09a11da;
-   valaddr_reg:x3; val_offset:652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xdaf87e09a11da and fs2 == 0 and fe2 == 0x000 and fm2 == 0xbc296938410f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffedaf87e09a11da; op2val:0xbc296938410f6;
-   valaddr_reg:x3; val_offset:654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xbc296938410f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbc296938410f6; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x12d0f0ec06819 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x12d0f0ec06819; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x12d0f0ec06819 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x12d0f0ec06819;
-   valaddr_reg:x3; val_offset:662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x12d0f0ec06819 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x12d0f0ec06819; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x0;
-   valaddr_reg:x3; val_offset:666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xa2ac7f4a5aece and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ffa2ac7f4a5aece; op2val:0x0;
-   valaddr_reg:x3; val_offset:668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xa2ac7f4a5aece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ffa2ac7f4a5aece;
-   valaddr_reg:x3; val_offset:670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xa2ac7f4a5aece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fed1ca42e21585b; op2val:0x3ffa2ac7f4a5aece;
-   valaddr_reg:x3; val_offset:672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xe77a5b3b92a36 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffae77a5b3b92a36;
-   valaddr_reg:x3; val_offset:688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x8c9148167a613 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x608daef2c2520 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff98c9148167a613; op2val:0xffc608daef2c2520;
-   valaddr_reg:x3; val_offset:704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x8c9148167a613 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0xff98c9148167a613;
-   valaddr_reg:x3; val_offset:706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x8c9148167a613 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff98c9148167a613; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x8c9148167a613 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xff98c9148167a613;
-   valaddr_reg:x3; val_offset:710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x320fdfdfa4c3c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x0a8686b58e06e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800320fdfdfa4c3c; op2val:0x7fe0a8686b58e06e;
-   valaddr_reg:x3; val_offset:714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x320fdfdfa4c3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x800320fdfdfa4c3c;
-   valaddr_reg:x3; val_offset:716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x320fdfdfa4c3c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800320fdfdfa4c3c; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x320fdfdfa4c3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x800320fdfdfa4c3c;
-   valaddr_reg:x3; val_offset:720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8d5e4d9c9a110 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x7fb8d5e4d9c9a110;
-   valaddr_reg:x3; val_offset:724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xcc6497dd9aeac and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x7fbcc6497dd9aeac;
-   valaddr_reg:x3; val_offset:734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x397fcfd029cc8 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x7fb397fcfd029cc8;
-   valaddr_reg:x3; val_offset:742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x9ac314c1e5de7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x7fb9ac314c1e5de7;
-   valaddr_reg:x3; val_offset:750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x77b6702c7d202 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0xffb77b6702c7d202;
-   valaddr_reg:x3; val_offset:758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x6134731b23d7b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0xffb6134731b23d7b;
-   valaddr_reg:x3; val_offset:766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf639b36c9b8db and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0xffaf639b36c9b8db;
-   valaddr_reg:x3; val_offset:774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7bf9fe6e1a7e1 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0xffb7bf9fe6e1a7e1;
-   valaddr_reg:x3; val_offset:782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf49ebebc6fa5a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x801f49ebebc6fa5a;
-   valaddr_reg:x3; val_offset:784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf49ebebc6fa5a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f49ebebc6fa5a; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x320fdfdfa4c3c and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xefff2c6cde040 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800320fdfdfa4c3c; op2val:0xffbefff2c6cde040;
-   valaddr_reg:x3; val_offset:790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x320fdfdfa4c3c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x800320fdfdfa4c3c;
-   valaddr_reg:x3; val_offset:792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x320fdfdfa4c3c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800320fdfdfa4c3c; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0x0;
-   valaddr_reg:x3; val_offset:796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 1 and fe1 == 0x401 and fm1 == 0x167aab18a177e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc01167aab18a177e; op2val:0x0;
-   valaddr_reg:x3; val_offset:798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x167aab18a177e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc01167aab18a177e;
-   valaddr_reg:x3; val_offset:800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xefb59a1c18f98 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x167aab18a177e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcefb59a1c18f98; op2val:0xc01167aab18a177e;
-   valaddr_reg:x3; val_offset:802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xe77a5b3b92a36 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xffae77a5b3b92a36;
-   valaddr_reg:x3; val_offset:810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xe77a5b3b92a36 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffae77a5b3b92a36; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0x85fb7c2fa882b and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff785fb7c2fa882b; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0x85fb7c2fa882b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0xff785fb7c2fa882b;
-   valaddr_reg:x3; val_offset:836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0x85fb7c2fa882b and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff785fb7c2fa882b; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0x85fb7c2fa882b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xff785fb7c2fa882b;
-   valaddr_reg:x3; val_offset:840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c4ec3fe9a819 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000c4ec3fe9a819; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0c4ec3fe9a819 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8000c4ec3fe9a819;
-   valaddr_reg:x3; val_offset:846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c4ec3fe9a819 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000c4ec3fe9a819; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0c4ec3fe9a819 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x8000c4ec3fe9a819;
-   valaddr_reg:x3; val_offset:850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xf0b5e103c0954 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x7fef0b5e103c0954;
-   valaddr_reg:x3; val_offset:854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xf0b5e103c0954 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fef0b5e103c0954; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x87dfc3c4343fa and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x7fe87dfc3c4343fa;
-   valaddr_reg:x3; val_offset:872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x87dfc3c4343fa and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe87dfc3c4343fa; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd5a40c379c682 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0xffed5a40c379c682;
-   valaddr_reg:x3; val_offset:884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd5a40c379c682 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed5a40c379c682; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb9818fe1eccda and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0xffeb9818fe1eccda;
-   valaddr_reg:x3; val_offset:892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb9818fe1eccda and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffeb9818fe1eccda; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x39e41023e1389 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0xffe39e41023e1389;
-   valaddr_reg:x3; val_offset:900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x39e41023e1389 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe39e41023e1389; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xdaf87e09a11da and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0xffedaf87e09a11da;
-   valaddr_reg:x3; val_offset:908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xdaf87e09a11da and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7b13a7f2090fc and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffedaf87e09a11da; op2val:0x8007b13a7f2090fc;
-   valaddr_reg:x3; val_offset:910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7b13a7f2090fc and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007b13a7f2090fc; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c4ec3fe9a819 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000c4ec3fe9a819; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0c4ec3fe9a819 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfff0000000000000; op2val:0x8000c4ec3fe9a819;
-   valaddr_reg:x3; val_offset:918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0c4ec3fe9a819 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000c4ec3fe9a819; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0x0;
-   valaddr_reg:x3; val_offset:922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x11dadc9e4eb85 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbff11dadc9e4eb85; op2val:0x0;
-   valaddr_reg:x3; val_offset:924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x11dadc9e4eb85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbff11dadc9e4eb85;
-   valaddr_reg:x3; val_offset:926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x30ac79053ba62 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x11dadc9e4eb85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe30ac79053ba62; op2val:0xbff11dadc9e4eb85;
-   valaddr_reg:x3; val_offset:928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x554b1e717e738 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x608daef2c2520 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffa554b1e717e738; op2val:0xffc608daef2c2520;
-   valaddr_reg:x3; val_offset:946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x554b1e717e738 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0xffa554b1e717e738;
-   valaddr_reg:x3; val_offset:948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0x554b1e717e738 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffa554b1e717e738; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0x554b1e717e738 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xffa554b1e717e738;
-   valaddr_reg:x3; val_offset:952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x562b29f60d7ba and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x0a8686b58e06e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800562b29f60d7ba; op2val:0x7fe0a8686b58e06e;
-   valaddr_reg:x3; val_offset:956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x562b29f60d7ba and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x800562b29f60d7ba;
-   valaddr_reg:x3; val_offset:958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x562b29f60d7ba and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800562b29f60d7ba; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x562b29f60d7ba and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x800562b29f60d7ba;
-   valaddr_reg:x3; val_offset:962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8d5e4d9c9a110 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x7fb8d5e4d9c9a110;
-   valaddr_reg:x3; val_offset:966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xcc6497dd9aeac and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x7fbcc6497dd9aeac;
-   valaddr_reg:x3; val_offset:976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x397fcfd029cc8 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x7fb397fcfd029cc8;
-   valaddr_reg:x3; val_offset:984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:990*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x9ac314c1e5de7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x7fb9ac314c1e5de7;
-   valaddr_reg:x3; val_offset:992*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:994*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:996*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:998*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x77b6702c7d202 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0xffb77b6702c7d202;
-   valaddr_reg:x3; val_offset:1000*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:1002*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1004*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1006*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x6134731b23d7b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0xffb6134731b23d7b;
-   valaddr_reg:x3; val_offset:1008*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:1010*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1012*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1014*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf639b36c9b8db and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0xffaf639b36c9b8db;
-   valaddr_reg:x3; val_offset:1016*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:1018*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1020*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1022*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7bf9fe6e1a7e1 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0xffb7bf9fe6e1a7e1;
-   valaddr_reg:x3; val_offset:1024*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 1 and fe2 == 0x002 and fm2 == 0xaed7d1ce436a0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x802aed7d1ce436a0;
-   valaddr_reg:x3; val_offset:1026*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0x002 and fm1 == 0xaed7d1ce436a0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x802aed7d1ce436a0; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1028*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1030*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x562b29f60d7ba and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xefff2c6cde040 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800562b29f60d7ba; op2val:0xffbefff2c6cde040;
-   valaddr_reg:x3; val_offset:1032*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x562b29f60d7ba and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x800562b29f60d7ba;
-   valaddr_reg:x3; val_offset:1034*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x562b29f60d7ba and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800562b29f60d7ba; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1036*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0x0;
-   valaddr_reg:x3; val_offset:1038*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0x401 and fm1 == 0xdf542c221f050 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc01df542c221f050; op2val:0x0;
-   valaddr_reg:x3; val_offset:1040*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0xdf542c221f050 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc01df542c221f050;
-   valaddr_reg:x3; val_offset:1042*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaa9de60dde106 and fs2 == 1 and fe2 == 0x401 and fm2 == 0xdf542c221f050 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffdaa9de60dde106; op2val:0xc01df542c221f050;
-   valaddr_reg:x3; val_offset:1044*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1046*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1048*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1050*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1052*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1054*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1056*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x901723ec94233 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x608daef2c2520 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff9901723ec94233; op2val:0xffc608daef2c2520;
-   valaddr_reg:x3; val_offset:1058*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x901723ec94233 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0xff9901723ec94233;
-   valaddr_reg:x3; val_offset:1060*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x901723ec94233 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff9901723ec94233; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1062*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x901723ec94233 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xff9901723ec94233;
-   valaddr_reg:x3; val_offset:1064*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1066*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x3281b93f72b1c and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x0a8686b58e06e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8003281b93f72b1c; op2val:0x7fe0a8686b58e06e;
-   valaddr_reg:x3; val_offset:1068*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x3281b93f72b1c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x8003281b93f72b1c;
-   valaddr_reg:x3; val_offset:1070*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x3281b93f72b1c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8003281b93f72b1c; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1072*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x3281b93f72b1c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x8003281b93f72b1c;
-   valaddr_reg:x3; val_offset:1074*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1076*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8d5e4d9c9a110 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x7fb8d5e4d9c9a110;
-   valaddr_reg:x3; val_offset:1078*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1080*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1082*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1084*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1086*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xcc6497dd9aeac and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x7fbcc6497dd9aeac;
-   valaddr_reg:x3; val_offset:1088*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1090*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1092*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1094*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x397fcfd029cc8 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x7fb397fcfd029cc8;
-   valaddr_reg:x3; val_offset:1096*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1098*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x9ac314c1e5de7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x7fb9ac314c1e5de7;
-   valaddr_reg:x3; val_offset:1104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x77b6702c7d202 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0xffb77b6702c7d202;
-   valaddr_reg:x3; val_offset:1112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x6134731b23d7b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0xffb6134731b23d7b;
-   valaddr_reg:x3; val_offset:1120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf639b36c9b8db and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0xffaf639b36c9b8db;
-   valaddr_reg:x3; val_offset:1128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7bf9fe6e1a7e1 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0xffb7bf9fe6e1a7e1;
-   valaddr_reg:x3; val_offset:1136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 1 and fe2 == 0x001 and fm2 == 0xf9113c7a7af1a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x801f9113c7a7af1a;
-   valaddr_reg:x3; val_offset:1138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0xf9113c7a7af1a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801f9113c7a7af1a; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x3281b93f72b1c and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xefff2c6cde040 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8003281b93f72b1c; op2val:0xffbefff2c6cde040;
-   valaddr_reg:x3; val_offset:1144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x3281b93f72b1c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x8003281b93f72b1c;
-   valaddr_reg:x3; val_offset:1146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x3281b93f72b1c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8003281b93f72b1c; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0x0;
-   valaddr_reg:x3; val_offset:1150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 1 and fe1 == 0x401 and fm1 == 0x18f3f99f3a7ab and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc0118f3f99f3a7ab; op2val:0x0;
-   valaddr_reg:x3; val_offset:1152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x18f3f99f3a7ab and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc0118f3f99f3a7ab;
-   valaddr_reg:x3; val_offset:1154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-
-inst_578:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0xf41cece7b92c0 and fs2 == 1 and fe2 == 0x401 and fm2 == 0x18f3f99f3a7ab and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffcf41cece7b92c0; op2val:0xc0118f3f99f3a7ab;
-   valaddr_reg:x3; val_offset:1156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1156*FLEN/8, x4, x1, x2)
-
-inst_579:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1158*FLEN/8, x4, x1, x2)
-
-inst_580:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:1160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1160*FLEN/8, x4, x1, x2)
-
-inst_581:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1162*FLEN/8, x4, x1, x2)
-
-inst_582:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1164*FLEN/8, x4, x1, x2)
-
-inst_583:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1166*FLEN/8, x4, x1, x2)
-
-inst_584:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0x608daef2c2520 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xffc608daef2c2520;
-   valaddr_reg:x3; val_offset:1168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1168*FLEN/8, x4, x1, x2)
-
-inst_585:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1170*FLEN/8, x4, x1, x2)
-
-inst_586:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1172*FLEN/8, x4, x1, x2)
-
-inst_587:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1174*FLEN/8, x4, x1, x2)
-
-inst_588:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1176*FLEN/8, x4, x1, x2)
-
-inst_589:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1178*FLEN/8, x4, x1, x2)
-
-inst_590:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1180*FLEN/8, x4, x1, x2)
-
-inst_591:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1182*FLEN/8, x4, x1, x2)
-
-inst_592:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1184*FLEN/8, x4, x1, x2)
-
-inst_593:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1186*FLEN/8, x4, x1, x2)
-
-inst_594:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1188*FLEN/8, x4, x1, x2)
-
-inst_595:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1190*FLEN/8, x4, x1, x2)
-
-inst_596:
-// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x608daef2c2520 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc608daef2c2520; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1192*FLEN/8, x4, x1, x2)
-
-inst_597:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1194*FLEN/8, x4, x1, x2)
-
-inst_598:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x239ac7113abba and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xaa70d788e33e4 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800239ac7113abba; op2val:0x7faaa70d788e33e4;
-   valaddr_reg:x3; val_offset:1196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1196*FLEN/8, x4, x1, x2)
-
-inst_599:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xaa70d788e33e4 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x239ac7113abba and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7faaa70d788e33e4; op2val:0x800239ac7113abba;
-   valaddr_reg:x3; val_offset:1198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1198*FLEN/8, x4, x1, x2)
-
-inst_600:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x239ac7113abba and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800239ac7113abba; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1200*FLEN/8, x4, x1, x2)
-
-inst_601:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x239ac7113abba and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x800239ac7113abba;
-   valaddr_reg:x3; val_offset:1202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1202*FLEN/8, x4, x1, x2)
-
-inst_602:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1204*FLEN/8, x4, x1, x2)
-
-inst_603:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x3de50ae3ae740 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x7f83de50ae3ae740;
-   valaddr_reg:x3; val_offset:1206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1206*FLEN/8, x4, x1, x2)
-
-inst_604:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x3de50ae3ae740 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f83de50ae3ae740; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1208*FLEN/8, x4, x1, x2)
-
-inst_605:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1210*FLEN/8, x4, x1, x2)
-
-inst_606:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1212*FLEN/8, x4, x1, x2)
-
-inst_607:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1214*FLEN/8, x4, x1, x2)
-
-inst_608:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x7050797e15889 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x7f87050797e15889;
-   valaddr_reg:x3; val_offset:1216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1216*FLEN/8, x4, x1, x2)
-
-inst_609:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x7050797e15889 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f87050797e15889; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1218*FLEN/8, x4, x1, x2)
-
-inst_610:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1220*FLEN/8, x4, x1, x2)
-
-inst_611:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1222*FLEN/8, x4, x1, x2)
-
-inst_612:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xf5994c8042e0c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x7f7f5994c8042e0c;
-   valaddr_reg:x3; val_offset:1224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1224*FLEN/8, x4, x1, x2)
-
-inst_613:
-// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xf5994c8042e0c and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f7f5994c8042e0c; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1226*FLEN/8, x4, x1, x2)
-
-inst_614:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1228*FLEN/8, x4, x1, x2)
-
-inst_615:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1230*FLEN/8, x4, x1, x2)
-
-inst_616:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x489c109b1e4b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x7f8489c109b1e4b9;
-   valaddr_reg:x3; val_offset:1232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1232*FLEN/8, x4, x1, x2)
-
-inst_617:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x489c109b1e4b9 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f8489c109b1e4b9; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1234*FLEN/8, x4, x1, x2)
-
-inst_618:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1236*FLEN/8, x4, x1, x2)
-
-inst_619:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1238*FLEN/8, x4, x1, x2)
-
-inst_620:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x2c91f356ca801 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0xff82c91f356ca801;
-   valaddr_reg:x3; val_offset:1240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1240*FLEN/8, x4, x1, x2)
-
-inst_621:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x2c91f356ca801 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff82c91f356ca801; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1242*FLEN/8, x4, x1, x2)
-
-inst_622:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1244*FLEN/8, x4, x1, x2)
-
-inst_623:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1246*FLEN/8, x4, x1, x2)
-
-inst_624:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x1a905c15b6463 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0xff81a905c15b6463;
-   valaddr_reg:x3; val_offset:1248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1248*FLEN/8, x4, x1, x2)
-
-inst_625:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x1a905c15b6463 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff81a905c15b6463; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1250*FLEN/8, x4, x1, x2)
-
-inst_626:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1252*FLEN/8, x4, x1, x2)
-
-inst_627:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1254*FLEN/8, x4, x1, x2)
-
-inst_628:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0x91c7c2bd493e3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0xff791c7c2bd493e3;
-   valaddr_reg:x3; val_offset:1256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1256*FLEN/8, x4, x1, x2)
-
-inst_629:
-// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0x91c7c2bd493e3 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff791c7c2bd493e3; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1258*FLEN/8, x4, x1, x2)
-
-inst_630:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1260*FLEN/8, x4, x1, x2)
-
-inst_631:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1262*FLEN/8, x4, x1, x2)
-
-inst_632:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x2ffb31f1aecb4 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0xff82ffb31f1aecb4;
-   valaddr_reg:x3; val_offset:1264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1264*FLEN/8, x4, x1, x2)
-
-inst_633:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x2ffb31f1aecb4 and fs2 == 1 and fe2 == 0x001 and fm2 == 0x640bc6ac4b541 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff82ffb31f1aecb4; op2val:0x801640bc6ac4b541;
-   valaddr_reg:x3; val_offset:1266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1266*FLEN/8, x4, x1, x2)
-
-inst_634:
-// fs1 == 1 and fe1 == 0x001 and fm1 == 0x640bc6ac4b541 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x801640bc6ac4b541; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1268*FLEN/8, x4, x1, x2)
-
-inst_635:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1270*FLEN/8, x4, x1, x2)
-
-inst_636:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x239ac7113abba and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x8ccc238a4b367 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800239ac7113abba; op2val:0xff88ccc238a4b367;
-   valaddr_reg:x3; val_offset:1272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1272*FLEN/8, x4, x1, x2)
-
-inst_637:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x8ccc238a4b367 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x239ac7113abba and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff88ccc238a4b367; op2val:0x800239ac7113abba;
-   valaddr_reg:x3; val_offset:1274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1274*FLEN/8, x4, x1, x2)
-
-inst_638:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x239ac7113abba and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800239ac7113abba; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1276*FLEN/8, x4, x1, x2)
-
-inst_639:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0x0;
-   valaddr_reg:x3; val_offset:1278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1278*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_6)
-
-inst_640:
-// fs1 == 1 and fe1 == 0x400 and fm1 == 0x8c1d44531ee36 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc008c1d44531ee36; op2val:0x0;
-   valaddr_reg:x3; val_offset:1280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1280*FLEN/8, x4, x1, x2)
-
-inst_641:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x8c1d44531ee36 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc008c1d44531ee36;
-   valaddr_reg:x3; val_offset:1282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1282*FLEN/8, x4, x1, x2)
-
-inst_642:
-// fs1 == 1 and fe1 == 0x7f9 and fm1 == 0x1a0af25bcea80 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x8c1d44531ee36 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff91a0af25bcea80; op2val:0xc008c1d44531ee36;
-   valaddr_reg:x3; val_offset:1284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1284*FLEN/8, x4, x1, x2)
-
-inst_643:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1286*FLEN/8, x4, x1, x2)
-
-inst_644:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1288*FLEN/8, x4, x1, x2)
-
-inst_645:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1290*FLEN/8, x4, x1, x2)
-
-inst_646:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1292*FLEN/8, x4, x1, x2)
-
-inst_647:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1294*FLEN/8, x4, x1, x2)
-
-inst_648:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x0a8686b58e06e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7fe0a8686b58e06e;
-   valaddr_reg:x3; val_offset:1296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1296*FLEN/8, x4, x1, x2)
-
-inst_649:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1298*FLEN/8, x4, x1, x2)
-
-inst_650:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1300*FLEN/8, x4, x1, x2)
-
-inst_651:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1302*FLEN/8, x4, x1, x2)
-
-inst_652:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1304*FLEN/8, x4, x1, x2)
-
-inst_653:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1306*FLEN/8, x4, x1, x2)
-
-inst_654:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1308*FLEN/8, x4, x1, x2)
-
-inst_655:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1310*FLEN/8, x4, x1, x2)
-
-inst_656:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1312*FLEN/8, x4, x1, x2)
-
-inst_657:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1314*FLEN/8, x4, x1, x2)
-
-inst_658:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1316*FLEN/8, x4, x1, x2)
-
-inst_659:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1318*FLEN/8, x4, x1, x2)
-
-inst_660:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x0a8686b58e06e and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe0a8686b58e06e; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1320*FLEN/8, x4, x1, x2)
-
-inst_661:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1322*FLEN/8, x4, x1, x2)
-
-inst_662:
-// fs1 == 0 and fe1 == 0x7fa and fm1 == 0xaa70d788e33e4 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7faaa70d788e33e4; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1324*FLEN/8, x4, x1, x2)
-
-inst_663:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x7fa and fm2 == 0xaa70d788e33e4 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x7faaa70d788e33e4;
-   valaddr_reg:x3; val_offset:1326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1326*FLEN/8, x4, x1, x2)
-
-inst_664:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1328*FLEN/8, x4, x1, x2)
-
-inst_665:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1410b3d2a7d0c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x1410b3d2a7d0c;
-   valaddr_reg:x3; val_offset:1330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1330*FLEN/8, x4, x1, x2)
-
-inst_666:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1410b3d2a7d0c and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1410b3d2a7d0c; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1332*FLEN/8, x4, x1, x2)
-
-inst_667:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1334*FLEN/8, x4, x1, x2)
-
-inst_668:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1336*FLEN/8, x4, x1, x2)
-
-inst_669:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1338*FLEN/8, x4, x1, x2)
-
-inst_670:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x173f689a4c8c6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x173f689a4c8c6;
-   valaddr_reg:x3; val_offset:1340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1340*FLEN/8, x4, x1, x2)
-
-inst_671:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x173f689a4c8c6 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x173f689a4c8c6; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1342*FLEN/8, x4, x1, x2)
-
-inst_672:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1344*FLEN/8, x4, x1, x2)
-
-inst_673:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1346*FLEN/8, x4, x1, x2)
-
-inst_674:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0fd48b05c2121 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0xfd48b05c2121;
-   valaddr_reg:x3; val_offset:1348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1348*FLEN/8, x4, x1, x2)
-
-inst_675:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fd48b05c2121 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfd48b05c2121; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1350*FLEN/8, x4, x1, x2)
-
-inst_676:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1352*FLEN/8, x4, x1, x2)
-
-inst_677:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1354*FLEN/8, x4, x1, x2)
-
-inst_678:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0x14bdd6f520473 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x14bdd6f520473;
-   valaddr_reg:x3; val_offset:1356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1356*FLEN/8, x4, x1, x2)
-
-inst_679:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x14bdd6f520473 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x14bdd6f520473; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1358*FLEN/8, x4, x1, x2)
-
-inst_680:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1360*FLEN/8, x4, x1, x2)
-
-inst_681:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1362*FLEN/8, x4, x1, x2)
-
-inst_682:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x12f8c3601c4a9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x80012f8c3601c4a9;
-   valaddr_reg:x3; val_offset:1364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1364*FLEN/8, x4, x1, x2)
-
-inst_683:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12f8c3601c4a9 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80012f8c3601c4a9; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1366*FLEN/8, x4, x1, x2)
-
-inst_684:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1368*FLEN/8, x4, x1, x2)
-
-inst_685:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1370*FLEN/8, x4, x1, x2)
-
-inst_686:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x11d5cf49b3fa7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x80011d5cf49b3fa7;
-   valaddr_reg:x3; val_offset:1372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1372*FLEN/8, x4, x1, x2)
-
-inst_687:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11d5cf49b3fa7 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80011d5cf49b3fa7; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1374*FLEN/8, x4, x1, x2)
-
-inst_688:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1376*FLEN/8, x4, x1, x2)
-
-inst_689:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1378*FLEN/8, x4, x1, x2)
-
-inst_690:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0cae158f8de83 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x8000cae158f8de83;
-   valaddr_reg:x3; val_offset:1380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1380*FLEN/8, x4, x1, x2)
-
-inst_691:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0cae158f8de83 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000cae158f8de83; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1382*FLEN/8, x4, x1, x2)
-
-inst_692:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1384*FLEN/8, x4, x1, x2)
-
-inst_693:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1386*FLEN/8, x4, x1, x2)
-
-inst_694:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0x132fe1b33da32 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x800132fe1b33da32;
-   valaddr_reg:x3; val_offset:1388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1388*FLEN/8, x4, x1, x2)
-
-inst_695:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x132fe1b33da32 and fs2 == 0 and fe2 == 0x003 and fm2 == 0x0d2a72a33d1eb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800132fe1b33da32; op2val:0x30d2a72a33d1eb;
-   valaddr_reg:x3; val_offset:1390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1390*FLEN/8, x4, x1, x2)
-
-inst_696:
-// fs1 == 0 and fe1 == 0x003 and fm1 == 0x0d2a72a33d1eb and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x30d2a72a33d1eb; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1392*FLEN/8, x4, x1, x2)
-
-inst_697:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1394*FLEN/8, x4, x1, x2)
-
-inst_698:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1396*FLEN/8, x4, x1, x2)
-
-inst_699:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x0;
-   valaddr_reg:x3; val_offset:1398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1398*FLEN/8, x4, x1, x2)
-
-inst_700:
-// fs1 == 0 and fe1 == 0x402 and fm1 == 0x2b74f7c4aeb28 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x4022b74f7c4aeb28; op2val:0x0;
-   valaddr_reg:x3; val_offset:1400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1400*FLEN/8, x4, x1, x2)
-
-inst_701:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x402 and fm2 == 0x2b74f7c4aeb28 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x4022b74f7c4aeb28;
-   valaddr_reg:x3; val_offset:1402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1402*FLEN/8, x4, x1, x2)
-
-inst_702:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x6baa94414ba5e and fs2 == 0 and fe2 == 0x402 and fm2 == 0x2b74f7c4aeb28 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x6baa94414ba5e; op2val:0x4022b74f7c4aeb28;
-   valaddr_reg:x3; val_offset:1404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1404*FLEN/8, x4, x1, x2)
-
-inst_703:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1406*FLEN/8, x4, x1, x2)
-
-inst_704:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xf0b5e103c0954 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fef0b5e103c0954; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1408*FLEN/8, x4, x1, x2)
-
-inst_705:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xf0b5e103c0954 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7fef0b5e103c0954;
-   valaddr_reg:x3; val_offset:1410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1410*FLEN/8, x4, x1, x2)
-
-inst_706:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1412*FLEN/8, x4, x1, x2)
-
-inst_707:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1414*FLEN/8, x4, x1, x2)
-
-inst_708:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1416*FLEN/8, x4, x1, x2)
-
-inst_709:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x8d5e4d9c9a110 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7fb8d5e4d9c9a110;
-   valaddr_reg:x3; val_offset:1418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1418*FLEN/8, x4, x1, x2)
-
-inst_710:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1420*FLEN/8, x4, x1, x2)
-
-inst_711:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1422*FLEN/8, x4, x1, x2)
-
-inst_712:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1424*FLEN/8, x4, x1, x2)
-
-inst_713:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1426*FLEN/8, x4, x1, x2)
-
-inst_714:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1428*FLEN/8, x4, x1, x2)
-
-inst_715:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xf0b5e103c0954 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fef0b5e103c0954; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1430*FLEN/8, x4, x1, x2)
-
-inst_716:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1432*FLEN/8, x4, x1, x2)
-
-inst_717:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1434*FLEN/8, x4, x1, x2)
-
-inst_718:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1436*FLEN/8, x4, x1, x2)
-
-inst_719:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xf0b5e103c0954 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fef0b5e103c0954; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1438*FLEN/8, x4, x1, x2)
-
-inst_720:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1440*FLEN/8, x4, x1, x2)
-
-inst_721:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1442*FLEN/8, x4, x1, x2)
-
-inst_722:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1444*FLEN/8, x4, x1, x2)
-
-inst_723:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x8d5e4d9c9a110 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb8d5e4d9c9a110; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1446*FLEN/8, x4, x1, x2)
-
-inst_724:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1448*FLEN/8, x4, x1, x2)
-
-inst_725:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x3de50ae3ae740 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f83de50ae3ae740; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1450*FLEN/8, x4, x1, x2)
-
-inst_726:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x3de50ae3ae740 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x7f83de50ae3ae740;
-   valaddr_reg:x3; val_offset:1452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1452*FLEN/8, x4, x1, x2)
-
-inst_727:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1454*FLEN/8, x4, x1, x2)
-
-inst_728:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1410b3d2a7d0c and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1410b3d2a7d0c; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1456*FLEN/8, x4, x1, x2)
-
-inst_729:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1410b3d2a7d0c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x1410b3d2a7d0c;
-   valaddr_reg:x3; val_offset:1458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1458*FLEN/8, x4, x1, x2)
-
-inst_730:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1460*FLEN/8, x4, x1, x2)
-
-inst_731:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1462*FLEN/8, x4, x1, x2)
-
-inst_732:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1464*FLEN/8, x4, x1, x2)
-
-inst_733:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1466*FLEN/8, x4, x1, x2)
-
-inst_734:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1468*FLEN/8, x4, x1, x2)
-
-inst_735:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1470*FLEN/8, x4, x1, x2)
-
-inst_736:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1472*FLEN/8, x4, x1, x2)
-
-inst_737:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1474*FLEN/8, x4, x1, x2)
-
-inst_738:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1476*FLEN/8, x4, x1, x2)
-
-inst_739:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1478*FLEN/8, x4, x1, x2)
-
-inst_740:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1480*FLEN/8, x4, x1, x2)
-
-inst_741:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1482*FLEN/8, x4, x1, x2)
-
-inst_742:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1484*FLEN/8, x4, x1, x2)
-
-inst_743:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:1486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1486*FLEN/8, x4, x1, x2)
-
-inst_744:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1488*FLEN/8, x4, x1, x2)
-
-inst_745:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1410b3d2a7d0c and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1410b3d2a7d0c; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:1490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1490*FLEN/8, x4, x1, x2)
-
-inst_746:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0x1410b3d2a7d0c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x1410b3d2a7d0c;
-   valaddr_reg:x3; val_offset:1492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1492*FLEN/8, x4, x1, x2)
-
-inst_747:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x1410b3d2a7d0c and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x1410b3d2a7d0c; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1494*FLEN/8, x4, x1, x2)
-
-inst_748:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x0;
-   valaddr_reg:x3; val_offset:1496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1496*FLEN/8, x4, x1, x2)
-
-inst_749:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xbe776c4b9309a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ffbe776c4b9309a; op2val:0x0;
-   valaddr_reg:x3; val_offset:1498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1498*FLEN/8, x4, x1, x2)
-
-inst_750:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xbe776c4b9309a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ffbe776c4b9309a;
-   valaddr_reg:x3; val_offset:1500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1500*FLEN/8, x4, x1, x2)
-
-inst_751:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xc8a7063a8e27a and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xbe776c4b9309a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc8a7063a8e27a; op2val:0x3ffbe776c4b9309a;
-   valaddr_reg:x3; val_offset:1502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1502*FLEN/8, x4, x1, x2)
-
-inst_752:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1504*FLEN/8, x4, x1, x2)
-
-inst_753:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1506*FLEN/8, x4, x1, x2)
-
-inst_754:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1508*FLEN/8, x4, x1, x2)
-
-inst_755:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1510*FLEN/8, x4, x1, x2)
-
-inst_756:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1512*FLEN/8, x4, x1, x2)
-
-inst_757:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0xcc6497dd9aeac and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7fbcc6497dd9aeac;
-   valaddr_reg:x3; val_offset:1514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1514*FLEN/8, x4, x1, x2)
-
-inst_758:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1516*FLEN/8, x4, x1, x2)
-
-inst_759:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1518*FLEN/8, x4, x1, x2)
-
-inst_760:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1520*FLEN/8, x4, x1, x2)
-
-inst_761:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1522*FLEN/8, x4, x1, x2)
-
-inst_762:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1524*FLEN/8, x4, x1, x2)
-
-inst_763:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1526*FLEN/8, x4, x1, x2)
-
-inst_764:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1528*FLEN/8, x4, x1, x2)
-
-inst_765:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1530*FLEN/8, x4, x1, x2)
-
-inst_766:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1532*FLEN/8, x4, x1, x2)
-
-inst_767:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1534*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_7)
-
-inst_768:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1536*FLEN/8, x4, x1, x2)
-
-inst_769:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0xcc6497dd9aeac and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fbcc6497dd9aeac; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1538*FLEN/8, x4, x1, x2)
-
-inst_770:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1540*FLEN/8, x4, x1, x2)
-
-inst_771:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x7050797e15889 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f87050797e15889; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1542*FLEN/8, x4, x1, x2)
-
-inst_772:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x7050797e15889 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x7f87050797e15889;
-   valaddr_reg:x3; val_offset:1544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1544*FLEN/8, x4, x1, x2)
-
-inst_773:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1546*FLEN/8, x4, x1, x2)
-
-inst_774:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x173f689a4c8c6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x173f689a4c8c6; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1548*FLEN/8, x4, x1, x2)
-
-inst_775:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x173f689a4c8c6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x173f689a4c8c6;
-   valaddr_reg:x3; val_offset:1550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1550*FLEN/8, x4, x1, x2)
-
-inst_776:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1552*FLEN/8, x4, x1, x2)
-
-inst_777:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1554*FLEN/8, x4, x1, x2)
-
-inst_778:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1556*FLEN/8, x4, x1, x2)
-
-inst_779:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1558*FLEN/8, x4, x1, x2)
-
-inst_780:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1560*FLEN/8, x4, x1, x2)
-
-inst_781:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1562*FLEN/8, x4, x1, x2)
-
-inst_782:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1564*FLEN/8, x4, x1, x2)
-
-inst_783:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1566*FLEN/8, x4, x1, x2)
-
-inst_784:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1568*FLEN/8, x4, x1, x2)
-
-inst_785:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1570*FLEN/8, x4, x1, x2)
-
-inst_786:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1572*FLEN/8, x4, x1, x2)
-
-inst_787:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:1574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1574*FLEN/8, x4, x1, x2)
-
-inst_788:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1576*FLEN/8, x4, x1, x2)
-
-inst_789:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x173f689a4c8c6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x173f689a4c8c6; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:1578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1578*FLEN/8, x4, x1, x2)
-
-inst_790:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0x173f689a4c8c6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x173f689a4c8c6;
-   valaddr_reg:x3; val_offset:1580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1580*FLEN/8, x4, x1, x2)
-
-inst_791:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x173f689a4c8c6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x173f689a4c8c6; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1582*FLEN/8, x4, x1, x2)
-
-inst_792:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x0;
-   valaddr_reg:x3; val_offset:1584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1584*FLEN/8, x4, x1, x2)
-
-inst_793:
-// fs1 == 0 and fe1 == 0x400 and fm1 == 0x02a39e584db8a and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x40002a39e584db8a; op2val:0x0;
-   valaddr_reg:x3; val_offset:1586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1586*FLEN/8, x4, x1, x2)
-
-inst_794:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x02a39e584db8a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x40002a39e584db8a;
-   valaddr_reg:x3; val_offset:1588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1588*FLEN/8, x4, x1, x2)
-
-inst_795:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xe87a1606fd7b9 and fs2 == 0 and fe2 == 0x400 and fm2 == 0x02a39e584db8a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xe87a1606fd7b9; op2val:0x40002a39e584db8a;
-   valaddr_reg:x3; val_offset:1590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1590*FLEN/8, x4, x1, x2)
-
-inst_796:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1592*FLEN/8, x4, x1, x2)
-
-inst_797:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x87dfc3c4343fa and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe87dfc3c4343fa; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1594*FLEN/8, x4, x1, x2)
-
-inst_798:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x87dfc3c4343fa and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7fe87dfc3c4343fa;
-   valaddr_reg:x3; val_offset:1596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1596*FLEN/8, x4, x1, x2)
-
-inst_799:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1598*FLEN/8, x4, x1, x2)
-
-inst_800:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1600*FLEN/8, x4, x1, x2)
-
-inst_801:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1602*FLEN/8, x4, x1, x2)
-
-inst_802:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x397fcfd029cc8 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7fb397fcfd029cc8;
-   valaddr_reg:x3; val_offset:1604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1604*FLEN/8, x4, x1, x2)
-
-inst_803:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1606*FLEN/8, x4, x1, x2)
-
-inst_804:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1608*FLEN/8, x4, x1, x2)
-
-inst_805:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1610*FLEN/8, x4, x1, x2)
-
-inst_806:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1612*FLEN/8, x4, x1, x2)
-
-inst_807:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1614*FLEN/8, x4, x1, x2)
-
-inst_808:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x87dfc3c4343fa and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe87dfc3c4343fa; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1616*FLEN/8, x4, x1, x2)
-
-inst_809:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1618*FLEN/8, x4, x1, x2)
-
-inst_810:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1620*FLEN/8, x4, x1, x2)
-
-inst_811:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1622*FLEN/8, x4, x1, x2)
-
-inst_812:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0x87dfc3c4343fa and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fe87dfc3c4343fa; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1624*FLEN/8, x4, x1, x2)
-
-inst_813:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1626*FLEN/8, x4, x1, x2)
-
-inst_814:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1628*FLEN/8, x4, x1, x2)
-
-inst_815:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1630*FLEN/8, x4, x1, x2)
-
-inst_816:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x397fcfd029cc8 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb397fcfd029cc8; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1632*FLEN/8, x4, x1, x2)
-
-inst_817:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1634*FLEN/8, x4, x1, x2)
-
-inst_818:
-// fs1 == 0 and fe1 == 0x7f7 and fm1 == 0xf5994c8042e0c and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f7f5994c8042e0c; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1636*FLEN/8, x4, x1, x2)
-
-inst_819:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x7f7 and fm2 == 0xf5994c8042e0c and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x7f7f5994c8042e0c;
-   valaddr_reg:x3; val_offset:1638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1638*FLEN/8, x4, x1, x2)
-
-inst_820:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1640*FLEN/8, x4, x1, x2)
-
-inst_821:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fd48b05c2121 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfd48b05c2121; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1642*FLEN/8, x4, x1, x2)
-
-inst_822:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0fd48b05c2121 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xfd48b05c2121;
-   valaddr_reg:x3; val_offset:1644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1644*FLEN/8, x4, x1, x2)
-
-inst_823:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1646*FLEN/8, x4, x1, x2)
-
-inst_824:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1648*FLEN/8, x4, x1, x2)
-
-inst_825:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1650*FLEN/8, x4, x1, x2)
-
-inst_826:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1652*FLEN/8, x4, x1, x2)
-
-inst_827:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1654*FLEN/8, x4, x1, x2)
-
-inst_828:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1656*FLEN/8, x4, x1, x2)
-
-inst_829:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1658*FLEN/8, x4, x1, x2)
-
-inst_830:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1660*FLEN/8, x4, x1, x2)
-
-inst_831:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1662*FLEN/8, x4, x1, x2)
-
-inst_832:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:1664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1664*FLEN/8, x4, x1, x2)
-
-inst_833:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1666*FLEN/8, x4, x1, x2)
-
-inst_834:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fd48b05c2121 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfd48b05c2121; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:1668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1668*FLEN/8, x4, x1, x2)
-
-inst_835:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0fd48b05c2121 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0xfd48b05c2121;
-   valaddr_reg:x3; val_offset:1670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1670*FLEN/8, x4, x1, x2)
-
-inst_836:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0fd48b05c2121 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xfd48b05c2121; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1672*FLEN/8, x4, x1, x2)
-
-inst_837:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x0;
-   valaddr_reg:x3; val_offset:1674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1674*FLEN/8, x4, x1, x2)
-
-inst_838:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x603c137f0d51f and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ff603c137f0d51f; op2val:0x0;
-   valaddr_reg:x3; val_offset:1676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1676*FLEN/8, x4, x1, x2)
-
-inst_839:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x603c137f0d51f and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ff603c137f0d51f;
-   valaddr_reg:x3; val_offset:1678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1678*FLEN/8, x4, x1, x2)
-
-inst_840:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x9e4d6e3994b4b and fs2 == 0 and fe2 == 0x3ff and fm2 == 0x603c137f0d51f and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x9e4d6e3994b4b; op2val:0x3ff603c137f0d51f;
-   valaddr_reg:x3; val_offset:1680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1680*FLEN/8, x4, x1, x2)
-
-inst_841:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1682*FLEN/8, x4, x1, x2)
-
-inst_842:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7ff0000000000000;
-   valaddr_reg:x3; val_offset:1684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1684*FLEN/8, x4, x1, x2)
-
-inst_843:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1686*FLEN/8, x4, x1, x2)
-
-inst_844:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1688*FLEN/8, x4, x1, x2)
-
-inst_845:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1690*FLEN/8, x4, x1, x2)
-
-inst_846:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x9ac314c1e5de7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7fb9ac314c1e5de7;
-   valaddr_reg:x3; val_offset:1692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1692*FLEN/8, x4, x1, x2)
-
-inst_847:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1694*FLEN/8, x4, x1, x2)
-
-inst_848:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1696*FLEN/8, x4, x1, x2)
-
-inst_849:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1698*FLEN/8, x4, x1, x2)
-
-inst_850:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1700*FLEN/8, x4, x1, x2)
-
-inst_851:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1702*FLEN/8, x4, x1, x2)
-
-inst_852:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1704*FLEN/8, x4, x1, x2)
-
-inst_853:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1706*FLEN/8, x4, x1, x2)
-
-inst_854:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1708*FLEN/8, x4, x1, x2)
-
-inst_855:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1710*FLEN/8, x4, x1, x2)
-
-inst_856:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1712*FLEN/8, x4, x1, x2)
-
-inst_857:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1714*FLEN/8, x4, x1, x2)
-
-inst_858:
-// fs1 == 0 and fe1 == 0x7fb and fm1 == 0x9ac314c1e5de7 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7fb9ac314c1e5de7; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1716*FLEN/8, x4, x1, x2)
-
-inst_859:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1718*FLEN/8, x4, x1, x2)
-
-inst_860:
-// fs1 == 0 and fe1 == 0x7f8 and fm1 == 0x489c109b1e4b9 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7f8489c109b1e4b9; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1720*FLEN/8, x4, x1, x2)
-
-inst_861:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x7f8 and fm2 == 0x489c109b1e4b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x7f8489c109b1e4b9;
-   valaddr_reg:x3; val_offset:1722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1722*FLEN/8, x4, x1, x2)
-
-inst_862:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1724*FLEN/8, x4, x1, x2)
-
-inst_863:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x14bdd6f520473 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x14bdd6f520473; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1726*FLEN/8, x4, x1, x2)
-
-inst_864:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x14bdd6f520473 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x14bdd6f520473;
-   valaddr_reg:x3; val_offset:1728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1728*FLEN/8, x4, x1, x2)
-
-inst_865:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1730*FLEN/8, x4, x1, x2)
-
-inst_866:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1732*FLEN/8, x4, x1, x2)
-
-inst_867:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1734*FLEN/8, x4, x1, x2)
-
-inst_868:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1736*FLEN/8, x4, x1, x2)
-
-inst_869:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1738*FLEN/8, x4, x1, x2)
-
-inst_870:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1740*FLEN/8, x4, x1, x2)
-
-inst_871:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1742*FLEN/8, x4, x1, x2)
-
-inst_872:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:1744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1744*FLEN/8, x4, x1, x2)
-
-inst_873:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1746*FLEN/8, x4, x1, x2)
-
-inst_874:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x14bdd6f520473 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x14bdd6f520473; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:1748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1748*FLEN/8, x4, x1, x2)
-
-inst_875:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0x14bdd6f520473 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x14bdd6f520473;
-   valaddr_reg:x3; val_offset:1750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1750*FLEN/8, x4, x1, x2)
-
-inst_876:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x14bdd6f520473 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x14bdd6f520473; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1752*FLEN/8, x4, x1, x2)
-
-inst_877:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x0;
-   valaddr_reg:x3; val_offset:1754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1754*FLEN/8, x4, x1, x2)
-
-inst_878:
-// fs1 == 0 and fe1 == 0x3ff and fm1 == 0xcd83dac71068d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x3ffcd83dac71068d; op2val:0x0;
-   valaddr_reg:x3; val_offset:1756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1756*FLEN/8, x4, x1, x2)
-
-inst_879:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xcd83dac71068d and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x3ffcd83dac71068d;
-   valaddr_reg:x3; val_offset:1758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1758*FLEN/8, x4, x1, x2)
-
-inst_880:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0xcf6a659342c81 and fs2 == 0 and fe2 == 0x3ff and fm2 == 0xcd83dac71068d and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xcf6a659342c81; op2val:0x3ffcd83dac71068d;
-   valaddr_reg:x3; val_offset:1760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1760*FLEN/8, x4, x1, x2)
-
-inst_881:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1762*FLEN/8, x4, x1, x2)
-
-inst_882:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd5a40c379c682 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed5a40c379c682; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1764*FLEN/8, x4, x1, x2)
-
-inst_883:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xd5a40c379c682 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xffed5a40c379c682;
-   valaddr_reg:x3; val_offset:1766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1766*FLEN/8, x4, x1, x2)
-
-inst_884:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1768*FLEN/8, x4, x1, x2)
-
-inst_885:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1770*FLEN/8, x4, x1, x2)
-
-inst_886:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1772*FLEN/8, x4, x1, x2)
-
-inst_887:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x77b6702c7d202 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xffb77b6702c7d202;
-   valaddr_reg:x3; val_offset:1774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1774*FLEN/8, x4, x1, x2)
-
-inst_888:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1776*FLEN/8, x4, x1, x2)
-
-inst_889:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1778*FLEN/8, x4, x1, x2)
-
-inst_890:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1780*FLEN/8, x4, x1, x2)
-
-inst_891:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1782*FLEN/8, x4, x1, x2)
-
-inst_892:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1784*FLEN/8, x4, x1, x2)
-
-inst_893:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd5a40c379c682 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed5a40c379c682; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1786*FLEN/8, x4, x1, x2)
-
-inst_894:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1788*FLEN/8, x4, x1, x2)
-
-inst_895:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1790*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_8)
-
-inst_896:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1792*FLEN/8, x4, x1, x2)
-
-inst_897:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd5a40c379c682 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed5a40c379c682; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1794*FLEN/8, x4, x1, x2)
-
-inst_898:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1796*FLEN/8, x4, x1, x2)
-
-inst_899:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1798*FLEN/8, x4, x1, x2)
-
-inst_900:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1800*FLEN/8, x4, x1, x2)
-
-inst_901:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x77b6702c7d202 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb77b6702c7d202; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1802*FLEN/8, x4, x1, x2)
-
-inst_902:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1804*FLEN/8, x4, x1, x2)
-
-inst_903:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x2c91f356ca801 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff82c91f356ca801; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1806*FLEN/8, x4, x1, x2)
-
-inst_904:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x2c91f356ca801 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xff82c91f356ca801;
-   valaddr_reg:x3; val_offset:1808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1808*FLEN/8, x4, x1, x2)
-
-inst_905:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1810*FLEN/8, x4, x1, x2)
-
-inst_906:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12f8c3601c4a9 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80012f8c3601c4a9; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1812*FLEN/8, x4, x1, x2)
-
-inst_907:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x12f8c3601c4a9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x80012f8c3601c4a9;
-   valaddr_reg:x3; val_offset:1814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1814*FLEN/8, x4, x1, x2)
-
-inst_908:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1816*FLEN/8, x4, x1, x2)
-
-inst_909:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1818*FLEN/8, x4, x1, x2)
-
-inst_910:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1820*FLEN/8, x4, x1, x2)
-
-inst_911:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1822*FLEN/8, x4, x1, x2)
-
-inst_912:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1824*FLEN/8, x4, x1, x2)
-
-inst_913:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:1826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1826*FLEN/8, x4, x1, x2)
-
-inst_914:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1828*FLEN/8, x4, x1, x2)
-
-inst_915:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12f8c3601c4a9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80012f8c3601c4a9; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:1830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1830*FLEN/8, x4, x1, x2)
-
-inst_916:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0x12f8c3601c4a9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x80012f8c3601c4a9;
-   valaddr_reg:x3; val_offset:1832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1832*FLEN/8, x4, x1, x2)
-
-inst_917:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x12f8c3601c4a9 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80012f8c3601c4a9; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1834*FLEN/8, x4, x1, x2)
-
-inst_918:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0x0;
-   valaddr_reg:x3; val_offset:1836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1836*FLEN/8, x4, x1, x2)
-
-inst_919:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xa6229168cb10d and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbffa6229168cb10d; op2val:0x0;
-   valaddr_reg:x3; val_offset:1838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1838*FLEN/8, x4, x1, x2)
-
-inst_920:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xa6229168cb10d and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbffa6229168cb10d;
-   valaddr_reg:x3; val_offset:1840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1840*FLEN/8, x4, x1, x2)
-
-inst_921:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbdb7a1c11ae96 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xa6229168cb10d and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bdb7a1c11ae96; op2val:0xbffa6229168cb10d;
-   valaddr_reg:x3; val_offset:1842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1842*FLEN/8, x4, x1, x2)
-
-inst_922:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1844*FLEN/8, x4, x1, x2)
-
-inst_923:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb9818fe1eccda and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffeb9818fe1eccda; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1846*FLEN/8, x4, x1, x2)
-
-inst_924:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xb9818fe1eccda and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xffeb9818fe1eccda;
-   valaddr_reg:x3; val_offset:1848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1848*FLEN/8, x4, x1, x2)
-
-inst_925:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1850*FLEN/8, x4, x1, x2)
-
-inst_926:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1852*FLEN/8, x4, x1, x2)
-
-inst_927:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1854*FLEN/8, x4, x1, x2)
-
-inst_928:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x6134731b23d7b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xffb6134731b23d7b;
-   valaddr_reg:x3; val_offset:1856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1856*FLEN/8, x4, x1, x2)
-
-inst_929:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1858*FLEN/8, x4, x1, x2)
-
-inst_930:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1860*FLEN/8, x4, x1, x2)
-
-inst_931:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1862*FLEN/8, x4, x1, x2)
-
-inst_932:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1864*FLEN/8, x4, x1, x2)
-
-inst_933:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1866*FLEN/8, x4, x1, x2)
-
-inst_934:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb9818fe1eccda and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffeb9818fe1eccda; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1868*FLEN/8, x4, x1, x2)
-
-inst_935:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1870*FLEN/8, x4, x1, x2)
-
-inst_936:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1872*FLEN/8, x4, x1, x2)
-
-inst_937:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1874*FLEN/8, x4, x1, x2)
-
-inst_938:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb9818fe1eccda and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffeb9818fe1eccda; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1876*FLEN/8, x4, x1, x2)
-
-inst_939:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1878*FLEN/8, x4, x1, x2)
-
-inst_940:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1880*FLEN/8, x4, x1, x2)
-
-inst_941:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1882*FLEN/8, x4, x1, x2)
-
-inst_942:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x6134731b23d7b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb6134731b23d7b; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1884*FLEN/8, x4, x1, x2)
-
-inst_943:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1886*FLEN/8, x4, x1, x2)
-
-inst_944:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x1a905c15b6463 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff81a905c15b6463; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1888*FLEN/8, x4, x1, x2)
-
-inst_945:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x1a905c15b6463 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xff81a905c15b6463;
-   valaddr_reg:x3; val_offset:1890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1890*FLEN/8, x4, x1, x2)
-
-inst_946:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1892*FLEN/8, x4, x1, x2)
-
-inst_947:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11d5cf49b3fa7 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80011d5cf49b3fa7; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1894*FLEN/8, x4, x1, x2)
-
-inst_948:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x11d5cf49b3fa7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x80011d5cf49b3fa7;
-   valaddr_reg:x3; val_offset:1896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1896*FLEN/8, x4, x1, x2)
-
-inst_949:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1898*FLEN/8, x4, x1, x2)
-
-inst_950:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1900*FLEN/8, x4, x1, x2)
-
-inst_951:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1902*FLEN/8, x4, x1, x2)
-
-inst_952:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:1904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1904*FLEN/8, x4, x1, x2)
-
-inst_953:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1906*FLEN/8, x4, x1, x2)
-
-inst_954:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11d5cf49b3fa7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80011d5cf49b3fa7; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:1908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1908*FLEN/8, x4, x1, x2)
-
-inst_955:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0x11d5cf49b3fa7 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x80011d5cf49b3fa7;
-   valaddr_reg:x3; val_offset:1910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1910*FLEN/8, x4, x1, x2)
-
-inst_956:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x11d5cf49b3fa7 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x80011d5cf49b3fa7; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1912*FLEN/8, x4, x1, x2)
-
-inst_957:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0x0;
-   valaddr_reg:x3; val_offset:1914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1914*FLEN/8, x4, x1, x2)
-
-inst_958:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8cd8a372f0f06 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbff8cd8a372f0f06; op2val:0x0;
-   valaddr_reg:x3; val_offset:1916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1916*FLEN/8, x4, x1, x2)
-
-inst_959:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x8cd8a372f0f06 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbff8cd8a372f0f06;
-   valaddr_reg:x3; val_offset:1918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1918*FLEN/8, x4, x1, x2)
-
-inst_960:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xb25a18e107c85 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x8cd8a372f0f06 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800b25a18e107c85; op2val:0xbff8cd8a372f0f06;
-   valaddr_reg:x3; val_offset:1920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1920*FLEN/8, x4, x1, x2)
-
-inst_961:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1922*FLEN/8, x4, x1, x2)
-
-inst_962:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x39e41023e1389 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe39e41023e1389; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1924*FLEN/8, x4, x1, x2)
-
-inst_963:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x39e41023e1389 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xffe39e41023e1389;
-   valaddr_reg:x3; val_offset:1926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1926*FLEN/8, x4, x1, x2)
-
-inst_964:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1928*FLEN/8, x4, x1, x2)
-
-inst_965:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1930*FLEN/8, x4, x1, x2)
-
-inst_966:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:1932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1932*FLEN/8, x4, x1, x2)
-
-inst_967:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7fa and fm2 == 0xf639b36c9b8db and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xffaf639b36c9b8db;
-   valaddr_reg:x3; val_offset:1934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1934*FLEN/8, x4, x1, x2)
-
-inst_968:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1936*FLEN/8, x4, x1, x2)
-
-inst_969:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:1938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1938*FLEN/8, x4, x1, x2)
-
-inst_970:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1940*FLEN/8, x4, x1, x2)
-
-inst_971:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:1942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1942*FLEN/8, x4, x1, x2)
-
-inst_972:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1944*FLEN/8, x4, x1, x2)
-
-inst_973:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x39e41023e1389 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe39e41023e1389; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:1946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1946*FLEN/8, x4, x1, x2)
-
-inst_974:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1948*FLEN/8, x4, x1, x2)
-
-inst_975:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:1950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1950*FLEN/8, x4, x1, x2)
-
-inst_976:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1952*FLEN/8, x4, x1, x2)
-
-inst_977:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x39e41023e1389 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe39e41023e1389; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:1954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1954*FLEN/8, x4, x1, x2)
-
-inst_978:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1956*FLEN/8, x4, x1, x2)
-
-inst_979:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:1958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1958*FLEN/8, x4, x1, x2)
-
-inst_980:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1960*FLEN/8, x4, x1, x2)
-
-inst_981:
-// fs1 == 1 and fe1 == 0x7fa and fm1 == 0xf639b36c9b8db and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffaf639b36c9b8db; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:1962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1962*FLEN/8, x4, x1, x2)
-
-inst_982:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1964*FLEN/8, x4, x1, x2)
-
-inst_983:
-// fs1 == 1 and fe1 == 0x7f7 and fm1 == 0x91c7c2bd493e3 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff791c7c2bd493e3; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:1966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1966*FLEN/8, x4, x1, x2)
-
-inst_984:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x7f7 and fm2 == 0x91c7c2bd493e3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xff791c7c2bd493e3;
-   valaddr_reg:x3; val_offset:1968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1968*FLEN/8, x4, x1, x2)
-
-inst_985:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1970*FLEN/8, x4, x1, x2)
-
-inst_986:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0cae158f8de83 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000cae158f8de83; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:1972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1972*FLEN/8, x4, x1, x2)
-
-inst_987:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0cae158f8de83 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x8000cae158f8de83;
-   valaddr_reg:x3; val_offset:1974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1974*FLEN/8, x4, x1, x2)
-
-inst_988:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:1976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1976*FLEN/8, x4, x1, x2)
-
-inst_989:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:1978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1978*FLEN/8, x4, x1, x2)
-
-inst_990:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1980*FLEN/8, x4, x1, x2)
-
-inst_991:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0cae158f8de83 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000cae158f8de83; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:1982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1982*FLEN/8, x4, x1, x2)
-
-inst_992:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0x0cae158f8de83 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x8000cae158f8de83;
-   valaddr_reg:x3; val_offset:1984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1984*FLEN/8, x4, x1, x2)
-
-inst_993:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x0cae158f8de83 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8000cae158f8de83; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:1986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1986*FLEN/8, x4, x1, x2)
-
-inst_994:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0x0;
-   valaddr_reg:x3; val_offset:1988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1988*FLEN/8, x4, x1, x2)
-
-inst_995:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1a23c57d41a27 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbff1a23c57d41a27; op2val:0x0;
-   valaddr_reg:x3; val_offset:1990*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1990*FLEN/8, x4, x1, x2)
-
-inst_996:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x1a23c57d41a27 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbff1a23c57d41a27;
-   valaddr_reg:x3; val_offset:1992*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1992*FLEN/8, x4, x1, x2)
-
-inst_997:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x7eccd79b8b11e and fs2 == 1 and fe2 == 0x3ff and fm2 == 0x1a23c57d41a27 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x8007eccd79b8b11e; op2val:0xbff1a23c57d41a27;
-   valaddr_reg:x3; val_offset:1994*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1994*FLEN/8, x4, x1, x2)
-
-inst_998:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1996*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1996*FLEN/8, x4, x1, x2)
-
-inst_999:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xdaf87e09a11da and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffedaf87e09a11da; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:1998*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 1998*FLEN/8, x4, x1, x2)
-
-inst_1000:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0xdaf87e09a11da and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xffedaf87e09a11da;
-   valaddr_reg:x3; val_offset:2000*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2000*FLEN/8, x4, x1, x2)
-
-inst_1001:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:2002*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2002*FLEN/8, x4, x1, x2)
-
-inst_1002:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:2004*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2004*FLEN/8, x4, x1, x2)
-
-inst_1003:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:2006*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2006*FLEN/8, x4, x1, x2)
-
-inst_1004:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7fb and fm2 == 0x7bf9fe6e1a7e1 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xffb7bf9fe6e1a7e1;
-   valaddr_reg:x3; val_offset:2008*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2008*FLEN/8, x4, x1, x2)
-
-inst_1005:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:2010*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2010*FLEN/8, x4, x1, x2)
-
-inst_1006:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:2012*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2012*FLEN/8, x4, x1, x2)
-
-inst_1007:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:2014*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2014*FLEN/8, x4, x1, x2)
-
-inst_1008:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:2016*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2016*FLEN/8, x4, x1, x2)
-
-inst_1009:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:2018*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2018*FLEN/8, x4, x1, x2)
-
-inst_1010:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xdaf87e09a11da and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffedaf87e09a11da; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:2020*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2020*FLEN/8, x4, x1, x2)
-
-inst_1011:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:2022*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2022*FLEN/8, x4, x1, x2)
-
-inst_1012:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:2024*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2024*FLEN/8, x4, x1, x2)
-
-inst_1013:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:2026*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2026*FLEN/8, x4, x1, x2)
-
-inst_1014:
-// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xdaf87e09a11da and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffedaf87e09a11da; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:2028*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2028*FLEN/8, x4, x1, x2)
-
-inst_1015:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:2030*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2030*FLEN/8, x4, x1, x2)
-
-inst_1016:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:2032*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2032*FLEN/8, x4, x1, x2)
-
-inst_1017:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:2034*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2034*FLEN/8, x4, x1, x2)
-
-inst_1018:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x7bf9fe6e1a7e1 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb7bf9fe6e1a7e1; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:2036*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2036*FLEN/8, x4, x1, x2)
-
-inst_1019:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:2038*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2038*FLEN/8, x4, x1, x2)
-
-inst_1020:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x2ffb31f1aecb4 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff82ffb31f1aecb4; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:2040*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2040*FLEN/8, x4, x1, x2)
-
-inst_1021:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x2ffb31f1aecb4 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xff82ffb31f1aecb4;
-   valaddr_reg:x3; val_offset:2042*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2042*FLEN/8, x4, x1, x2)
-
-inst_1022:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:2044*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2044*FLEN/8, x4, x1, x2)
-
-inst_1023:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x132fe1b33da32 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800132fe1b33da32; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:2046*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2046*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_9)
-
-inst_1024:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x132fe1b33da32 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x800132fe1b33da32;
-   valaddr_reg:x3; val_offset:2048*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2048*FLEN/8, x4, x1, x2)
-
-inst_1025:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:2050*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2050*FLEN/8, x4, x1, x2)
-
-inst_1026:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x132fe1b33da32 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800132fe1b33da32; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:2052*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2052*FLEN/8, x4, x1, x2)
-
-inst_1027:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0x132fe1b33da32 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x800132fe1b33da32;
-   valaddr_reg:x3; val_offset:2054*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2054*FLEN/8, x4, x1, x2)
-
-inst_1028:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x132fe1b33da32 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800132fe1b33da32; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:2056*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2056*FLEN/8, x4, x1, x2)
-
-inst_1029:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0x0;
-   valaddr_reg:x3; val_offset:2058*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2058*FLEN/8, x4, x1, x2)
-
-inst_1030:
-// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xaaecfe8e63ec3 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xbffaaecfe8e63ec3; op2val:0x0;
-   valaddr_reg:x3; val_offset:2060*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2060*FLEN/8, x4, x1, x2)
-
-inst_1031:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xaaecfe8e63ec3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xbffaaecfe8e63ec3;
-   valaddr_reg:x3; val_offset:2062*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2062*FLEN/8, x4, x1, x2)
-
-inst_1032:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xbfded100685f6 and fs2 == 1 and fe2 == 0x3ff and fm2 == 0xaaecfe8e63ec3 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800bfded100685f6; op2val:0xbffaaecfe8e63ec3;
-   valaddr_reg:x3; val_offset:2064*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2064*FLEN/8, x4, x1, x2)
-
-inst_1033:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:2066*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2066*FLEN/8, x4, x1, x2)
-
-inst_1034:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7ff and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xfff0000000000000;
-   valaddr_reg:x3; val_offset:2068*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2068*FLEN/8, x4, x1, x2)
-
-inst_1035:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:2070*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2070*FLEN/8, x4, x1, x2)
-
-inst_1036:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:2072*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2072*FLEN/8, x4, x1, x2)
-
-inst_1037:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:2074*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2074*FLEN/8, x4, x1, x2)
-
-inst_1038:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7fb and fm2 == 0xefff2c6cde040 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xffbefff2c6cde040;
-   valaddr_reg:x3; val_offset:2076*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2076*FLEN/8, x4, x1, x2)
-
-inst_1039:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:2078*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2078*FLEN/8, x4, x1, x2)
-
-inst_1040:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:2080*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2080*FLEN/8, x4, x1, x2)
-
-inst_1041:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:2082*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2082*FLEN/8, x4, x1, x2)
-
-inst_1042:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:2084*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2084*FLEN/8, x4, x1, x2)
-
-inst_1043:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:2086*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2086*FLEN/8, x4, x1, x2)
-
-inst_1044:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:2088*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2088*FLEN/8, x4, x1, x2)
-
-inst_1045:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:2090*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2090*FLEN/8, x4, x1, x2)
-
-inst_1046:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:2092*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2092*FLEN/8, x4, x1, x2)
-
-inst_1047:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:2094*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2094*FLEN/8, x4, x1, x2)
-
-inst_1048:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:2096*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2096*FLEN/8, x4, x1, x2)
-
-inst_1049:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:2098*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2098*FLEN/8, x4, x1, x2)
-
-inst_1050:
-// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xefff2c6cde040 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbefff2c6cde040; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:2100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2100*FLEN/8, x4, x1, x2)
-
-inst_1051:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:2102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2102*FLEN/8, x4, x1, x2)
-
-inst_1052:
-// fs1 == 1 and fe1 == 0x7f8 and fm1 == 0x8ccc238a4b367 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xff88ccc238a4b367; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:2104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2104*FLEN/8, x4, x1, x2)
-
-inst_1053:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x7f8 and fm2 == 0x8ccc238a4b367 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xff88ccc238a4b367;
-   valaddr_reg:x3; val_offset:2106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2106*FLEN/8, x4, x1, x2)
-
-inst_1054:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:2108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2108*FLEN/8, x4, x1, x2)
-
-inst_1055:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:2110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2110*FLEN/8, x4, x1, x2)
-
-inst_1056:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xfa7485d0f8ece and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x800fa7485d0f8ece;
-   valaddr_reg:x3; val_offset:2112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2112*FLEN/8, x4, x1, x2)
-
-inst_1057:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:2114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2114*FLEN/8, x4, x1, x2)
-
-inst_1058:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:2116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2116*FLEN/8, x4, x1, x2)
-
-inst_1059:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:2118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2118*FLEN/8, x4, x1, x2)
-
-inst_1060:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:2120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2120*FLEN/8, x4, x1, x2)
-
-inst_1061:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:2122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2122*FLEN/8, x4, x1, x2)
-
-inst_1062:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:2124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2124*FLEN/8, x4, x1, x2)
-
-inst_1063:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:2126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2126*FLEN/8, x4, x1, x2)
-
-inst_1064:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:2128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2128*FLEN/8, x4, x1, x2)
-
-inst_1065:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:2130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2130*FLEN/8, x4, x1, x2)
-
-inst_1066:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:2132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2132*FLEN/8, x4, x1, x2)
-
-inst_1067:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:2134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2134*FLEN/8, x4, x1, x2)
-
-inst_1068:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:2136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2136*FLEN/8, x4, x1, x2)
-
-inst_1069:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:2138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2138*FLEN/8, x4, x1, x2)
-
-inst_1070:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0xfa7485d0f8ece and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800fa7485d0f8ece; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:2140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2140*FLEN/8, x4, x1, x2)
-
-inst_1071:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0x0;
-   valaddr_reg:x3; val_offset:2142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2142*FLEN/8, x4, x1, x2)
-
-inst_1072:
-// fs1 == 1 and fe1 == 0x400 and fm1 == 0x16a3ffd234a38 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0xc0016a3ffd234a38; op2val:0x0;
-   valaddr_reg:x3; val_offset:2144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2144*FLEN/8, x4, x1, x2)
-
-inst_1073:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x400 and fm2 == 0x16a3ffd234a38 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc0016a3ffd234a38;
-   valaddr_reg:x3; val_offset:2146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2146*FLEN/8, x4, x1, x2)
-
-inst_1074:
-// fs1 == 1 and fe1 == 0x000 and fm1 == 0x190ba6fb4c17b and fs2 == 1 and fe2 == 0x400 and fm2 == 0x16a3ffd234a38 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x800190ba6fb4c17b; op2val:0xc0016a3ffd234a38;
-   valaddr_reg:x3; val_offset:2148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2148*FLEN/8, x4, x1, x2)
-
-inst_1075:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xb0580f98a7dbd and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7feb0580f98a7dbd;
-   valaddr_reg:x3; val_offset:2150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2150*FLEN/8, x4, x1, x2)
-
-inst_1076:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x0000000000000 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:2152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2152*FLEN/8, x4, x1, x2)
-
-inst_1077:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:2154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2154*FLEN/8, x4, x1, x2)
-
-inst_1078:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xe809082dd48fb and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fde809082dd48fb;
-   valaddr_reg:x3; val_offset:2156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2156*FLEN/8, x4, x1, x2)
-
-inst_1079:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x209a1991e3307 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fd209a1991e3307;
-   valaddr_reg:x3; val_offset:2158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2158*FLEN/8, x4, x1, x2)
-
-inst_1080:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd1ca42e21585b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x7fed1ca42e21585b;
-   valaddr_reg:x3; val_offset:2160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2160*FLEN/8, x4, x1, x2)
-
-inst_1081:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xefb59a1c18f98 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffcefb59a1c18f98;
-   valaddr_reg:x3; val_offset:2162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2162*FLEN/8, x4, x1, x2)
-
-inst_1082:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fe and fm2 == 0x30ac79053ba62 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffe30ac79053ba62;
-   valaddr_reg:x3; val_offset:2164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2164*FLEN/8, x4, x1, x2)
-
-inst_1083:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fd and fm2 == 0xaa9de60dde106 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffdaa9de60dde106;
-   valaddr_reg:x3; val_offset:2166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2166*FLEN/8, x4, x1, x2)
-
-inst_1084:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7fc and fm2 == 0xf41cece7b92c0 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xffcf41cece7b92c0;
-   valaddr_reg:x3; val_offset:2168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2168*FLEN/8, x4, x1, x2)
-
-inst_1085:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x7f9 and fm2 == 0x1a0af25bcea80 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xff91a0af25bcea80;
-   valaddr_reg:x3; val_offset:2170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2170*FLEN/8, x4, x1, x2)
-
-inst_1086:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x6baa94414ba5e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x6baa94414ba5e;
-   valaddr_reg:x3; val_offset:2172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2172*FLEN/8, x4, x1, x2)
-
-inst_1087:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xc8a7063a8e27a and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xc8a7063a8e27a;
-   valaddr_reg:x3; val_offset:2174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2174*FLEN/8, x4, x1, x2)
-
-inst_1088:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xe87a1606fd7b9 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xe87a1606fd7b9;
-   valaddr_reg:x3; val_offset:2176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2176*FLEN/8, x4, x1, x2)
-
-inst_1089:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0x9e4d6e3994b4b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x9e4d6e3994b4b;
-   valaddr_reg:x3; val_offset:2178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2178*FLEN/8, x4, x1, x2)
-
-inst_1090:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x000 and fm2 == 0xcf6a659342c81 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xcf6a659342c81;
-   valaddr_reg:x3; val_offset:2180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2180*FLEN/8, x4, x1, x2)
-
-inst_1091:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbdb7a1c11ae96 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x800bdb7a1c11ae96;
-   valaddr_reg:x3; val_offset:2182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2182*FLEN/8, x4, x1, x2)
-
-inst_1092:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xb25a18e107c85 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x800b25a18e107c85;
-   valaddr_reg:x3; val_offset:2184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2184*FLEN/8, x4, x1, x2)
-
-inst_1093:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x7eccd79b8b11e and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x8007eccd79b8b11e;
-   valaddr_reg:x3; val_offset:2186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2186*FLEN/8, x4, x1, x2)
-
-inst_1094:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0xbfded100685f6 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x800bfded100685f6;
-   valaddr_reg:x3; val_offset:2188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2188*FLEN/8, x4, x1, x2)
-
-inst_1095:
-// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fs2 == 1 and fe2 == 0x000 and fm2 == 0x190ba6fb4c17b and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x800190ba6fb4c17b;
-   valaddr_reg:x3; val_offset:2190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2190*FLEN/8, x4, x1, x2)
-
-inst_1096:
-// fs1 == 0 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x05c5ccdf19706 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7feb0580f98a7dbd; op2val:0x7fe05c5ccdf19706;
-   valaddr_reg:x3; val_offset:2192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2192*FLEN/8, x4, x1, x2)
-
-inst_1097:
-// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fs2 == 0 and fe2 == 0x7fb and fm2 == 0x59e00c7a1fe31 and  fcsr == 0  
-/* opcode: fminm.d ; op1:f30; op2:f29; dest:f31; op1val:0x7ff0000000000000; op2val:0x7fb59e00c7a1fe31;
-   valaddr_reg:x3; val_offset:2194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.d, f31, f30, f29, 0, 0, x3, 2194*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(9214466391261943558,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9213943245805799675,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(9213943245805799675,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9210434777589363463,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(9210434777589363463,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9218055503771424859,64,FLEN)
-NAN_BOXED(9218055503771424859,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(18432946687258496920,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(18432946687258496920,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(18438593151621118562,64,FLEN)
-NAN_BOXED(18438593151621118562,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(18436234797167534342,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(18436234797167534342,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(18433024156334002880,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-NAN_BOXED(18433024156334002880,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(18415677025407527552,64,FLEN)
-NAN_BOXED(9187707400766357133,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9187707400766357133,64,FLEN)
-NAN_BOXED(9187707400766357133,64,FLEN)
-NAN_BOXED(18415677025407527552,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(9187707400766357133,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(1894086014712414,64,FLEN)
-NAN_BOXED(307248920905963,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(307248920905963,64,FLEN)
-NAN_BOXED(307248920905963,64,FLEN)
-NAN_BOXED(1894086014712414,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(307248920905963,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(3529915033510522,64,FLEN)
-NAN_BOXED(3072489209059625,64,FLEN)
-NAN_BOXED(9218599460877896020,64,FLEN)
-NAN_BOXED(9218599460877896020,64,FLEN)
-NAN_BOXED(3072489209059625,64,FLEN)
-NAN_BOXED(3072489209059625,64,FLEN)
-NAN_BOXED(3529915033510522,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
-NAN_BOXED(3072489209059625,64,FLEN)
-NAN_BOXED(9217467113844407741,64,FLEN)
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-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(9202435139787947569,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_7:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_8:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_9:
-    .fill 148*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b1-01.S
deleted file mode 100644
index b06235644..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b1-01.S
+++ /dev/null
@@ -1,409 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:10:02 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fminm.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fminm.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fminm_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rd != rs2, rs1==f31, rs2==f30, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f31; op2:f30; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f29; op1val:0x0; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f29, f30, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 == rs2 == rd, rs1==f28, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f28; op2:f28; dest:f28; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f28, f28, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 == rs2 != rd, rs1==f27, rs2==f27, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f27; op2:f27; dest:f30; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f30, f27, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f29, rs2==f31, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f29; op2:f31; dest:f27; op1val:0x0; op2val:0x2;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f27, f29, f31, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f25, rs2==f24, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f25; op2:f24; dest:f26; op1val:0x0; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f26, f25, f24, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f24; op2:f26; dest:f25; op1val:0x0; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f25, f24, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f26, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f26; op2:f25; dest:f24; op1val:0x0; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f24, f26, f25, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f21, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f22; op2:f21; dest:f23; op1val:0x0; op2val:0x800000;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f23, f22, f21, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rs2==f23, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f21; op2:f23; dest:f22; op1val:0x0; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f22, f21, f23, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f23, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f23; op2:f22; dest:f21; op1val:0x0; op2val:0x800001;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f21, f23, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f19, rs2==f18, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f19; op2:f18; dest:f20; op1val:0x0; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f20, f19, f18, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f18; op2:f20; dest:f19; op1val:0x0; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f20, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f20; op2:f19; dest:f18; op1val:0x0; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f18, f20, f19, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f15, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f16; op2:f15; dest:f17; op1val:0x0; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f17, f16, f15, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rs2==f17, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f15; op2:f17; dest:f16; op1val:0x0; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f16, f15, f17, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f17, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f17; op2:f16; dest:f15; op1val:0x0; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f15, f17, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f13, rs2==f12, rd==f14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f13; op2:f12; dest:f14; op1val:0x0; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f14, f13, f12, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f12; op2:f14; dest:f13; op1val:0x0; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f14, rs2==f13, rd==f12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f14; op2:f13; dest:f12; op1val:0x0; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f12, f14, f13, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f9, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f10; op2:f9; dest:f11; op1val:0x0; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f11, f10, f9, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rs2==f11, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f9; op2:f11; dest:f10; op1val:0x0; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f10, f9, f11, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f11, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f11; op2:f10; dest:f9; op1val:0x0; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f9, f11, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f7, rs2==f6, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f7; op2:f6; dest:f8; op1val:0x0; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f8, f7, f6, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f6; op2:f8; dest:f7; op1val:0x80000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f8, rs2==f7, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f8; op2:f7; dest:f6; op1val:0x80000000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f6, f8, f7, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f3, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f4; op2:f3; dest:f5; op1val:0x80000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f5, f4, f3, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rs2==f5, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f3; op2:f5; dest:f4; op1val:0x80000000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f4, f3, f5, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f5, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f5; op2:f4; dest:f3; op1val:0x80000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f3, f5, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f1, rs2==f0, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f1; op2:f0; dest:f2; op1val:0x80000000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f2, f1, f0, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f0; op2:f2; dest:f1; op1val:0x80000000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f2, rs2==f1, rd==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f2; op2:f1; dest:f0; op1val:0x80000000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f0, f2, f1, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 64*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b19-01.S
deleted file mode 100644
index 686d6efbd..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fminm_b19-01.S
+++ /dev/null
@@ -1,409 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:10:02 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fminm.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fminm.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fminm_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rd != rs2, rs1==f31, rs2==f30, rd==f31,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f31; op2:f30; dest:f31; op1val:0x7f222105; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f29; op1val:0x7f222105; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f29, f30, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 == rs2 == rd, rs1==f28, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f28; op2:f28; dest:f28; op1val:0x7ec45459; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f28, f28, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 == rs2 != rd, rs1==f27, rs2==f27, rd==f30,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f27; op2:f27; dest:f30; op1val:0x7f222105; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f30, f27, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f29, rs2==f31, rd==f27,fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f29; op2:f31; dest:f27; op1val:0x7eb70362; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f27, f29, f31, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f25, rs2==f24, rd==f26,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f25; op2:f24; dest:f26; op1val:0x7f222105; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f26, f25, f24, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f26, rd==f25,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f24; op2:f26; dest:f25; op1val:0x7d81b404; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f25, f24, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f26, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x01b404 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f26; op2:f25; dest:f24; op1val:0x7f7fffff; op2val:0x7d81b404;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f24, f26, f25, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f21, rd==f23,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f22; op2:f21; dest:f23; op1val:0x7d81b404; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f23, f22, f21, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rs2==f23, rd==f22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x01b404 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f21; op2:f23; dest:f22; op1val:0x7f222105; op2val:0x7d81b404;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f22, f21, f23, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f23, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f23; op2:f22; dest:f21; op1val:0x7f222105; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f21, f23, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f19, rs2==f18, rd==f20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f19; op2:f18; dest:f20; op1val:0x7f2eabd8; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f20, f19, f18, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f18; op2:f20; dest:f19; op1val:0x7f222105; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f20, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f20; op2:f19; dest:f18; op1val:0x7d81b404; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f18, f20, f19, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f15, rd==f17,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x01b404 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f16; op2:f15; dest:f17; op1val:0xff7fffff; op2val:0x7d81b404;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f17, f16, f15, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rs2==f17, rd==f16,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f15; op2:f17; dest:f16; op1val:0x7d81b404; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f16, f15, f17, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f17, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f17; op2:f16; dest:f15; op1val:0x7f222105; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f15, f17, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f13, rs2==f12, rd==f14,fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f13; op2:f12; dest:f14; op1val:0xfee4815a; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f14, f13, f12, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f12; op2:f14; dest:f13; op1val:0x7f222105; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f14, rs2==f13, rd==f12,fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f14; op2:f13; dest:f12; op1val:0xfe9ffb35; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f12, f14, f13, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f9, rd==f11,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f10; op2:f9; dest:f11; op1val:0x7f222105; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f11, f10, f9, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rs2==f11, rd==f10,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f9; op2:f11; dest:f10; op1val:0x7d81b404; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f10, f9, f11, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f11, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f11; op2:f10; dest:f9; op1val:0x7f222105; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f9, f11, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f7, rs2==f6, rd==f8,fs1 == 0 and fe1 == 0xf7 and fm1 == 0x4f866d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f7; op2:f6; dest:f8; op1val:0x7bcf866d; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f8, f7, f6, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x4f866d and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f6; op2:f8; dest:f7; op1val:0xff7fffff; op2val:0x7bcf866d;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f8, rs2==f7, rd==f6,fs1 == 0 and fe1 == 0xf7 and fm1 == 0x4f866d and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f8; op2:f7; dest:f6; op1val:0x7bcf866d; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f6, f8, f7, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f3, rd==f5,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x4f866d and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f4; op2:f3; dest:f5; op1val:0x7f222105; op2val:0x7bcf866d;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f5, f4, f3, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rs2==f5, rd==f4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f3; op2:f5; dest:f4; op1val:0x7f222105; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f4, f3, f5, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f5, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f5; op2:f4; dest:f3; op1val:0x177770; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f3, f5, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f1, rs2==f0, rd==f2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f1; op2:f0; dest:f2; op1val:0x7f39f704; op2val:0x177770;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f2, f1, f0, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f0; op2:f2; dest:f1; op1val:0x177770; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f2, rs2==f1, rd==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and  fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff  
-/* opcode: fminm.s ; op1:f2; op2:f1; dest:f0; op1val:0x7f222105; op2val:0x177770;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f0, f2, f1, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2125923170,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2133765080,32,FLEN)
-NAN_BOXED(2133765080,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4276388186,32,FLEN)
-NAN_BOXED(4276388186,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4271897397,32,FLEN)
-NAN_BOXED(4271897397,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(2077197933,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2077197933,32,FLEN)
-NAN_BOXED(2077197933,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2077197933,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(1764005,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(2134505220,32,FLEN)
-NAN_BOXED(2134505220,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(1764005,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 64*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fround.d_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fround.d_b1-01.S
deleted file mode 100644
index 19fcf6e68..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fround.d_b1-01.S
+++ /dev/null
@@ -1,353 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:11:55 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fround.d.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fround.d instruction of the RISC-V RV64FD_Zicsr_Zfa extension for the fround.d_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fround.d_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f31, f30, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f29; dest:f29; op1val:0x8000000000000000; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f29, f29, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f31; dest:f30; op1val:0x1; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f30, f31, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f27; dest:f28; op1val:0x8000000000000001; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f28, f27, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f27, f28, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f25; dest:f26; op1val:0x8000000000000002; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f26, f25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f26; dest:f25; op1val:0xfffffffffffff; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f25, f26, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f23; dest:f24; op1val:0x800fffffffffffff; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f24, f23, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f24; dest:f23; op1val:0x10000000000000; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f23, f24, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f21; dest:f22; op1val:0x8010000000000000; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f22, f21, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f22; dest:f21; op1val:0x10000000000002; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f21, f22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f19; dest:f20; op1val:0x8010000000000002; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f20, f19, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f20; dest:f19; op1val:0x7fefffffffffffff; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f19, f20, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f17; dest:f18; op1val:0xffefffffffffffff; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f18, f17, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f18; dest:f17; op1val:0x7ff0000000000000; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f17, f18, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f15; dest:f16; op1val:0xfff0000000000000; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f16, f15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f16; dest:f15; op1val:0x7ff8000000000000; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f15, f16, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f13; dest:f14; op1val:0xfff8000000000000; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f14, f13, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f14; dest:f13; op1val:0x7ff8000000000001; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f13, f14, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f11; dest:f12; op1val:0xfff8000000000001; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f12, f11, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f12; dest:f11; op1val:0x7ff0000000000001; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f11, f12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f9; dest:f10; op1val:0xfff0000000000001; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f10, f9, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f10; dest:f9; op1val:0x3ff0000000000000; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f9, f10, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.d ; op1:f7; dest:f8; op1val:0xbf80000000000000; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f8, f7, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f8, rd==f7,
-/* opcode: fround.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
-val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f7, f8, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f5, rd==f6,
-/* opcode: fround.d ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
-val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f6, f5, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f6, rd==f5,
-/* opcode: fround.d ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
-val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f5, f6, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rd==f4,
-/* opcode: fround.d ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
-val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f4, f3, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f4, rd==f3,
-/* opcode: fround.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
-val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f3, f4, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f1, rd==f2,
-/* opcode: fround.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
-val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f2, f1, dyn, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f2, rd==f1,
-/* opcode: fround.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
-val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f1, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f0,
-/* opcode: fround.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
-val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f31, f0, dyn, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rd==f0,
-/* opcode: fround.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
-val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.d, f0, f31, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(9223372036854775808,64,FLEN)
-NAN_BOXED(1,64,FLEN)
-NAN_BOXED(9223372036854775809,64,FLEN)
-NAN_BOXED(2,64,FLEN)
-NAN_BOXED(9223372036854775810,64,FLEN)
-NAN_BOXED(4503599627370495,64,FLEN)
-NAN_BOXED(9227875636482146303,64,FLEN)
-NAN_BOXED(4503599627370496,64,FLEN)
-NAN_BOXED(9227875636482146304,64,FLEN)
-NAN_BOXED(4503599627370498,64,FLEN)
-NAN_BOXED(9227875636482146306,64,FLEN)
-NAN_BOXED(9218868437227405311,64,FLEN)
-NAN_BOXED(18442240474082181119,64,FLEN)
-NAN_BOXED(9218868437227405312,64,FLEN)
-NAN_BOXED(18442240474082181120,64,FLEN)
-NAN_BOXED(9221120237041090560,64,FLEN)
-NAN_BOXED(18444492273895866368,64,FLEN)
-NAN_BOXED(9221120237041090561,64,FLEN)
-NAN_BOXED(18444492273895866369,64,FLEN)
-NAN_BOXED(9218868437227405313,64,FLEN)
-NAN_BOXED(18442240474082181121,64,FLEN)
-NAN_BOXED(4607182418800017408,64,FLEN)
-NAN_BOXED(13799029258263199744,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 66*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fround_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fround_b1-01.S
deleted file mode 100644
index 4e09a6b54..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/D_Zfa/src/fround_b1-01.S
+++ /dev/null
@@ -1,353 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:11:49 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fround.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fround.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fround_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*64.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fround_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f31, f30, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f29; dest:f29; op1val:0x80000000; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f29, f29, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f31; dest:f30; op1val:0x1; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f30, f31, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f28, f27, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f27, f28, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f25; dest:f26; op1val:0x807ffffe; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f26, f25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f26; dest:f25; op1val:0x7fffff; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f25, f26, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f23; dest:f24; op1val:0x807fffff; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f24, f23, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f23, f24, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f22, f21, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f22; dest:f21; op1val:0x800001; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f21, f22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f19; dest:f20; op1val:0x80855555; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f20, f19, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f20; dest:f19; op1val:0x7f7fffff; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f19, f20, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f17; dest:f18; op1val:0xff7fffff; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f18, f17, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f18; dest:f17; op1val:0x7f800000; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f17, f18, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f15; dest:f16; op1val:0xff800000; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f16, f15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f16; dest:f15; op1val:0x7fc00000; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f15, f16, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f13; dest:f14; op1val:0xffc00000; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f14, f13, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f14; dest:f13; op1val:0x7fc00001; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f13, f14, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f11; dest:f12; op1val:0xffc55555; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f12, f11, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f12; dest:f11; op1val:0x7f800001; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f11, f12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f9; dest:f10; op1val:0xffaaaaaa; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f10, f9, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f10; dest:f9; op1val:0x3f800000; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f9, f10, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7  and rs1_nan_prefix == 0xffffffff  
-/* opcode: fround.s ; op1:f7; dest:f8; op1val:0xbf800000; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f8, f7, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f8, rd==f7,
-/* opcode: fround.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
-val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f7, f8, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f5, rd==f6,
-/* opcode: fround.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
-val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f6, f5, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f6, rd==f5,
-/* opcode: fround.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
-val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f5, f6, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rd==f4,
-/* opcode: fround.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
-val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f4, f3, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f4, rd==f3,
-/* opcode: fround.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
-val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f3, f4, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f1, rd==f2,
-/* opcode: fround.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
-val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f2, f1, dyn, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f2, rd==f1,
-/* opcode: fround.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
-val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f1, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f0,
-/* opcode: fround.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
-val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f31, f0, dyn, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rd==f0,
-/* opcode: fround.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
-val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f0, f31, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-NAN_BOXED(0,64,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 66*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b1-01.S
deleted file mode 100644
index b59ab190d..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b1-01.S
+++ /dev/null
@@ -1,4740 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:13:17 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fleq.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fleq.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fleq_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f29; op2:f29; dest:x30; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f30; op2:f31; dest:x29; op1val:0x0; op2val:0x1;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f28; op2:f27; dest:x28; op1val:0x0; op2val:0x80000001;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f27; op2:f28; dest:x27; op1val:0x0; op2val:0x2;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f26; op2:f25; dest:x26; op1val:0x0; op2val:0x807ffffe;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f25; op2:f26; dest:x25; op1val:0x0; op2val:0x7fffff;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f24; op2:f23; dest:x24; op1val:0x0; op2val:0x807fffff;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f23; op2:f24; dest:x23; op1val:0x0; op2val:0x800000;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f22; op2:f21; dest:x22; op1val:0x0; op2val:0x80800000;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f21; op2:f22; dest:x21; op1val:0x0; op2val:0x800001;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f20; op2:f19; dest:x20; op1val:0x0; op2val:0x80855555;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f19; op2:f20; dest:x19; op1val:0x0; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f18; op2:f17; dest:x18; op1val:0x0; op2val:0xff7fffff;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f17; op2:f18; dest:x17; op1val:0x0; op2val:0x7f800000;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f16; op2:f15; dest:x16; op1val:0x0; op2val:0xff800000;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f15; op2:f16; dest:x15; op1val:0x0; op2val:0x7fc00000;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f14; op2:f13; dest:x14; op1val:0x0; op2val:0xffc00000;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f13; op2:f14; dest:x13; op1val:0x0; op2val:0x7fc00001;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f12; op2:f11; dest:x12; op1val:0x0; op2val:0xffc55555;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f11; op2:f12; dest:x11; op1val:0x0; op2val:0x7f800001;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f10; op2:f9; dest:x10; op1val:0x0; op2val:0xffaaaaaa;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f9; op2:f10; dest:x9; op1val:0x0; op2val:0x3f800000;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f8; op2:f7; dest:x8; op1val:0x0; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f7; op2:f8; dest:x7; op1val:0x80000000; op2val:0x0;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f6; op2:f5; dest:x6; op1val:0x80000000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f5; op2:f6; dest:x5; op1val:0x80000000; op2val:0x1;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f4; op2:f3; dest:x4; op1val:0x80000000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f3; op2:f4; dest:x3; op1val:0x80000000; op2val:0x2;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f2; op2:f1; dest:x2; op1val:0x80000000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f1; op2:f2; dest:x1; op1val:0x80000000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f0; op2:f31; dest:x31; op1val:0x80000000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f0; dest:x31; op1val:0x80000000; op2val:0x800000;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x0; op1val:0x80000000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x800001;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x0;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80000000;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x1;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80000001;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x2;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x800000;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80800000;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x800001;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80855555;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xff800000;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x0;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x1;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x2;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x800000;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x800001;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x0;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80000000;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x1;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80000001;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x2;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x800000;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80800000;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x800001;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80855555;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xff800000;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x0;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x1;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x2;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x800000;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x800001;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x0;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x1;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x2;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x0;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x1;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x2;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x0;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x1;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x2;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x800000;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x800001;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x0;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80000000;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x1;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80000001;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x2;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x800000;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80800000;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x800001;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80855555;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xff800000;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x0;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x1;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x2;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x0;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x1;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x2;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x0;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x1;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x2;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x800000;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x800001;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x0;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x1;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x2;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x800000;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x800001;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x0;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x1;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x2;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x800000;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x800001;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x0;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80000000;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x1;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80000001;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x2;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x800000;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80800000;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x800001;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80855555;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xff800000;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x0;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x1;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x2;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x800000;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x800001;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x0;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x1;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x2;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x0;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x1;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x2;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x80000000;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-test_dataset_1:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
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-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 80*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b19-01.S
deleted file mode 100644
index 2544b5700..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fleq_b19-01.S
+++ /dev/null
@@ -1,8712 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:13:17 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fleq.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fleq.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fleq_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x7e36c1bf;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f29; op2:f29; dest:x30; op1val:0x7e36c1bf; op2val:0x7e36c1bf;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x4038a5 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f30; op2:f31; dest:x29; op1val:0x7f7fffff; op2val:0x7d4038a5;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0xfa and fm1 == 0x4038a5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f28; op2:f27; dest:x28; op1val:0x7d4038a5; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f27; op2:f28; dest:x27; op1val:0x7f7fffff; op2val:0x7ef046ce;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f26; op2:f25; dest:x26; op1val:0x7e36c1bf; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f25; op2:f26; dest:x25; op1val:0x7e36c1bf; op2val:0x7e472f12;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f24; op2:f23; dest:x24; op1val:0x7e472f12; op2val:0x7e36c1bf;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f23; op2:f24; dest:x23; op1val:0x7e36c1bf; op2val:0x7f2099c0;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x007b00 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f22; op2:f21; dest:x22; op1val:0x7f7fffff; op2val:0x7d807b00;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0xfb and fm1 == 0x007b00 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f21; op2:f22; dest:x21; op1val:0x7d807b00; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f20; op2:f19; dest:x20; op1val:0x7f7fffff; op2val:0x7f2099c0;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f19; op2:f20; dest:x19; op1val:0x7e36c1bf; op2val:0x7ef3c956;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x430778 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f18; op2:f17; dest:x18; op1val:0x7f7fffff; op2val:0x7d430778;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0xfa and fm1 == 0x430778 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f17; op2:f18; dest:x17; op1val:0x7d430778; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f16; op2:f15; dest:x16; op1val:0x7f7fffff; op2val:0x7ef3c956;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f15; op2:f16; dest:x15; op1val:0x7e36c1bf; op2val:0xfeaf0416;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x0c0345 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f14; op2:f13; dest:x14; op1val:0x7f7fffff; op2val:0xfd0c0345;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c0345 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f13; op2:f14; dest:x13; op1val:0xfd0c0345; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f12; op2:f11; dest:x12; op1val:0x7f7fffff; op2val:0xfeaf0416;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f11; op2:f12; dest:x11; op1val:0x7e36c1bf; op2val:0xff336b1f;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0f88e6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f10; op2:f9; dest:x10; op1val:0x7f7fffff; op2val:0xfd8f88e6;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 1 and fe1 == 0xfb and fm1 == 0x0f88e6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f9; op2:f10; dest:x9; op1val:0xfd8f88e6; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f8; op2:f7; dest:x8; op1val:0x7f7fffff; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f7; op2:f8; dest:x7; op1val:0x7e36c1bf; op2val:0xff130229;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x6b36a9 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f6; op2:f5; dest:x6; op1val:0x7f7fffff; op2val:0xfd6b36a9;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0xfa and fm1 == 0x6b36a9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f5; op2:f6; dest:x5; op1val:0xfd6b36a9; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f4; op2:f3; dest:x4; op1val:0x7f7fffff; op2val:0xff130229;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f3; op2:f4; dest:x3; op1val:0x7e36c1bf; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x20dd41 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f2; op2:f1; dest:x2; op1val:0x7f7fffff; op2val:0xfd20dd41;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0xfa and fm1 == 0x20dd41 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f1; op2:f2; dest:x1; op1val:0xfd20dd41; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f0; op2:f31; dest:x31; op1val:0x7f7fffff; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f0; dest:x31; op1val:0x7e36c1bf; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x0; op1val:0xfdcaaeb1; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0xfb and fm2 == 0x02ddf4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x7d82ddf4;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x02ddf4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d82ddf4; op2val:0x42216f;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x42216f;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a94b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68e714 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xa94b; op2val:0x7e68e714;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68e714 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a94b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e68e714; op2val:0xa94b;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a94b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xa94b; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a94b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0xa94b;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0xfc and fm2 == 0x301931 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x7e301931;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x301931 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e301931; op2val:0x42216f;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0xfb and fm2 == 0x620ff4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x7de20ff4;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x620ff4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7de20ff4; op2val:0x42216f;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39119c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x7db9119c;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39119c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7db9119c; op2val:0x42216f;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0c1bbb and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0xfd8c1bbb;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0c1bbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8c1bbb; op2val:0x42216f;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x069cf1 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x0fbbb6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x69cf1; op2val:0xfe8fbbb6;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x0fbbb6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x069cf1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe8fbbb6; op2val:0x69cf1;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x069cf1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x69cf1; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x069cf1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x69cf1;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x3b633c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0xfdbb633c;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x3b633c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdbb633c; op2val:0x42216f;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0xfc and fm2 == 0x163ab8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0xfe163ab8;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x163ab8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe163ab8; op2val:0x42216f;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0xfa and fm2 == 0x370ed0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0xfd370ed0;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x370ed0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x42216f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd370ed0; op2val:0x42216f;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x42216f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x42216f; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x7f0;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 0 and fe1 == 0x81 and fm1 == 0x425723 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x40c25723; op2val:0x7f0;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x425723 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x40c25723;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0x81 and fm2 == 0x425723 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x40c25723;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x4038a5 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d4038a5; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0xfa and fm2 == 0x4038a5 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x7d4038a5;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x4038a5 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d4038a5; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0xff130229;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x4038a5 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d4038a5; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 0 and fe2 == 0xfa and fm2 == 0x4038a5 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0x7d4038a5;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x4038a5 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d4038a5; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x11638a;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x11638a;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002c83 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2c83; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002c83 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x2c83;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002c83 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2c83; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002c83 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x2c83;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x11638a;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x11638a;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x11638a;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01bd27 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1bd27; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01bd27 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x1bd27;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01bd27 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1bd27; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01bd27 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x1bd27;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x11638a;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x11638a;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11638a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x11638a;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11638a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11638a; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x7f0;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x4c679b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fcc679b; op2val:0x7f0;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c679b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x3fcc679b;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x7046ce and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4c679b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef046ce; op2val:0x3fcc679b;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0xff130229;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x02ddf4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x7d82ddf4;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x02ddf4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d82ddf4; op2val:0x481322;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x481322;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b882 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68e714 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xb882; op2val:0x7e68e714;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68e714 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b882 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e68e714; op2val:0xb882;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00b882 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xb882; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00b882 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0xb882;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x301931 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x7e301931;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x301931 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e301931; op2val:0x481322;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x620ff4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x7de20ff4;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x620ff4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7de20ff4; op2val:0x481322;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39119c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x7db9119c;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39119c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7db9119c; op2val:0x481322;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0c1bbb and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0xfd8c1bbb;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0c1bbb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8c1bbb; op2val:0x481322;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x07351d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x0fbbb6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7351d; op2val:0xfe8fbbb6;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x0fbbb6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07351d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe8fbbb6; op2val:0x7351d;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x07351d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7351d; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07351d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x7351d;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x3b633c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0xfdbb633c;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x3b633c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdbb633c; op2val:0x481322;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x163ab8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0xfe163ab8;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x163ab8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe163ab8; op2val:0x481322;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x370ed0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0xfd370ed0;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x370ed0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x481322 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd370ed0; op2val:0x481322;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x481322 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x481322; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x7f0;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x81 and fm1 == 0x53cf02 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x40d3cf02; op2val:0x7f0;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x53cf02 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x40d3cf02;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x53cf02 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e472f12; op2val:0x40d3cf02;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x007b00 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d807b00; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x007b00 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x7d807b00;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x007b00 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d807b00; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0xff130229;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x007b00 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d807b00; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 0 and fe2 == 0xfb and fm2 == 0x007b00 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0x7d807b00;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x007b00 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d807b00; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003b82 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3b82; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003b82 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x3b82;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003b82 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3b82; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003b82 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x3b82;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025314 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x25314; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025314 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x25314;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025314 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x25314; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025314 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x25314;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x173ecf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x173ecf;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x173ecf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x173ecf; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x7f0;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x089fb6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x40089fb6; op2val:0x7f0;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x089fb6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x40089fb6;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2099c0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x089fb6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f2099c0; op2val:0x40089fb6;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x430778 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d430778; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0xfa and fm2 == 0x430778 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x7d430778;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x430778 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d430778; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0xff130229;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x430778 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d430778; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 0 and fe2 == 0xfa and fm2 == 0x430778 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0x7d430778;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x430778 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d430778; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x11a491;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x11a491;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002d2a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2d2a; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002d2a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x2d2a;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002d2a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2d2a; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002d2a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x2d2a;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x11a491;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x11a491;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x11a491;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c3a8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c3a8; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01c3a8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x1c3a8;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01c3a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c3a8; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01c3a8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x1c3a8;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x11a491;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x11a491;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x11a491 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x11a491;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x11a491 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x11a491; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x7f0;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x4f63fe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fcf63fe; op2val:0x7f0;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4f63fe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x3fcf63fe;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x73c956 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x4f63fe and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ef3c956; op2val:0x3fcf63fe;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c0345 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c0345; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x0c0345 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xfd0c0345;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c0345 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c0345; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xff130229;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c0345 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c0345; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x0c0345 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xfd0c0345;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c0345 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c0345; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00206c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000206c; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00206c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x8000206c;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00206c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000206c; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00206c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x8000206c;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01443f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001443f; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01443f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x8001443f;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01443f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001443f; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01443f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x8001443f;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caa79 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x800caa79;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caa79 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caa79; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0x7f0;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x14e31a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf94e31a; op2val:0x7f0;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x14e31a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbf94e31a;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0416 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x14e31a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0416; op2val:0xbf94e31a;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0f88e6 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8f88e6; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0f88e6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xfd8f88e6;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0f88e6 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8f88e6; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xff130229;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0f88e6 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8f88e6; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0f88e6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xfd8f88e6;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0f88e6 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8f88e6; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00427b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000427b; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00427b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x8000427b;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00427b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000427b; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00427b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x8000427b;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0298ce and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800298ce; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0298ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800298ce;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0298ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800298ce; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0298ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x800298ce;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19f813 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x8019f813;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19f813 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019f813; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0x7f0;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 1 and fe1 == 0x80 and fm1 == 0x18a1e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc018a1e0; op2val:0x7f0;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x18a1e0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc018a1e0;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x336b1f and fs2 == 1 and fe2 == 0x80 and fm2 == 0x18a1e0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff336b1f; op2val:0xc018a1e0;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x6b36a9 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd6b36a9; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x6b36a9 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xfd6b36a9;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xff130229;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x6b36a9 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd6b36a9; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xff130229;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x6b36a9 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd6b36a9; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x6b36a9 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xfd6b36a9;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x6b36a9 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd6b36a9; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003678 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80003678; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003678 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80003678;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x003678 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80003678; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x003678 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x80003678;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0220b7 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800220b7; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0220b7 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800220b7;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0220b7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800220b7; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0220b7 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x800220b7;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x15472c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x8015472c;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x15472c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8015472c; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0x7f0;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x7a1f35 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbffa1f35; op2val:0x7f0;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x7a1f35 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbffa1f35;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x130229 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x7a1f35 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff130229; op2val:0xbffa1f35;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x20dd41 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd20dd41; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x20dd41 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xfd20dd41;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x20dd41 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd20dd41; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x20dd41 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd20dd41; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x20dd41 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xfd20dd41;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x20dd41 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd20dd41; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002540 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80002540; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002540 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80002540;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002540 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80002540; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002540 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x80002540;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x017489 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80017489; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x017489 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80017489;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x017489 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80017489; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x017489 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x80017489;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e8d5c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x800e8d5c;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e8d5c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e8d5c; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x2b0f6c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbfab0f6c; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x2b0f6c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbfab0f6c;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x491492 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x2b0f6c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec91492; op2val:0xbfab0f6c;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7d5a5e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xff7d5a5e;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-
-inst_578:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1110*FLEN/8, x10, x6, x7)
-
-inst_579:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1112*FLEN/8, x10, x6, x7)
-
-inst_580:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1114*FLEN/8, x10, x6, x7)
-
-inst_581:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7d5a5e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7d5a5e; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1116*FLEN/8, x10, x6, x7)
-
-inst_582:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1118*FLEN/8, x10, x6, x7)
-
-inst_583:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x02ddf4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x7d82ddf4;
-valaddr_reg:x9; val_offset:1120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1120*FLEN/8, x10, x6, x7)
-
-inst_584:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x02ddf4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d82ddf4; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1122*FLEN/8, x10, x6, x7)
-
-inst_585:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1124*FLEN/8, x10, x6, x7)
-
-inst_586:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1126*FLEN/8, x10, x6, x7)
-
-inst_587:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1128*FLEN/8, x10, x6, x7)
-
-inst_588:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x005de0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68e714 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80005de0; op2val:0x7e68e714;
-valaddr_reg:x9; val_offset:1130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1130*FLEN/8, x10, x6, x7)
-
-inst_589:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68e714 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005de0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e68e714; op2val:0x80005de0;
-valaddr_reg:x9; val_offset:1132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1132*FLEN/8, x10, x6, x7)
-
-inst_590:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x005de0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80005de0; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1134*FLEN/8, x10, x6, x7)
-
-inst_591:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x005de0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x80005de0;
-valaddr_reg:x9; val_offset:1136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1136*FLEN/8, x10, x6, x7)
-
-inst_592:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1138*FLEN/8, x10, x6, x7)
-
-inst_593:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x301931 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x7e301931;
-valaddr_reg:x9; val_offset:1140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1140*FLEN/8, x10, x6, x7)
-
-inst_594:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x301931 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e301931; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1142*FLEN/8, x10, x6, x7)
-
-inst_595:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1144*FLEN/8, x10, x6, x7)
-
-inst_596:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1146*FLEN/8, x10, x6, x7)
-
-inst_597:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x620ff4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x7de20ff4;
-valaddr_reg:x9; val_offset:1148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1148*FLEN/8, x10, x6, x7)
-
-inst_598:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x620ff4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7de20ff4; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1150*FLEN/8, x10, x6, x7)
-
-inst_599:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1152*FLEN/8, x10, x6, x7)
-
-inst_600:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1154*FLEN/8, x10, x6, x7)
-
-inst_601:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39119c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x7db9119c;
-valaddr_reg:x9; val_offset:1156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1156*FLEN/8, x10, x6, x7)
-
-inst_602:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39119c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7db9119c; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1158*FLEN/8, x10, x6, x7)
-
-inst_603:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1160*FLEN/8, x10, x6, x7)
-
-inst_604:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1162*FLEN/8, x10, x6, x7)
-
-inst_605:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0c1bbb and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0xfd8c1bbb;
-valaddr_reg:x9; val_offset:1164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1164*FLEN/8, x10, x6, x7)
-
-inst_606:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0c1bbb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8c1bbb; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1166*FLEN/8, x10, x6, x7)
-
-inst_607:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1168*FLEN/8, x10, x6, x7)
-
-inst_608:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1170*FLEN/8, x10, x6, x7)
-
-inst_609:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03aac2 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x0fbbb6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8003aac2; op2val:0xfe8fbbb6;
-valaddr_reg:x9; val_offset:1172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1172*FLEN/8, x10, x6, x7)
-
-inst_610:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x0fbbb6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03aac2 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe8fbbb6; op2val:0x8003aac2;
-valaddr_reg:x9; val_offset:1174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1174*FLEN/8, x10, x6, x7)
-
-inst_611:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x03aac2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8003aac2; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1176*FLEN/8, x10, x6, x7)
-
-inst_612:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x03aac2 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x8003aac2;
-valaddr_reg:x9; val_offset:1178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1178*FLEN/8, x10, x6, x7)
-
-inst_613:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1180*FLEN/8, x10, x6, x7)
-
-inst_614:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x3b633c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0xfdbb633c;
-valaddr_reg:x9; val_offset:1182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1182*FLEN/8, x10, x6, x7)
-
-inst_615:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x3b633c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdbb633c; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1184*FLEN/8, x10, x6, x7)
-
-inst_616:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1186*FLEN/8, x10, x6, x7)
-
-inst_617:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1188*FLEN/8, x10, x6, x7)
-
-inst_618:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x163ab8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0xfe163ab8;
-valaddr_reg:x9; val_offset:1190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1190*FLEN/8, x10, x6, x7)
-
-inst_619:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x163ab8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe163ab8; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1192*FLEN/8, x10, x6, x7)
-
-inst_620:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1194*FLEN/8, x10, x6, x7)
-
-inst_621:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1196*FLEN/8, x10, x6, x7)
-
-inst_622:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x370ed0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0xfd370ed0;
-valaddr_reg:x9; val_offset:1198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1198*FLEN/8, x10, x6, x7)
-
-inst_623:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x370ed0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x24ab9b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd370ed0; op2val:0x8024ab9b;
-valaddr_reg:x9; val_offset:1200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1200*FLEN/8, x10, x6, x7)
-
-inst_624:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x24ab9b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8024ab9b; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1202*FLEN/8, x10, x6, x7)
-
-inst_625:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1204*FLEN/8, x10, x6, x7)
-
-inst_626:// fs1 == 1 and fe1 == 0x80 and fm1 == 0x578765 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc0578765; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1206*FLEN/8, x10, x6, x7)
-
-inst_627:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x578765 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc0578765;
-valaddr_reg:x9; val_offset:1208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1208*FLEN/8, x10, x6, x7)
-
-inst_628:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x578765 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0xc0578765;
-valaddr_reg:x9; val_offset:1210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1210*FLEN/8, x10, x6, x7)
-
-inst_629:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1212*FLEN/8, x10, x6, x7)
-
-inst_630:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x02ddf4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d82ddf4; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1214*FLEN/8, x10, x6, x7)
-
-inst_631:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x02ddf4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7d82ddf4;
-valaddr_reg:x9; val_offset:1216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1216*FLEN/8, x10, x6, x7)
-
-inst_632:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1218*FLEN/8, x10, x6, x7)
-
-inst_633:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1220*FLEN/8, x10, x6, x7)
-
-inst_634:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1222*FLEN/8, x10, x6, x7)
-
-inst_635:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x239571 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7f239571;
-valaddr_reg:x9; val_offset:1224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1224*FLEN/8, x10, x6, x7)
-
-inst_636:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1226*FLEN/8, x10, x6, x7)
-
-inst_637:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x02ddf4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d82ddf4; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1228*FLEN/8, x10, x6, x7)
-
-inst_638:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1230*FLEN/8, x10, x6, x7)
-
-inst_639:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1232*FLEN/8, x10, x6, x7)
-
-inst_640:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1234*FLEN/8, x10, x6, x7)
-
-inst_641:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1236*FLEN/8, x10, x6, x7)
-
-inst_642:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1238*FLEN/8, x10, x6, x7)
-
-inst_643:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1240*FLEN/8, x10, x6, x7)
-
-inst_644:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1242*FLEN/8, x10, x6, x7)
-
-inst_645:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1244*FLEN/8, x10, x6, x7)
-
-inst_646:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1246*FLEN/8, x10, x6, x7)
-
-inst_647:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1248*FLEN/8, x10, x6, x7)
-
-inst_648:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1250*FLEN/8, x10, x6, x7)
-
-inst_649:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x239571 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f239571; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1252*FLEN/8, x10, x6, x7)
-
-inst_650:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1254*FLEN/8, x10, x6, x7)
-
-inst_651:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x02ddf4 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d82ddf4; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1256*FLEN/8, x10, x6, x7)
-
-inst_652:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1258*FLEN/8, x10, x6, x7)
-
-inst_653:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003c9d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3c9d; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1260*FLEN/8, x10, x6, x7)
-
-inst_654:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003c9d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x3c9d;
-valaddr_reg:x9; val_offset:1262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1262*FLEN/8, x10, x6, x7)
-
-inst_655:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003c9d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3c9d; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1264*FLEN/8, x10, x6, x7)
-
-inst_656:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003c9d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x3c9d;
-valaddr_reg:x9; val_offset:1266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1266*FLEN/8, x10, x6, x7)
-
-inst_657:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1268*FLEN/8, x10, x6, x7)
-
-inst_658:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1270*FLEN/8, x10, x6, x7)
-
-inst_659:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1272*FLEN/8, x10, x6, x7)
-
-inst_660:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1274*FLEN/8, x10, x6, x7)
-
-inst_661:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1276*FLEN/8, x10, x6, x7)
-
-inst_662:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1278*FLEN/8, x10, x6, x7)
-
-inst_663:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1280*FLEN/8, x10, x6, x7)
-
-inst_664:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1282*FLEN/8, x10, x6, x7)
-
-inst_665:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1284*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_5)
-
-inst_666:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025e22 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x25e22; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1286*FLEN/8, x10, x6, x7)
-
-inst_667:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025e22 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x25e22;
-valaddr_reg:x9; val_offset:1288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1288*FLEN/8, x10, x6, x7)
-
-inst_668:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025e22 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x25e22; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1290*FLEN/8, x10, x6, x7)
-
-inst_669:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025e22 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x25e22;
-valaddr_reg:x9; val_offset:1292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1292*FLEN/8, x10, x6, x7)
-
-inst_670:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1294*FLEN/8, x10, x6, x7)
-
-inst_671:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1296*FLEN/8, x10, x6, x7)
-
-inst_672:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1298*FLEN/8, x10, x6, x7)
-
-inst_673:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1300*FLEN/8, x10, x6, x7)
-
-inst_674:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1302*FLEN/8, x10, x6, x7)
-
-inst_675:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1304*FLEN/8, x10, x6, x7)
-
-inst_676:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1306*FLEN/8, x10, x6, x7)
-
-inst_677:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x0b2963 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x400b2963; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1308*FLEN/8, x10, x6, x7)
-
-inst_678:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0b2963 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x400b2963;
-valaddr_reg:x9; val_offset:1310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1310*FLEN/8, x10, x6, x7)
-
-inst_679:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x17ad58 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x0b2963 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x17ad58; op2val:0x400b2963;
-valaddr_reg:x9; val_offset:1312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1312*FLEN/8, x10, x6, x7)
-
-inst_680:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1314*FLEN/8, x10, x6, x7)
-
-inst_681:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68e714 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e68e714; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1316*FLEN/8, x10, x6, x7)
-
-inst_682:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x68e714 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7e68e714;
-valaddr_reg:x9; val_offset:1318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1318*FLEN/8, x10, x6, x7)
-
-inst_683:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1320*FLEN/8, x10, x6, x7)
-
-inst_684:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1322*FLEN/8, x10, x6, x7)
-
-inst_685:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1324*FLEN/8, x10, x6, x7)
-
-inst_686:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1326*FLEN/8, x10, x6, x7)
-
-inst_687:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68e714 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e68e714; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1328*FLEN/8, x10, x6, x7)
-
-inst_688:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1330*FLEN/8, x10, x6, x7)
-
-inst_689:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1332*FLEN/8, x10, x6, x7)
-
-inst_690:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1334*FLEN/8, x10, x6, x7)
-
-inst_691:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1336*FLEN/8, x10, x6, x7)
-
-inst_692:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1338*FLEN/8, x10, x6, x7)
-
-inst_693:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1340*FLEN/8, x10, x6, x7)
-
-inst_694:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1342*FLEN/8, x10, x6, x7)
-
-inst_695:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x68e714 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e68e714; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1344*FLEN/8, x10, x6, x7)
-
-inst_696:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1346*FLEN/8, x10, x6, x7)
-
-inst_697:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1348*FLEN/8, x10, x6, x7)
-
-inst_698:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1350*FLEN/8, x10, x6, x7)
-
-inst_699:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1352*FLEN/8, x10, x6, x7)
-
-inst_700:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a320 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0xa320;
-valaddr_reg:x9; val_offset:1354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1354*FLEN/8, x10, x6, x7)
-
-inst_701:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a320 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xa320; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1356*FLEN/8, x10, x6, x7)
-
-inst_702:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1358*FLEN/8, x10, x6, x7)
-
-inst_703:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1360*FLEN/8, x10, x6, x7)
-
-inst_704:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0068b4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x68b4;
-valaddr_reg:x9; val_offset:1362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1362*FLEN/8, x10, x6, x7)
-
-inst_705:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0068b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x68b4; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1364*FLEN/8, x10, x6, x7)
-
-inst_706:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1366*FLEN/8, x10, x6, x7)
-
-inst_707:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1368*FLEN/8, x10, x6, x7)
-
-inst_708:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0055b7 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x55b7;
-valaddr_reg:x9; val_offset:1370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1370*FLEN/8, x10, x6, x7)
-
-inst_709:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0055b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x55b7; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1372*FLEN/8, x10, x6, x7)
-
-inst_710:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1374*FLEN/8, x10, x6, x7)
-
-inst_711:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1376*FLEN/8, x10, x6, x7)
-
-inst_712:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0040e4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x800040e4;
-valaddr_reg:x9; val_offset:1378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1378*FLEN/8, x10, x6, x7)
-
-inst_713:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0040e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800040e4; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1380*FLEN/8, x10, x6, x7)
-
-inst_714:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1382*FLEN/8, x10, x6, x7)
-
-inst_715:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1384*FLEN/8, x10, x6, x7)
-
-inst_716:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x086d76 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x010a4a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x86d76; op2val:0x80010a4a;
-valaddr_reg:x9; val_offset:1386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1386*FLEN/8, x10, x6, x7)
-
-inst_717:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x010a4a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x086d76 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80010a4a; op2val:0x86d76;
-valaddr_reg:x9; val_offset:1388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1388*FLEN/8, x10, x6, x7)
-
-inst_718:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x086d76 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x86d76; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1390*FLEN/8, x10, x6, x7)
-
-inst_719:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x086d76 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x86d76;
-valaddr_reg:x9; val_offset:1392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1392*FLEN/8, x10, x6, x7)
-
-inst_720:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1394*FLEN/8, x10, x6, x7)
-
-inst_721:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0056ca and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x800056ca;
-valaddr_reg:x9; val_offset:1396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1396*FLEN/8, x10, x6, x7)
-
-inst_722:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0056ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800056ca; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1398*FLEN/8, x10, x6, x7)
-
-inst_723:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1400*FLEN/8, x10, x6, x7)
-
-inst_724:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1402*FLEN/8, x10, x6, x7)
-
-inst_725:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008b29 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x80008b29;
-valaddr_reg:x9; val_offset:1404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1404*FLEN/8, x10, x6, x7)
-
-inst_726:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x008b29 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80008b29; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1406*FLEN/8, x10, x6, x7)
-
-inst_727:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1408*FLEN/8, x10, x6, x7)
-
-inst_728:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1410*FLEN/8, x10, x6, x7)
-
-inst_729:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002a64 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x80002a64;
-valaddr_reg:x9; val_offset:1412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1412*FLEN/8, x10, x6, x7)
-
-inst_730:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002a64 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x5446a0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80002a64; op2val:0x5446a0;
-valaddr_reg:x9; val_offset:1414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1414*FLEN/8, x10, x6, x7)
-
-inst_731:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x5446a0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5446a0; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1416*FLEN/8, x10, x6, x7)
-
-inst_732:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1418*FLEN/8, x10, x6, x7)
-
-inst_733:// fs1 == 0 and fe1 == 0x81 and fm1 == 0x77aa21 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x40f7aa21; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1420*FLEN/8, x10, x6, x7)
-
-inst_734:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x77aa21 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x40f7aa21;
-valaddr_reg:x9; val_offset:1422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1422*FLEN/8, x10, x6, x7)
-
-inst_735:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00d7bf and fs2 == 0 and fe2 == 0x81 and fm2 == 0x77aa21 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xd7bf; op2val:0x40f7aa21;
-valaddr_reg:x9; val_offset:1424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1424*FLEN/8, x10, x6, x7)
-
-inst_736:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1426*FLEN/8, x10, x6, x7)
-
-inst_737:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x301931 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e301931; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1428*FLEN/8, x10, x6, x7)
-
-inst_738:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x301931 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7e301931;
-valaddr_reg:x9; val_offset:1430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1430*FLEN/8, x10, x6, x7)
-
-inst_739:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1432*FLEN/8, x10, x6, x7)
-
-inst_740:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1434*FLEN/8, x10, x6, x7)
-
-inst_741:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1436*FLEN/8, x10, x6, x7)
-
-inst_742:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1438*FLEN/8, x10, x6, x7)
-
-inst_743:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x301931 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e301931; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1440*FLEN/8, x10, x6, x7)
-
-inst_744:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1442*FLEN/8, x10, x6, x7)
-
-inst_745:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1444*FLEN/8, x10, x6, x7)
-
-inst_746:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1446*FLEN/8, x10, x6, x7)
-
-inst_747:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1448*FLEN/8, x10, x6, x7)
-
-inst_748:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1450*FLEN/8, x10, x6, x7)
-
-inst_749:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1452*FLEN/8, x10, x6, x7)
-
-inst_750:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1454*FLEN/8, x10, x6, x7)
-
-inst_751:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x301931 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e301931; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1456*FLEN/8, x10, x6, x7)
-
-inst_752:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1458*FLEN/8, x10, x6, x7)
-
-inst_753:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00a320 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xa320; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1460*FLEN/8, x10, x6, x7)
-
-inst_754:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00a320 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0xa320;
-valaddr_reg:x9; val_offset:1462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1462*FLEN/8, x10, x6, x7)
-
-inst_755:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1464*FLEN/8, x10, x6, x7)
-
-inst_756:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1466*FLEN/8, x10, x6, x7)
-
-inst_757:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1468*FLEN/8, x10, x6, x7)
-
-inst_758:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1470*FLEN/8, x10, x6, x7)
-
-inst_759:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1472*FLEN/8, x10, x6, x7)
-
-inst_760:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1474*FLEN/8, x10, x6, x7)
-
-inst_761:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1476*FLEN/8, x10, x6, x7)
-
-inst_762:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x065f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x65f43; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1478*FLEN/8, x10, x6, x7)
-
-inst_763:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x065f43 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x65f43;
-valaddr_reg:x9; val_offset:1480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1480*FLEN/8, x10, x6, x7)
-
-inst_764:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x065f43 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x65f43; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1482*FLEN/8, x10, x6, x7)
-
-inst_765:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x065f43 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x65f43;
-valaddr_reg:x9; val_offset:1484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1484*FLEN/8, x10, x6, x7)
-
-inst_766:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1486*FLEN/8, x10, x6, x7)
-
-inst_767:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1488*FLEN/8, x10, x6, x7)
-
-inst_768:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1490*FLEN/8, x10, x6, x7)
-
-inst_769:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1492*FLEN/8, x10, x6, x7)
-
-inst_770:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1494*FLEN/8, x10, x6, x7)
-
-inst_771:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1496*FLEN/8, x10, x6, x7)
-
-inst_772:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1498*FLEN/8, x10, x6, x7)
-
-inst_773:// fs1 == 0 and fe1 == 0x81 and fm1 == 0x3b428c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x40bb428c; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1500*FLEN/8, x10, x6, x7)
-
-inst_774:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3b428c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x40bb428c;
-valaddr_reg:x9; val_offset:1502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1502*FLEN/8, x10, x6, x7)
-
-inst_775:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3fb8a4 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3b428c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fb8a4; op2val:0x40bb428c;
-valaddr_reg:x9; val_offset:1504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1504*FLEN/8, x10, x6, x7)
-
-inst_776:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1506*FLEN/8, x10, x6, x7)
-
-inst_777:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x620ff4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7de20ff4; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1508*FLEN/8, x10, x6, x7)
-
-inst_778:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0xfb and fm2 == 0x620ff4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7de20ff4;
-valaddr_reg:x9; val_offset:1510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1510*FLEN/8, x10, x6, x7)
-
-inst_779:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1512*FLEN/8, x10, x6, x7)
-
-inst_780:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1514*FLEN/8, x10, x6, x7)
-
-inst_781:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1516*FLEN/8, x10, x6, x7)
-
-inst_782:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1518*FLEN/8, x10, x6, x7)
-
-inst_783:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x620ff4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7de20ff4; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1520*FLEN/8, x10, x6, x7)
-
-inst_784:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1522*FLEN/8, x10, x6, x7)
-
-inst_785:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1524*FLEN/8, x10, x6, x7)
-
-inst_786:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1526*FLEN/8, x10, x6, x7)
-
-inst_787:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1528*FLEN/8, x10, x6, x7)
-
-inst_788:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1530*FLEN/8, x10, x6, x7)
-
-inst_789:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1532*FLEN/8, x10, x6, x7)
-
-inst_790:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1534*FLEN/8, x10, x6, x7)
-
-inst_791:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x620ff4 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7de20ff4; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1536*FLEN/8, x10, x6, x7)
-
-inst_792:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1538*FLEN/8, x10, x6, x7)
-
-inst_793:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0068b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x68b4; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1540*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_6)
-
-inst_794:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0068b4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x68b4;
-valaddr_reg:x9; val_offset:1542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1542*FLEN/8, x10, x6, x7)
-
-inst_795:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1544*FLEN/8, x10, x6, x7)
-
-inst_796:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1546*FLEN/8, x10, x6, x7)
-
-inst_797:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1548*FLEN/8, x10, x6, x7)
-
-inst_798:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1550*FLEN/8, x10, x6, x7)
-
-inst_799:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1552*FLEN/8, x10, x6, x7)
-
-inst_800:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04170c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4170c; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1554*FLEN/8, x10, x6, x7)
-
-inst_801:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x04170c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x4170c;
-valaddr_reg:x9; val_offset:1556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1556*FLEN/8, x10, x6, x7)
-
-inst_802:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04170c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4170c; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1558*FLEN/8, x10, x6, x7)
-
-inst_803:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x04170c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x4170c;
-valaddr_reg:x9; val_offset:1560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1560*FLEN/8, x10, x6, x7)
-
-inst_804:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1562*FLEN/8, x10, x6, x7)
-
-inst_805:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1564*FLEN/8, x10, x6, x7)
-
-inst_806:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1566*FLEN/8, x10, x6, x7)
-
-inst_807:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1568*FLEN/8, x10, x6, x7)
-
-inst_808:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1570*FLEN/8, x10, x6, x7)
-
-inst_809:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1572*FLEN/8, x10, x6, x7)
-
-inst_810:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1574*FLEN/8, x10, x6, x7)
-
-inst_811:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x706405 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x40706405; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1576*FLEN/8, x10, x6, x7)
-
-inst_812:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x706405 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x40706405;
-valaddr_reg:x9; val_offset:1578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1578*FLEN/8, x10, x6, x7)
-
-inst_813:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x28e67d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x706405 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x28e67d; op2val:0x40706405;
-valaddr_reg:x9; val_offset:1580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1580*FLEN/8, x10, x6, x7)
-
-inst_814:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1582*FLEN/8, x10, x6, x7)
-
-inst_815:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39119c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7db9119c; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1584*FLEN/8, x10, x6, x7)
-
-inst_816:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0xfb and fm2 == 0x39119c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7db9119c;
-valaddr_reg:x9; val_offset:1586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1586*FLEN/8, x10, x6, x7)
-
-inst_817:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1588*FLEN/8, x10, x6, x7)
-
-inst_818:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1590*FLEN/8, x10, x6, x7)
-
-inst_819:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1592*FLEN/8, x10, x6, x7)
-
-inst_820:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0xfe and fm2 == 0x675603 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7f675603;
-valaddr_reg:x9; val_offset:1594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1594*FLEN/8, x10, x6, x7)
-
-inst_821:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1596*FLEN/8, x10, x6, x7)
-
-inst_822:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39119c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7db9119c; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1598*FLEN/8, x10, x6, x7)
-
-inst_823:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1600*FLEN/8, x10, x6, x7)
-
-inst_824:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1602*FLEN/8, x10, x6, x7)
-
-inst_825:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1604*FLEN/8, x10, x6, x7)
-
-inst_826:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1606*FLEN/8, x10, x6, x7)
-
-inst_827:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1608*FLEN/8, x10, x6, x7)
-
-inst_828:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1610*FLEN/8, x10, x6, x7)
-
-inst_829:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1612*FLEN/8, x10, x6, x7)
-
-inst_830:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1614*FLEN/8, x10, x6, x7)
-
-inst_831:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1616*FLEN/8, x10, x6, x7)
-
-inst_832:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1618*FLEN/8, x10, x6, x7)
-
-inst_833:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1620*FLEN/8, x10, x6, x7)
-
-inst_834:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x675603 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f675603; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1622*FLEN/8, x10, x6, x7)
-
-inst_835:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1624*FLEN/8, x10, x6, x7)
-
-inst_836:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x39119c and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7db9119c; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1626*FLEN/8, x10, x6, x7)
-
-inst_837:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1628*FLEN/8, x10, x6, x7)
-
-inst_838:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0055b7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x55b7; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1630*FLEN/8, x10, x6, x7)
-
-inst_839:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0055b7 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x55b7;
-valaddr_reg:x9; val_offset:1632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1632*FLEN/8, x10, x6, x7)
-
-inst_840:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1634*FLEN/8, x10, x6, x7)
-
-inst_841:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1636*FLEN/8, x10, x6, x7)
-
-inst_842:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1638*FLEN/8, x10, x6, x7)
-
-inst_843:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03592e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3592e; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1640*FLEN/8, x10, x6, x7)
-
-inst_844:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03592e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x3592e;
-valaddr_reg:x9; val_offset:1642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1642*FLEN/8, x10, x6, x7)
-
-inst_845:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03592e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3592e; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1644*FLEN/8, x10, x6, x7)
-
-inst_846:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03592e and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x3592e;
-valaddr_reg:x9; val_offset:1646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1646*FLEN/8, x10, x6, x7)
-
-inst_847:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1648*FLEN/8, x10, x6, x7)
-
-inst_848:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1650*FLEN/8, x10, x6, x7)
-
-inst_849:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1652*FLEN/8, x10, x6, x7)
-
-inst_850:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1654*FLEN/8, x10, x6, x7)
-
-inst_851:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1656*FLEN/8, x10, x6, x7)
-
-inst_852:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1658*FLEN/8, x10, x6, x7)
-
-inst_853:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1660*FLEN/8, x10, x6, x7)
-
-inst_854:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x44cc84 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4044cc84; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1662*FLEN/8, x10, x6, x7)
-
-inst_855:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x44cc84 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x4044cc84;
-valaddr_reg:x9; val_offset:1664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1664*FLEN/8, x10, x6, x7)
-
-inst_856:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x217bcd and fs2 == 0 and fe2 == 0x80 and fm2 == 0x44cc84 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x217bcd; op2val:0x4044cc84;
-valaddr_reg:x9; val_offset:1666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1666*FLEN/8, x10, x6, x7)
-
-inst_857:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1668*FLEN/8, x10, x6, x7)
-
-inst_858:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0c1bbb and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8c1bbb; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1670*FLEN/8, x10, x6, x7)
-
-inst_859:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0c1bbb and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xfd8c1bbb;
-valaddr_reg:x9; val_offset:1672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1672*FLEN/8, x10, x6, x7)
-
-inst_860:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1674*FLEN/8, x10, x6, x7)
-
-inst_861:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1676*FLEN/8, x10, x6, x7)
-
-inst_862:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1678*FLEN/8, x10, x6, x7)
-
-inst_863:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x2f22aa and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xff2f22aa;
-valaddr_reg:x9; val_offset:1680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1680*FLEN/8, x10, x6, x7)
-
-inst_864:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1682*FLEN/8, x10, x6, x7)
-
-inst_865:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0c1bbb and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8c1bbb; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1684*FLEN/8, x10, x6, x7)
-
-inst_866:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1686*FLEN/8, x10, x6, x7)
-
-inst_867:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1688*FLEN/8, x10, x6, x7)
-
-inst_868:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1690*FLEN/8, x10, x6, x7)
-
-inst_869:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1692*FLEN/8, x10, x6, x7)
-
-inst_870:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1694*FLEN/8, x10, x6, x7)
-
-inst_871:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1696*FLEN/8, x10, x6, x7)
-
-inst_872:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1698*FLEN/8, x10, x6, x7)
-
-inst_873:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1700*FLEN/8, x10, x6, x7)
-
-inst_874:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1702*FLEN/8, x10, x6, x7)
-
-inst_875:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1704*FLEN/8, x10, x6, x7)
-
-inst_876:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1706*FLEN/8, x10, x6, x7)
-
-inst_877:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x2f22aa and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff2f22aa; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1708*FLEN/8, x10, x6, x7)
-
-inst_878:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1710*FLEN/8, x10, x6, x7)
-
-inst_879:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x0c1bbb and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd8c1bbb; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1712*FLEN/8, x10, x6, x7)
-
-inst_880:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1714*FLEN/8, x10, x6, x7)
-
-inst_881:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0040e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800040e4; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1716*FLEN/8, x10, x6, x7)
-
-inst_882:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0040e4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x800040e4;
-valaddr_reg:x9; val_offset:1718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1718*FLEN/8, x10, x6, x7)
-
-inst_883:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1720*FLEN/8, x10, x6, x7)
-
-inst_884:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0288ef and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800288ef; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1722*FLEN/8, x10, x6, x7)
-
-inst_885:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0288ef and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x800288ef;
-valaddr_reg:x9; val_offset:1724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1724*FLEN/8, x10, x6, x7)
-
-inst_886:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0288ef and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800288ef; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1726*FLEN/8, x10, x6, x7)
-
-inst_887:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0288ef and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x800288ef;
-valaddr_reg:x9; val_offset:1728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1728*FLEN/8, x10, x6, x7)
-
-inst_888:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1730*FLEN/8, x10, x6, x7)
-
-inst_889:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1732*FLEN/8, x10, x6, x7)
-
-inst_890:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1734*FLEN/8, x10, x6, x7)
-
-inst_891:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1736*FLEN/8, x10, x6, x7)
-
-inst_892:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1738*FLEN/8, x10, x6, x7)
-
-inst_893:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1740*FLEN/8, x10, x6, x7)
-
-inst_894:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1742*FLEN/8, x10, x6, x7)
-
-inst_895:// fs1 == 1 and fe1 == 0x80 and fm1 == 0x14fd1d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc014fd1d; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1744*FLEN/8, x10, x6, x7)
-
-inst_896:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x14fd1d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc014fd1d;
-valaddr_reg:x9; val_offset:1746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1746*FLEN/8, x10, x6, x7)
-
-inst_897:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x19595f and fs2 == 1 and fe2 == 0x80 and fm2 == 0x14fd1d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8019595f; op2val:0xc014fd1d;
-valaddr_reg:x9; val_offset:1748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1748*FLEN/8, x10, x6, x7)
-
-inst_898:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1750*FLEN/8, x10, x6, x7)
-
-inst_899:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x0fbbb6 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe8fbbb6; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1752*FLEN/8, x10, x6, x7)
-
-inst_900:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x0fbbb6 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xfe8fbbb6;
-valaddr_reg:x9; val_offset:1754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1754*FLEN/8, x10, x6, x7)
-
-inst_901:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1756*FLEN/8, x10, x6, x7)
-
-inst_902:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1758*FLEN/8, x10, x6, x7)
-
-inst_903:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1760*FLEN/8, x10, x6, x7)
-
-inst_904:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1762*FLEN/8, x10, x6, x7)
-
-inst_905:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1764*FLEN/8, x10, x6, x7)
-
-inst_906:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x0fbbb6 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe8fbbb6; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1766*FLEN/8, x10, x6, x7)
-
-inst_907:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1768*FLEN/8, x10, x6, x7)
-
-inst_908:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1770*FLEN/8, x10, x6, x7)
-
-inst_909:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1772*FLEN/8, x10, x6, x7)
-
-inst_910:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1774*FLEN/8, x10, x6, x7)
-
-inst_911:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1776*FLEN/8, x10, x6, x7)
-
-inst_912:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1778*FLEN/8, x10, x6, x7)
-
-inst_913:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1780*FLEN/8, x10, x6, x7)
-
-inst_914:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1782*FLEN/8, x10, x6, x7)
-
-inst_915:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1784*FLEN/8, x10, x6, x7)
-
-inst_916:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1786*FLEN/8, x10, x6, x7)
-
-inst_917:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1788*FLEN/8, x10, x6, x7)
-
-inst_918:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1790*FLEN/8, x10, x6, x7)
-
-inst_919:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1792*FLEN/8, x10, x6, x7)
-
-inst_920:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x0fbbb6 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe8fbbb6; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1794*FLEN/8, x10, x6, x7)
-
-inst_921:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1796*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_7)
-
-inst_922:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:1798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1798*FLEN/8, x10, x6, x7)
-
-inst_923:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1800*FLEN/8, x10, x6, x7)
-
-inst_924:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1802*FLEN/8, x10, x6, x7)
-
-inst_925:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x010a4a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80010a4a; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1804*FLEN/8, x10, x6, x7)
-
-inst_926:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x010a4a and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x80010a4a;
-valaddr_reg:x9; val_offset:1806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1806*FLEN/8, x10, x6, x7)
-
-inst_927:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1808*FLEN/8, x10, x6, x7)
-
-inst_928:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:1810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1810*FLEN/8, x10, x6, x7)
-
-inst_929:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1812*FLEN/8, x10, x6, x7)
-
-inst_930:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:1814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1814*FLEN/8, x10, x6, x7)
-
-inst_931:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1816*FLEN/8, x10, x6, x7)
-
-inst_932:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:1818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1818*FLEN/8, x10, x6, x7)
-
-inst_933:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1820*FLEN/8, x10, x6, x7)
-
-inst_934:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:1822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1822*FLEN/8, x10, x6, x7)
-
-inst_935:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1824*FLEN/8, x10, x6, x7)
-
-inst_936:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0363eb and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x800363eb;
-valaddr_reg:x9; val_offset:1826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1826*FLEN/8, x10, x6, x7)
-
-inst_937:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0363eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800363eb; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1828*FLEN/8, x10, x6, x7)
-
-inst_938:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1830*FLEN/8, x10, x6, x7)
-
-inst_939:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1832*FLEN/8, x10, x6, x7)
-
-inst_940:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x056fa1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x80056fa1;
-valaddr_reg:x9; val_offset:1834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1834*FLEN/8, x10, x6, x7)
-
-inst_941:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x056fa1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80056fa1; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1836*FLEN/8, x10, x6, x7)
-
-inst_942:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1838*FLEN/8, x10, x6, x7)
-
-inst_943:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1840*FLEN/8, x10, x6, x7)
-
-inst_944:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a7ee and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x8001a7ee;
-valaddr_reg:x9; val_offset:1842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1842*FLEN/8, x10, x6, x7)
-
-inst_945:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01a7ee and fs2 == 1 and fe2 == 0x00 and fm2 == 0x680514 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001a7ee; op2val:0x80680514;
-valaddr_reg:x9; val_offset:1844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1844*FLEN/8, x10, x6, x7)
-
-inst_946:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x680514 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80680514; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1846*FLEN/8, x10, x6, x7)
-
-inst_947:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1848*FLEN/8, x10, x6, x7)
-
-inst_948:// fs1 == 1 and fe1 == 0x82 and fm1 == 0x18d7ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc118d7ea; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1850*FLEN/8, x10, x6, x7)
-
-inst_949:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x18d7ea and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc118d7ea;
-valaddr_reg:x9; val_offset:1852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1852*FLEN/8, x10, x6, x7)
-
-inst_950:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0a66e8 and fs2 == 1 and fe2 == 0x82 and fm2 == 0x18d7ea and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800a66e8; op2val:0xc118d7ea;
-valaddr_reg:x9; val_offset:1854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1854*FLEN/8, x10, x6, x7)
-
-inst_951:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1856*FLEN/8, x10, x6, x7)
-
-inst_952:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x3b633c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdbb633c; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1858*FLEN/8, x10, x6, x7)
-
-inst_953:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x3b633c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xfdbb633c;
-valaddr_reg:x9; val_offset:1860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1860*FLEN/8, x10, x6, x7)
-
-inst_954:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1862*FLEN/8, x10, x6, x7)
-
-inst_955:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1864*FLEN/8, x10, x6, x7)
-
-inst_956:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1866*FLEN/8, x10, x6, x7)
-
-inst_957:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6a3c0b and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xff6a3c0b;
-valaddr_reg:x9; val_offset:1868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1868*FLEN/8, x10, x6, x7)
-
-inst_958:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1870*FLEN/8, x10, x6, x7)
-
-inst_959:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x3b633c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdbb633c; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1872*FLEN/8, x10, x6, x7)
-
-inst_960:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1874*FLEN/8, x10, x6, x7)
-
-inst_961:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1876*FLEN/8, x10, x6, x7)
-
-inst_962:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1878*FLEN/8, x10, x6, x7)
-
-inst_963:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1880*FLEN/8, x10, x6, x7)
-
-inst_964:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1882*FLEN/8, x10, x6, x7)
-
-inst_965:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1884*FLEN/8, x10, x6, x7)
-
-inst_966:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1886*FLEN/8, x10, x6, x7)
-
-inst_967:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1888*FLEN/8, x10, x6, x7)
-
-inst_968:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1890*FLEN/8, x10, x6, x7)
-
-inst_969:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1892*FLEN/8, x10, x6, x7)
-
-inst_970:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1894*FLEN/8, x10, x6, x7)
-
-inst_971:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6a3c0b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6a3c0b; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1896*FLEN/8, x10, x6, x7)
-
-inst_972:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1898*FLEN/8, x10, x6, x7)
-
-inst_973:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x3b633c and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdbb633c; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1900*FLEN/8, x10, x6, x7)
-
-inst_974:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1902*FLEN/8, x10, x6, x7)
-
-inst_975:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0056ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800056ca; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1904*FLEN/8, x10, x6, x7)
-
-inst_976:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0056ca and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x800056ca;
-valaddr_reg:x9; val_offset:1906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1906*FLEN/8, x10, x6, x7)
-
-inst_977:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1908*FLEN/8, x10, x6, x7)
-
-inst_978:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0363eb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800363eb; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1910*FLEN/8, x10, x6, x7)
-
-inst_979:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0363eb and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x800363eb;
-valaddr_reg:x9; val_offset:1912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1912*FLEN/8, x10, x6, x7)
-
-inst_980:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1914*FLEN/8, x10, x6, x7)
-
-inst_981:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1916*FLEN/8, x10, x6, x7)
-
-inst_982:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1918*FLEN/8, x10, x6, x7)
-
-inst_983:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:1920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1920*FLEN/8, x10, x6, x7)
-
-inst_984:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1922*FLEN/8, x10, x6, x7)
-
-inst_985:// fs1 == 1 and fe1 == 0x80 and fm1 == 0x4743c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc04743c4; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1924*FLEN/8, x10, x6, x7)
-
-inst_986:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4743c4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc04743c4;
-valaddr_reg:x9; val_offset:1926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1926*FLEN/8, x10, x6, x7)
-
-inst_987:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x21e733 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x4743c4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8021e733; op2val:0xc04743c4;
-valaddr_reg:x9; val_offset:1928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1928*FLEN/8, x10, x6, x7)
-
-inst_988:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1930*FLEN/8, x10, x6, x7)
-
-inst_989:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x163ab8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe163ab8; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1932*FLEN/8, x10, x6, x7)
-
-inst_990:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0xfc and fm2 == 0x163ab8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xfe163ab8;
-valaddr_reg:x9; val_offset:1934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1934*FLEN/8, x10, x6, x7)
-
-inst_991:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1936*FLEN/8, x10, x6, x7)
-
-inst_992:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1938*FLEN/8, x10, x6, x7)
-
-inst_993:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1940*FLEN/8, x10, x6, x7)
-
-inst_994:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1942*FLEN/8, x10, x6, x7)
-
-inst_995:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x163ab8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe163ab8; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:1944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1944*FLEN/8, x10, x6, x7)
-
-inst_996:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:1946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1946*FLEN/8, x10, x6, x7)
-
-inst_997:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:1948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1948*FLEN/8, x10, x6, x7)
-
-inst_998:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:1950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1950*FLEN/8, x10, x6, x7)
-
-inst_999:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:1952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1952*FLEN/8, x10, x6, x7)
-
-inst_1000:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xff130229;
-valaddr_reg:x9; val_offset:1954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1954*FLEN/8, x10, x6, x7)
-
-inst_1001:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:1956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1956*FLEN/8, x10, x6, x7)
-
-inst_1002:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1958*FLEN/8, x10, x6, x7)
-
-inst_1003:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x163ab8 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe163ab8; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:1960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1960*FLEN/8, x10, x6, x7)
-
-inst_1004:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1962*FLEN/8, x10, x6, x7)
-
-inst_1005:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x008b29 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80008b29; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:1964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1964*FLEN/8, x10, x6, x7)
-
-inst_1006:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008b29 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x80008b29;
-valaddr_reg:x9; val_offset:1966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1966*FLEN/8, x10, x6, x7)
-
-inst_1007:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1968*FLEN/8, x10, x6, x7)
-
-inst_1008:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x056fa1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80056fa1; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:1970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1970*FLEN/8, x10, x6, x7)
-
-inst_1009:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x056fa1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x80056fa1;
-valaddr_reg:x9; val_offset:1972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1972*FLEN/8, x10, x6, x7)
-
-inst_1010:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1974*FLEN/8, x10, x6, x7)
-
-inst_1011:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:1976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1976*FLEN/8, x10, x6, x7)
-
-inst_1012:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1978*FLEN/8, x10, x6, x7)
-
-inst_1013:// fs1 == 1 and fe1 == 0x81 and fm1 == 0x1fc053 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc09fc053; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1980*FLEN/8, x10, x6, x7)
-
-inst_1014:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1fc053 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc09fc053;
-valaddr_reg:x9; val_offset:1982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1982*FLEN/8, x10, x6, x7)
-
-inst_1015:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x365c4c and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1fc053 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80365c4c; op2val:0xc09fc053;
-valaddr_reg:x9; val_offset:1984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1984*FLEN/8, x10, x6, x7)
-
-inst_1016:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1986*FLEN/8, x10, x6, x7)
-
-inst_1017:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x370ed0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd370ed0; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:1988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1988*FLEN/8, x10, x6, x7)
-
-inst_1018:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x370ed0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xfd370ed0;
-valaddr_reg:x9; val_offset:1990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1990*FLEN/8, x10, x6, x7)
-
-inst_1019:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:1992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1992*FLEN/8, x10, x6, x7)
-
-inst_1020:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1994*FLEN/8, x10, x6, x7)
-
-inst_1021:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:1996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1996*FLEN/8, x10, x6, x7)
-
-inst_1022:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64d284 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xfee4d284;
-valaddr_reg:x9; val_offset:1998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 1998*FLEN/8, x10, x6, x7)
-
-inst_1023:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:2000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2000*FLEN/8, x10, x6, x7)
-
-inst_1024:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x370ed0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd370ed0; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:2002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2002*FLEN/8, x10, x6, x7)
-
-inst_1025:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:2004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2004*FLEN/8, x10, x6, x7)
-
-inst_1026:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:2006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2006*FLEN/8, x10, x6, x7)
-
-inst_1027:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:2008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2008*FLEN/8, x10, x6, x7)
-
-inst_1028:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:2010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2010*FLEN/8, x10, x6, x7)
-
-inst_1029:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:2012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2012*FLEN/8, x10, x6, x7)
-
-inst_1030:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:2014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2014*FLEN/8, x10, x6, x7)
-
-inst_1031:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:2016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2016*FLEN/8, x10, x6, x7)
-
-inst_1032:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:2018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2018*FLEN/8, x10, x6, x7)
-
-inst_1033:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xff130229;
-valaddr_reg:x9; val_offset:2020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2020*FLEN/8, x10, x6, x7)
-
-inst_1034:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0xff130229;
-valaddr_reg:x9; val_offset:2022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2022*FLEN/8, x10, x6, x7)
-
-inst_1035:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:2024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2024*FLEN/8, x10, x6, x7)
-
-inst_1036:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64d284 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee4d284; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:2026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2026*FLEN/8, x10, x6, x7)
-
-inst_1037:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:2028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2028*FLEN/8, x10, x6, x7)
-
-inst_1038:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x370ed0 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd370ed0; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:2030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2030*FLEN/8, x10, x6, x7)
-
-inst_1039:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:2032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2032*FLEN/8, x10, x6, x7)
-
-inst_1040:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002a64 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80002a64; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:2034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2034*FLEN/8, x10, x6, x7)
-
-inst_1041:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002a64 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x80002a64;
-valaddr_reg:x9; val_offset:2036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2036*FLEN/8, x10, x6, x7)
-
-inst_1042:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:2038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2038*FLEN/8, x10, x6, x7)
-
-inst_1043:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01a7ee and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001a7ee; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:2040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2040*FLEN/8, x10, x6, x7)
-
-inst_1044:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a7ee and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x8001a7ee;
-valaddr_reg:x9; val_offset:2042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2042*FLEN/8, x10, x6, x7)
-
-inst_1045:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0x7f0;
-valaddr_reg:x9; val_offset:2044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2044*FLEN/8, x10, x6, x7)
-
-inst_1046:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x42a917 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbfc2a917; op2val:0x7f0;
-valaddr_reg:x9; val_offset:2046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2046*FLEN/8, x10, x6, x7)
-
-inst_1047:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x42a917 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbfc2a917;
-valaddr_reg:x9; val_offset:2048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2048*FLEN/8, x10, x6, x7)
-
-inst_1048:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108f54 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x42a917 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80108f54; op2val:0xbfc2a917;
-valaddr_reg:x9; val_offset:2050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2050*FLEN/8, x10, x6, x7)
-
-inst_1049:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:2052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2052*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_8)
-
-inst_1050:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7f0;
-valaddr_reg:x9; val_offset:2054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2054*FLEN/8, x10, x6, x7)
-
-inst_1051:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:2056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2056*FLEN/8, x10, x6, x7)
-
-inst_1052:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7e472f12;
-valaddr_reg:x9; val_offset:2058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2058*FLEN/8, x10, x6, x7)
-
-inst_1053:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7f2099c0;
-valaddr_reg:x9; val_offset:2060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2060*FLEN/8, x10, x6, x7)
-
-inst_1054:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7ef3c956;
-valaddr_reg:x9; val_offset:2062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2062*FLEN/8, x10, x6, x7)
-
-inst_1055:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfeaf0416;
-valaddr_reg:x9; val_offset:2064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2064*FLEN/8, x10, x6, x7)
-
-inst_1056:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xff336b1f;
-valaddr_reg:x9; val_offset:2066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2066*FLEN/8, x10, x6, x7)
-
-inst_1057:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xff130229;
-valaddr_reg:x9; val_offset:2068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2068*FLEN/8, x10, x6, x7)
-
-inst_1058:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfec91492;
-valaddr_reg:x9; val_offset:2070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2070*FLEN/8, x10, x6, x7)
-
-inst_1059:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfdcaaeb1;
-valaddr_reg:x9; val_offset:2072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2072*FLEN/8, x10, x6, x7)
-
-inst_1060:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17ad58 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x17ad58;
-valaddr_reg:x9; val_offset:2074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2074*FLEN/8, x10, x6, x7)
-
-inst_1061:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00d7bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xd7bf;
-valaddr_reg:x9; val_offset:2076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2076*FLEN/8, x10, x6, x7)
-
-inst_1062:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3fb8a4 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x3fb8a4;
-valaddr_reg:x9; val_offset:2078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2078*FLEN/8, x10, x6, x7)
-
-inst_1063:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x28e67d and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x28e67d;
-valaddr_reg:x9; val_offset:2080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2080*FLEN/8, x10, x6, x7)
-
-inst_1064:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x217bcd and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x217bcd;
-valaddr_reg:x9; val_offset:2082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2082*FLEN/8, x10, x6, x7)
-
-inst_1065:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x19595f and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x8019595f;
-valaddr_reg:x9; val_offset:2084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2084*FLEN/8, x10, x6, x7)
-
-inst_1066:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0a66e8 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x800a66e8;
-valaddr_reg:x9; val_offset:2086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2086*FLEN/8, x10, x6, x7)
-
-inst_1067:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x21e733 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x8021e733;
-valaddr_reg:x9; val_offset:2088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2088*FLEN/8, x10, x6, x7)
-
-inst_1068:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x365c4c and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x80365c4c;
-valaddr_reg:x9; val_offset:2090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2090*FLEN/8, x10, x6, x7)
-
-inst_1069:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108f54 and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x80108f54;
-valaddr_reg:x9; val_offset:2092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2092*FLEN/8, x10, x6, x7)
-
-inst_1070:// fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x7ef046ce;
-valaddr_reg:x9; val_offset:2094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2094*FLEN/8, x10, x6, x7)
-
-inst_1071:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and  fcsr == 0  
-/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdcaaeb1; op2val:0x7e36c1bf;
-valaddr_reg:x9; val_offset:2096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x9, 2096*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2101360805,32,FLEN)
-NAN_BOXED(2101360805,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2105572096,32,FLEN)
-NAN_BOXED(2105572096,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2101544824,32,FLEN)
-NAN_BOXED(2101544824,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4245422917,32,FLEN)
-NAN_BOXED(4245422917,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4254042342,32,FLEN)
-NAN_BOXED(4254042342,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-test_dataset_1:
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4251661993,32,FLEN)
-NAN_BOXED(4251661993,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4246789441,32,FLEN)
-NAN_BOXED(4246789441,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(1551704,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(2105728500,32,FLEN)
-NAN_BOXED(2105728500,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(1551704,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(43339,32,FLEN)
-NAN_BOXED(2120804116,32,FLEN)
-NAN_BOXED(2120804116,32,FLEN)
-NAN_BOXED(43339,32,FLEN)
-NAN_BOXED(43339,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(43339,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4176036,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(2117081393,32,FLEN)
-NAN_BOXED(2117081393,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(4176036,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2680445,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(2111967220,32,FLEN)
-NAN_BOXED(2111967220,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(2680445,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2194381,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(2109280668,32,FLEN)
-NAN_BOXED(2109280668,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(2194381,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2149144927,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(4253817787,32,FLEN)
-NAN_BOXED(4253817787,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(2149144927,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(433393,32,FLEN)
-NAN_BOXED(4270832566,32,FLEN)
-NAN_BOXED(4270832566,32,FLEN)
-NAN_BOXED(433393,32,FLEN)
-NAN_BOXED(433393,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(433393,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(4256916284,32,FLEN)
-NAN_BOXED(4256916284,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(4262869688,32,FLEN)
-NAN_BOXED(4262869688,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(4248243920,32,FLEN)
-NAN_BOXED(4248243920,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(4333935,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1086478115,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1086478115,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(1086478115,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2101360805,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2101360805,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2101360805,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(2101360805,32,FLEN)
-NAN_BOXED(4286405214,32,FLEN)
-NAN_BOXED(4286405214,32,FLEN)
-NAN_BOXED(2101360805,32,FLEN)
-NAN_BOXED(2101360805,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(1551704,32,FLEN)
-NAN_BOXED(1139594,32,FLEN)
-NAN_BOXED(2133038449,32,FLEN)
-NAN_BOXED(2133038449,32,FLEN)
-NAN_BOXED(1139594,32,FLEN)
-NAN_BOXED(1139594,32,FLEN)
-NAN_BOXED(1551704,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(1139594,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(11395,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(11395,32,FLEN)
-NAN_BOXED(11395,32,FLEN)
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-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3225895876,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3225895876,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(3225895876,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4262869688,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(4262869688,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(4262869688,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(4262869688,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(2147519273,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2147519273,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2147839905,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2147839905,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3231694931,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3231694931,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(3231694931,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(4248243920,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(4248243920,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(4248243920,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(4276408964,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(4248243920,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(2147494500,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2147494500,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2147592174,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2147592174,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3217205527,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3217205527,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(3217205527,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2118594322,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2132842944,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2129906006,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4272882710,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4281559839,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4279435817,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4274590866,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1551704,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(55231,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4176036,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2680445,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2194381,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2149144927,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2148165352,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2149705523,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2151046220,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2148568916,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-NAN_BOXED(2129675982,32,FLEN)
-NAN_BOXED(4257918641,32,FLEN)
-NAN_BOXED(2117517759,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_7:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_8:
-    .fill 44*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fli.s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fli.s-01.S
deleted file mode 100644
index 1558be873..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fli.s-01.S
+++ /dev/null
@@ -1,204 +0,0 @@
-// Copyright (c) 2023. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fli.s instruction
-// for the following ISA configurations:
-// * RV32IF_Zfa
-// * RV64IF_Zfa
-
-#include "model_test.h"
-#include "arch_test.h"
-
-RVTEST_ISA("RV32IF_Zfa,RV64IF_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-
-RVMODEL_BOOT
-
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fli.s)
-
-// Registers with a special purpose
-#define SIG_BASEREG x1
-#define FCSR_REG x2
-#define DATA_BASEREG x3
-
-// Initialize the FPU
-RVTEST_FP_ENABLE()
-// Prepare the DATA_BASEREG register
-RVTEST_VALBASEUPD(DATA_BASEREG, dataset_tc1)
-// Prepare the SIG_BASEREG register
-RVTEST_SIGBASE(SIG_BASEREG, signature_tc1)
-
-// FLI.S loads a pre-defined constant into a FP register.
-// FLI.S has the following inputs and outputs:
-// - input rs1: 5-bit immediate holding the constants ID
-// - output fld: FP register
-
-// TEST_CASE_FLI_S executes a FLI.S insn and stores the result in the sig
-// 1) the FCSR_OLD value will be store into FCSR using FCSR_REG
-// 2) fli.s is executed using FLD as dest register and FLI_CONST as constant
-// 3) The constents of FLD and FCSR are stored in the signature
-#define TEST_CASE_FLI_S(fld, fli_const, fcsr_old, fcsr_reg) \
-    li fcsr_reg, fcsr_old ;\
-    csrw fcsr, fcsr_reg   ;\
-    fli.s fld, fli_const  ;\
-    csrr fcsr_reg, fcsr   ;\
-    RVTEST_SIGUPD_F(SIG_BASEREG, fld, fcsr_reg) ;\
-
-// Below we have one instruction test per constant
-
-inst_0:
-TEST_CASE_FLI_S(f16, -0x1p+0, 0, FCSR_REG)
-
-inst_1:
-TEST_CASE_FLI_S(f17, min, 0, FCSR_REG)
-
-inst_2:
-TEST_CASE_FLI_S(f18, 0x1p-16, 0, FCSR_REG)
-
-inst_3:
-TEST_CASE_FLI_S(f19, 0x1p-15, 0, FCSR_REG)
-
-inst_4:
-TEST_CASE_FLI_S(f20, 0x1p-8, 0, FCSR_REG)
-
-inst_5:
-TEST_CASE_FLI_S(f21, 0x1p-7, 0, FCSR_REG)
-
-inst_6:
-TEST_CASE_FLI_S(f22, 0x1p-4, 0, FCSR_REG)
-
-inst_7:
-TEST_CASE_FLI_S(f23, 0x1p-3, 0, FCSR_REG)
-
-inst_8:
-TEST_CASE_FLI_S(f24, 0x1p-2, 0, FCSR_REG)
-
-inst_9:
-TEST_CASE_FLI_S(f25, 0x1.4p-2, 0, FCSR_REG)
-
-inst_10:
-TEST_CASE_FLI_S(f26, 0x1.8p-2, 0, FCSR_REG)
-
-inst_11:
-TEST_CASE_FLI_S(f27, 0x1.cp-2, 0, FCSR_REG)
-
-inst_12:
-TEST_CASE_FLI_S(f28, 0x1p-1, 0, FCSR_REG)
-
-inst_13:
-TEST_CASE_FLI_S(f29, 0x1.4p-1, 0, FCSR_REG)
-
-inst_14:
-TEST_CASE_FLI_S(f30, 0x1.8p-1, 0, FCSR_REG)
-
-inst_15:
-TEST_CASE_FLI_S(f31, 0x1.cp-1, 0, FCSR_REG)
-
-inst_16:
-TEST_CASE_FLI_S(f0, 0x1p0, 0, FCSR_REG)
-
-inst_17:
-TEST_CASE_FLI_S(f1, 0x1.4p+0, 0, FCSR_REG)
-
-inst_18:
-TEST_CASE_FLI_S(f2, 0x1.8p+0, 0, FCSR_REG)
-
-inst_19:
-TEST_CASE_FLI_S(f3, 0x1.cp+0, 0, FCSR_REG)
-
-inst_20:
-TEST_CASE_FLI_S(f4, 0x1p+1, 0, FCSR_REG)
-
-inst_21:
-TEST_CASE_FLI_S(f5, 0x1.4p+1, 0, FCSR_REG)
-
-inst_22:
-TEST_CASE_FLI_S(f6, 0x1.8p+1, 0, FCSR_REG)
-
-inst_23:
-TEST_CASE_FLI_S(f7, 0x1p+2, 0, FCSR_REG)
-
-inst_24:
-TEST_CASE_FLI_S(f8, 0x1p+3, 0, FCSR_REG)
-
-inst_25:
-TEST_CASE_FLI_S(f9, 0x1p+4, 0, FCSR_REG)
-
-inst_26:
-TEST_CASE_FLI_S(f10, 0x1p+7, 0, FCSR_REG)
-
-inst_27:
-TEST_CASE_FLI_S(f11, 0x1p+8, 0, FCSR_REG)
-
-inst_28:
-TEST_CASE_FLI_S(f12, 0x1p+15, 0, FCSR_REG)
-
-inst_29:
-TEST_CASE_FLI_S(f13, 0x1p+16, 0, FCSR_REG)
-
-inst_30:
-TEST_CASE_FLI_S(f14, inf, 0, FCSR_REG)
-
-inst_31:
-TEST_CASE_FLI_S(f15, nan, 0, FCSR_REG)
-
-#endif // TEST_CASE_1
-
-RVTEST_CODE_END
-
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.word 0xbabecafe // trapreg_sv
-.word 0xabecafeb // tramptbl_sv
-.word 0xbecafeba // mtvec_save
-.word 0xecafebab // mscratch_save
-dataset_tc1:
-/* empty */
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-signature_tc1:
-// We have 32 test cases and store for each test case:
-// - 32-bit FP register (fld)
-// - 32-bit FCSR content after the instruction
-    .fill 64*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-
-tsig_begin_canary:
-CANARY;
-tsig_begin_canary:
-CANARY;
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-tsig_end_canary:
-CANARY;
-tsig_end_canary:
-CANARY;
-
-#endif // rvtest_mtrap_routine
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif // rvtest_gpr_save
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b1-01.S
deleted file mode 100644
index c07dc85b3..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b1-01.S
+++ /dev/null
@@ -1,4740 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:16:34 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fltq.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fltq.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fltq_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f29; op2:f29; dest:x30; op1val:0x0; op2val:0x0;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f30; op2:f31; dest:x29; op1val:0x0; op2val:0x1;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f28; op2:f27; dest:x28; op1val:0x0; op2val:0x80000001;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f27; op2:f28; dest:x27; op1val:0x0; op2val:0x2;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f26; op2:f25; dest:x26; op1val:0x0; op2val:0x807ffffe;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f25; op2:f26; dest:x25; op1val:0x0; op2val:0x7fffff;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f24; op2:f23; dest:x24; op1val:0x0; op2val:0x807fffff;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f23; op2:f24; dest:x23; op1val:0x0; op2val:0x800000;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f22; op2:f21; dest:x22; op1val:0x0; op2val:0x80800000;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f21; op2:f22; dest:x21; op1val:0x0; op2val:0x800001;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f20; op2:f19; dest:x20; op1val:0x0; op2val:0x80855555;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f19; op2:f20; dest:x19; op1val:0x0; op2val:0x7f7fffff;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f18; op2:f17; dest:x18; op1val:0x0; op2val:0xff7fffff;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f17; op2:f18; dest:x17; op1val:0x0; op2val:0x7f800000;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f16; op2:f15; dest:x16; op1val:0x0; op2val:0xff800000;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f15; op2:f16; dest:x15; op1val:0x0; op2val:0x7fc00000;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f14; op2:f13; dest:x14; op1val:0x0; op2val:0xffc00000;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f13; op2:f14; dest:x13; op1val:0x0; op2val:0x7fc00001;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f12; op2:f11; dest:x12; op1val:0x0; op2val:0xffc55555;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f11; op2:f12; dest:x11; op1val:0x0; op2val:0x7f800001;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f10; op2:f9; dest:x10; op1val:0x0; op2val:0xffaaaaaa;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f9; op2:f10; dest:x9; op1val:0x0; op2val:0x3f800000;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f8; op2:f7; dest:x8; op1val:0x0; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f7; op2:f8; dest:x7; op1val:0x80000000; op2val:0x0;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f6; op2:f5; dest:x6; op1val:0x80000000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f5; op2:f6; dest:x5; op1val:0x80000000; op2val:0x1;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f4; op2:f3; dest:x4; op1val:0x80000000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f3; op2:f4; dest:x3; op1val:0x80000000; op2val:0x2;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f2; op2:f1; dest:x2; op1val:0x80000000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f1; op2:f2; dest:x1; op1val:0x80000000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f0; op2:f31; dest:x31; op1val:0x80000000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f0; dest:x31; op1val:0x80000000; op2val:0x800000;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x0; op1val:0x80000000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x800001;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x0;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80000000;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x1;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80000001;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x2;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x800000;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80800000;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x800001;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x80855555;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xff800000;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x0;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x1;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x2;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x800000;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x800001;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x0;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80000000;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x1;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80000001;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x2;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x800000;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80800000;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x800001;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x80855555;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xff800000;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x0;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80000000;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x1;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80000001;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x2;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x800000;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80800000;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x800001;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x80855555;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xff800000;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807ffffe; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x807fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x0;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x1;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x2;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x0;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x1;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x2;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x0;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x1;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x2;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x800000;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x800001;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x0;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80000000;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x1;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80000001;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x2;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x800000;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80800000;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x800001;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x80855555;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xff800000;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80855555; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x0;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80000000;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x1;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80000001;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x2;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800000;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80800000;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800001;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x80855555;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xff800000;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x0;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x1;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x2;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x0;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x1;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x2;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x0;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x1;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x2;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x800000;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x800001;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x0;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x1;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x2;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x800000;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x800001;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc00000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x0;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x1;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x2;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x800000;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x800001;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7fc00001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x0;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80000000;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x1;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80000001;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x2;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x800000;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80800000;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x800001;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x80855555;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xff800000;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffc55555; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x0;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80000000;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x1;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80000001;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x2;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x800000;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80800000;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x800001;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x80855555;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xff800000;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f800001; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x0;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80000000;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x1;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80000001;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x2;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x800000;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80800000;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x800001;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x80855555;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xff800000;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xffaaaaaa; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x0;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x1;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x2;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x0;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80000000;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x1;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80000001;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x2;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x807ffffe;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7fffff;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x807fffff;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x800000;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x800001;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x80855555;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7f800000;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xff800000;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7fc00000;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xffc00000;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7fc00001;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xffc55555;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x7f800001;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xffaaaaaa;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0x3f800000;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf800000; op2val:0xbf800000;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x80000000;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80000000; op2val:0x80800000;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-test_dataset_1:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
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-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 80*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b19-01.S
deleted file mode 100644
index b2fdfe8a2..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fltq_b19-01.S
+++ /dev/null
@@ -1,8027 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:16:34 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fltq.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fltq.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fltq_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f29; op2:f29; dest:x30; op1val:0x7f378efe; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f30; op2:f31; dest:x29; op1val:0x7f206a70; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f28; op2:f27; dest:x28; op1val:0x7f378efe; op2val:0x7ee8aebb;
-valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f27; op2:f28; dest:x27; op1val:0x7ee8aebb; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f26; op2:f25; dest:x26; op1val:0x7f378efe; op2val:0x7ea5608b;
-valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f25; op2:f26; dest:x25; op1val:0x7ea5608b; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f24; op2:f23; dest:x24; op1val:0x7f378efe; op2val:0x7f3648af;
-valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f23; op2:f24; dest:x23; op1val:0x7f3648af; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f22; op2:f21; dest:x22; op1val:0x7f378efe; op2val:0xfd204621;
-valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f21; op2:f22; dest:x21; op1val:0x7d92d8cb; op2val:0xfec857aa;
-valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfb and fm2 == 0x12d8cb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f20; op2:f19; dest:x20; op1val:0xfec857aa; op2val:0x7d92d8cb;
-valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f19; op2:f20; dest:x19; op1val:0x7d92d8cb; op2val:0xfd204621;
-valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfb and fm2 == 0x12d8cb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f18; op2:f17; dest:x18; op1val:0x7f378efe; op2val:0x7d92d8cb;
-valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f17; op2:f18; dest:x17; op1val:0x7f378efe; op2val:0xfe4ac669;
-valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f16; op2:f15; dest:x16; op1val:0x7d92d8cb; op2val:0xff7fffff;
-valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x12d8cb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f15; op2:f16; dest:x15; op1val:0xff7fffff; op2val:0x7d92d8cb;
-valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f14; op2:f13; dest:x14; op1val:0x7d92d8cb; op2val:0xfe4ac669;
-valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f13; op2:f14; dest:x13; op1val:0x7f378efe; op2val:0xfe96fcf5;
-valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f12; op2:f11; dest:x12; op1val:0xfe96fcf5; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f11; op2:f12; dest:x11; op1val:0x7f378efe; op2val:0xfee8e23e;
-valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f10; op2:f9; dest:x10; op1val:0xfee8e23e; op2val:0x7f378efe;
-valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f9; op2:f10; dest:x9; op1val:0x7f378efe; op2val:0xfeaf0937;
-valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-RVTEST_VALBASEUPD(x9,test_dataset_1)
-
-inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f8; op2:f7; dest:x8; op1val:0xfeaf0937; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
-
-inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f7; op2:f8; dest:x7; op1val:0x7f378efe; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
-
-inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a825 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f6; op2:f5; dest:x6; op1val:0x2a825; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
-RVTEST_SIGBASE(x6,signature_x6_0)
-
-inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a825 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f5; op2:f6; dest:x5; op1val:0x7f7a0dff; op2val:0x2a825;
-valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
-
-inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a825 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f4; op2:f3; dest:x4; op1val:0x2a825; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
-
-inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a825 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f3; op2:f4; dest:x3; op1val:0x7f378efe; op2val:0x2a825;
-valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
-
-inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f2; op2:f1; dest:x2; op1val:0x7f378efe; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
-
-inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f1; op2:f2; dest:x1; op1val:0x1a917b; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
-
-inst_31:// rs1==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f0; op2:f31; dest:x31; op1val:0x7f7fffff; op2val:0x1a917b;
-valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
-
-inst_32:// rs2==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f0; dest:x31; op1val:0x1a917b; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
-
-inst_33:// rd==x0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x0; op1val:0x7f378efe; op2val:0x1a917b;
-valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
-
-inst_34:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x253272;
-valaddr_reg:x9; val_offset:22*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 22*FLEN/8, x10, x6, x7)
-
-inst_35:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x253272;
-valaddr_reg:x9; val_offset:24*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 24*FLEN/8, x10, x6, x7)
-
-inst_36:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:26*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 26*FLEN/8, x10, x6, x7)
-
-inst_37:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:28*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 28*FLEN/8, x10, x6, x7)
-
-inst_38:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:30*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 30*FLEN/8, x10, x6, x7)
-
-inst_39:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:32*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 32*FLEN/8, x10, x6, x7)
-
-inst_40:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x1a917b;
-valaddr_reg:x9; val_offset:34*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 34*FLEN/8, x10, x6, x7)
-
-inst_41:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:36*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 36*FLEN/8, x10, x6, x7)
-
-inst_42:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:38*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 38*FLEN/8, x10, x6, x7)
-
-inst_43:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:40*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 40*FLEN/8, x10, x6, x7)
-
-inst_44:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x1a917b;
-valaddr_reg:x9; val_offset:42*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 42*FLEN/8, x10, x6, x7)
-
-inst_45:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:44*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 44*FLEN/8, x10, x6, x7)
-
-inst_46:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:46*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 46*FLEN/8, x10, x6, x7)
-
-inst_47:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:48*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 48*FLEN/8, x10, x6, x7)
-
-inst_48:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:50*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 50*FLEN/8, x10, x6, x7)
-
-inst_49:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:52*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 52*FLEN/8, x10, x6, x7)
-
-inst_50:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:54*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 54*FLEN/8, x10, x6, x7)
-
-inst_51:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x004403 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4403; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:56*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 56*FLEN/8, x10, x6, x7)
-
-inst_52:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004403 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x4403;
-valaddr_reg:x9; val_offset:58*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 58*FLEN/8, x10, x6, x7)
-
-inst_53:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x004403 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4403; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:60*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 60*FLEN/8, x10, x6, x7)
-
-inst_54:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x004403 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x4403;
-valaddr_reg:x9; val_offset:62*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 62*FLEN/8, x10, x6, x7)
-
-inst_55:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:64*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 64*FLEN/8, x10, x6, x7)
-
-inst_56:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a917b; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:66*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 66*FLEN/8, x10, x6, x7)
-
-inst_57:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x7f0;
-valaddr_reg:x9; val_offset:68*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 68*FLEN/8, x10, x6, x7)
-
-inst_58:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x1c2784 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x401c2784; op2val:0x7f0;
-valaddr_reg:x9; val_offset:70*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 70*FLEN/8, x10, x6, x7)
-
-inst_59:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1c2784 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x401c2784;
-valaddr_reg:x9; val_offset:72*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 72*FLEN/8, x10, x6, x7)
-
-inst_60:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1c2784 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x401c2784;
-valaddr_reg:x9; val_offset:74*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 74*FLEN/8, x10, x6, x7)
-
-inst_61:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:76*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 76*FLEN/8, x10, x6, x7)
-
-inst_62:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:78*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 78*FLEN/8, x10, x6, x7)
-
-inst_63:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:80*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 80*FLEN/8, x10, x6, x7)
-
-inst_64:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:82*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 82*FLEN/8, x10, x6, x7)
-
-inst_65:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:84*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 84*FLEN/8, x10, x6, x7)
-
-inst_66:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:86*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 86*FLEN/8, x10, x6, x7)
-
-inst_67:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:88*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 88*FLEN/8, x10, x6, x7)
-
-inst_68:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:90*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 90*FLEN/8, x10, x6, x7)
-
-inst_69:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x005526 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d805526; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:92*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 92*FLEN/8, x10, x6, x7)
-
-inst_70:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfb and fm2 == 0x005526 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7d805526;
-valaddr_reg:x9; val_offset:94*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 94*FLEN/8, x10, x6, x7)
-
-inst_71:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x005526 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d805526; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:96*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 96*FLEN/8, x10, x6, x7)
-
-inst_72:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x005526 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x7d805526;
-valaddr_reg:x9; val_offset:98*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 98*FLEN/8, x10, x6, x7)
-
-inst_73:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 100*FLEN/8, x10, x6, x7)
-
-inst_74:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x005526 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d805526; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 102*FLEN/8, x10, x6, x7)
-
-inst_75:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x005526 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7d805526;
-valaddr_reg:x9; val_offset:104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 104*FLEN/8, x10, x6, x7)
-
-inst_76:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x005526 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d805526; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 106*FLEN/8, x10, x6, x7)
-
-inst_77:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 108*FLEN/8, x10, x6, x7)
-
-inst_78:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 110*FLEN/8, x10, x6, x7)
-
-inst_79:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 112*FLEN/8, x10, x6, x7)
-
-inst_80:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 114*FLEN/8, x10, x6, x7)
-
-inst_81:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 116*FLEN/8, x10, x6, x7)
-
-inst_82:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 118*FLEN/8, x10, x6, x7)
-
-inst_83:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 120*FLEN/8, x10, x6, x7)
-
-inst_84:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025265 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x25265; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 122*FLEN/8, x10, x6, x7)
-
-inst_85:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025265 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x25265;
-valaddr_reg:x9; val_offset:124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 124*FLEN/8, x10, x6, x7)
-
-inst_86:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x025265 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x25265; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 126*FLEN/8, x10, x6, x7)
-
-inst_87:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x025265 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x25265;
-valaddr_reg:x9; val_offset:128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 128*FLEN/8, x10, x6, x7)
-
-inst_88:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 130*FLEN/8, x10, x6, x7)
-
-inst_89:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 132*FLEN/8, x10, x6, x7)
-
-inst_90:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1737f6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x1737f6;
-valaddr_reg:x9; val_offset:134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 134*FLEN/8, x10, x6, x7)
-
-inst_91:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 136*FLEN/8, x10, x6, x7)
-
-inst_92:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1737f6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x1737f6;
-valaddr_reg:x9; val_offset:138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 138*FLEN/8, x10, x6, x7)
-
-inst_93:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x253272;
-valaddr_reg:x9; val_offset:140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 140*FLEN/8, x10, x6, x7)
-
-inst_94:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x253272;
-valaddr_reg:x9; val_offset:142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 142*FLEN/8, x10, x6, x7)
-
-inst_95:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 144*FLEN/8, x10, x6, x7)
-
-inst_96:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 146*FLEN/8, x10, x6, x7)
-
-inst_97:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 148*FLEN/8, x10, x6, x7)
-
-inst_98:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 150*FLEN/8, x10, x6, x7)
-
-inst_99:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1737f6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x1737f6;
-valaddr_reg:x9; val_offset:152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 152*FLEN/8, x10, x6, x7)
-
-inst_100:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 154*FLEN/8, x10, x6, x7)
-
-inst_101:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 156*FLEN/8, x10, x6, x7)
-
-inst_102:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 158*FLEN/8, x10, x6, x7)
-
-inst_103:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1737f6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x1737f6;
-valaddr_reg:x9; val_offset:160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 160*FLEN/8, x10, x6, x7)
-
-inst_104:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 162*FLEN/8, x10, x6, x7)
-
-inst_105:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 164*FLEN/8, x10, x6, x7)
-
-inst_106:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 166*FLEN/8, x10, x6, x7)
-
-inst_107:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 168*FLEN/8, x10, x6, x7)
-
-inst_108:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 170*FLEN/8, x10, x6, x7)
-
-inst_109:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 172*FLEN/8, x10, x6, x7)
-
-inst_110:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003b70 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3b70; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 174*FLEN/8, x10, x6, x7)
-
-inst_111:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003b70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x3b70;
-valaddr_reg:x9; val_offset:176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 176*FLEN/8, x10, x6, x7)
-
-inst_112:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x003b70 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3b70; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 178*FLEN/8, x10, x6, x7)
-
-inst_113:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x003b70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x3b70;
-valaddr_reg:x9; val_offset:180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 180*FLEN/8, x10, x6, x7)
-
-inst_114:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 182*FLEN/8, x10, x6, x7)
-
-inst_115:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1737f6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1737f6; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 184*FLEN/8, x10, x6, x7)
-
-inst_116:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x7f0;
-valaddr_reg:x9; val_offset:186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 186*FLEN/8, x10, x6, x7)
-
-inst_117:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x087776 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x40087776; op2val:0x7f0;
-valaddr_reg:x9; val_offset:188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 188*FLEN/8, x10, x6, x7)
-
-inst_118:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x087776 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x40087776;
-valaddr_reg:x9; val_offset:190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 190*FLEN/8, x10, x6, x7)
-
-inst_119:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x087776 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f206a70; op2val:0x40087776;
-valaddr_reg:x9; val_offset:192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 192*FLEN/8, x10, x6, x7)
-
-inst_120:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 194*FLEN/8, x10, x6, x7)
-
-inst_121:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 196*FLEN/8, x10, x6, x7)
-
-inst_122:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 198*FLEN/8, x10, x6, x7)
-
-inst_123:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 200*FLEN/8, x10, x6, x7)
-
-inst_124:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 202*FLEN/8, x10, x6, x7)
-
-inst_125:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 204*FLEN/8, x10, x6, x7)
-
-inst_126:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x3a2562 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d3a2562; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 206*FLEN/8, x10, x6, x7)
-
-inst_127:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfa and fm2 == 0x3a2562 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7d3a2562;
-valaddr_reg:x9; val_offset:208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 208*FLEN/8, x10, x6, x7)
-
-inst_128:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x3a2562 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d3a2562; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 210*FLEN/8, x10, x6, x7)
-
-inst_129:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0xfa and fm2 == 0x3a2562 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x7d3a2562;
-valaddr_reg:x9; val_offset:212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 212*FLEN/8, x10, x6, x7)
-
-inst_130:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 214*FLEN/8, x10, x6, x7)
-
-inst_131:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x3a2562 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d3a2562; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 216*FLEN/8, x10, x6, x7)
-
-inst_132:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x3a2562 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7d3a2562;
-valaddr_reg:x9; val_offset:218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 218*FLEN/8, x10, x6, x7)
-
-inst_133:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x3a2562 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d3a2562; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 220*FLEN/8, x10, x6, x7)
-
-inst_134:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 222*FLEN/8, x10, x6, x7)
-
-inst_135:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 224*FLEN/8, x10, x6, x7)
-
-inst_136:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 226*FLEN/8, x10, x6, x7)
-
-inst_137:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 228*FLEN/8, x10, x6, x7)
-
-inst_138:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 230*FLEN/8, x10, x6, x7)
-
-inst_139:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 232*FLEN/8, x10, x6, x7)
-
-inst_140:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 234*FLEN/8, x10, x6, x7)
-
-inst_141:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01af15 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1af15; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 236*FLEN/8, x10, x6, x7)
-
-inst_142:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01af15 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x1af15;
-valaddr_reg:x9; val_offset:238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 238*FLEN/8, x10, x6, x7)
-
-inst_143:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x01af15 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1af15; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 240*FLEN/8, x10, x6, x7)
-
-inst_144:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x01af15 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x1af15;
-valaddr_reg:x9; val_offset:242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 242*FLEN/8, x10, x6, x7)
-
-inst_145:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 244*FLEN/8, x10, x6, x7)
-
-inst_146:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 246*FLEN/8, x10, x6, x7)
-
-inst_147:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x10d6d9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x10d6d9;
-valaddr_reg:x9; val_offset:248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 248*FLEN/8, x10, x6, x7)
-
-inst_148:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 250*FLEN/8, x10, x6, x7)
-
-inst_149:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x10d6d9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x10d6d9;
-valaddr_reg:x9; val_offset:252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 252*FLEN/8, x10, x6, x7)
-
-inst_150:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x253272;
-valaddr_reg:x9; val_offset:254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 254*FLEN/8, x10, x6, x7)
-
-inst_151:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x253272;
-valaddr_reg:x9; val_offset:256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 256*FLEN/8, x10, x6, x7)
-
-inst_152:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 258*FLEN/8, x10, x6, x7)
-
-inst_153:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 260*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_1)
-
-inst_154:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 262*FLEN/8, x10, x6, x7)
-
-inst_155:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 264*FLEN/8, x10, x6, x7)
-
-inst_156:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x10d6d9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x10d6d9;
-valaddr_reg:x9; val_offset:266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 266*FLEN/8, x10, x6, x7)
-
-inst_157:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 268*FLEN/8, x10, x6, x7)
-
-inst_158:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 270*FLEN/8, x10, x6, x7)
-
-inst_159:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 272*FLEN/8, x10, x6, x7)
-
-inst_160:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x10d6d9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x10d6d9;
-valaddr_reg:x9; val_offset:274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 274*FLEN/8, x10, x6, x7)
-
-inst_161:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 276*FLEN/8, x10, x6, x7)
-
-inst_162:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 278*FLEN/8, x10, x6, x7)
-
-inst_163:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 280*FLEN/8, x10, x6, x7)
-
-inst_164:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 282*FLEN/8, x10, x6, x7)
-
-inst_165:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 284*FLEN/8, x10, x6, x7)
-
-inst_166:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 286*FLEN/8, x10, x6, x7)
-
-inst_167:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002b1b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2b1b; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 288*FLEN/8, x10, x6, x7)
-
-inst_168:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002b1b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x2b1b;
-valaddr_reg:x9; val_offset:290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 290*FLEN/8, x10, x6, x7)
-
-inst_169:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x002b1b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2b1b; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 292*FLEN/8, x10, x6, x7)
-
-inst_170:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x002b1b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x2b1b;
-valaddr_reg:x9; val_offset:294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 294*FLEN/8, x10, x6, x7)
-
-inst_171:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 296*FLEN/8, x10, x6, x7)
-
-inst_172:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x10d6d9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x10d6d9; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 298*FLEN/8, x10, x6, x7)
-
-inst_173:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x7f0;
-valaddr_reg:x9; val_offset:300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 300*FLEN/8, x10, x6, x7)
-
-inst_174:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x45f1c5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3fc5f1c5; op2val:0x7f0;
-valaddr_reg:x9; val_offset:302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 302*FLEN/8, x10, x6, x7)
-
-inst_175:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x45f1c5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x3fc5f1c5;
-valaddr_reg:x9; val_offset:304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 304*FLEN/8, x10, x6, x7)
-
-inst_176:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0x7f and fm2 == 0x45f1c5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ee8aebb; op2val:0x3fc5f1c5;
-valaddr_reg:x9; val_offset:306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 306*FLEN/8, x10, x6, x7)
-
-inst_177:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 308*FLEN/8, x10, x6, x7)
-
-inst_178:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 310*FLEN/8, x10, x6, x7)
-
-inst_179:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 312*FLEN/8, x10, x6, x7)
-
-inst_180:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 314*FLEN/8, x10, x6, x7)
-
-inst_181:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x044d3c and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d044d3c; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 316*FLEN/8, x10, x6, x7)
-
-inst_182:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfa and fm2 == 0x044d3c and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7d044d3c;
-valaddr_reg:x9; val_offset:318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 318*FLEN/8, x10, x6, x7)
-
-inst_183:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x044d3c and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d044d3c; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 320*FLEN/8, x10, x6, x7)
-
-inst_184:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0xfa and fm2 == 0x044d3c and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x7d044d3c;
-valaddr_reg:x9; val_offset:322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 322*FLEN/8, x10, x6, x7)
-
-inst_185:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 324*FLEN/8, x10, x6, x7)
-
-inst_186:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x044d3c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d044d3c; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 326*FLEN/8, x10, x6, x7)
-
-inst_187:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x044d3c and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7d044d3c;
-valaddr_reg:x9; val_offset:328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 328*FLEN/8, x10, x6, x7)
-
-inst_188:// fs1 == 0 and fe1 == 0xfa and fm1 == 0x044d3c and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d044d3c; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 330*FLEN/8, x10, x6, x7)
-
-inst_189:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 332*FLEN/8, x10, x6, x7)
-
-inst_190:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 334*FLEN/8, x10, x6, x7)
-
-inst_191:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 336*FLEN/8, x10, x6, x7)
-
-inst_192:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 338*FLEN/8, x10, x6, x7)
-
-inst_193:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 340*FLEN/8, x10, x6, x7)
-
-inst_194:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 342*FLEN/8, x10, x6, x7)
-
-inst_195:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 344*FLEN/8, x10, x6, x7)
-
-inst_196:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x013263 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x13263; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 346*FLEN/8, x10, x6, x7)
-
-inst_197:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x013263 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x13263;
-valaddr_reg:x9; val_offset:348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 348*FLEN/8, x10, x6, x7)
-
-inst_198:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x013263 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x13263; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 350*FLEN/8, x10, x6, x7)
-
-inst_199:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x013263 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x13263;
-valaddr_reg:x9; val_offset:352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 352*FLEN/8, x10, x6, x7)
-
-inst_200:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 354*FLEN/8, x10, x6, x7)
-
-inst_201:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 356*FLEN/8, x10, x6, x7)
-
-inst_202:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0bf7e5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xbf7e5;
-valaddr_reg:x9; val_offset:358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 358*FLEN/8, x10, x6, x7)
-
-inst_203:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 360*FLEN/8, x10, x6, x7)
-
-inst_204:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0bf7e5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0xbf7e5;
-valaddr_reg:x9; val_offset:362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 362*FLEN/8, x10, x6, x7)
-
-inst_205:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x253272;
-valaddr_reg:x9; val_offset:364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 364*FLEN/8, x10, x6, x7)
-
-inst_206:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x253272;
-valaddr_reg:x9; val_offset:366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 366*FLEN/8, x10, x6, x7)
-
-inst_207:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 368*FLEN/8, x10, x6, x7)
-
-inst_208:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 370*FLEN/8, x10, x6, x7)
-
-inst_209:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 372*FLEN/8, x10, x6, x7)
-
-inst_210:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 374*FLEN/8, x10, x6, x7)
-
-inst_211:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0bf7e5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0xbf7e5;
-valaddr_reg:x9; val_offset:376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 376*FLEN/8, x10, x6, x7)
-
-inst_212:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 378*FLEN/8, x10, x6, x7)
-
-inst_213:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 380*FLEN/8, x10, x6, x7)
-
-inst_214:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 382*FLEN/8, x10, x6, x7)
-
-inst_215:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0bf7e5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xbf7e5;
-valaddr_reg:x9; val_offset:384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 384*FLEN/8, x10, x6, x7)
-
-inst_216:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 386*FLEN/8, x10, x6, x7)
-
-inst_217:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 388*FLEN/8, x10, x6, x7)
-
-inst_218:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 390*FLEN/8, x10, x6, x7)
-
-inst_219:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 392*FLEN/8, x10, x6, x7)
-
-inst_220:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 394*FLEN/8, x10, x6, x7)
-
-inst_221:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 396*FLEN/8, x10, x6, x7)
-
-inst_222:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001ea3 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1ea3; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 398*FLEN/8, x10, x6, x7)
-
-inst_223:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001ea3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x1ea3;
-valaddr_reg:x9; val_offset:400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 400*FLEN/8, x10, x6, x7)
-
-inst_224:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x001ea3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1ea3; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 402*FLEN/8, x10, x6, x7)
-
-inst_225:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x001ea3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x1ea3;
-valaddr_reg:x9; val_offset:404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 404*FLEN/8, x10, x6, x7)
-
-inst_226:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 406*FLEN/8, x10, x6, x7)
-
-inst_227:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0bf7e5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf7e5; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 408*FLEN/8, x10, x6, x7)
-
-inst_228:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x7f0;
-valaddr_reg:x9; val_offset:410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 410*FLEN/8, x10, x6, x7)
-
-inst_229:// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0caff3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3f8caff3; op2val:0x7f0;
-valaddr_reg:x9; val_offset:412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 412*FLEN/8, x10, x6, x7)
-
-inst_230:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0caff3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x3f8caff3;
-valaddr_reg:x9; val_offset:414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 414*FLEN/8, x10, x6, x7)
-
-inst_231:// fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0x7f and fm2 == 0x0caff3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7ea5608b; op2val:0x3f8caff3;
-valaddr_reg:x9; val_offset:416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 416*FLEN/8, x10, x6, x7)
-
-inst_232:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 418*FLEN/8, x10, x6, x7)
-
-inst_233:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 420*FLEN/8, x10, x6, x7)
-
-inst_234:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x11d3bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d91d3bf; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 422*FLEN/8, x10, x6, x7)
-
-inst_235:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfb and fm2 == 0x11d3bf and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7d91d3bf;
-valaddr_reg:x9; val_offset:424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 424*FLEN/8, x10, x6, x7)
-
-inst_236:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x11d3bf and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d91d3bf; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 426*FLEN/8, x10, x6, x7)
-
-inst_237:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0xfb and fm2 == 0x11d3bf and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x7d91d3bf;
-valaddr_reg:x9; val_offset:428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 428*FLEN/8, x10, x6, x7)
-
-inst_238:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 430*FLEN/8, x10, x6, x7)
-
-inst_239:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x11d3bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d91d3bf; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 432*FLEN/8, x10, x6, x7)
-
-inst_240:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x11d3bf and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7d91d3bf;
-valaddr_reg:x9; val_offset:434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 434*FLEN/8, x10, x6, x7)
-
-inst_241:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x11d3bf and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d91d3bf; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 436*FLEN/8, x10, x6, x7)
-
-inst_242:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 438*FLEN/8, x10, x6, x7)
-
-inst_243:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 440*FLEN/8, x10, x6, x7)
-
-inst_244:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 442*FLEN/8, x10, x6, x7)
-
-inst_245:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 444*FLEN/8, x10, x6, x7)
-
-inst_246:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 446*FLEN/8, x10, x6, x7)
-
-inst_247:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 448*FLEN/8, x10, x6, x7)
-
-inst_248:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 450*FLEN/8, x10, x6, x7)
-
-inst_249:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a36c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2a36c; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 452*FLEN/8, x10, x6, x7)
-
-inst_250:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a36c and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x2a36c;
-valaddr_reg:x9; val_offset:454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 454*FLEN/8, x10, x6, x7)
-
-inst_251:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a36c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2a36c; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 456*FLEN/8, x10, x6, x7)
-
-inst_252:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a36c and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x2a36c;
-valaddr_reg:x9; val_offset:458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 458*FLEN/8, x10, x6, x7)
-
-inst_253:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 460*FLEN/8, x10, x6, x7)
-
-inst_254:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 462*FLEN/8, x10, x6, x7)
-
-inst_255:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a6240 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x1a6240;
-valaddr_reg:x9; val_offset:464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 464*FLEN/8, x10, x6, x7)
-
-inst_256:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 466*FLEN/8, x10, x6, x7)
-
-inst_257:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a6240 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x1a6240;
-valaddr_reg:x9; val_offset:468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 468*FLEN/8, x10, x6, x7)
-
-inst_258:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x253272;
-valaddr_reg:x9; val_offset:470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 470*FLEN/8, x10, x6, x7)
-
-inst_259:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x253272;
-valaddr_reg:x9; val_offset:472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 472*FLEN/8, x10, x6, x7)
-
-inst_260:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 474*FLEN/8, x10, x6, x7)
-
-inst_261:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 476*FLEN/8, x10, x6, x7)
-
-inst_262:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 478*FLEN/8, x10, x6, x7)
-
-inst_263:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 480*FLEN/8, x10, x6, x7)
-
-inst_264:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a6240 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x1a6240;
-valaddr_reg:x9; val_offset:482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 482*FLEN/8, x10, x6, x7)
-
-inst_265:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 484*FLEN/8, x10, x6, x7)
-
-inst_266:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 486*FLEN/8, x10, x6, x7)
-
-inst_267:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 488*FLEN/8, x10, x6, x7)
-
-inst_268:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a6240 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x1a6240;
-valaddr_reg:x9; val_offset:490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 490*FLEN/8, x10, x6, x7)
-
-inst_269:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 492*FLEN/8, x10, x6, x7)
-
-inst_270:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 494*FLEN/8, x10, x6, x7)
-
-inst_271:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 496*FLEN/8, x10, x6, x7)
-
-inst_272:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 498*FLEN/8, x10, x6, x7)
-
-inst_273:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 500*FLEN/8, x10, x6, x7)
-
-inst_274:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 502*FLEN/8, x10, x6, x7)
-
-inst_275:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00438a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x438a; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 504*FLEN/8, x10, x6, x7)
-
-inst_276:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00438a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x438a;
-valaddr_reg:x9; val_offset:506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 506*FLEN/8, x10, x6, x7)
-
-inst_277:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x00438a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x438a; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 508*FLEN/8, x10, x6, x7)
-
-inst_278:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x00438a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x438a;
-valaddr_reg:x9; val_offset:510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 510*FLEN/8, x10, x6, x7)
-
-inst_279:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 512*FLEN/8, x10, x6, x7)
-
-inst_280:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a6240 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1a6240; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 514*FLEN/8, x10, x6, x7)
-
-inst_281:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x7f0;
-valaddr_reg:x9; val_offset:516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 516*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_2)
-
-inst_282:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x1b11ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x401b11ec; op2val:0x7f0;
-valaddr_reg:x9; val_offset:518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 518*FLEN/8, x10, x6, x7)
-
-inst_283:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1b11ec and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x401b11ec;
-valaddr_reg:x9; val_offset:520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 520*FLEN/8, x10, x6, x7)
-
-inst_284:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1b11ec and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f3648af; op2val:0x401b11ec;
-valaddr_reg:x9; val_offset:522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 522*FLEN/8, x10, x6, x7)
-
-inst_285:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 524*FLEN/8, x10, x6, x7)
-
-inst_286:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 526*FLEN/8, x10, x6, x7)
-
-inst_287:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 528*FLEN/8, x10, x6, x7)
-
-inst_288:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 530*FLEN/8, x10, x6, x7)
-
-inst_289:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 532*FLEN/8, x10, x6, x7)
-
-inst_290:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 534*FLEN/8, x10, x6, x7)
-
-inst_291:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 536*FLEN/8, x10, x6, x7)
-
-inst_292:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 538*FLEN/8, x10, x6, x7)
-
-inst_293:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 540*FLEN/8, x10, x6, x7)
-
-inst_294:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 542*FLEN/8, x10, x6, x7)
-
-inst_295:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 544*FLEN/8, x10, x6, x7)
-
-inst_296:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 546*FLEN/8, x10, x6, x7)
-
-inst_297:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 548*FLEN/8, x10, x6, x7)
-
-inst_298:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 550*FLEN/8, x10, x6, x7)
-
-inst_299:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 552*FLEN/8, x10, x6, x7)
-
-inst_300:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x7194bc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0xfcf194bc;
-valaddr_reg:x9; val_offset:554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 554*FLEN/8, x10, x6, x7)
-
-inst_301:// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7194bc and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfcf194bc; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 556*FLEN/8, x10, x6, x7)
-
-inst_302:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 558*FLEN/8, x10, x6, x7)
-
-inst_303:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 560*FLEN/8, x10, x6, x7)
-
-inst_304:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 1 and fe2 == 0xfa and fm2 == 0x3a4e98 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0xfd3a4e98;
-valaddr_reg:x9; val_offset:562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 562*FLEN/8, x10, x6, x7)
-
-inst_305:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x3a4e98 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd3a4e98; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 564*FLEN/8, x10, x6, x7)
-
-inst_306:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 566*FLEN/8, x10, x6, x7)
-
-inst_307:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 568*FLEN/8, x10, x6, x7)
-
-inst_308:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 1 and fe2 == 0xfa and fm2 == 0x0c075f and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0xfd0c075f;
-valaddr_reg:x9; val_offset:570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 570*FLEN/8, x10, x6, x7)
-
-inst_309:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c075f and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c075f; op2val:0xfec857aa;
-valaddr_reg:x9; val_offset:572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 572*FLEN/8, x10, x6, x7)
-
-inst_310:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfec857aa; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 574*FLEN/8, x10, x6, x7)
-
-inst_311:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 576*FLEN/8, x10, x6, x7)
-
-inst_312:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01732b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x480b33 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001732b; op2val:0x7dc80b33;
-valaddr_reg:x9; val_offset:578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 578*FLEN/8, x10, x6, x7)
-
-inst_313:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x480b33 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01732b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dc80b33; op2val:0x8001732b;
-valaddr_reg:x9; val_offset:580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 580*FLEN/8, x10, x6, x7)
-
-inst_314:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01732b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001732b; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 582*FLEN/8, x10, x6, x7)
-
-inst_315:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01732b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x8001732b;
-valaddr_reg:x9; val_offset:584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 584*FLEN/8, x10, x6, x7)
-
-inst_316:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 586*FLEN/8, x10, x6, x7)
-
-inst_317:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x6ce8a1 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x7dece8a1;
-valaddr_reg:x9; val_offset:588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 588*FLEN/8, x10, x6, x7)
-
-inst_318:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x6ce8a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dece8a1; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 590*FLEN/8, x10, x6, x7)
-
-inst_319:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 592*FLEN/8, x10, x6, x7)
-
-inst_320:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 594*FLEN/8, x10, x6, x7)
-
-inst_321:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x253272;
-valaddr_reg:x9; val_offset:596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 596*FLEN/8, x10, x6, x7)
-
-inst_322:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4d97f8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x7dcd97f8;
-valaddr_reg:x9; val_offset:598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 598*FLEN/8, x10, x6, x7)
-
-inst_323:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4d97f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dcd97f8; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 600*FLEN/8, x10, x6, x7)
-
-inst_324:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x253272;
-valaddr_reg:x9; val_offset:602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 602*FLEN/8, x10, x6, x7)
-
-inst_325:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 604*FLEN/8, x10, x6, x7)
-
-inst_326:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x7fc1a6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x7dffc1a6;
-valaddr_reg:x9; val_offset:606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 606*FLEN/8, x10, x6, x7)
-
-inst_327:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7fc1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dffc1a6; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 608*FLEN/8, x10, x6, x7)
-
-inst_328:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 610*FLEN/8, x10, x6, x7)
-
-inst_329:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 612*FLEN/8, x10, x6, x7)
-
-inst_330:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d5c91 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x7d9d5c91;
-valaddr_reg:x9; val_offset:614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 614*FLEN/8, x10, x6, x7)
-
-inst_331:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d5c91 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d9d5c91; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 616*FLEN/8, x10, x6, x7)
-
-inst_332:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 618*FLEN/8, x10, x6, x7)
-
-inst_333:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 620*FLEN/8, x10, x6, x7)
-
-inst_334:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x21db85 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0xfe21db85;
-valaddr_reg:x9; val_offset:622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 622*FLEN/8, x10, x6, x7)
-
-inst_335:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x21db85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe21db85; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 624*FLEN/8, x10, x6, x7)
-
-inst_336:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 626*FLEN/8, x10, x6, x7)
-
-inst_337:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 628*FLEN/8, x10, x6, x7)
-
-inst_338:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x74bcf0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0xfdf4bcf0;
-valaddr_reg:x9; val_offset:630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 630*FLEN/8, x10, x6, x7)
-
-inst_339:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x74bcf0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdf4bcf0; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 632*FLEN/8, x10, x6, x7)
-
-inst_340:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 634*FLEN/8, x10, x6, x7)
-
-inst_341:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 636*FLEN/8, x10, x6, x7)
-
-inst_342:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x14db11 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0xfe14db11;
-valaddr_reg:x9; val_offset:638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 638*FLEN/8, x10, x6, x7)
-
-inst_343:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x14db11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe14db11; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 640*FLEN/8, x10, x6, x7)
-
-inst_344:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 642*FLEN/8, x10, x6, x7)
-
-inst_345:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 644*FLEN/8, x10, x6, x7)
-
-inst_346:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00251d and fs2 == 1 and fe2 == 0xfb and fm2 == 0x374171 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000251d; op2val:0xfdb74171;
-valaddr_reg:x9; val_offset:646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 646*FLEN/8, x10, x6, x7)
-
-inst_347:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x374171 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00251d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdb74171; op2val:0x8000251d;
-valaddr_reg:x9; val_offset:648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 648*FLEN/8, x10, x6, x7)
-
-inst_348:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00251d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000251d; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 650*FLEN/8, x10, x6, x7)
-
-inst_349:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00251d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x8000251d;
-valaddr_reg:x9; val_offset:652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 652*FLEN/8, x10, x6, x7)
-
-inst_350:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 654*FLEN/8, x10, x6, x7)
-
-inst_351:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x016ce1 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0xfe016ce1;
-valaddr_reg:x9; val_offset:656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 656*FLEN/8, x10, x6, x7)
-
-inst_352:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x016ce1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0e7fb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe016ce1; op2val:0x800e7fb0;
-valaddr_reg:x9; val_offset:658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 658*FLEN/8, x10, x6, x7)
-
-inst_353:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0e7fb0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800e7fb0; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 660*FLEN/8, x10, x6, x7)
-
-inst_354:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0x7f0;
-valaddr_reg:x9; val_offset:662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 662*FLEN/8, x10, x6, x7)
-
-inst_355:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x2a6eb8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbfaa6eb8; op2val:0x7f0;
-valaddr_reg:x9; val_offset:664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 664*FLEN/8, x10, x6, x7)
-
-inst_356:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x2a6eb8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbfaa6eb8;
-valaddr_reg:x9; val_offset:666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 666*FLEN/8, x10, x6, x7)
-
-inst_357:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x204621 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x2a6eb8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd204621; op2val:0xbfaa6eb8;
-valaddr_reg:x9; val_offset:668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 668*FLEN/8, x10, x6, x7)
-
-inst_358:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 670*FLEN/8, x10, x6, x7)
-
-inst_359:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 672*FLEN/8, x10, x6, x7)
-
-inst_360:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 674*FLEN/8, x10, x6, x7)
-
-inst_361:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 676*FLEN/8, x10, x6, x7)
-
-inst_362:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 678*FLEN/8, x10, x6, x7)
-
-inst_363:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 680*FLEN/8, x10, x6, x7)
-
-inst_364:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 682*FLEN/8, x10, x6, x7)
-
-inst_365:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 684*FLEN/8, x10, x6, x7)
-
-inst_366:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 686*FLEN/8, x10, x6, x7)
-
-inst_367:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 688*FLEN/8, x10, x6, x7)
-
-inst_368:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 690*FLEN/8, x10, x6, x7)
-
-inst_369:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 692*FLEN/8, x10, x6, x7)
-
-inst_370:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 694*FLEN/8, x10, x6, x7)
-
-inst_371:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x7194bc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfcf194bc;
-valaddr_reg:x9; val_offset:696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 696*FLEN/8, x10, x6, x7)
-
-inst_372:// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7194bc and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfcf194bc; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 698*FLEN/8, x10, x6, x7)
-
-inst_373:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 700*FLEN/8, x10, x6, x7)
-
-inst_374:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 702*FLEN/8, x10, x6, x7)
-
-inst_375:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x3a4e98 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfd3a4e98;
-valaddr_reg:x9; val_offset:704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 704*FLEN/8, x10, x6, x7)
-
-inst_376:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x3a4e98 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd3a4e98; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 706*FLEN/8, x10, x6, x7)
-
-inst_377:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 708*FLEN/8, x10, x6, x7)
-
-inst_378:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 710*FLEN/8, x10, x6, x7)
-
-inst_379:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x0c075f and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfd0c075f;
-valaddr_reg:x9; val_offset:712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 712*FLEN/8, x10, x6, x7)
-
-inst_380:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c075f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c075f; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 714*FLEN/8, x10, x6, x7)
-
-inst_381:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 716*FLEN/8, x10, x6, x7)
-
-inst_382:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 718*FLEN/8, x10, x6, x7)
-
-inst_383:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x075661 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x480b33 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80075661; op2val:0x7dc80b33;
-valaddr_reg:x9; val_offset:720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 720*FLEN/8, x10, x6, x7)
-
-inst_384:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x480b33 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x075661 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dc80b33; op2val:0x80075661;
-valaddr_reg:x9; val_offset:722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 722*FLEN/8, x10, x6, x7)
-
-inst_385:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x075661 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80075661; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 724*FLEN/8, x10, x6, x7)
-
-inst_386:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x075661 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x80075661;
-valaddr_reg:x9; val_offset:726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 726*FLEN/8, x10, x6, x7)
-
-inst_387:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 728*FLEN/8, x10, x6, x7)
-
-inst_388:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0xfb and fm2 == 0x6ce8a1 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x7dece8a1;
-valaddr_reg:x9; val_offset:730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 730*FLEN/8, x10, x6, x7)
-
-inst_389:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x6ce8a1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dece8a1; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 732*FLEN/8, x10, x6, x7)
-
-inst_390:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 734*FLEN/8, x10, x6, x7)
-
-inst_391:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 736*FLEN/8, x10, x6, x7)
-
-inst_392:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x253272;
-valaddr_reg:x9; val_offset:738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 738*FLEN/8, x10, x6, x7)
-
-inst_393:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4d97f8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x7dcd97f8;
-valaddr_reg:x9; val_offset:740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 740*FLEN/8, x10, x6, x7)
-
-inst_394:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4d97f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dcd97f8; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 742*FLEN/8, x10, x6, x7)
-
-inst_395:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x253272;
-valaddr_reg:x9; val_offset:744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 744*FLEN/8, x10, x6, x7)
-
-inst_396:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 746*FLEN/8, x10, x6, x7)
-
-inst_397:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0xfb and fm2 == 0x7fc1a6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x7dffc1a6;
-valaddr_reg:x9; val_offset:748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 748*FLEN/8, x10, x6, x7)
-
-inst_398:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7fc1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dffc1a6; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 750*FLEN/8, x10, x6, x7)
-
-inst_399:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 752*FLEN/8, x10, x6, x7)
-
-inst_400:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 754*FLEN/8, x10, x6, x7)
-
-inst_401:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d5c91 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x7d9d5c91;
-valaddr_reg:x9; val_offset:756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 756*FLEN/8, x10, x6, x7)
-
-inst_402:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d5c91 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d9d5c91; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 758*FLEN/8, x10, x6, x7)
-
-inst_403:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 760*FLEN/8, x10, x6, x7)
-
-inst_404:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 762*FLEN/8, x10, x6, x7)
-
-inst_405:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x21db85 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0xfe21db85;
-valaddr_reg:x9; val_offset:764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 764*FLEN/8, x10, x6, x7)
-
-inst_406:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x21db85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe21db85; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 766*FLEN/8, x10, x6, x7)
-
-inst_407:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 768*FLEN/8, x10, x6, x7)
-
-inst_408:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 770*FLEN/8, x10, x6, x7)
-
-inst_409:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0xfb and fm2 == 0x74bcf0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0xfdf4bcf0;
-valaddr_reg:x9; val_offset:772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 772*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_3)
-
-inst_410:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x74bcf0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdf4bcf0; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 774*FLEN/8, x10, x6, x7)
-
-inst_411:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 776*FLEN/8, x10, x6, x7)
-
-inst_412:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 778*FLEN/8, x10, x6, x7)
-
-inst_413:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x14db11 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0xfe14db11;
-valaddr_reg:x9; val_offset:780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 780*FLEN/8, x10, x6, x7)
-
-inst_414:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x14db11 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe14db11; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 782*FLEN/8, x10, x6, x7)
-
-inst_415:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 784*FLEN/8, x10, x6, x7)
-
-inst_416:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 786*FLEN/8, x10, x6, x7)
-
-inst_417:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00bbd6 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x374171 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000bbd6; op2val:0xfdb74171;
-valaddr_reg:x9; val_offset:788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 788*FLEN/8, x10, x6, x7)
-
-inst_418:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x374171 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00bbd6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdb74171; op2val:0x8000bbd6;
-valaddr_reg:x9; val_offset:790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 790*FLEN/8, x10, x6, x7)
-
-inst_419:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00bbd6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000bbd6; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 792*FLEN/8, x10, x6, x7)
-
-inst_420:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00bbd6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x8000bbd6;
-valaddr_reg:x9; val_offset:794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 794*FLEN/8, x10, x6, x7)
-
-inst_421:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 796*FLEN/8, x10, x6, x7)
-
-inst_422:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x016ce1 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0xfe016ce1;
-valaddr_reg:x9; val_offset:798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 798*FLEN/8, x10, x6, x7)
-
-inst_423:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x016ce1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x495fcb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe016ce1; op2val:0x80495fcb;
-valaddr_reg:x9; val_offset:800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 800*FLEN/8, x10, x6, x7)
-
-inst_424:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x495fcb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80495fcb; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 802*FLEN/8, x10, x6, x7)
-
-inst_425:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0x7f0;
-valaddr_reg:x9; val_offset:804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 804*FLEN/8, x10, x6, x7)
-
-inst_426:// fs1 == 1 and fe1 == 0x81 and fm1 == 0x57a09d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc0d7a09d; op2val:0x7f0;
-valaddr_reg:x9; val_offset:806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 806*FLEN/8, x10, x6, x7)
-
-inst_427:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x57a09d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc0d7a09d;
-valaddr_reg:x9; val_offset:808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 808*FLEN/8, x10, x6, x7)
-
-inst_428:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x4ac669 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x57a09d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe4ac669; op2val:0xc0d7a09d;
-valaddr_reg:x9; val_offset:810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 810*FLEN/8, x10, x6, x7)
-
-inst_429:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 812*FLEN/8, x10, x6, x7)
-
-inst_430:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 814*FLEN/8, x10, x6, x7)
-
-inst_431:// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7194bc and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfcf194bc; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 816*FLEN/8, x10, x6, x7)
-
-inst_432:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x7194bc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0xfcf194bc;
-valaddr_reg:x9; val_offset:818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 818*FLEN/8, x10, x6, x7)
-
-inst_433:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 820*FLEN/8, x10, x6, x7)
-
-inst_434:// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7194bc and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfcf194bc; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 822*FLEN/8, x10, x6, x7)
-
-inst_435:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 824*FLEN/8, x10, x6, x7)
-
-inst_436:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 826*FLEN/8, x10, x6, x7)
-
-inst_437:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 828*FLEN/8, x10, x6, x7)
-
-inst_438:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 830*FLEN/8, x10, x6, x7)
-
-inst_439:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 832*FLEN/8, x10, x6, x7)
-
-inst_440:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0117bb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800117bb; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 834*FLEN/8, x10, x6, x7)
-
-inst_441:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0117bb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x800117bb;
-valaddr_reg:x9; val_offset:836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 836*FLEN/8, x10, x6, x7)
-
-inst_442:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0117bb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800117bb; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 838*FLEN/8, x10, x6, x7)
-
-inst_443:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0117bb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x800117bb;
-valaddr_reg:x9; val_offset:840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 840*FLEN/8, x10, x6, x7)
-
-inst_444:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 842*FLEN/8, x10, x6, x7)
-
-inst_445:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 844*FLEN/8, x10, x6, x7)
-
-inst_446:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0aed51 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800aed51;
-valaddr_reg:x9; val_offset:846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 846*FLEN/8, x10, x6, x7)
-
-inst_447:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 848*FLEN/8, x10, x6, x7)
-
-inst_448:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0aed51 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x800aed51;
-valaddr_reg:x9; val_offset:850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 850*FLEN/8, x10, x6, x7)
-
-inst_449:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x253272;
-valaddr_reg:x9; val_offset:852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 852*FLEN/8, x10, x6, x7)
-
-inst_450:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x253272;
-valaddr_reg:x9; val_offset:854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 854*FLEN/8, x10, x6, x7)
-
-inst_451:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 856*FLEN/8, x10, x6, x7)
-
-inst_452:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 858*FLEN/8, x10, x6, x7)
-
-inst_453:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 860*FLEN/8, x10, x6, x7)
-
-inst_454:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 862*FLEN/8, x10, x6, x7)
-
-inst_455:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0aed51 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x800aed51;
-valaddr_reg:x9; val_offset:864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 864*FLEN/8, x10, x6, x7)
-
-inst_456:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 866*FLEN/8, x10, x6, x7)
-
-inst_457:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 868*FLEN/8, x10, x6, x7)
-
-inst_458:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 870*FLEN/8, x10, x6, x7)
-
-inst_459:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0aed51 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800aed51;
-valaddr_reg:x9; val_offset:872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 872*FLEN/8, x10, x6, x7)
-
-inst_460:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 874*FLEN/8, x10, x6, x7)
-
-inst_461:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 876*FLEN/8, x10, x6, x7)
-
-inst_462:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 878*FLEN/8, x10, x6, x7)
-
-inst_463:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 880*FLEN/8, x10, x6, x7)
-
-inst_464:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 882*FLEN/8, x10, x6, x7)
-
-inst_465:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 884*FLEN/8, x10, x6, x7)
-
-inst_466:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001bf9 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80001bf9; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 886*FLEN/8, x10, x6, x7)
-
-inst_467:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001bf9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x80001bf9;
-valaddr_reg:x9; val_offset:888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 888*FLEN/8, x10, x6, x7)
-
-inst_468:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x001bf9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80001bf9; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 890*FLEN/8, x10, x6, x7)
-
-inst_469:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x001bf9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x80001bf9;
-valaddr_reg:x9; val_offset:892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 892*FLEN/8, x10, x6, x7)
-
-inst_470:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 894*FLEN/8, x10, x6, x7)
-
-inst_471:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0aed51 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800aed51; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 896*FLEN/8, x10, x6, x7)
-
-inst_472:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0x7f0;
-valaddr_reg:x9; val_offset:898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 898*FLEN/8, x10, x6, x7)
-
-inst_473:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x00724d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf80724d; op2val:0x7f0;
-valaddr_reg:x9; val_offset:900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 900*FLEN/8, x10, x6, x7)
-
-inst_474:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x00724d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbf80724d;
-valaddr_reg:x9; val_offset:902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 902*FLEN/8, x10, x6, x7)
-
-inst_475:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x00724d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe96fcf5; op2val:0xbf80724d;
-valaddr_reg:x9; val_offset:904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 904*FLEN/8, x10, x6, x7)
-
-inst_476:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 906*FLEN/8, x10, x6, x7)
-
-inst_477:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 908*FLEN/8, x10, x6, x7)
-
-inst_478:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x3a4e98 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd3a4e98; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 910*FLEN/8, x10, x6, x7)
-
-inst_479:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x3a4e98 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0xfd3a4e98;
-valaddr_reg:x9; val_offset:912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 912*FLEN/8, x10, x6, x7)
-
-inst_480:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 914*FLEN/8, x10, x6, x7)
-
-inst_481:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x3a4e98 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd3a4e98; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 916*FLEN/8, x10, x6, x7)
-
-inst_482:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 918*FLEN/8, x10, x6, x7)
-
-inst_483:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 920*FLEN/8, x10, x6, x7)
-
-inst_484:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 922*FLEN/8, x10, x6, x7)
-
-inst_485:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01af75 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001af75; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 924*FLEN/8, x10, x6, x7)
-
-inst_486:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01af75 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x8001af75;
-valaddr_reg:x9; val_offset:926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 926*FLEN/8, x10, x6, x7)
-
-inst_487:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01af75 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8001af75; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:928*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 928*FLEN/8, x10, x6, x7)
-
-inst_488:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01af75 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x8001af75;
-valaddr_reg:x9; val_offset:930*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 930*FLEN/8, x10, x6, x7)
-
-inst_489:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:932*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 932*FLEN/8, x10, x6, x7)
-
-inst_490:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:934*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 934*FLEN/8, x10, x6, x7)
-
-inst_491:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10da93 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x8010da93;
-valaddr_reg:x9; val_offset:936*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 936*FLEN/8, x10, x6, x7)
-
-inst_492:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:938*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 938*FLEN/8, x10, x6, x7)
-
-inst_493:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10da93 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x8010da93;
-valaddr_reg:x9; val_offset:940*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 940*FLEN/8, x10, x6, x7)
-
-inst_494:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x253272;
-valaddr_reg:x9; val_offset:942*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 942*FLEN/8, x10, x6, x7)
-
-inst_495:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x253272;
-valaddr_reg:x9; val_offset:944*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 944*FLEN/8, x10, x6, x7)
-
-inst_496:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:946*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 946*FLEN/8, x10, x6, x7)
-
-inst_497:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:948*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 948*FLEN/8, x10, x6, x7)
-
-inst_498:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:950*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 950*FLEN/8, x10, x6, x7)
-
-inst_499:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:952*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 952*FLEN/8, x10, x6, x7)
-
-inst_500:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10da93 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x8010da93;
-valaddr_reg:x9; val_offset:954*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 954*FLEN/8, x10, x6, x7)
-
-inst_501:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:956*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 956*FLEN/8, x10, x6, x7)
-
-inst_502:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:958*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 958*FLEN/8, x10, x6, x7)
-
-inst_503:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:960*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 960*FLEN/8, x10, x6, x7)
-
-inst_504:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x10da93 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x8010da93;
-valaddr_reg:x9; val_offset:962*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 962*FLEN/8, x10, x6, x7)
-
-inst_505:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:964*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 964*FLEN/8, x10, x6, x7)
-
-inst_506:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:966*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 966*FLEN/8, x10, x6, x7)
-
-inst_507:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:968*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 968*FLEN/8, x10, x6, x7)
-
-inst_508:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:970*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 970*FLEN/8, x10, x6, x7)
-
-inst_509:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:972*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 972*FLEN/8, x10, x6, x7)
-
-inst_510:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:974*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 974*FLEN/8, x10, x6, x7)
-
-inst_511:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002b25 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80002b25; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:976*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 976*FLEN/8, x10, x6, x7)
-
-inst_512:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002b25 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x80002b25;
-valaddr_reg:x9; val_offset:978*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 978*FLEN/8, x10, x6, x7)
-
-inst_513:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x002b25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80002b25; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:980*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 980*FLEN/8, x10, x6, x7)
-
-inst_514:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x002b25 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x80002b25;
-valaddr_reg:x9; val_offset:982*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 982*FLEN/8, x10, x6, x7)
-
-inst_515:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:984*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 984*FLEN/8, x10, x6, x7)
-
-inst_516:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x10da93 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8010da93; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:986*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 986*FLEN/8, x10, x6, x7)
-
-inst_517:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0x7f0;
-valaddr_reg:x9; val_offset:988*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 988*FLEN/8, x10, x6, x7)
-
-inst_518:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x461d98 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbfc61d98; op2val:0x7f0;
-valaddr_reg:x9; val_offset:990*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 990*FLEN/8, x10, x6, x7)
-
-inst_519:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x461d98 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbfc61d98;
-valaddr_reg:x9; val_offset:992*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 992*FLEN/8, x10, x6, x7)
-
-inst_520:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 1 and fe2 == 0x7f and fm2 == 0x461d98 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfee8e23e; op2val:0xbfc61d98;
-valaddr_reg:x9; val_offset:994*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 994*FLEN/8, x10, x6, x7)
-
-inst_521:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:996*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 996*FLEN/8, x10, x6, x7)
-
-inst_522:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:998*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 998*FLEN/8, x10, x6, x7)
-
-inst_523:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c075f and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c075f; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1000*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1000*FLEN/8, x10, x6, x7)
-
-inst_524:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x0c075f and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0xfd0c075f;
-valaddr_reg:x9; val_offset:1002*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1002*FLEN/8, x10, x6, x7)
-
-inst_525:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1004*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1004*FLEN/8, x10, x6, x7)
-
-inst_526:// fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c075f and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfd0c075f; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1006*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1006*FLEN/8, x10, x6, x7)
-
-inst_527:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1008*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1008*FLEN/8, x10, x6, x7)
-
-inst_528:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x014448 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80014448; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:1010*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1010*FLEN/8, x10, x6, x7)
-
-inst_529:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x014448 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x80014448;
-valaddr_reg:x9; val_offset:1012*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1012*FLEN/8, x10, x6, x7)
-
-inst_530:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x014448 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80014448; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1014*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1014*FLEN/8, x10, x6, x7)
-
-inst_531:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x014448 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x80014448;
-valaddr_reg:x9; val_offset:1016*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1016*FLEN/8, x10, x6, x7)
-
-inst_532:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1018*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1018*FLEN/8, x10, x6, x7)
-
-inst_533:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1020*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1020*FLEN/8, x10, x6, x7)
-
-inst_534:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caad8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x800caad8;
-valaddr_reg:x9; val_offset:1022*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1022*FLEN/8, x10, x6, x7)
-
-inst_535:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1024*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1024*FLEN/8, x10, x6, x7)
-
-inst_536:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caad8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x800caad8;
-valaddr_reg:x9; val_offset:1026*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1026*FLEN/8, x10, x6, x7)
-
-inst_537:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x253272;
-valaddr_reg:x9; val_offset:1028*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1028*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_4)
-
-inst_538:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x253272;
-valaddr_reg:x9; val_offset:1030*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1030*FLEN/8, x10, x6, x7)
-
-inst_539:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1032*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1032*FLEN/8, x10, x6, x7)
-
-inst_540:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1034*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1034*FLEN/8, x10, x6, x7)
-
-inst_541:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1036*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1036*FLEN/8, x10, x6, x7)
-
-inst_542:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:1038*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1038*FLEN/8, x10, x6, x7)
-
-inst_543:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caad8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x800caad8;
-valaddr_reg:x9; val_offset:1040*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1040*FLEN/8, x10, x6, x7)
-
-inst_544:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1042*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1042*FLEN/8, x10, x6, x7)
-
-inst_545:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1044*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1044*FLEN/8, x10, x6, x7)
-
-inst_546:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1046*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1046*FLEN/8, x10, x6, x7)
-
-inst_547:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0caad8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff7fffff; op2val:0x800caad8;
-valaddr_reg:x9; val_offset:1048*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1048*FLEN/8, x10, x6, x7)
-
-inst_548:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1050*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1050*FLEN/8, x10, x6, x7)
-
-inst_549:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1052*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1052*FLEN/8, x10, x6, x7)
-
-inst_550:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1054*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1054*FLEN/8, x10, x6, x7)
-
-inst_551:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1056*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1056*FLEN/8, x10, x6, x7)
-
-inst_552:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1058*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1058*FLEN/8, x10, x6, x7)
-
-inst_553:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1060*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1060*FLEN/8, x10, x6, x7)
-
-inst_554:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00206d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000206d; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:1062*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1062*FLEN/8, x10, x6, x7)
-
-inst_555:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00206d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x8000206d;
-valaddr_reg:x9; val_offset:1064*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1064*FLEN/8, x10, x6, x7)
-
-inst_556:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00206d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000206d; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1066*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1066*FLEN/8, x10, x6, x7)
-
-inst_557:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00206d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x8000206d;
-valaddr_reg:x9; val_offset:1068*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1068*FLEN/8, x10, x6, x7)
-
-inst_558:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1070*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1070*FLEN/8, x10, x6, x7)
-
-inst_559:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0caad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800caad8; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1072*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1072*FLEN/8, x10, x6, x7)
-
-inst_560:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1074*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1074*FLEN/8, x10, x6, x7)
-
-inst_561:// fs1 == 1 and fe1 == 0x7f and fm1 == 0x14e777 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xbf94e777; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1076*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1076*FLEN/8, x10, x6, x7)
-
-inst_562:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x14e777 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xbf94e777;
-valaddr_reg:x9; val_offset:1078*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1078*FLEN/8, x10, x6, x7)
-
-inst_563:// fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x14e777 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfeaf0937; op2val:0xbf94e777;
-valaddr_reg:x9; val_offset:1080*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1080*FLEN/8, x10, x6, x7)
-
-inst_564:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1082*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1082*FLEN/8, x10, x6, x7)
-
-inst_565:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1084*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1084*FLEN/8, x10, x6, x7)
-
-inst_566:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7f7a0dff;
-valaddr_reg:x9; val_offset:1086*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1086*FLEN/8, x10, x6, x7)
-
-inst_567:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1088*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1088*FLEN/8, x10, x6, x7)
-
-inst_568:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1090*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1090*FLEN/8, x10, x6, x7)
-
-inst_569:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1092*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1092*FLEN/8, x10, x6, x7)
-
-inst_570:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1094*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1094*FLEN/8, x10, x6, x7)
-
-inst_571:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1096*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1096*FLEN/8, x10, x6, x7)
-
-inst_572:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1098*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1098*FLEN/8, x10, x6, x7)
-
-inst_573:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1100*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1100*FLEN/8, x10, x6, x7)
-
-inst_574:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1102*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1102*FLEN/8, x10, x6, x7)
-
-inst_575:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1104*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1104*FLEN/8, x10, x6, x7)
-
-inst_576:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1106*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1106*FLEN/8, x10, x6, x7)
-
-inst_577:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x480b33 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dc80b33; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1108*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1108*FLEN/8, x10, x6, x7)
-
-inst_578:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0xfb and fm2 == 0x480b33 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7dc80b33;
-valaddr_reg:x9; val_offset:1110*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1110*FLEN/8, x10, x6, x7)
-
-inst_579:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1112*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1112*FLEN/8, x10, x6, x7)
-
-inst_580:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x480b33 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dc80b33; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1114*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1114*FLEN/8, x10, x6, x7)
-
-inst_581:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1116*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1116*FLEN/8, x10, x6, x7)
-
-inst_582:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1118*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1118*FLEN/8, x10, x6, x7)
-
-inst_583:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1120*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1120*FLEN/8, x10, x6, x7)
-
-inst_584:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1122*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1122*FLEN/8, x10, x6, x7)
-
-inst_585:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1124*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1124*FLEN/8, x10, x6, x7)
-
-inst_586:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7a0dff; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1126*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1126*FLEN/8, x10, x6, x7)
-
-inst_587:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1128*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1128*FLEN/8, x10, x6, x7)
-
-inst_588:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x044949 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x44949;
-valaddr_reg:x9; val_offset:1130*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1130*FLEN/8, x10, x6, x7)
-
-inst_589:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044949 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x44949; op2val:0x243164;
-valaddr_reg:x9; val_offset:1132*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1132*FLEN/8, x10, x6, x7)
-
-inst_590:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1134*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1134*FLEN/8, x10, x6, x7)
-
-inst_591:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x243164;
-valaddr_reg:x9; val_offset:1136*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1136*FLEN/8, x10, x6, x7)
-
-inst_592:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x253272;
-valaddr_reg:x9; val_offset:1138*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1138*FLEN/8, x10, x6, x7)
-
-inst_593:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03b83e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x3b83e;
-valaddr_reg:x9; val_offset:1140*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1140*FLEN/8, x10, x6, x7)
-
-inst_594:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03b83e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3b83e; op2val:0x243164;
-valaddr_reg:x9; val_offset:1142*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1142*FLEN/8, x10, x6, x7)
-
-inst_595:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x253272;
-valaddr_reg:x9; val_offset:1144*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1144*FLEN/8, x10, x6, x7)
-
-inst_596:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1146*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1146*FLEN/8, x10, x6, x7)
-
-inst_597:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x04a095 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x4a095;
-valaddr_reg:x9; val_offset:1148*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1148*FLEN/8, x10, x6, x7)
-
-inst_598:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a095 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4a095; op2val:0x243164;
-valaddr_reg:x9; val_offset:1150*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1150*FLEN/8, x10, x6, x7)
-
-inst_599:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1152*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1152*FLEN/8, x10, x6, x7)
-
-inst_600:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1154*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1154*FLEN/8, x10, x6, x7)
-
-inst_601:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02d8d9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x2d8d9;
-valaddr_reg:x9; val_offset:1156*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1156*FLEN/8, x10, x6, x7)
-
-inst_602:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02d8d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2d8d9; op2val:0x243164;
-valaddr_reg:x9; val_offset:1158*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1158*FLEN/8, x10, x6, x7)
-
-inst_603:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1160*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1160*FLEN/8, x10, x6, x7)
-
-inst_604:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1162*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1162*FLEN/8, x10, x6, x7)
-
-inst_605:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x05db58 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x8005db58;
-valaddr_reg:x9; val_offset:1164*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1164*FLEN/8, x10, x6, x7)
-
-inst_606:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x05db58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8005db58; op2val:0x243164;
-valaddr_reg:x9; val_offset:1166*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1166*FLEN/8, x10, x6, x7)
-
-inst_607:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1168*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1168*FLEN/8, x10, x6, x7)
-
-inst_608:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1170*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1170*FLEN/8, x10, x6, x7)
-
-inst_609:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x046d8c and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x80046d8c;
-valaddr_reg:x9; val_offset:1172*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1172*FLEN/8, x10, x6, x7)
-
-inst_610:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x046d8c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80046d8c; op2val:0x243164;
-valaddr_reg:x9; val_offset:1174*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1174*FLEN/8, x10, x6, x7)
-
-inst_611:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1176*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1176*FLEN/8, x10, x6, x7)
-
-inst_612:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1178*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1178*FLEN/8, x10, x6, x7)
-
-inst_613:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0562e7 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x800562e7;
-valaddr_reg:x9; val_offset:1180*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1180*FLEN/8, x10, x6, x7)
-
-inst_614:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0562e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800562e7; op2val:0x243164;
-valaddr_reg:x9; val_offset:1182*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1182*FLEN/8, x10, x6, x7)
-
-inst_615:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1184*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1184*FLEN/8, x10, x6, x7)
-
-inst_616:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1186*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1186*FLEN/8, x10, x6, x7)
-
-inst_617:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005ca7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0350c8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5ca7; op2val:0x800350c8;
-valaddr_reg:x9; val_offset:1188*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1188*FLEN/8, x10, x6, x7)
-
-inst_618:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0350c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005ca7 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800350c8; op2val:0x5ca7;
-valaddr_reg:x9; val_offset:1190*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1190*FLEN/8, x10, x6, x7)
-
-inst_619:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005ca7 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5ca7; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1192*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1192*FLEN/8, x10, x6, x7)
-
-inst_620:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005ca7 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x5ca7;
-valaddr_reg:x9; val_offset:1194*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1194*FLEN/8, x10, x6, x7)
-
-inst_621:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1196*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1196*FLEN/8, x10, x6, x7)
-
-inst_622:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04aeea and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x8004aeea;
-valaddr_reg:x9; val_offset:1198*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1198*FLEN/8, x10, x6, x7)
-
-inst_623:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04aeea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x243164 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8004aeea; op2val:0x243164;
-valaddr_reg:x9; val_offset:1200*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1200*FLEN/8, x10, x6, x7)
-
-inst_624:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x243164 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x243164; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1202*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1202*FLEN/8, x10, x6, x7)
-
-inst_625:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1204*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1204*FLEN/8, x10, x6, x7)
-
-inst_626:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x54b916 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4054b916; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1206*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1206*FLEN/8, x10, x6, x7)
-
-inst_627:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x54b916 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x4054b916;
-valaddr_reg:x9; val_offset:1208*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1208*FLEN/8, x10, x6, x7)
-
-inst_628:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x039e8a and fs2 == 0 and fe2 == 0x80 and fm2 == 0x54b916 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x39e8a; op2val:0x4054b916;
-valaddr_reg:x9; val_offset:1210*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1210*FLEN/8, x10, x6, x7)
-
-inst_629:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1212*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1212*FLEN/8, x10, x6, x7)
-
-inst_630:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1214*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1214*FLEN/8, x10, x6, x7)
-
-inst_631:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1216*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1216*FLEN/8, x10, x6, x7)
-
-inst_632:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1218*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1218*FLEN/8, x10, x6, x7)
-
-inst_633:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1220*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1220*FLEN/8, x10, x6, x7)
-
-inst_634:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1222*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1222*FLEN/8, x10, x6, x7)
-
-inst_635:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1224*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1224*FLEN/8, x10, x6, x7)
-
-inst_636:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1226*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1226*FLEN/8, x10, x6, x7)
-
-inst_637:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1228*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1228*FLEN/8, x10, x6, x7)
-
-inst_638:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1230*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1230*FLEN/8, x10, x6, x7)
-
-inst_639:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1232*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1232*FLEN/8, x10, x6, x7)
-
-inst_640:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1234*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1234*FLEN/8, x10, x6, x7)
-
-inst_641:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1236*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1236*FLEN/8, x10, x6, x7)
-
-inst_642:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x6ce8a1 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dece8a1; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1238*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1238*FLEN/8, x10, x6, x7)
-
-inst_643:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0xfb and fm2 == 0x6ce8a1 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7dece8a1;
-valaddr_reg:x9; val_offset:1240*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1240*FLEN/8, x10, x6, x7)
-
-inst_644:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1242*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1242*FLEN/8, x10, x6, x7)
-
-inst_645:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x6ce8a1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dece8a1; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1244*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1244*FLEN/8, x10, x6, x7)
-
-inst_646:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1246*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1246*FLEN/8, x10, x6, x7)
-
-inst_647:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1248*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1248*FLEN/8, x10, x6, x7)
-
-inst_648:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1250*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1250*FLEN/8, x10, x6, x7)
-
-inst_649:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1252*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1252*FLEN/8, x10, x6, x7)
-
-inst_650:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1254*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1254*FLEN/8, x10, x6, x7)
-
-inst_651:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f7fffff; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1256*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1256*FLEN/8, x10, x6, x7)
-
-inst_652:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1258*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1258*FLEN/8, x10, x6, x7)
-
-inst_653:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x044949 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x44949; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1260*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1260*FLEN/8, x10, x6, x7)
-
-inst_654:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x044949 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x44949;
-valaddr_reg:x9; val_offset:1262*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1262*FLEN/8, x10, x6, x7)
-
-inst_655:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x253272;
-valaddr_reg:x9; val_offset:1264*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1264*FLEN/8, x10, x6, x7)
-
-inst_656:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1266*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1266*FLEN/8, x10, x6, x7)
-
-inst_657:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1268*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1268*FLEN/8, x10, x6, x7)
-
-inst_658:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1270*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1270*FLEN/8, x10, x6, x7)
-
-inst_659:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1272*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1272*FLEN/8, x10, x6, x7)
-
-inst_660:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1274*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1274*FLEN/8, x10, x6, x7)
-
-inst_661:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1276*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1276*FLEN/8, x10, x6, x7)
-
-inst_662:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1278*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1278*FLEN/8, x10, x6, x7)
-
-inst_663:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1280*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1280*FLEN/8, x10, x6, x7)
-
-inst_664:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1282*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1282*FLEN/8, x10, x6, x7)
-
-inst_665:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1284*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1284*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_5)
-
-inst_666:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1286*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1286*FLEN/8, x10, x6, x7)
-
-inst_667:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1288*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1288*FLEN/8, x10, x6, x7)
-
-inst_668:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006dba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x6dba; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1290*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1290*FLEN/8, x10, x6, x7)
-
-inst_669:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006dba and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x6dba;
-valaddr_reg:x9; val_offset:1292*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1292*FLEN/8, x10, x6, x7)
-
-inst_670:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x006dba and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x6dba; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1294*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1294*FLEN/8, x10, x6, x7)
-
-inst_671:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x006dba and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x6dba;
-valaddr_reg:x9; val_offset:1296*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1296*FLEN/8, x10, x6, x7)
-
-inst_672:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1298*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1298*FLEN/8, x10, x6, x7)
-
-inst_673:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1300*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1300*FLEN/8, x10, x6, x7)
-
-inst_674:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1302*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1302*FLEN/8, x10, x6, x7)
-
-inst_675:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x7becb0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x407becb0; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1304*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1304*FLEN/8, x10, x6, x7)
-
-inst_676:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x7becb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x407becb0;
-valaddr_reg:x9; val_offset:1306*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1306*FLEN/8, x10, x6, x7)
-
-inst_677:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2adcdc and fs2 == 0 and fe2 == 0x80 and fm2 == 0x7becb0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2adcdc; op2val:0x407becb0;
-valaddr_reg:x9; val_offset:1308*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1308*FLEN/8, x10, x6, x7)
-
-inst_678:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1310*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1310*FLEN/8, x10, x6, x7)
-
-inst_679:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1312*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1312*FLEN/8, x10, x6, x7)
-
-inst_680:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x253272;
-valaddr_reg:x9; val_offset:1314*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1314*FLEN/8, x10, x6, x7)
-
-inst_681:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1316*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1316*FLEN/8, x10, x6, x7)
-
-inst_682:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1318*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1318*FLEN/8, x10, x6, x7)
-
-inst_683:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1320*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1320*FLEN/8, x10, x6, x7)
-
-inst_684:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1322*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1322*FLEN/8, x10, x6, x7)
-
-inst_685:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1324*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1324*FLEN/8, x10, x6, x7)
-
-inst_686:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4d97f8 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dcd97f8; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1326*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1326*FLEN/8, x10, x6, x7)
-
-inst_687:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4d97f8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7dcd97f8;
-valaddr_reg:x9; val_offset:1328*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1328*FLEN/8, x10, x6, x7)
-
-inst_688:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1330*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1330*FLEN/8, x10, x6, x7)
-
-inst_689:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4d97f8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dcd97f8; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1332*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1332*FLEN/8, x10, x6, x7)
-
-inst_690:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1334*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1334*FLEN/8, x10, x6, x7)
-
-inst_691:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1336*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1336*FLEN/8, x10, x6, x7)
-
-inst_692:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1338*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1338*FLEN/8, x10, x6, x7)
-
-inst_693:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1340*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1340*FLEN/8, x10, x6, x7)
-
-inst_694:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03b83e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x3b83e; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1342*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1342*FLEN/8, x10, x6, x7)
-
-inst_695:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03b83e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x3b83e;
-valaddr_reg:x9; val_offset:1344*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1344*FLEN/8, x10, x6, x7)
-
-inst_696:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1346*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1346*FLEN/8, x10, x6, x7)
-
-inst_697:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x253272;
-valaddr_reg:x9; val_offset:1348*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1348*FLEN/8, x10, x6, x7)
-
-inst_698:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1350*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1350*FLEN/8, x10, x6, x7)
-
-inst_699:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x253272;
-valaddr_reg:x9; val_offset:1352*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1352*FLEN/8, x10, x6, x7)
-
-inst_700:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1354*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1354*FLEN/8, x10, x6, x7)
-
-inst_701:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x253272;
-valaddr_reg:x9; val_offset:1356*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1356*FLEN/8, x10, x6, x7)
-
-inst_702:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1358*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1358*FLEN/8, x10, x6, x7)
-
-inst_703:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x253272;
-valaddr_reg:x9; val_offset:1360*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1360*FLEN/8, x10, x6, x7)
-
-inst_704:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1362*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1362*FLEN/8, x10, x6, x7)
-
-inst_705:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x253272;
-valaddr_reg:x9; val_offset:1364*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1364*FLEN/8, x10, x6, x7)
-
-inst_706:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1366*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1366*FLEN/8, x10, x6, x7)
-
-inst_707:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005f39 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5f39; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1368*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1368*FLEN/8, x10, x6, x7)
-
-inst_708:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005f39 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x5f39;
-valaddr_reg:x9; val_offset:1370*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1370*FLEN/8, x10, x6, x7)
-
-inst_709:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x005f39 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x5f39; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1372*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1372*FLEN/8, x10, x6, x7)
-
-inst_710:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x005f39 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x5f39;
-valaddr_reg:x9; val_offset:1374*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1374*FLEN/8, x10, x6, x7)
-
-inst_711:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1376*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1376*FLEN/8, x10, x6, x7)
-
-inst_712:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x253272;
-valaddr_reg:x9; val_offset:1378*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1378*FLEN/8, x10, x6, x7)
-
-inst_713:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1380*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1380*FLEN/8, x10, x6, x7)
-
-inst_714:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x5a9fe8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x405a9fe8; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1382*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1382*FLEN/8, x10, x6, x7)
-
-inst_715:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a9fe8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x405a9fe8;
-valaddr_reg:x9; val_offset:1384*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1384*FLEN/8, x10, x6, x7)
-
-inst_716:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x253272 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5a9fe8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x253272; op2val:0x405a9fe8;
-valaddr_reg:x9; val_offset:1386*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1386*FLEN/8, x10, x6, x7)
-
-inst_717:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1388*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1388*FLEN/8, x10, x6, x7)
-
-inst_718:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7f7fffff;
-valaddr_reg:x9; val_offset:1390*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1390*FLEN/8, x10, x6, x7)
-
-inst_719:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1392*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1392*FLEN/8, x10, x6, x7)
-
-inst_720:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1394*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1394*FLEN/8, x10, x6, x7)
-
-inst_721:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1396*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1396*FLEN/8, x10, x6, x7)
-
-inst_722:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1398*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1398*FLEN/8, x10, x6, x7)
-
-inst_723:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1400*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1400*FLEN/8, x10, x6, x7)
-
-inst_724:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1402*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1402*FLEN/8, x10, x6, x7)
-
-inst_725:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7fc1a6 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dffc1a6; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1404*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1404*FLEN/8, x10, x6, x7)
-
-inst_726:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x7fc1a6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7dffc1a6;
-valaddr_reg:x9; val_offset:1406*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1406*FLEN/8, x10, x6, x7)
-
-inst_727:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1408*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1408*FLEN/8, x10, x6, x7)
-
-inst_728:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x7fc1a6 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7dffc1a6; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1410*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1410*FLEN/8, x10, x6, x7)
-
-inst_729:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1412*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1412*FLEN/8, x10, x6, x7)
-
-inst_730:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1414*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1414*FLEN/8, x10, x6, x7)
-
-inst_731:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1416*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1416*FLEN/8, x10, x6, x7)
-
-inst_732:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1418*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1418*FLEN/8, x10, x6, x7)
-
-inst_733:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x04a095 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4a095; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1420*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1420*FLEN/8, x10, x6, x7)
-
-inst_734:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x04a095 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x4a095;
-valaddr_reg:x9; val_offset:1422*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1422*FLEN/8, x10, x6, x7)
-
-inst_735:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1424*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1424*FLEN/8, x10, x6, x7)
-
-inst_736:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1426*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1426*FLEN/8, x10, x6, x7)
-
-inst_737:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1428*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1428*FLEN/8, x10, x6, x7)
-
-inst_738:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1430*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1430*FLEN/8, x10, x6, x7)
-
-inst_739:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1432*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1432*FLEN/8, x10, x6, x7)
-
-inst_740:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1434*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1434*FLEN/8, x10, x6, x7)
-
-inst_741:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1436*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1436*FLEN/8, x10, x6, x7)
-
-inst_742:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1438*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1438*FLEN/8, x10, x6, x7)
-
-inst_743:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1440*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1440*FLEN/8, x10, x6, x7)
-
-inst_744:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007675 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7675; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1442*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1442*FLEN/8, x10, x6, x7)
-
-inst_745:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007675 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x7675;
-valaddr_reg:x9; val_offset:1444*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1444*FLEN/8, x10, x6, x7)
-
-inst_746:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x007675 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7675; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1446*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1446*FLEN/8, x10, x6, x7)
-
-inst_747:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x007675 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7675;
-valaddr_reg:x9; val_offset:1448*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1448*FLEN/8, x10, x6, x7)
-
-inst_748:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1450*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1450*FLEN/8, x10, x6, x7)
-
-inst_749:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1452*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1452*FLEN/8, x10, x6, x7)
-
-inst_750:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1454*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1454*FLEN/8, x10, x6, x7)
-
-inst_751:// fs1 == 0 and fe1 == 0x81 and fm1 == 0x07fbc3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x4087fbc3; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1456*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1456*FLEN/8, x10, x6, x7)
-
-inst_752:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x07fbc3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x4087fbc3;
-valaddr_reg:x9; val_offset:1458*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1458*FLEN/8, x10, x6, x7)
-
-inst_753:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x2e45d4 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x07fbc3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2e45d4; op2val:0x4087fbc3;
-valaddr_reg:x9; val_offset:1460*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1460*FLEN/8, x10, x6, x7)
-
-inst_754:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1462*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1462*FLEN/8, x10, x6, x7)
-
-inst_755:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1464*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1464*FLEN/8, x10, x6, x7)
-
-inst_756:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44b3b6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7f44b3b6;
-valaddr_reg:x9; val_offset:1466*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1466*FLEN/8, x10, x6, x7)
-
-inst_757:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1468*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1468*FLEN/8, x10, x6, x7)
-
-inst_758:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1470*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1470*FLEN/8, x10, x6, x7)
-
-inst_759:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1472*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1472*FLEN/8, x10, x6, x7)
-
-inst_760:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1474*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1474*FLEN/8, x10, x6, x7)
-
-inst_761:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1476*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1476*FLEN/8, x10, x6, x7)
-
-inst_762:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1478*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1478*FLEN/8, x10, x6, x7)
-
-inst_763:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1480*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1480*FLEN/8, x10, x6, x7)
-
-inst_764:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1482*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1482*FLEN/8, x10, x6, x7)
-
-inst_765:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1484*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1484*FLEN/8, x10, x6, x7)
-
-inst_766:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1486*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1486*FLEN/8, x10, x6, x7)
-
-inst_767:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d5c91 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d9d5c91; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1488*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1488*FLEN/8, x10, x6, x7)
-
-inst_768:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d5c91 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7d9d5c91;
-valaddr_reg:x9; val_offset:1490*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1490*FLEN/8, x10, x6, x7)
-
-inst_769:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1492*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1492*FLEN/8, x10, x6, x7)
-
-inst_770:// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d5c91 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7d9d5c91; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1494*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1494*FLEN/8, x10, x6, x7)
-
-inst_771:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1496*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1496*FLEN/8, x10, x6, x7)
-
-inst_772:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1498*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1498*FLEN/8, x10, x6, x7)
-
-inst_773:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1500*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1500*FLEN/8, x10, x6, x7)
-
-inst_774:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1502*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1502*FLEN/8, x10, x6, x7)
-
-inst_775:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1504*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1504*FLEN/8, x10, x6, x7)
-
-inst_776:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44b3b6 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f44b3b6; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1506*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1506*FLEN/8, x10, x6, x7)
-
-inst_777:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1508*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1508*FLEN/8, x10, x6, x7)
-
-inst_778:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02d8d9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x2d8d9; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1510*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1510*FLEN/8, x10, x6, x7)
-
-inst_779:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02d8d9 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x2d8d9;
-valaddr_reg:x9; val_offset:1512*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1512*FLEN/8, x10, x6, x7)
-
-inst_780:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1514*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1514*FLEN/8, x10, x6, x7)
-
-inst_781:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1516*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1516*FLEN/8, x10, x6, x7)
-
-inst_782:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1518*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1518*FLEN/8, x10, x6, x7)
-
-inst_783:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1520*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1520*FLEN/8, x10, x6, x7)
-
-inst_784:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1522*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1522*FLEN/8, x10, x6, x7)
-
-inst_785:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1524*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1524*FLEN/8, x10, x6, x7)
-
-inst_786:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1526*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1526*FLEN/8, x10, x6, x7)
-
-inst_787:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0048e2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x48e2; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1528*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1528*FLEN/8, x10, x6, x7)
-
-inst_788:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0048e2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x48e2;
-valaddr_reg:x9; val_offset:1530*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1530*FLEN/8, x10, x6, x7)
-
-inst_789:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0048e2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x48e2; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1532*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1532*FLEN/8, x10, x6, x7)
-
-inst_790:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0048e2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x48e2;
-valaddr_reg:x9; val_offset:1534*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1534*FLEN/8, x10, x6, x7)
-
-inst_791:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1536*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1536*FLEN/8, x10, x6, x7)
-
-inst_792:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1538*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1538*FLEN/8, x10, x6, x7)
-
-inst_793:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1540*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1540*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_6)
-
-inst_794:// fs1 == 0 and fe1 == 0x80 and fm1 == 0x2755e6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x402755e6; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1542*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1542*FLEN/8, x10, x6, x7)
-
-inst_795:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2755e6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x402755e6;
-valaddr_reg:x9; val_offset:1544*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1544*FLEN/8, x10, x6, x7)
-
-inst_796:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c787d and fs2 == 0 and fe2 == 0x80 and fm2 == 0x2755e6 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x1c787d; op2val:0x402755e6;
-valaddr_reg:x9; val_offset:1546*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1546*FLEN/8, x10, x6, x7)
-
-inst_797:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1548*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1548*FLEN/8, x10, x6, x7)
-
-inst_798:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1550*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1550*FLEN/8, x10, x6, x7)
-
-inst_799:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1552*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1552*FLEN/8, x10, x6, x7)
-
-inst_800:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1554*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1554*FLEN/8, x10, x6, x7)
-
-inst_801:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1556*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1556*FLEN/8, x10, x6, x7)
-
-inst_802:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1558*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1558*FLEN/8, x10, x6, x7)
-
-inst_803:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1560*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1560*FLEN/8, x10, x6, x7)
-
-inst_804:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1562*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1562*FLEN/8, x10, x6, x7)
-
-inst_805:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x21db85 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe21db85; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1564*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1564*FLEN/8, x10, x6, x7)
-
-inst_806:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x21db85 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xfe21db85;
-valaddr_reg:x9; val_offset:1566*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1566*FLEN/8, x10, x6, x7)
-
-inst_807:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1568*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1568*FLEN/8, x10, x6, x7)
-
-inst_808:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x21db85 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe21db85; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1570*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1570*FLEN/8, x10, x6, x7)
-
-inst_809:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1572*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1572*FLEN/8, x10, x6, x7)
-
-inst_810:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1574*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1574*FLEN/8, x10, x6, x7)
-
-inst_811:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1576*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1576*FLEN/8, x10, x6, x7)
-
-inst_812:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1578*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1578*FLEN/8, x10, x6, x7)
-
-inst_813:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x05db58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8005db58; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1580*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1580*FLEN/8, x10, x6, x7)
-
-inst_814:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x05db58 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x8005db58;
-valaddr_reg:x9; val_offset:1582*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1582*FLEN/8, x10, x6, x7)
-
-inst_815:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1584*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1584*FLEN/8, x10, x6, x7)
-
-inst_816:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1586*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1586*FLEN/8, x10, x6, x7)
-
-inst_817:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1588*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1588*FLEN/8, x10, x6, x7)
-
-inst_818:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1590*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1590*FLEN/8, x10, x6, x7)
-
-inst_819:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1592*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1592*FLEN/8, x10, x6, x7)
-
-inst_820:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0095ef and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800095ef; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1594*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1594*FLEN/8, x10, x6, x7)
-
-inst_821:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0095ef and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x800095ef;
-valaddr_reg:x9; val_offset:1596*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1596*FLEN/8, x10, x6, x7)
-
-inst_822:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0095ef and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800095ef; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1598*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1598*FLEN/8, x10, x6, x7)
-
-inst_823:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0095ef and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x800095ef;
-valaddr_reg:x9; val_offset:1600*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1600*FLEN/8, x10, x6, x7)
-
-inst_824:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1602*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1602*FLEN/8, x10, x6, x7)
-
-inst_825:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1604*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1604*FLEN/8, x10, x6, x7)
-
-inst_826:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1606*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1606*FLEN/8, x10, x6, x7)
-
-inst_827:// fs1 == 1 and fe1 == 0x81 and fm1 == 0x2c1dce and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc0ac1dce; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1608*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1608*FLEN/8, x10, x6, x7)
-
-inst_828:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x2c1dce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc0ac1dce;
-valaddr_reg:x9; val_offset:1610*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1610*FLEN/8, x10, x6, x7)
-
-inst_829:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3a9174 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x2c1dce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x803a9174; op2val:0xc0ac1dce;
-valaddr_reg:x9; val_offset:1612*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1612*FLEN/8, x10, x6, x7)
-
-inst_830:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1614*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1614*FLEN/8, x10, x6, x7)
-
-inst_831:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1616*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1616*FLEN/8, x10, x6, x7)
-
-inst_832:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1618*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1618*FLEN/8, x10, x6, x7)
-
-inst_833:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1620*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1620*FLEN/8, x10, x6, x7)
-
-inst_834:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1622*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1622*FLEN/8, x10, x6, x7)
-
-inst_835:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1624*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1624*FLEN/8, x10, x6, x7)
-
-inst_836:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1626*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1626*FLEN/8, x10, x6, x7)
-
-inst_837:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1628*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1628*FLEN/8, x10, x6, x7)
-
-inst_838:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x74bcf0 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdf4bcf0; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1630*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1630*FLEN/8, x10, x6, x7)
-
-inst_839:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0xfb and fm2 == 0x74bcf0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xfdf4bcf0;
-valaddr_reg:x9; val_offset:1632*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1632*FLEN/8, x10, x6, x7)
-
-inst_840:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1634*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1634*FLEN/8, x10, x6, x7)
-
-inst_841:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x74bcf0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdf4bcf0; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1636*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1636*FLEN/8, x10, x6, x7)
-
-inst_842:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1638*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1638*FLEN/8, x10, x6, x7)
-
-inst_843:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1640*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1640*FLEN/8, x10, x6, x7)
-
-inst_844:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1642*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1642*FLEN/8, x10, x6, x7)
-
-inst_845:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1644*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1644*FLEN/8, x10, x6, x7)
-
-inst_846:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x046d8c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x80046d8c; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1646*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1646*FLEN/8, x10, x6, x7)
-
-inst_847:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x046d8c and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x80046d8c;
-valaddr_reg:x9; val_offset:1648*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1648*FLEN/8, x10, x6, x7)
-
-inst_848:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1650*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1650*FLEN/8, x10, x6, x7)
-
-inst_849:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1652*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1652*FLEN/8, x10, x6, x7)
-
-inst_850:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1654*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1654*FLEN/8, x10, x6, x7)
-
-inst_851:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00715a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000715a; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1656*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1656*FLEN/8, x10, x6, x7)
-
-inst_852:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00715a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x8000715a;
-valaddr_reg:x9; val_offset:1658*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1658*FLEN/8, x10, x6, x7)
-
-inst_853:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x00715a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8000715a; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1660*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1660*FLEN/8, x10, x6, x7)
-
-inst_854:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x00715a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x8000715a;
-valaddr_reg:x9; val_offset:1662*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1662*FLEN/8, x10, x6, x7)
-
-inst_855:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1664*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1664*FLEN/8, x10, x6, x7)
-
-inst_856:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1666*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1666*FLEN/8, x10, x6, x7)
-
-inst_857:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1668*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1668*FLEN/8, x10, x6, x7)
-
-inst_858:// fs1 == 1 and fe1 == 0x81 and fm1 == 0x022004 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc0822004; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1670*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1670*FLEN/8, x10, x6, x7)
-
-inst_859:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x022004 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc0822004;
-valaddr_reg:x9; val_offset:1672*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1672*FLEN/8, x10, x6, x7)
-
-inst_860:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c477d and fs2 == 1 and fe2 == 0x81 and fm2 == 0x022004 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802c477d; op2val:0xc0822004;
-valaddr_reg:x9; val_offset:1674*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1674*FLEN/8, x10, x6, x7)
-
-inst_861:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1676*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1676*FLEN/8, x10, x6, x7)
-
-inst_862:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1678*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1678*FLEN/8, x10, x6, x7)
-
-inst_863:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1680*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1680*FLEN/8, x10, x6, x7)
-
-inst_864:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1682*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1682*FLEN/8, x10, x6, x7)
-
-inst_865:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1684*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1684*FLEN/8, x10, x6, x7)
-
-inst_866:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1686*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1686*FLEN/8, x10, x6, x7)
-
-inst_867:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1688*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1688*FLEN/8, x10, x6, x7)
-
-inst_868:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1690*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1690*FLEN/8, x10, x6, x7)
-
-inst_869:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x14db11 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe14db11; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1692*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1692*FLEN/8, x10, x6, x7)
-
-inst_870:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0xfc and fm2 == 0x14db11 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xfe14db11;
-valaddr_reg:x9; val_offset:1694*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1694*FLEN/8, x10, x6, x7)
-
-inst_871:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1696*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1696*FLEN/8, x10, x6, x7)
-
-inst_872:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x14db11 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe14db11; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1698*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1698*FLEN/8, x10, x6, x7)
-
-inst_873:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1700*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1700*FLEN/8, x10, x6, x7)
-
-inst_874:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1702*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1702*FLEN/8, x10, x6, x7)
-
-inst_875:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1704*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1704*FLEN/8, x10, x6, x7)
-
-inst_876:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1706*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1706*FLEN/8, x10, x6, x7)
-
-inst_877:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0562e7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800562e7; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1708*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1708*FLEN/8, x10, x6, x7)
-
-inst_878:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0562e7 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x800562e7;
-valaddr_reg:x9; val_offset:1710*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1710*FLEN/8, x10, x6, x7)
-
-inst_879:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1712*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1712*FLEN/8, x10, x6, x7)
-
-inst_880:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0089e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800089e3; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1714*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1714*FLEN/8, x10, x6, x7)
-
-inst_881:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0089e3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x800089e3;
-valaddr_reg:x9; val_offset:1716*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1716*FLEN/8, x10, x6, x7)
-
-inst_882:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0089e3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800089e3; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1718*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1718*FLEN/8, x10, x6, x7)
-
-inst_883:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0089e3 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x800089e3;
-valaddr_reg:x9; val_offset:1720*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1720*FLEN/8, x10, x6, x7)
-
-inst_884:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1722*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1722*FLEN/8, x10, x6, x7)
-
-inst_885:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1724*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1724*FLEN/8, x10, x6, x7)
-
-inst_886:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1726*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1726*FLEN/8, x10, x6, x7)
-
-inst_887:// fs1 == 1 and fe1 == 0x81 and fm1 == 0x1e4a63 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc09e4a63; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1728*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1728*FLEN/8, x10, x6, x7)
-
-inst_888:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1e4a63 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc09e4a63;
-valaddr_reg:x9; val_offset:1730*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1730*FLEN/8, x10, x6, x7)
-
-inst_889:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x35dd0d and fs2 == 1 and fe2 == 0x81 and fm2 == 0x1e4a63 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8035dd0d; op2val:0xc09e4a63;
-valaddr_reg:x9; val_offset:1732*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1732*FLEN/8, x10, x6, x7)
-
-inst_890:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1734*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1734*FLEN/8, x10, x6, x7)
-
-inst_891:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1736*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1736*FLEN/8, x10, x6, x7)
-
-inst_892:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x6511ce and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xff6511ce;
-valaddr_reg:x9; val_offset:1738*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1738*FLEN/8, x10, x6, x7)
-
-inst_893:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1740*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1740*FLEN/8, x10, x6, x7)
-
-inst_894:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1742*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1742*FLEN/8, x10, x6, x7)
-
-inst_895:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1744*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1744*FLEN/8, x10, x6, x7)
-
-inst_896:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1746*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1746*FLEN/8, x10, x6, x7)
-
-inst_897:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1748*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1748*FLEN/8, x10, x6, x7)
-
-inst_898:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1750*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1750*FLEN/8, x10, x6, x7)
-
-inst_899:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1752*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1752*FLEN/8, x10, x6, x7)
-
-inst_900:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1754*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1754*FLEN/8, x10, x6, x7)
-
-inst_901:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1756*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1756*FLEN/8, x10, x6, x7)
-
-inst_902:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1758*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1758*FLEN/8, x10, x6, x7)
-
-inst_903:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x374171 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdb74171; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1760*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1760*FLEN/8, x10, x6, x7)
-
-inst_904:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x374171 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xfdb74171;
-valaddr_reg:x9; val_offset:1762*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1762*FLEN/8, x10, x6, x7)
-
-inst_905:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1764*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1764*FLEN/8, x10, x6, x7)
-
-inst_906:// fs1 == 1 and fe1 == 0xfb and fm1 == 0x374171 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfdb74171; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1766*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1766*FLEN/8, x10, x6, x7)
-
-inst_907:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1768*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1768*FLEN/8, x10, x6, x7)
-
-inst_908:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1770*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1770*FLEN/8, x10, x6, x7)
-
-inst_909:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1772*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1772*FLEN/8, x10, x6, x7)
-
-inst_910:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1774*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1774*FLEN/8, x10, x6, x7)
-
-inst_911:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1776*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1776*FLEN/8, x10, x6, x7)
-
-inst_912:// fs1 == 1 and fe1 == 0xfe and fm1 == 0x6511ce and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xff6511ce; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1778*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1778*FLEN/8, x10, x6, x7)
-
-inst_913:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1780*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1780*FLEN/8, x10, x6, x7)
-
-inst_914:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0350c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800350c8; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1782*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1782*FLEN/8, x10, x6, x7)
-
-inst_915:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0350c8 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x800350c8;
-valaddr_reg:x9; val_offset:1784*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1784*FLEN/8, x10, x6, x7)
-
-inst_916:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1786*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1786*FLEN/8, x10, x6, x7)
-
-inst_917:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1788*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1788*FLEN/8, x10, x6, x7)
-
-inst_918:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1790*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1790*FLEN/8, x10, x6, x7)
-
-inst_919:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x253272;
-valaddr_reg:x9; val_offset:1792*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1792*FLEN/8, x10, x6, x7)
-
-inst_920:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x253272;
-valaddr_reg:x9; val_offset:1794*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1794*FLEN/8, x10, x6, x7)
-
-inst_921:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1796*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1796*FLEN/8, x10, x6, x7)
-RVTEST_SIGBASE(x6,signature_x6_7)
-
-inst_922:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1798*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1798*FLEN/8, x10, x6, x7)
-
-inst_923:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1800*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1800*FLEN/8, x10, x6, x7)
-
-inst_924:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1802*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1802*FLEN/8, x10, x6, x7)
-
-inst_925:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1804*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1804*FLEN/8, x10, x6, x7)
-
-inst_926:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1806*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1806*FLEN/8, x10, x6, x7)
-
-inst_927:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1808*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1808*FLEN/8, x10, x6, x7)
-
-inst_928:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1810*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1810*FLEN/8, x10, x6, x7)
-
-inst_929:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1812*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1812*FLEN/8, x10, x6, x7)
-
-inst_930:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1814*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1814*FLEN/8, x10, x6, x7)
-
-inst_931:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1816*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1816*FLEN/8, x10, x6, x7)
-
-inst_932:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0077e4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x800077e4;
-valaddr_reg:x9; val_offset:1818*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1818*FLEN/8, x10, x6, x7)
-
-inst_933:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0077e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2127d2 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800077e4; op2val:0x802127d2;
-valaddr_reg:x9; val_offset:1820*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1820*FLEN/8, x10, x6, x7)
-
-inst_934:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2127d2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802127d2; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1822*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1822*FLEN/8, x10, x6, x7)
-
-inst_935:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1824*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1824*FLEN/8, x10, x6, x7)
-
-inst_936:// fs1 == 1 and fe1 == 0x80 and fm1 == 0x42deee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc042deee; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1826*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1826*FLEN/8, x10, x6, x7)
-
-inst_937:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x42deee and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc042deee;
-valaddr_reg:x9; val_offset:1828*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1828*FLEN/8, x10, x6, x7)
-
-inst_938:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0054e0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x42deee and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800054e0; op2val:0xc042deee;
-valaddr_reg:x9; val_offset:1830*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1830*FLEN/8, x10, x6, x7)
-
-inst_939:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1832*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1832*FLEN/8, x10, x6, x7)
-
-inst_940:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xff7fffff;
-valaddr_reg:x9; val_offset:1834*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1834*FLEN/8, x10, x6, x7)
-
-inst_941:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1836*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1836*FLEN/8, x10, x6, x7)
-
-inst_942:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1838*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1838*FLEN/8, x10, x6, x7)
-
-inst_943:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1840*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1840*FLEN/8, x10, x6, x7)
-
-inst_944:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1842*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1842*FLEN/8, x10, x6, x7)
-
-inst_945:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1844*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1844*FLEN/8, x10, x6, x7)
-
-inst_946:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1846*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1846*FLEN/8, x10, x6, x7)
-
-inst_947:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x016ce1 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe016ce1; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1848*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1848*FLEN/8, x10, x6, x7)
-
-inst_948:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x016ce1 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xfe016ce1;
-valaddr_reg:x9; val_offset:1850*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1850*FLEN/8, x10, x6, x7)
-
-inst_949:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1852*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1852*FLEN/8, x10, x6, x7)
-
-inst_950:// fs1 == 1 and fe1 == 0xfc and fm1 == 0x016ce1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xfe016ce1; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1854*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1854*FLEN/8, x10, x6, x7)
-
-inst_951:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1856*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1856*FLEN/8, x10, x6, x7)
-
-inst_952:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1858*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1858*FLEN/8, x10, x6, x7)
-
-inst_953:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1860*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1860*FLEN/8, x10, x6, x7)
-
-inst_954:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1862*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1862*FLEN/8, x10, x6, x7)
-
-inst_955:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04aeea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x8004aeea; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1864*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1864*FLEN/8, x10, x6, x7)
-
-inst_956:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04aeea and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x8004aeea;
-valaddr_reg:x9; val_offset:1866*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1866*FLEN/8, x10, x6, x7)
-
-inst_957:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1868*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1868*FLEN/8, x10, x6, x7)
-
-inst_958:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0077e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x800077e4; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1870*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1870*FLEN/8, x10, x6, x7)
-
-inst_959:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0077e4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x800077e4;
-valaddr_reg:x9; val_offset:1872*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1872*FLEN/8, x10, x6, x7)
-
-inst_960:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1874*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1874*FLEN/8, x10, x6, x7)
-
-inst_961:// fs1 == 1 and fe1 == 0x81 and fm1 == 0x09a0ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0xc089a0ec; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1876*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1876*FLEN/8, x10, x6, x7)
-
-inst_962:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x09a0ec and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xc089a0ec;
-valaddr_reg:x9; val_offset:1878*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1878*FLEN/8, x10, x6, x7)
-
-inst_963:// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ed524 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x09a0ec and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x802ed524; op2val:0xc089a0ec;
-valaddr_reg:x9; val_offset:1880*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1880*FLEN/8, x10, x6, x7)
-
-inst_964:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7f378efe;
-valaddr_reg:x9; val_offset:1882*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1882*FLEN/8, x10, x6, x7)
-
-inst_965:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7f0;
-valaddr_reg:x9; val_offset:1884*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1884*FLEN/8, x10, x6, x7)
-
-inst_966:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1886*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1886*FLEN/8, x10, x6, x7)
-
-inst_967:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7ee8aebb;
-valaddr_reg:x9; val_offset:1888*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1888*FLEN/8, x10, x6, x7)
-
-inst_968:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7ea5608b;
-valaddr_reg:x9; val_offset:1890*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1890*FLEN/8, x10, x6, x7)
-
-inst_969:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x7f3648af;
-valaddr_reg:x9; val_offset:1892*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1892*FLEN/8, x10, x6, x7)
-
-inst_970:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfd204621;
-valaddr_reg:x9; val_offset:1894*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1894*FLEN/8, x10, x6, x7)
-
-inst_971:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfe4ac669;
-valaddr_reg:x9; val_offset:1896*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1896*FLEN/8, x10, x6, x7)
-
-inst_972:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfe96fcf5;
-valaddr_reg:x9; val_offset:1898*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1898*FLEN/8, x10, x6, x7)
-
-inst_973:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfee8e23e;
-valaddr_reg:x9; val_offset:1900*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1900*FLEN/8, x10, x6, x7)
-
-inst_974:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0xfeaf0937;
-valaddr_reg:x9; val_offset:1902*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1902*FLEN/8, x10, x6, x7)
-
-inst_975:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x39e8a;
-valaddr_reg:x9; val_offset:1904*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1904*FLEN/8, x10, x6, x7)
-
-inst_976:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x2adcdc;
-valaddr_reg:x9; val_offset:1906*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1906*FLEN/8, x10, x6, x7)
-
-inst_977:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x253272 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x253272;
-valaddr_reg:x9; val_offset:1908*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1908*FLEN/8, x10, x6, x7)
-
-inst_978:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2e45d4 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x2e45d4;
-valaddr_reg:x9; val_offset:1910*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1910*FLEN/8, x10, x6, x7)
-
-inst_979:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c787d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x1c787d;
-valaddr_reg:x9; val_offset:1912*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1912*FLEN/8, x10, x6, x7)
-
-inst_980:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3a9174 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x803a9174;
-valaddr_reg:x9; val_offset:1914*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1914*FLEN/8, x10, x6, x7)
-
-inst_981:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c477d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x802c477d;
-valaddr_reg:x9; val_offset:1916*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1916*FLEN/8, x10, x6, x7)
-
-inst_982:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x35dd0d and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x8035dd0d;
-valaddr_reg:x9; val_offset:1918*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1918*FLEN/8, x10, x6, x7)
-
-inst_983:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0054e0 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x800054e0;
-valaddr_reg:x9; val_offset:1920*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1920*FLEN/8, x10, x6, x7)
-
-inst_984:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ed524 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f0; op2val:0x802ed524;
-valaddr_reg:x9; val_offset:1922*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1922*FLEN/8, x10, x6, x7)
-
-inst_985:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x7f206a70;
-valaddr_reg:x9; val_offset:1924*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1924*FLEN/8, x10, x6, x7)
-
-inst_986:// fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and  fcsr == 0  
-/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x1a917b;
-valaddr_reg:x9; val_offset:1926*FLEN/8; correctval:??; testreg:x7;
-fcsr_val: 0*/
-TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x9, 1926*FLEN/8, x10, x6, x7)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(2106775755,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-test_dataset_1:
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(2138705407,32,FLEN)
-NAN_BOXED(2138705407,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(174117,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2437746,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2437746,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(3032532,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(3032532,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(1865853,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2135208886,32,FLEN)
-NAN_BOXED(2135208886,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(1865853,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2151321972,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2151321972,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(17411,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(17411,32,FLEN)
-NAN_BOXED(17411,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(17411,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1075586948,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1075586948,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(1075586948,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2105562406,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(2105562406,32,FLEN)
-NAN_BOXED(2105562406,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2105562406,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2105562406,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2105562406,32,FLEN)
-NAN_BOXED(2105562406,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(152165,32,FLEN)
-NAN_BOXED(2138705407,32,FLEN)
-NAN_BOXED(2138705407,32,FLEN)
-NAN_BOXED(152165,32,FLEN)
-NAN_BOXED(152165,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(152165,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(1521654,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1521654,32,FLEN)
-NAN_BOXED(1521654,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(1521654,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2437746,32,FLEN)
-NAN_BOXED(1521654,32,FLEN)
-NAN_BOXED(2437746,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(3032532,32,FLEN)
-NAN_BOXED(1521654,32,FLEN)
-NAN_BOXED(3032532,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(1865853,32,FLEN)
-NAN_BOXED(1521654,32,FLEN)
-NAN_BOXED(2135208886,32,FLEN)
-NAN_BOXED(2135208886,32,FLEN)
-NAN_BOXED(1521654,32,FLEN)
-NAN_BOXED(1521654,32,FLEN)
-NAN_BOXED(1865853,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2151321972,32,FLEN)
-NAN_BOXED(1521654,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1521654,32,FLEN)
-NAN_BOXED(1521654,32,FLEN)
-NAN_BOXED(2151321972,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(1521654,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(1521654,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(15216,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(15216,32,FLEN)
-NAN_BOXED(15216,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(15216,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(1521654,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1074296694,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1074296694,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(1074296694,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2100962658,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(2100962658,32,FLEN)
-NAN_BOXED(2100962658,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2100962658,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2100962658,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2100962658,32,FLEN)
-NAN_BOXED(2100962658,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(110357,32,FLEN)
-NAN_BOXED(2138705407,32,FLEN)
-NAN_BOXED(2138705407,32,FLEN)
-NAN_BOXED(110357,32,FLEN)
-NAN_BOXED(110357,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(110357,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(1103577,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1103577,32,FLEN)
-NAN_BOXED(1103577,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(1103577,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2437746,32,FLEN)
-NAN_BOXED(1103577,32,FLEN)
-NAN_BOXED(2437746,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(3032532,32,FLEN)
-NAN_BOXED(1103577,32,FLEN)
-NAN_BOXED(3032532,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(1865853,32,FLEN)
-NAN_BOXED(1103577,32,FLEN)
-NAN_BOXED(2135208886,32,FLEN)
-NAN_BOXED(2135208886,32,FLEN)
-NAN_BOXED(1103577,32,FLEN)
-NAN_BOXED(1103577,32,FLEN)
-NAN_BOXED(1865853,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2151321972,32,FLEN)
-NAN_BOXED(1103577,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1103577,32,FLEN)
-NAN_BOXED(1103577,32,FLEN)
-NAN_BOXED(2151321972,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(1103577,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(1103577,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(11035,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(11035,32,FLEN)
-NAN_BOXED(11035,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(11035,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(1103577,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1069937093,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1069937093,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(1069937093,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2097433916,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(4274542506,32,FLEN)
-NAN_BOXED(2097433916,32,FLEN)
-NAN_BOXED(2097433916,32,FLEN)
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-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(4260674800,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(4260674800,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2147773836,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2147773836,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2147512666,32,FLEN)
-NAN_BOXED(2149656530,32,FLEN)
-NAN_BOXED(2149656530,32,FLEN)
-NAN_BOXED(2147512666,32,FLEN)
-NAN_BOXED(2147512666,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2147512666,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3229753348,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3229753348,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(3229753348,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(4262779665,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(4262779665,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(4262779665,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2147836647,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2147836647,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2147518947,32,FLEN)
-NAN_BOXED(2149656530,32,FLEN)
-NAN_BOXED(2149656530,32,FLEN)
-NAN_BOXED(2147518947,32,FLEN)
-NAN_BOXED(2147518947,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2147518947,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3231599203,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3231599203,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(3231599203,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(4256645489,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(4256645489,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(4256645489,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(4284813774,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2147700936,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2147700936,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(2149656530,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2149656530,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2437746,32,FLEN)
-NAN_BOXED(2149656530,32,FLEN)
-NAN_BOXED(2437746,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(3032532,32,FLEN)
-NAN_BOXED(2149656530,32,FLEN)
-NAN_BOXED(3032532,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(1865853,32,FLEN)
-NAN_BOXED(2149656530,32,FLEN)
-NAN_BOXED(1865853,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2151321972,32,FLEN)
-NAN_BOXED(2149656530,32,FLEN)
-NAN_BOXED(2151321972,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2149656530,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2149656530,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2149656530,32,FLEN)
-NAN_BOXED(2147514340,32,FLEN)
-NAN_BOXED(2147514340,32,FLEN)
-NAN_BOXED(2149656530,32,FLEN)
-NAN_BOXED(2149656530,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3225607918,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3225607918,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(3225607918,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(4261506273,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(4261506273,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(4261506273,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2147790570,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2147790570,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2147514340,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2147514340,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3230245100,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3230245100,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(3230245100,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2129178299,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2124767371,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2134263983,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4246750753,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4266313321,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4271308021,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4276675134,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4272884023,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(237194,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2809052,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2437746,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3032532,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1865853,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2151321972,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2150385533,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2151013645,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2147505376,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2150552868,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(2132830832,32,FLEN)
-NAN_BOXED(2134347518,32,FLEN)
-NAN_BOXED(1741179,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 52*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_0:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x6_7:
-    .fill 130*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b1-01.S
deleted file mode 100644
index 8e87c7bbb..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b1-01.S
+++ /dev/null
@@ -1,5889 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:06:24 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmaxm.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmaxm.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fmaxm_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs2 == rd != rs1, rs1==f30, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f31; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f31, rs2==f29, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f31; op2:f29; dest:f30; op1val:0x0; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f30, f31, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 == rs2 == rd, rs1==f28, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f28; op2:f28; dest:f28; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f28, f28, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 == rs2 != rd, rs1==f27, rs2==f27, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f27; op2:f27; dest:f29; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f29, f27, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rd != rs2, rs1==f26, rs2==f30, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f26; op2:f30; dest:f26; op1val:0x0; op2val:0x2;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f26, f26, f30, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f29, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f29; op2:f26; dest:f27; op1val:0x0; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f27, f29, f26, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f23, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f24; op2:f23; dest:f25; op1val:0x0; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f25, f24, f23, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f23, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f23; op2:f25; dest:f24; op1val:0x0; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f24, f23, f25, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f25, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f25; op2:f24; dest:f23; op1val:0x0; op2val:0x800000;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f23, f25, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rs2==f20, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f21; op2:f20; dest:f22; op1val:0x0; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f22, f21, f20, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x800001;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f22, rs2==f21, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f22; op2:f21; dest:f20; op1val:0x0; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f20, f22, f21, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f17, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f18; op2:f17; dest:f19; op1val:0x0; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f19, f18, f17, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f17, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f17; op2:f19; dest:f18; op1val:0x0; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f18, f17, f19, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f19, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f19; op2:f18; dest:f17; op1val:0x0; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f17, f19, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rs2==f14, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f15; op2:f14; dest:f16; op1val:0x0; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f16, f15, f14, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f16, rs2==f15, rd==f14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f16; op2:f15; dest:f14; op1val:0x0; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f14, f16, f15, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f11, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f12; op2:f11; dest:f13; op1val:0x0; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f13, f12, f11, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f11, rs2==f13, rd==f12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f11; op2:f13; dest:f12; op1val:0x0; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f12, f11, f13, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f13, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f13; op2:f12; dest:f11; op1val:0x0; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f11, f13, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rs2==f8, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f9; op2:f8; dest:f10; op1val:0x0; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f10, f9, f8, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f10, rs2==f9, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f10; op2:f9; dest:f8; op1val:0x0; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f8, f10, f9, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f5, rd==f7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f6; op2:f5; dest:f7; op1val:0x80000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f7, f6, f5, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f5, rs2==f7, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f5; op2:f7; dest:f6; op1val:0x80000000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f6, f5, f7, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f7, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f7; op2:f6; dest:f5; op1val:0x80000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f5, f7, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rs2==f2, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f3; op2:f2; dest:f4; op1val:0x80000000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f4, f3, f2, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f2; op2:f4; dest:f3; op1val:0x80000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f4, rs2==f3, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f4; op2:f3; dest:f2; op1val:0x80000000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f2, f4, f3, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f1; op2:f30; dest:f31; op1val:0x80000000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f1, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f0; op2:f30; dest:f31; op1val:0x80000000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f0, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f1; dest:f31; op1val:0x80000000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f1, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f0; dest:f31; op1val:0x80000000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f0, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// rd==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f1; op1val:0x80000000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f1, f31, f30, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// rd==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f0; op1val:0x80000000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f0, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:72*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:74*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:76*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:78*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:80*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:82*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:84*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:86*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:88*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:90*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:92*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:94*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x0;
-   valaddr_reg:x3; val_offset:96*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:98*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x1;
-   valaddr_reg:x3; val_offset:100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x2;
-   valaddr_reg:x3; val_offset:104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x800000;
-   valaddr_reg:x3; val_offset:112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x800001;
-   valaddr_reg:x3; val_offset:116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x0;
-   valaddr_reg:x3; val_offset:192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x1;
-   valaddr_reg:x3; val_offset:196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x2;
-   valaddr_reg:x3; val_offset:200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x800000;
-   valaddr_reg:x3; val_offset:208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x800001;
-   valaddr_reg:x3; val_offset:212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x0;
-   valaddr_reg:x3; val_offset:240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x1;
-   valaddr_reg:x3; val_offset:244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x2;
-   valaddr_reg:x3; val_offset:248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x800000;
-   valaddr_reg:x3; val_offset:256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x800001;
-   valaddr_reg:x3; val_offset:260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x0;
-   valaddr_reg:x3; val_offset:480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x1;
-   valaddr_reg:x3; val_offset:484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x2;
-   valaddr_reg:x3; val_offset:488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x0;
-   valaddr_reg:x3; val_offset:528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x1;
-   valaddr_reg:x3; val_offset:532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x2;
-   valaddr_reg:x3; val_offset:536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x800000;
-   valaddr_reg:x3; val_offset:544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x800001;
-   valaddr_reg:x3; val_offset:548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x0;
-   valaddr_reg:x3; val_offset:768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x1;
-   valaddr_reg:x3; val_offset:772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x2;
-   valaddr_reg:x3; val_offset:776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x0;
-   valaddr_reg:x3; val_offset:816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x1;
-   valaddr_reg:x3; val_offset:820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x2;
-   valaddr_reg:x3; val_offset:824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x0;
-   valaddr_reg:x3; val_offset:864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x1;
-   valaddr_reg:x3; val_offset:868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x2;
-   valaddr_reg:x3; val_offset:872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x0;
-   valaddr_reg:x3; val_offset:912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x1;
-   valaddr_reg:x3; val_offset:916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x2;
-   valaddr_reg:x3; val_offset:920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x800000;
-   valaddr_reg:x3; val_offset:928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x800001;
-   valaddr_reg:x3; val_offset:932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x0;
-   valaddr_reg:x3; val_offset:960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x1;
-   valaddr_reg:x3; val_offset:964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x2;
-   valaddr_reg:x3; val_offset:968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:990*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:992*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:994*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:996*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:998*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1000*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1002*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1004*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1006*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x0;
-   valaddr_reg:x3; val_offset:1008*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:1010*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x1;
-   valaddr_reg:x3; val_offset:1012*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:1014*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x2;
-   valaddr_reg:x3; val_offset:1016*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:1018*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:1020*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:1022*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x800000;
-   valaddr_reg:x3; val_offset:1024*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:1026*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x800001;
-   valaddr_reg:x3; val_offset:1028*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:1030*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1032*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1034*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:1036*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:1038*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:1040*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:1042*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:1044*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:1046*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1048*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1050*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1052*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1054*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1056*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:1058*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1060*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:1062*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1064*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:1066*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:1068*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:1070*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:1072*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:1074*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:1076*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:1078*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1080*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1082*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:1084*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:1086*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:1088*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:1090*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:1092*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:1094*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1096*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1098*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:1106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:1110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:1114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:1116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:1118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:1120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:1122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:1124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:1126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:1132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:1134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:1136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:1138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:1140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:1142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x1;
-   valaddr_reg:x3; val_offset:1152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:1154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
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-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 132*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b19-01.S
deleted file mode 100644
index ebdb51576..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fmaxm_b19-01.S
+++ /dev/null
@@ -1,9704 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:06:24 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmaxm.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fmaxm.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fmaxm_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs2 == rd != rs1, rs1==f30, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f31; dest:f31; op1val:0x7dce622b; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f31, rs2==f29, rd==f30,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f31; op2:f29; dest:f30; op1val:0x7dce622b; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f30, f31, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 == rs2 == rd, rs1==f28, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x183299 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f28; op2:f28; dest:f28; op1val:0x7f7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f28, f28, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1 == rs2 != rd, rs1==f27, rs2==f27, rd==f29,fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f27; op2:f27; dest:f29; op1val:0x7d183299; op2val:0x7d183299;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f29, f27, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 == rd != rs2, rs1==f26, rs2==f30, rd==f26,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f26; op2:f30; dest:f26; op1val:0x7f7fffff; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f26, f26, f30, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f29, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f29; op2:f26; dest:f27; op1val:0x7dce622b; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f27, f29, f26, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f23, rd==f25,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f24; op2:f23; dest:f25; op1val:0x7dce622b; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f25, f24, f23, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f23, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f23; op2:f25; dest:f24; op1val:0x7d902b16; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f24, f23, f25, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f25, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f25; op2:f24; dest:f23; op1val:0x7dce622b; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f23, f25, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rs2==f20, rd==f22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x6a2c24 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f21; op2:f20; dest:f22; op1val:0x7f7fffff; op2val:0x7d6a2c24;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f22, f21, f20, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f20; op2:f22; dest:f21; op1val:0x7d6a2c24; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f22, rs2==f21, rd==f20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f22; op2:f21; dest:f20; op1val:0x7f7fffff; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f20, f22, f21, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f17, rd==f19,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f18; op2:f17; dest:f19; op1val:0x7dce622b; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f19, f18, f17, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f17, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f17; op2:f19; dest:f18; op1val:0x7e2fb07b; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f18, f17, f19, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f19, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f19; op2:f18; dest:f17; op1val:0x7dce622b; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f17, f19, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rs2==f14, rd==f16,fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f15; op2:f14; dest:f16; op1val:0xfdea577e; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f16, f15, f14, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f14; op2:f16; dest:f15; op1val:0x7dce622b; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f16, rs2==f15, rd==f14,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x291dc8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f16; op2:f15; dest:f14; op1val:0x7f7fffff; op2val:0xfd291dc8;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f14, f16, f15, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f11, rd==f13,fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f12; op2:f11; dest:f13; op1val:0xfd291dc8; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f13, f12, f11, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f11, rs2==f13, rd==f12,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f11; op2:f13; dest:f12; op1val:0x7f7fffff; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f12, f11, f13, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f13, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f13; op2:f12; dest:f11; op1val:0x7dce622b; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f11, f13, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rs2==f8, rd==f10,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x153eee and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f9; op2:f8; dest:f10; op1val:0x7f7fffff; op2val:0xfd953eee;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f10, f9, f8, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f8, rs2==f10, rd==f9,fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f8; op2:f10; dest:f9; op1val:0xfd953eee; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f10, rs2==f9, rd==f8,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f10; op2:f9; dest:f8; op1val:0x7f7fffff; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f8, f10, f9, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f5, rd==f7,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f6; op2:f5; dest:f7; op1val:0x7dce622b; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f7, f6, f5, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f5, rs2==f7, rd==f6,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x1946c8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f5; op2:f7; dest:f6; op1val:0x7f7fffff; op2val:0xfd9946c8;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f6, f5, f7, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f7, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f7; op2:f6; dest:f5; op1val:0xfd9946c8; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f5, f7, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rs2==f2, rd==f4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f3; op2:f2; dest:f4; op1val:0x7f7fffff; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f4, f3, f2, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f2; op2:f4; dest:f3; op1val:0x7dce622b; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f4, rs2==f3, rd==f2,fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f4; op2:f3; dest:f2; op1val:0xfd2820df; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f2, f4, f3, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f1,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f1; op2:f30; dest:f31; op1val:0x7dce622b; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f1, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x07167c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f0; op2:f30; dest:f31; op1val:0x255707; op2val:0x7e07167c;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f0, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rs2==f1,fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f1; dest:f31; op1val:0x7e07167c; op2val:0x255707;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f1, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// rs2==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f0; dest:f31; op1val:0x255707; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f0, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// rd==f1,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f1; op1val:0x7dce622b; op2val:0x255707;
-   valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f1, f31, f30, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// rd==f0,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f0; op1val:0x7dce622b; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f0, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x667e2a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x7de67e2a;
-   valaddr_reg:x3; val_offset:72*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x255707;
-   valaddr_reg:x3; val_offset:74*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:76*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:78*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x13d219 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x7e13d219;
-   valaddr_reg:x3; val_offset:80*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x255707;
-   valaddr_reg:x3; val_offset:82*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:84*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:86*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d8cd6 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x7d9d8cd6;
-   valaddr_reg:x3; val_offset:88*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x255707;
-   valaddr_reg:x3; val_offset:90*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:92*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:94*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x1f6f2f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x7e1f6f2f;
-   valaddr_reg:x3; val_offset:96*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x255707;
-   valaddr_reg:x3; val_offset:98*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03c146 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0xfe03c146;
-   valaddr_reg:x3; val_offset:104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x255707;
-   valaddr_reg:x3; val_offset:106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x157915 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0xfd157915;
-   valaddr_reg:x3; val_offset:112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x255707;
-   valaddr_reg:x3; val_offset:114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x48a6ca and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0xfdc8a6ca;
-   valaddr_reg:x3; val_offset:120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x255707;
-   valaddr_reg:x3; val_offset:122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x4500e4 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0xfd4500e4;
-   valaddr_reg:x3; val_offset:128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x255707;
-   valaddr_reg:x3; val_offset:130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2b7553 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0xfe2b7553;
-   valaddr_reg:x3; val_offset:136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x255707;
-   valaddr_reg:x3; val_offset:138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x255707; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x5b76ec and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x405b76ec; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5b76ec and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x405b76ec;
-   valaddr_reg:x3; val_offset:146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x5b76ec and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7dce622b; op2val:0x405b76ec;
-   valaddr_reg:x3; val_offset:148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfa and fm2 == 0x183299 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7d183299;
-   valaddr_reg:x3; val_offset:154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3435dc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0x7f3435dc;
-   valaddr_reg:x3; val_offset:160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 0 and fe2 == 0xfa and fm2 == 0x183299 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0x7d183299;
-   valaddr_reg:x3; val_offset:162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x183299 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7d183299;
-   valaddr_reg:x3; val_offset:178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x522917 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0xfed22917;
-   valaddr_reg:x3; val_offset:196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 0 and fe2 == 0xfa and fm2 == 0x183299 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0x7d183299;
-   valaddr_reg:x3; val_offset:198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0dc4a8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xdc4a8;
-   valaddr_reg:x3; val_offset:206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0dc4a8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0xdc4a8;
-   valaddr_reg:x3; val_offset:210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44f00b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x7f44f00b;
-   valaddr_reg:x3; val_offset:222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0dc4a8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0xdc4a8;
-   valaddr_reg:x3; val_offset:224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0dc4a8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xdc4a8;
-   valaddr_reg:x3; val_offset:236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x3ad75a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0xfebad75a;
-   valaddr_reg:x3; val_offset:242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0dc4a8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0xdc4a8;
-   valaddr_reg:x3; val_offset:244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7ad07d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0xff7ad07d;
-   valaddr_reg:x3; val_offset:250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0dc4a8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0xdc4a8;
-   valaddr_reg:x3; val_offset:252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x76411d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0xfef6411d;
-   valaddr_reg:x3; val_offset:258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0dc4a8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0xdc4a8;
-   valaddr_reg:x3; val_offset:260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0dc4a8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xdc4a8; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x21d824 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3fa1d824; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x21d824 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x3fa1d824;
-   valaddr_reg:x3; val_offset:272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x3e3f3f and fs2 == 0 and fe2 == 0x7f and fm2 == 0x21d824 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ebe3f3f; op2val:0x3fa1d824;
-   valaddr_reg:x3; val_offset:274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3435dc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x7f3435dc;
-   valaddr_reg:x3; val_offset:282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 0 and fe2 == 0xfa and fm2 == 0x6a2c24 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0x7d6a2c24;
-   valaddr_reg:x3; val_offset:286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3435dc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0x7f3435dc;
-   valaddr_reg:x3; val_offset:288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 1 and fe2 == 0xfa and fm2 == 0x291dc8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0xfd291dc8;
-   valaddr_reg:x3; val_offset:302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3435dc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0x7f3435dc;
-   valaddr_reg:x3; val_offset:304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 1 and fe2 == 0xfb and fm2 == 0x153eee and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0xfd953eee;
-   valaddr_reg:x3; val_offset:310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3435dc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0x7f3435dc;
-   valaddr_reg:x3; val_offset:312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 1 and fe2 == 0xfb and fm2 == 0x1946c8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0xfd9946c8;
-   valaddr_reg:x3; val_offset:318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3435dc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0x7f3435dc;
-   valaddr_reg:x3; val_offset:320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x3435dc and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f3435dc; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x07167c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x7e07167c;
-   valaddr_reg:x3; val_offset:330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x667e2a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x7de67e2a;
-   valaddr_reg:x3; val_offset:340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x13d219 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x7e13d219;
-   valaddr_reg:x3; val_offset:348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d8cd6 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x7d9d8cd6;
-   valaddr_reg:x3; val_offset:356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x1f6f2f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x7e1f6f2f;
-   valaddr_reg:x3; val_offset:364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03c146 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0xfe03c146;
-   valaddr_reg:x3; val_offset:372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x157915 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0xfd157915;
-   valaddr_reg:x3; val_offset:380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x48a6ca and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0xfdc8a6ca;
-   valaddr_reg:x3; val_offset:388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x4500e4 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0xfd4500e4;
-   valaddr_reg:x3; val_offset:396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2b7553 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0xfe2b7553;
-   valaddr_reg:x3; val_offset:404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a156b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x1a156b;
-   valaddr_reg:x3; val_offset:406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a156b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1a156b; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x194e59 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40194e59; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x194e59 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40194e59;
-   valaddr_reg:x3; val_offset:414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x194e59 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d902b16; op2val:0x40194e59;
-   valaddr_reg:x3; val_offset:416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfa and fm2 == 0x6a2c24 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7d6a2c24;
-   valaddr_reg:x3; val_offset:422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x6a2c24 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7d6a2c24;
-   valaddr_reg:x3; val_offset:438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x522917 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0xfed22917;
-   valaddr_reg:x3; val_offset:456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 0 and fe2 == 0xfa and fm2 == 0x6a2c24 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0x7d6a2c24;
-   valaddr_reg:x3; val_offset:458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d6a2c24; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x152f10 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x152f10;
-   valaddr_reg:x3; val_offset:466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x152f10 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x152f10;
-   valaddr_reg:x3; val_offset:470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44f00b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x7f44f00b;
-   valaddr_reg:x3; val_offset:482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x152f10 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0x152f10;
-   valaddr_reg:x3; val_offset:484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x152f10 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x152f10;
-   valaddr_reg:x3; val_offset:496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x3ad75a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0xfebad75a;
-   valaddr_reg:x3; val_offset:502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x152f10 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0x152f10;
-   valaddr_reg:x3; val_offset:504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7ad07d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0xff7ad07d;
-   valaddr_reg:x3; val_offset:510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x152f10 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0x152f10;
-   valaddr_reg:x3; val_offset:512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x76411d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0xfef6411d;
-   valaddr_reg:x3; val_offset:518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x152f10 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0x152f10;
-   valaddr_reg:x3; val_offset:520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x152f10 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x152f10; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x7903cc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3ff903cc; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7903cc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x3ff903cc;
-   valaddr_reg:x3; val_offset:532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x125b96 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x7903cc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f125b96; op2val:0x3ff903cc;
-   valaddr_reg:x3; val_offset:534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x07167c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x7e07167c;
-   valaddr_reg:x3; val_offset:560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x667e2a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x7de67e2a;
-   valaddr_reg:x3; val_offset:570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x13d219 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x7e13d219;
-   valaddr_reg:x3; val_offset:578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d8cd6 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x7d9d8cd6;
-   valaddr_reg:x3; val_offset:586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x1f6f2f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x7e1f6f2f;
-   valaddr_reg:x3; val_offset:594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03c146 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0xfe03c146;
-   valaddr_reg:x3; val_offset:602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x157915 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0xfd157915;
-   valaddr_reg:x3; val_offset:610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x48a6ca and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0xfdc8a6ca;
-   valaddr_reg:x3; val_offset:618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x4500e4 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0xfd4500e4;
-   valaddr_reg:x3; val_offset:626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2b7553 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0xfe2b7553;
-   valaddr_reg:x3; val_offset:634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3f92c0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x3f92c0;
-   valaddr_reg:x3; val_offset:636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3f92c0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f92c0; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x3ad332 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40bad332; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3ad332 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40bad332;
-   valaddr_reg:x3; val_offset:644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0x81 and fm2 == 0x3ad332 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e2fb07b; op2val:0x40bad332;
-   valaddr_reg:x3; val_offset:646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x291dc8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfd291dc8;
-   valaddr_reg:x3; val_offset:662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x153eee and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfd953eee;
-   valaddr_reg:x3; val_offset:670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x1946c8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfd9946c8;
-   valaddr_reg:x3; val_offset:678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x07167c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x7e07167c;
-   valaddr_reg:x3; val_offset:690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x667e2a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x7de67e2a;
-   valaddr_reg:x3; val_offset:700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x13d219 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x7e13d219;
-   valaddr_reg:x3; val_offset:708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d8cd6 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x7d9d8cd6;
-   valaddr_reg:x3; val_offset:716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x1f6f2f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x7e1f6f2f;
-   valaddr_reg:x3; val_offset:724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03c146 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0xfe03c146;
-   valaddr_reg:x3; val_offset:732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x157915 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0xfd157915;
-   valaddr_reg:x3; val_offset:740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x48a6ca and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0xfdc8a6ca;
-   valaddr_reg:x3; val_offset:748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x4500e4 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0xfd4500e4;
-   valaddr_reg:x3; val_offset:756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2b7553 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0xfe2b7553;
-   valaddr_reg:x3; val_offset:764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2a65f8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x802a65f8;
-   valaddr_reg:x3; val_offset:766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2a65f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802a65f8; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 1 and fe1 == 0x80 and fm1 == 0x7931e5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc07931e5; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x7931e5 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc07931e5;
-   valaddr_reg:x3; val_offset:774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 1 and fe2 == 0x80 and fm2 == 0x7931e5 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdea577e; op2val:0xc07931e5;
-   valaddr_reg:x3; val_offset:776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0xfa and fm2 == 0x291dc8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0xfd291dc8;
-   valaddr_reg:x3; val_offset:782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x522917 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0xfed22917;
-   valaddr_reg:x3; val_offset:808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x291dc8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0xfd291dc8;
-   valaddr_reg:x3; val_offset:810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd291dc8; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f4c77 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x800f4c77;
-   valaddr_reg:x3; val_offset:818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f4c77 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x800f4c77;
-   valaddr_reg:x3; val_offset:822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44f00b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x7f44f00b;
-   valaddr_reg:x3; val_offset:834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f4c77 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0x800f4c77;
-   valaddr_reg:x3; val_offset:836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f4c77 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x800f4c77;
-   valaddr_reg:x3; val_offset:848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x3ad75a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0xfebad75a;
-   valaddr_reg:x3; val_offset:854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f4c77 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0x800f4c77;
-   valaddr_reg:x3; val_offset:856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7ad07d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0xff7ad07d;
-   valaddr_reg:x3; val_offset:862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f4c77 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0x800f4c77;
-   valaddr_reg:x3; val_offset:864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x76411d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0xfef6411d;
-   valaddr_reg:x3; val_offset:870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f4c77 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0x800f4c77;
-   valaddr_reg:x3; val_offset:872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f4c77 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f4c77; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x33d5d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbfb3d5d8; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x33d5d8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xbfb3d5d8;
-   valaddr_reg:x3; val_offset:884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x53653a and fs2 == 1 and fe2 == 0x7f and fm2 == 0x33d5d8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed3653a; op2val:0xbfb3d5d8;
-   valaddr_reg:x3; val_offset:886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x153eee and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0xfd953eee;
-   valaddr_reg:x3; val_offset:892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 1 and fe2 == 0xfd and fm2 == 0x522917 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0xfed22917;
-   valaddr_reg:x3; val_offset:914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x153eee and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0xfd953eee;
-   valaddr_reg:x3; val_offset:916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd953eee; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0098 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x801b0098;
-   valaddr_reg:x3; val_offset:924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0098 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x801b0098;
-   valaddr_reg:x3; val_offset:928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44f00b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x7f44f00b;
-   valaddr_reg:x3; val_offset:940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0098 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0x801b0098;
-   valaddr_reg:x3; val_offset:942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0098 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x801b0098;
-   valaddr_reg:x3; val_offset:954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x3ad75a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0xfebad75a;
-   valaddr_reg:x3; val_offset:960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0098 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0x801b0098;
-   valaddr_reg:x3; val_offset:962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7ad07d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0xff7ad07d;
-   valaddr_reg:x3; val_offset:968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0098 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0x801b0098;
-   valaddr_reg:x3; val_offset:970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x76411d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0xfef6411d;
-   valaddr_reg:x3; val_offset:976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1b0098 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0x801b0098;
-   valaddr_reg:x3; val_offset:978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1b0098 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801b0098; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 1 and fe1 == 0x80 and fm1 == 0x1eb493 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc01eb493; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x1eb493 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc01eb493;
-   valaddr_reg:x3; val_offset:990*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3a8ea9 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x1eb493 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3a8ea9; op2val:0xc01eb493;
-   valaddr_reg:x3; val_offset:992*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:994*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:996*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x1946c8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0xfd9946c8;
-   valaddr_reg:x3; val_offset:998*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1000*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1002*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1004*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1006*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1008*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1010*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1012*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1014*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x522917 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0xfed22917;
-   valaddr_reg:x3; val_offset:1016*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x1946c8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0xfd9946c8;
-   valaddr_reg:x3; val_offset:1018*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd9946c8; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1020*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1022*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1024*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1bbb48 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x801bbb48;
-   valaddr_reg:x3; val_offset:1026*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1028*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1bbb48 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x801bbb48;
-   valaddr_reg:x3; val_offset:1030*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1032*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1034*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1036*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1038*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1040*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44f00b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x7f44f00b;
-   valaddr_reg:x3; val_offset:1042*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1bbb48 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0x801bbb48;
-   valaddr_reg:x3; val_offset:1044*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1046*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1048*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1050*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1052*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1054*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1bbb48 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x801bbb48;
-   valaddr_reg:x3; val_offset:1056*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1058*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1060*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x3ad75a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0xfebad75a;
-   valaddr_reg:x3; val_offset:1062*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1bbb48 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0x801bbb48;
-   valaddr_reg:x3; val_offset:1064*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1066*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1068*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7ad07d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0xff7ad07d;
-   valaddr_reg:x3; val_offset:1070*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1bbb48 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0x801bbb48;
-   valaddr_reg:x3; val_offset:1072*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1074*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1076*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x76411d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0xfef6411d;
-   valaddr_reg:x3; val_offset:1078*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1bbb48 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0x801bbb48;
-   valaddr_reg:x3; val_offset:1080*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1082*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1084*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1bbb48 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801bbb48; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1086*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1088*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 1 and fe1 == 0x80 and fm1 == 0x22fdd5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc022fdd5; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1090*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x22fdd5 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc022fdd5;
-   valaddr_reg:x3; val_offset:1092*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x3f987b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x22fdd5 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff3f987b; op2val:0xc022fdd5;
-   valaddr_reg:x3; val_offset:1094*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1096*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1098*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0xfd and fm2 == 0x522917 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0xfed22917;
-   valaddr_reg:x3; val_offset:1102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x522917 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfed22917; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x07167c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x7e07167c;
-   valaddr_reg:x3; val_offset:1122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x667e2a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x7de67e2a;
-   valaddr_reg:x3; val_offset:1132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x13d219 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x7e13d219;
-   valaddr_reg:x3; val_offset:1140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d8cd6 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x7d9d8cd6;
-   valaddr_reg:x3; val_offset:1148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-
-inst_578:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x1f6f2f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x7e1f6f2f;
-   valaddr_reg:x3; val_offset:1156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1156*FLEN/8, x4, x1, x2)
-
-inst_579:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1158*FLEN/8, x4, x1, x2)
-
-inst_580:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1160*FLEN/8, x4, x1, x2)
-
-inst_581:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1162*FLEN/8, x4, x1, x2)
-
-inst_582:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03c146 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0xfe03c146;
-   valaddr_reg:x3; val_offset:1164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1164*FLEN/8, x4, x1, x2)
-
-inst_583:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1166*FLEN/8, x4, x1, x2)
-
-inst_584:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1168*FLEN/8, x4, x1, x2)
-
-inst_585:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1170*FLEN/8, x4, x1, x2)
-
-inst_586:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x157915 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0xfd157915;
-   valaddr_reg:x3; val_offset:1172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1172*FLEN/8, x4, x1, x2)
-
-inst_587:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1174*FLEN/8, x4, x1, x2)
-
-inst_588:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1176*FLEN/8, x4, x1, x2)
-
-inst_589:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1178*FLEN/8, x4, x1, x2)
-
-inst_590:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x48a6ca and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0xfdc8a6ca;
-   valaddr_reg:x3; val_offset:1180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1180*FLEN/8, x4, x1, x2)
-
-inst_591:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1182*FLEN/8, x4, x1, x2)
-
-inst_592:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1184*FLEN/8, x4, x1, x2)
-
-inst_593:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1186*FLEN/8, x4, x1, x2)
-
-inst_594:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x4500e4 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0xfd4500e4;
-   valaddr_reg:x3; val_offset:1188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1188*FLEN/8, x4, x1, x2)
-
-inst_595:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1190*FLEN/8, x4, x1, x2)
-
-inst_596:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1192*FLEN/8, x4, x1, x2)
-
-inst_597:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1194*FLEN/8, x4, x1, x2)
-
-inst_598:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2b7553 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0xfe2b7553;
-   valaddr_reg:x3; val_offset:1196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1196*FLEN/8, x4, x1, x2)
-
-inst_599:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0f3596 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x800f3596;
-   valaddr_reg:x3; val_offset:1198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1198*FLEN/8, x4, x1, x2)
-
-inst_600:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0f3596 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800f3596; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1200*FLEN/8, x4, x1, x2)
-
-inst_601:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1202*FLEN/8, x4, x1, x2)
-
-inst_602:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x32c8e8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbfb2c8e8; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1204*FLEN/8, x4, x1, x2)
-
-inst_603:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x32c8e8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xbfb2c8e8;
-   valaddr_reg:x3; val_offset:1206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1206*FLEN/8, x4, x1, x2)
-
-inst_604:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 1 and fe2 == 0x7f and fm2 == 0x32c8e8 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd2820df; op2val:0xbfb2c8e8;
-   valaddr_reg:x3; val_offset:1208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1208*FLEN/8, x4, x1, x2)
-
-inst_605:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1210*FLEN/8, x4, x1, x2)
-
-inst_606:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1212*FLEN/8, x4, x1, x2)
-
-inst_607:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0xfc and fm2 == 0x07167c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7e07167c;
-   valaddr_reg:x3; val_offset:1214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1214*FLEN/8, x4, x1, x2)
-
-inst_608:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1216*FLEN/8, x4, x1, x2)
-
-inst_609:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1218*FLEN/8, x4, x1, x2)
-
-inst_610:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1220*FLEN/8, x4, x1, x2)
-
-inst_611:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1222*FLEN/8, x4, x1, x2)
-
-inst_612:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1224*FLEN/8, x4, x1, x2)
-
-inst_613:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1226*FLEN/8, x4, x1, x2)
-
-inst_614:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1228*FLEN/8, x4, x1, x2)
-
-inst_615:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1230*FLEN/8, x4, x1, x2)
-
-inst_616:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1232*FLEN/8, x4, x1, x2)
-
-inst_617:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1234*FLEN/8, x4, x1, x2)
-
-inst_618:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1236*FLEN/8, x4, x1, x2)
-
-inst_619:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1238*FLEN/8, x4, x1, x2)
-
-inst_620:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1240*FLEN/8, x4, x1, x2)
-
-inst_621:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1242*FLEN/8, x4, x1, x2)
-
-inst_622:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e07167c; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1244*FLEN/8, x4, x1, x2)
-
-inst_623:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1246*FLEN/8, x4, x1, x2)
-
-inst_624:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1248*FLEN/8, x4, x1, x2)
-
-inst_625:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1250*FLEN/8, x4, x1, x2)
-
-inst_626:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1252*FLEN/8, x4, x1, x2)
-
-inst_627:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1254*FLEN/8, x4, x1, x2)
-
-inst_628:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1256*FLEN/8, x4, x1, x2)
-
-inst_629:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1258*FLEN/8, x4, x1, x2)
-
-inst_630:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1260*FLEN/8, x4, x1, x2)
-
-inst_631:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1262*FLEN/8, x4, x1, x2)
-
-inst_632:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1264*FLEN/8, x4, x1, x2)
-
-inst_633:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1266*FLEN/8, x4, x1, x2)
-
-inst_634:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1268*FLEN/8, x4, x1, x2)
-
-inst_635:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1270*FLEN/8, x4, x1, x2)
-
-inst_636:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1272*FLEN/8, x4, x1, x2)
-
-inst_637:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1274*FLEN/8, x4, x1, x2)
-
-inst_638:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1276*FLEN/8, x4, x1, x2)
-
-inst_639:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1278*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_6)
-
-inst_640:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1280*FLEN/8, x4, x1, x2)
-
-inst_641:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1282*FLEN/8, x4, x1, x2)
-
-inst_642:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x0fa668 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x408fa668; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1284*FLEN/8, x4, x1, x2)
-
-inst_643:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0fa668 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x408fa668;
-   valaddr_reg:x3; val_offset:1286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1286*FLEN/8, x4, x1, x2)
-
-inst_644:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x30e1ae and fs2 == 0 and fe2 == 0x81 and fm2 == 0x0fa668 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x30e1ae; op2val:0x408fa668;
-   valaddr_reg:x3; val_offset:1288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1288*FLEN/8, x4, x1, x2)
-
-inst_645:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1290*FLEN/8, x4, x1, x2)
-
-inst_646:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1292*FLEN/8, x4, x1, x2)
-
-inst_647:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x667e2a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7de67e2a;
-   valaddr_reg:x3; val_offset:1294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1294*FLEN/8, x4, x1, x2)
-
-inst_648:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1296*FLEN/8, x4, x1, x2)
-
-inst_649:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1298*FLEN/8, x4, x1, x2)
-
-inst_650:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1300*FLEN/8, x4, x1, x2)
-
-inst_651:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1302*FLEN/8, x4, x1, x2)
-
-inst_652:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1304*FLEN/8, x4, x1, x2)
-
-inst_653:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1306*FLEN/8, x4, x1, x2)
-
-inst_654:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1308*FLEN/8, x4, x1, x2)
-
-inst_655:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1310*FLEN/8, x4, x1, x2)
-
-inst_656:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1312*FLEN/8, x4, x1, x2)
-
-inst_657:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1314*FLEN/8, x4, x1, x2)
-
-inst_658:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1316*FLEN/8, x4, x1, x2)
-
-inst_659:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1318*FLEN/8, x4, x1, x2)
-
-inst_660:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1320*FLEN/8, x4, x1, x2)
-
-inst_661:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1322*FLEN/8, x4, x1, x2)
-
-inst_662:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x667e2a and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7de67e2a; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1324*FLEN/8, x4, x1, x2)
-
-inst_663:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1326*FLEN/8, x4, x1, x2)
-
-inst_664:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1328*FLEN/8, x4, x1, x2)
-
-inst_665:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1330*FLEN/8, x4, x1, x2)
-
-inst_666:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1332*FLEN/8, x4, x1, x2)
-
-inst_667:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1334*FLEN/8, x4, x1, x2)
-
-inst_668:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1336*FLEN/8, x4, x1, x2)
-
-inst_669:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1338*FLEN/8, x4, x1, x2)
-
-inst_670:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1340*FLEN/8, x4, x1, x2)
-
-inst_671:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1342*FLEN/8, x4, x1, x2)
-
-inst_672:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1344*FLEN/8, x4, x1, x2)
-
-inst_673:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1346*FLEN/8, x4, x1, x2)
-
-inst_674:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1348*FLEN/8, x4, x1, x2)
-
-inst_675:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1350*FLEN/8, x4, x1, x2)
-
-inst_676:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1352*FLEN/8, x4, x1, x2)
-
-inst_677:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1354*FLEN/8, x4, x1, x2)
-
-inst_678:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1356*FLEN/8, x4, x1, x2)
-
-inst_679:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1358*FLEN/8, x4, x1, x2)
-
-inst_680:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x751a1e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40751a1e; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1360*FLEN/8, x4, x1, x2)
-
-inst_681:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x751a1e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40751a1e;
-   valaddr_reg:x3; val_offset:1362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1362*FLEN/8, x4, x1, x2)
-
-inst_682:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x29b3b2 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x751a1e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x29b3b2; op2val:0x40751a1e;
-   valaddr_reg:x3; val_offset:1364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1364*FLEN/8, x4, x1, x2)
-
-inst_683:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1366*FLEN/8, x4, x1, x2)
-
-inst_684:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1368*FLEN/8, x4, x1, x2)
-
-inst_685:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x13d219 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7e13d219;
-   valaddr_reg:x3; val_offset:1370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1370*FLEN/8, x4, x1, x2)
-
-inst_686:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1372*FLEN/8, x4, x1, x2)
-
-inst_687:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1374*FLEN/8, x4, x1, x2)
-
-inst_688:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1376*FLEN/8, x4, x1, x2)
-
-inst_689:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1378*FLEN/8, x4, x1, x2)
-
-inst_690:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1380*FLEN/8, x4, x1, x2)
-
-inst_691:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1382*FLEN/8, x4, x1, x2)
-
-inst_692:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1384*FLEN/8, x4, x1, x2)
-
-inst_693:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1386*FLEN/8, x4, x1, x2)
-
-inst_694:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1388*FLEN/8, x4, x1, x2)
-
-inst_695:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1390*FLEN/8, x4, x1, x2)
-
-inst_696:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1392*FLEN/8, x4, x1, x2)
-
-inst_697:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1394*FLEN/8, x4, x1, x2)
-
-inst_698:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1396*FLEN/8, x4, x1, x2)
-
-inst_699:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1398*FLEN/8, x4, x1, x2)
-
-inst_700:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x13d219 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e13d219; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1400*FLEN/8, x4, x1, x2)
-
-inst_701:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1402*FLEN/8, x4, x1, x2)
-
-inst_702:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1404*FLEN/8, x4, x1, x2)
-
-inst_703:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1406*FLEN/8, x4, x1, x2)
-
-inst_704:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1408*FLEN/8, x4, x1, x2)
-
-inst_705:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1410*FLEN/8, x4, x1, x2)
-
-inst_706:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1412*FLEN/8, x4, x1, x2)
-
-inst_707:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1414*FLEN/8, x4, x1, x2)
-
-inst_708:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1416*FLEN/8, x4, x1, x2)
-
-inst_709:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1418*FLEN/8, x4, x1, x2)
-
-inst_710:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1420*FLEN/8, x4, x1, x2)
-
-inst_711:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1422*FLEN/8, x4, x1, x2)
-
-inst_712:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1424*FLEN/8, x4, x1, x2)
-
-inst_713:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1426*FLEN/8, x4, x1, x2)
-
-inst_714:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1428*FLEN/8, x4, x1, x2)
-
-inst_715:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1430*FLEN/8, x4, x1, x2)
-
-inst_716:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x1d309f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x409d309f; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1432*FLEN/8, x4, x1, x2)
-
-inst_717:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x1d309f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x409d309f;
-   valaddr_reg:x3; val_offset:1434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1434*FLEN/8, x4, x1, x2)
-
-inst_718:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x357d2c and fs2 == 0 and fe2 == 0x81 and fm2 == 0x1d309f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x357d2c; op2val:0x409d309f;
-   valaddr_reg:x3; val_offset:1436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1436*FLEN/8, x4, x1, x2)
-
-inst_719:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1438*FLEN/8, x4, x1, x2)
-
-inst_720:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1440*FLEN/8, x4, x1, x2)
-
-inst_721:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x1d8cd6 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7d9d8cd6;
-   valaddr_reg:x3; val_offset:1442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1442*FLEN/8, x4, x1, x2)
-
-inst_722:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1444*FLEN/8, x4, x1, x2)
-
-inst_723:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1446*FLEN/8, x4, x1, x2)
-
-inst_724:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1448*FLEN/8, x4, x1, x2)
-
-inst_725:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x44f00b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7f44f00b;
-   valaddr_reg:x3; val_offset:1450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1450*FLEN/8, x4, x1, x2)
-
-inst_726:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1452*FLEN/8, x4, x1, x2)
-
-inst_727:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1454*FLEN/8, x4, x1, x2)
-
-inst_728:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1456*FLEN/8, x4, x1, x2)
-
-inst_729:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1458*FLEN/8, x4, x1, x2)
-
-inst_730:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1460*FLEN/8, x4, x1, x2)
-
-inst_731:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1462*FLEN/8, x4, x1, x2)
-
-inst_732:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1464*FLEN/8, x4, x1, x2)
-
-inst_733:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1466*FLEN/8, x4, x1, x2)
-
-inst_734:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1468*FLEN/8, x4, x1, x2)
-
-inst_735:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1470*FLEN/8, x4, x1, x2)
-
-inst_736:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1472*FLEN/8, x4, x1, x2)
-
-inst_737:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1474*FLEN/8, x4, x1, x2)
-
-inst_738:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1476*FLEN/8, x4, x1, x2)
-
-inst_739:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x44f00b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f44f00b; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1478*FLEN/8, x4, x1, x2)
-
-inst_740:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1480*FLEN/8, x4, x1, x2)
-
-inst_741:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x1d8cd6 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d9d8cd6; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1482*FLEN/8, x4, x1, x2)
-
-inst_742:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1484*FLEN/8, x4, x1, x2)
-
-inst_743:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1486*FLEN/8, x4, x1, x2)
-
-inst_744:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1488*FLEN/8, x4, x1, x2)
-
-inst_745:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1490*FLEN/8, x4, x1, x2)
-
-inst_746:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1492*FLEN/8, x4, x1, x2)
-
-inst_747:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1494*FLEN/8, x4, x1, x2)
-
-inst_748:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1496*FLEN/8, x4, x1, x2)
-
-inst_749:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1498*FLEN/8, x4, x1, x2)
-
-inst_750:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1500*FLEN/8, x4, x1, x2)
-
-inst_751:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1502*FLEN/8, x4, x1, x2)
-
-inst_752:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1504*FLEN/8, x4, x1, x2)
-
-inst_753:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1506*FLEN/8, x4, x1, x2)
-
-inst_754:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1508*FLEN/8, x4, x1, x2)
-
-inst_755:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x27893a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4027893a; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1510*FLEN/8, x4, x1, x2)
-
-inst_756:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27893a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x4027893a;
-   valaddr_reg:x3; val_offset:1512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1512*FLEN/8, x4, x1, x2)
-
-inst_757:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1c8139 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x27893a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1c8139; op2val:0x4027893a;
-   valaddr_reg:x3; val_offset:1514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1514*FLEN/8, x4, x1, x2)
-
-inst_758:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1516*FLEN/8, x4, x1, x2)
-
-inst_759:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1518*FLEN/8, x4, x1, x2)
-
-inst_760:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0xfc and fm2 == 0x1f6f2f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7e1f6f2f;
-   valaddr_reg:x3; val_offset:1520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1520*FLEN/8, x4, x1, x2)
-
-inst_761:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1522*FLEN/8, x4, x1, x2)
-
-inst_762:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1524*FLEN/8, x4, x1, x2)
-
-inst_763:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1526*FLEN/8, x4, x1, x2)
-
-inst_764:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1528*FLEN/8, x4, x1, x2)
-
-inst_765:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1530*FLEN/8, x4, x1, x2)
-
-inst_766:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1532*FLEN/8, x4, x1, x2)
-
-inst_767:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1534*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_7)
-
-inst_768:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1536*FLEN/8, x4, x1, x2)
-
-inst_769:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1538*FLEN/8, x4, x1, x2)
-
-inst_770:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1540*FLEN/8, x4, x1, x2)
-
-inst_771:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1542*FLEN/8, x4, x1, x2)
-
-inst_772:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1544*FLEN/8, x4, x1, x2)
-
-inst_773:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1546*FLEN/8, x4, x1, x2)
-
-inst_774:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1548*FLEN/8, x4, x1, x2)
-
-inst_775:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x1f6f2f and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e1f6f2f; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1550*FLEN/8, x4, x1, x2)
-
-inst_776:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1552*FLEN/8, x4, x1, x2)
-
-inst_777:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1554*FLEN/8, x4, x1, x2)
-
-inst_778:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1556*FLEN/8, x4, x1, x2)
-
-inst_779:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1558*FLEN/8, x4, x1, x2)
-
-inst_780:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1560*FLEN/8, x4, x1, x2)
-
-inst_781:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1562*FLEN/8, x4, x1, x2)
-
-inst_782:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1564*FLEN/8, x4, x1, x2)
-
-inst_783:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1566*FLEN/8, x4, x1, x2)
-
-inst_784:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1568*FLEN/8, x4, x1, x2)
-
-inst_785:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1570*FLEN/8, x4, x1, x2)
-
-inst_786:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1572*FLEN/8, x4, x1, x2)
-
-inst_787:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x298a26 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40a98a26; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1574*FLEN/8, x4, x1, x2)
-
-inst_788:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x298a26 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40a98a26;
-   valaddr_reg:x3; val_offset:1576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1576*FLEN/8, x4, x1, x2)
-
-inst_789:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x39b0fc and fs2 == 0 and fe2 == 0x81 and fm2 == 0x298a26 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x39b0fc; op2val:0x40a98a26;
-   valaddr_reg:x3; val_offset:1578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1578*FLEN/8, x4, x1, x2)
-
-inst_790:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1580*FLEN/8, x4, x1, x2)
-
-inst_791:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1582*FLEN/8, x4, x1, x2)
-
-inst_792:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03c146 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xfe03c146;
-   valaddr_reg:x3; val_offset:1584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1584*FLEN/8, x4, x1, x2)
-
-inst_793:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1586*FLEN/8, x4, x1, x2)
-
-inst_794:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1588*FLEN/8, x4, x1, x2)
-
-inst_795:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1590*FLEN/8, x4, x1, x2)
-
-inst_796:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1592*FLEN/8, x4, x1, x2)
-
-inst_797:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1594*FLEN/8, x4, x1, x2)
-
-inst_798:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1596*FLEN/8, x4, x1, x2)
-
-inst_799:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1598*FLEN/8, x4, x1, x2)
-
-inst_800:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1600*FLEN/8, x4, x1, x2)
-
-inst_801:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1602*FLEN/8, x4, x1, x2)
-
-inst_802:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1604*FLEN/8, x4, x1, x2)
-
-inst_803:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1606*FLEN/8, x4, x1, x2)
-
-inst_804:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1608*FLEN/8, x4, x1, x2)
-
-inst_805:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1610*FLEN/8, x4, x1, x2)
-
-inst_806:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1612*FLEN/8, x4, x1, x2)
-
-inst_807:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03c146 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03c146; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1614*FLEN/8, x4, x1, x2)
-
-inst_808:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1616*FLEN/8, x4, x1, x2)
-
-inst_809:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1618*FLEN/8, x4, x1, x2)
-
-inst_810:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1620*FLEN/8, x4, x1, x2)
-
-inst_811:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1622*FLEN/8, x4, x1, x2)
-
-inst_812:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1624*FLEN/8, x4, x1, x2)
-
-inst_813:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1626*FLEN/8, x4, x1, x2)
-
-inst_814:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1628*FLEN/8, x4, x1, x2)
-
-inst_815:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1630*FLEN/8, x4, x1, x2)
-
-inst_816:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1632*FLEN/8, x4, x1, x2)
-
-inst_817:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x0c1b1e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc08c1b1e; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1634*FLEN/8, x4, x1, x2)
-
-inst_818:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0c1b1e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc08c1b1e;
-   valaddr_reg:x3; val_offset:1636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1636*FLEN/8, x4, x1, x2)
-
-inst_819:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2facf2 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0c1b1e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802facf2; op2val:0xc08c1b1e;
-   valaddr_reg:x3; val_offset:1638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1638*FLEN/8, x4, x1, x2)
-
-inst_820:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1640*FLEN/8, x4, x1, x2)
-
-inst_821:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1642*FLEN/8, x4, x1, x2)
-
-inst_822:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x157915 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xfd157915;
-   valaddr_reg:x3; val_offset:1644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1644*FLEN/8, x4, x1, x2)
-
-inst_823:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1646*FLEN/8, x4, x1, x2)
-
-inst_824:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1648*FLEN/8, x4, x1, x2)
-
-inst_825:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1650*FLEN/8, x4, x1, x2)
-
-inst_826:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x3ad75a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xfebad75a;
-   valaddr_reg:x3; val_offset:1652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1652*FLEN/8, x4, x1, x2)
-
-inst_827:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1654*FLEN/8, x4, x1, x2)
-
-inst_828:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1656*FLEN/8, x4, x1, x2)
-
-inst_829:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1658*FLEN/8, x4, x1, x2)
-
-inst_830:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1660*FLEN/8, x4, x1, x2)
-
-inst_831:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1662*FLEN/8, x4, x1, x2)
-
-inst_832:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1664*FLEN/8, x4, x1, x2)
-
-inst_833:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1666*FLEN/8, x4, x1, x2)
-
-inst_834:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1668*FLEN/8, x4, x1, x2)
-
-inst_835:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1670*FLEN/8, x4, x1, x2)
-
-inst_836:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1672*FLEN/8, x4, x1, x2)
-
-inst_837:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1674*FLEN/8, x4, x1, x2)
-
-inst_838:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1676*FLEN/8, x4, x1, x2)
-
-inst_839:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1678*FLEN/8, x4, x1, x2)
-
-inst_840:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x3ad75a and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfebad75a; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1680*FLEN/8, x4, x1, x2)
-
-inst_841:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1682*FLEN/8, x4, x1, x2)
-
-inst_842:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x157915 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd157915; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1684*FLEN/8, x4, x1, x2)
-
-inst_843:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1686*FLEN/8, x4, x1, x2)
-
-inst_844:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1688*FLEN/8, x4, x1, x2)
-
-inst_845:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1690*FLEN/8, x4, x1, x2)
-
-inst_846:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1692*FLEN/8, x4, x1, x2)
-
-inst_847:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1694*FLEN/8, x4, x1, x2)
-
-inst_848:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1696*FLEN/8, x4, x1, x2)
-
-inst_849:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1698*FLEN/8, x4, x1, x2)
-
-inst_850:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x1ef26a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf9ef26a; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1700*FLEN/8, x4, x1, x2)
-
-inst_851:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x1ef26a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xbf9ef26a;
-   valaddr_reg:x3; val_offset:1702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1702*FLEN/8, x4, x1, x2)
-
-inst_852:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0d858e and fs2 == 1 and fe2 == 0x7f and fm2 == 0x1ef26a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800d858e; op2val:0xbf9ef26a;
-   valaddr_reg:x3; val_offset:1704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1704*FLEN/8, x4, x1, x2)
-
-inst_853:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1706*FLEN/8, x4, x1, x2)
-
-inst_854:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1708*FLEN/8, x4, x1, x2)
-
-inst_855:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x48a6ca and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xfdc8a6ca;
-   valaddr_reg:x3; val_offset:1710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1710*FLEN/8, x4, x1, x2)
-
-inst_856:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1712*FLEN/8, x4, x1, x2)
-
-inst_857:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1714*FLEN/8, x4, x1, x2)
-
-inst_858:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1716*FLEN/8, x4, x1, x2)
-
-inst_859:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7ad07d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xff7ad07d;
-   valaddr_reg:x3; val_offset:1718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1718*FLEN/8, x4, x1, x2)
-
-inst_860:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1720*FLEN/8, x4, x1, x2)
-
-inst_861:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1722*FLEN/8, x4, x1, x2)
-
-inst_862:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1724*FLEN/8, x4, x1, x2)
-
-inst_863:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1726*FLEN/8, x4, x1, x2)
-
-inst_864:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1728*FLEN/8, x4, x1, x2)
-
-inst_865:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1730*FLEN/8, x4, x1, x2)
-
-inst_866:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1732*FLEN/8, x4, x1, x2)
-
-inst_867:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1734*FLEN/8, x4, x1, x2)
-
-inst_868:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1736*FLEN/8, x4, x1, x2)
-
-inst_869:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1738*FLEN/8, x4, x1, x2)
-
-inst_870:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1740*FLEN/8, x4, x1, x2)
-
-inst_871:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1742*FLEN/8, x4, x1, x2)
-
-inst_872:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1744*FLEN/8, x4, x1, x2)
-
-inst_873:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7ad07d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7ad07d; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1746*FLEN/8, x4, x1, x2)
-
-inst_874:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1748*FLEN/8, x4, x1, x2)
-
-inst_875:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x48a6ca and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdc8a6ca; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1750*FLEN/8, x4, x1, x2)
-
-inst_876:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1752*FLEN/8, x4, x1, x2)
-
-inst_877:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1754*FLEN/8, x4, x1, x2)
-
-inst_878:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1756*FLEN/8, x4, x1, x2)
-
-inst_879:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1758*FLEN/8, x4, x1, x2)
-
-inst_880:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1760*FLEN/8, x4, x1, x2)
-
-inst_881:
-// fs1 == 1 and fe1 == 0x80 and fm1 == 0x555e8a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc0555e8a; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1762*FLEN/8, x4, x1, x2)
-
-inst_882:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x555e8a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc0555e8a;
-   valaddr_reg:x3; val_offset:1764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1764*FLEN/8, x4, x1, x2)
-
-inst_883:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x244d8b and fs2 == 1 and fe2 == 0x80 and fm2 == 0x555e8a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80244d8b; op2val:0xc0555e8a;
-   valaddr_reg:x3; val_offset:1766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1766*FLEN/8, x4, x1, x2)
-
-inst_884:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1768*FLEN/8, x4, x1, x2)
-
-inst_885:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1770*FLEN/8, x4, x1, x2)
-
-inst_886:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x4500e4 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xfd4500e4;
-   valaddr_reg:x3; val_offset:1772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1772*FLEN/8, x4, x1, x2)
-
-inst_887:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1774*FLEN/8, x4, x1, x2)
-
-inst_888:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1776*FLEN/8, x4, x1, x2)
-
-inst_889:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1778*FLEN/8, x4, x1, x2)
-
-inst_890:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x76411d and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xfef6411d;
-   valaddr_reg:x3; val_offset:1780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1780*FLEN/8, x4, x1, x2)
-
-inst_891:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1782*FLEN/8, x4, x1, x2)
-
-inst_892:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1784*FLEN/8, x4, x1, x2)
-
-inst_893:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1786*FLEN/8, x4, x1, x2)
-
-inst_894:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1788*FLEN/8, x4, x1, x2)
-
-inst_895:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1790*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_8)
-
-inst_896:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1792*FLEN/8, x4, x1, x2)
-
-inst_897:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1794*FLEN/8, x4, x1, x2)
-
-inst_898:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1796*FLEN/8, x4, x1, x2)
-
-inst_899:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1798*FLEN/8, x4, x1, x2)
-
-inst_900:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1800*FLEN/8, x4, x1, x2)
-
-inst_901:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1802*FLEN/8, x4, x1, x2)
-
-inst_902:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1804*FLEN/8, x4, x1, x2)
-
-inst_903:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1806*FLEN/8, x4, x1, x2)
-
-inst_904:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x76411d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfef6411d; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1808*FLEN/8, x4, x1, x2)
-
-inst_905:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1810*FLEN/8, x4, x1, x2)
-
-inst_906:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x4500e4 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd4500e4; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1812*FLEN/8, x4, x1, x2)
-
-inst_907:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1814*FLEN/8, x4, x1, x2)
-
-inst_908:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1816*FLEN/8, x4, x1, x2)
-
-inst_909:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1818*FLEN/8, x4, x1, x2)
-
-inst_910:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x517d72 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbfd17d72; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1820*FLEN/8, x4, x1, x2)
-
-inst_911:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x517d72 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xbfd17d72;
-   valaddr_reg:x3; val_offset:1822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1822*FLEN/8, x4, x1, x2)
-
-inst_912:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x11d249 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x517d72 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8011d249; op2val:0xbfd17d72;
-   valaddr_reg:x3; val_offset:1824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1824*FLEN/8, x4, x1, x2)
-
-inst_913:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1826*FLEN/8, x4, x1, x2)
-
-inst_914:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1828*FLEN/8, x4, x1, x2)
-
-inst_915:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2b7553 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xfe2b7553;
-   valaddr_reg:x3; val_offset:1830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1830*FLEN/8, x4, x1, x2)
-
-inst_916:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1832*FLEN/8, x4, x1, x2)
-
-inst_917:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1834*FLEN/8, x4, x1, x2)
-
-inst_918:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1836*FLEN/8, x4, x1, x2)
-
-inst_919:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1838*FLEN/8, x4, x1, x2)
-
-inst_920:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1840*FLEN/8, x4, x1, x2)
-
-inst_921:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1842*FLEN/8, x4, x1, x2)
-
-inst_922:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1844*FLEN/8, x4, x1, x2)
-
-inst_923:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1846*FLEN/8, x4, x1, x2)
-
-inst_924:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1848*FLEN/8, x4, x1, x2)
-
-inst_925:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1850*FLEN/8, x4, x1, x2)
-
-inst_926:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1852*FLEN/8, x4, x1, x2)
-
-inst_927:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1854*FLEN/8, x4, x1, x2)
-
-inst_928:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1856*FLEN/8, x4, x1, x2)
-
-inst_929:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1858*FLEN/8, x4, x1, x2)
-
-inst_930:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2b7553 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2b7553; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1860*FLEN/8, x4, x1, x2)
-
-inst_931:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1862*FLEN/8, x4, x1, x2)
-
-inst_932:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x365363 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc0b65363; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1864*FLEN/8, x4, x1, x2)
-
-inst_933:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x365363 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc0b65363;
-   valaddr_reg:x3; val_offset:1866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1866*FLEN/8, x4, x1, x2)
-
-inst_934:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e0acf and fs2 == 1 and fe2 == 0x81 and fm2 == 0x365363 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e0acf; op2val:0xc0b65363;
-   valaddr_reg:x3; val_offset:1868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1868*FLEN/8, x4, x1, x2)
-
-inst_935:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7dce622b;
-   valaddr_reg:x3; val_offset:1870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1870*FLEN/8, x4, x1, x2)
-
-inst_936:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1872*FLEN/8, x4, x1, x2)
-
-inst_937:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7ebe3f3f;
-   valaddr_reg:x3; val_offset:1874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1874*FLEN/8, x4, x1, x2)
-
-inst_938:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7d902b16;
-   valaddr_reg:x3; val_offset:1876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1876*FLEN/8, x4, x1, x2)
-
-inst_939:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7f125b96;
-   valaddr_reg:x3; val_offset:1878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1878*FLEN/8, x4, x1, x2)
-
-inst_940:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7e2fb07b;
-   valaddr_reg:x3; val_offset:1880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1880*FLEN/8, x4, x1, x2)
-
-inst_941:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfdea577e;
-   valaddr_reg:x3; val_offset:1882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1882*FLEN/8, x4, x1, x2)
-
-inst_942:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfed3653a;
-   valaddr_reg:x3; val_offset:1884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1884*FLEN/8, x4, x1, x2)
-
-inst_943:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xff3a8ea9;
-   valaddr_reg:x3; val_offset:1886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1886*FLEN/8, x4, x1, x2)
-
-inst_944:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xff3f987b;
-   valaddr_reg:x3; val_offset:1888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1888*FLEN/8, x4, x1, x2)
-
-inst_945:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfd2820df;
-   valaddr_reg:x3; val_offset:1890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1890*FLEN/8, x4, x1, x2)
-
-inst_946:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x30e1ae;
-   valaddr_reg:x3; val_offset:1892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1892*FLEN/8, x4, x1, x2)
-
-inst_947:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x29b3b2;
-   valaddr_reg:x3; val_offset:1894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1894*FLEN/8, x4, x1, x2)
-
-inst_948:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x357d2c and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x357d2c;
-   valaddr_reg:x3; val_offset:1896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1896*FLEN/8, x4, x1, x2)
-
-inst_949:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1c8139 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x1c8139;
-   valaddr_reg:x3; val_offset:1898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1898*FLEN/8, x4, x1, x2)
-
-inst_950:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x39b0fc and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x39b0fc;
-   valaddr_reg:x3; val_offset:1900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1900*FLEN/8, x4, x1, x2)
-
-inst_951:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2facf2 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x802facf2;
-   valaddr_reg:x3; val_offset:1902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1902*FLEN/8, x4, x1, x2)
-
-inst_952:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0d858e and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x800d858e;
-   valaddr_reg:x3; val_offset:1904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1904*FLEN/8, x4, x1, x2)
-
-inst_953:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x244d8b and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x80244d8b;
-   valaddr_reg:x3; val_offset:1906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1906*FLEN/8, x4, x1, x2)
-
-inst_954:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x11d249 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x8011d249;
-   valaddr_reg:x3; val_offset:1908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1908*FLEN/8, x4, x1, x2)
-
-inst_955:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e0acf and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x803e0acf;
-   valaddr_reg:x3; val_offset:1910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1910*FLEN/8, x4, x1, x2)
-
-inst_956:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x183299 and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7d183299;
-   valaddr_reg:x3; val_offset:1912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1912*FLEN/8, x4, x1, x2)
-
-inst_957:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fmaxm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d183299; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f29, 0, 0, x3, 1914*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2104110116,32,FLEN)
-NAN_BOXED(2104110116,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4247330248,32,FLEN)
-NAN_BOXED(4247330248,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4254416622,32,FLEN)
-NAN_BOXED(4254416622,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4254680776,32,FLEN)
-NAN_BOXED(4254680776,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(3203502,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2114393724,32,FLEN)
-NAN_BOXED(2114393724,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(3203502,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2732978,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2112257578,32,FLEN)
-NAN_BOXED(2112257578,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2732978,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(3505452,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2115228185,32,FLEN)
-NAN_BOXED(2115228185,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(3505452,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(1868089,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2107477206,32,FLEN)
-NAN_BOXED(2107477206,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(1868089,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2115989295,32,FLEN)
-NAN_BOXED(2115989295,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(4261658950,32,FLEN)
-NAN_BOXED(4261658950,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(4246042901,32,FLEN)
-NAN_BOXED(4246042901,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(4257785546,32,FLEN)
-NAN_BOXED(4257785546,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(4249157860,32,FLEN)
-NAN_BOXED(4249157860,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(4264260947,32,FLEN)
-NAN_BOXED(4264260947,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2447111,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1079736044,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1079736044,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(1079736044,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2134128092,32,FLEN)
-NAN_BOXED(2134128092,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(4275185943,32,FLEN)
-NAN_BOXED(4275185943,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(3203502,32,FLEN)
-NAN_BOXED(902312,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(902312,32,FLEN)
-NAN_BOXED(902312,32,FLEN)
-NAN_BOXED(3203502,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(902312,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2732978,32,FLEN)
-NAN_BOXED(902312,32,FLEN)
-NAN_BOXED(2732978,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(3505452,32,FLEN)
-NAN_BOXED(902312,32,FLEN)
-NAN_BOXED(3505452,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(1868089,32,FLEN)
-NAN_BOXED(902312,32,FLEN)
-NAN_BOXED(2135224331,32,FLEN)
-NAN_BOXED(2135224331,32,FLEN)
-NAN_BOXED(902312,32,FLEN)
-NAN_BOXED(902312,32,FLEN)
-NAN_BOXED(1868089,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(902312,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
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-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2115989295,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2115989295,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2115989295,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(2115989295,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1084852774,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1084852774,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(1084852774,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4261658950,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(4261658950,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(4261658950,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(4261658950,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(4261658950,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(4261658950,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3230407454,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3230407454,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(3230407454,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4246042901,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(4246042901,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(4273657690,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(4273657690,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(4246042901,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(4273657690,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(4246042901,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(4246042901,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(4273657690,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
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-NAN_BOXED(4273657690,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(4273657690,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(4246042901,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3214865002,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3214865002,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(3214865002,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4257785546,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(4257785546,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(4286238845,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(4286238845,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(4257785546,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(4286238845,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(4257785546,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(4257785546,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(4286238845,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(4286238845,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(4286238845,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(4257785546,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3226820234,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3226820234,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(3226820234,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4249157860,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(4249157860,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(4277551389,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(4277551389,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(4249157860,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(4277551389,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(4249157860,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(4249157860,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(4277551389,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(4277551389,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(4277551389,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(4249157860,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3218177394,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3218177394,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(3218177394,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(4264260947,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(4264260947,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(4264260947,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(4264260947,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(4264260947,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(4264260947,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3233174371,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3233174371,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(3233174371,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2110677547,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2126397247,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2106600214,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2131909526,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2117054587,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4259993470,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4275266874,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4282027689,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4282357883,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4247265503,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3203502,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2732978,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3505452,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1868089,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3780860,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2150608114,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2148369806,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2149862795,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2148651593,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2151549647,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2098737817,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_7:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_8:
-    .fill 124*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b1-01.S
deleted file mode 100644
index 9cf9888e4..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b1-01.S
+++ /dev/null
@@ -1,5889 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:09:34 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fminm.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fminm.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fminm_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rd != rs2, rs1==f31, rs2==f30, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f31; op2:f30; dest:f31; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rs2 != rd, rs1==f29, rs2==f29, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f29; op2:f29; dest:f30; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 == rs2 == rd, rs1==f28, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f28; op2:f28; dest:f28; op1val:0x0; op2val:0x0;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f28, f28, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs2 == rd != rs1, rs1==f30, rs2==f27, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f27; dest:f27; op1val:0x0; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f27, f30, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f27, rs2==f31, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f27; op2:f31; dest:f29; op1val:0x0; op2val:0x2;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f29, f27, f31, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f25, rs2==f24, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f25; op2:f24; dest:f26; op1val:0x0; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f26, f25, f24, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f24; op2:f26; dest:f25; op1val:0x0; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f25, f24, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f26, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f26; op2:f25; dest:f24; op1val:0x0; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f24, f26, f25, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f21, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f22; op2:f21; dest:f23; op1val:0x0; op2val:0x800000;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f23, f22, f21, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rs2==f23, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f21; op2:f23; dest:f22; op1val:0x0; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f22, f21, f23, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f23, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f23; op2:f22; dest:f21; op1val:0x0; op2val:0x800001;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f21, f23, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f19, rs2==f18, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f19; op2:f18; dest:f20; op1val:0x0; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f20, f19, f18, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f18; op2:f20; dest:f19; op1val:0x0; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f20, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f20; op2:f19; dest:f18; op1val:0x0; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f18, f20, f19, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f15, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f16; op2:f15; dest:f17; op1val:0x0; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f17, f16, f15, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rs2==f17, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f15; op2:f17; dest:f16; op1val:0x0; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f16, f15, f17, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f17, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f17; op2:f16; dest:f15; op1val:0x0; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f15, f17, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f13, rs2==f12, rd==f14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f13; op2:f12; dest:f14; op1val:0x0; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f14, f13, f12, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f12; op2:f14; dest:f13; op1val:0x0; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f14, rs2==f13, rd==f12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f14; op2:f13; dest:f12; op1val:0x0; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f12, f14, f13, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f9, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f10; op2:f9; dest:f11; op1val:0x0; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f11, f10, f9, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rs2==f11, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f9; op2:f11; dest:f10; op1val:0x0; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f10, f9, f11, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f11, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f11; op2:f10; dest:f9; op1val:0x0; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f9, f11, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f7, rs2==f6, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f7; op2:f6; dest:f8; op1val:0x0; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f8, f7, f6, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f6; op2:f8; dest:f7; op1val:0x80000000; op2val:0x0;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f8, rs2==f7, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f8; op2:f7; dest:f6; op1val:0x80000000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f6, f8, f7, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f3, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f4; op2:f3; dest:f5; op1val:0x80000000; op2val:0x1;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f5, f4, f3, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rs2==f5, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f3; op2:f5; dest:f4; op1val:0x80000000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f4, f3, f5, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f5, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f5; op2:f4; dest:f3; op1val:0x80000000; op2val:0x2;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f3, f5, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f1, rs2==f0, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f1; op2:f0; dest:f2; op1val:0x80000000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f2, f1, f0, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f0; op2:f2; dest:f1; op1val:0x80000000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f2, rs2==f1, rd==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f2; op2:f1; dest:f0; op1val:0x80000000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f0, f2, f1, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:72*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:74*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:76*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:78*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:80*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:82*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:84*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:86*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:88*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:90*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:92*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:94*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x0;
-   valaddr_reg:x3; val_offset:96*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:98*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x1;
-   valaddr_reg:x3; val_offset:100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x2;
-   valaddr_reg:x3; val_offset:104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x800000;
-   valaddr_reg:x3; val_offset:112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x800001;
-   valaddr_reg:x3; val_offset:116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x0;
-   valaddr_reg:x3; val_offset:144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x1;
-   valaddr_reg:x3; val_offset:148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x2;
-   valaddr_reg:x3; val_offset:152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80000001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x0;
-   valaddr_reg:x3; val_offset:192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x1;
-   valaddr_reg:x3; val_offset:196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x2;
-   valaddr_reg:x3; val_offset:200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x800000;
-   valaddr_reg:x3; val_offset:208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x800001;
-   valaddr_reg:x3; val_offset:212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x0;
-   valaddr_reg:x3; val_offset:240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x1;
-   valaddr_reg:x3; val_offset:244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x2;
-   valaddr_reg:x3; val_offset:248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x800000;
-   valaddr_reg:x3; val_offset:256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x800001;
-   valaddr_reg:x3; val_offset:260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807ffffe; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x807fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x0;
-   valaddr_reg:x3; val_offset:480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x1;
-   valaddr_reg:x3; val_offset:484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x2;
-   valaddr_reg:x3; val_offset:488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x0;
-   valaddr_reg:x3; val_offset:528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x1;
-   valaddr_reg:x3; val_offset:532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x2;
-   valaddr_reg:x3; val_offset:536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x800000;
-   valaddr_reg:x3; val_offset:544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x800001;
-   valaddr_reg:x3; val_offset:548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80855555; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x0;
-   valaddr_reg:x3; val_offset:624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x1;
-   valaddr_reg:x3; val_offset:628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x2;
-   valaddr_reg:x3; val_offset:632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x800000;
-   valaddr_reg:x3; val_offset:640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x800001;
-   valaddr_reg:x3; val_offset:644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x0;
-   valaddr_reg:x3; val_offset:768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x1;
-   valaddr_reg:x3; val_offset:772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x2;
-   valaddr_reg:x3; val_offset:776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x0;
-   valaddr_reg:x3; val_offset:816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x1;
-   valaddr_reg:x3; val_offset:820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x2;
-   valaddr_reg:x3; val_offset:824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc00000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x0;
-   valaddr_reg:x3; val_offset:864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x1;
-   valaddr_reg:x3; val_offset:868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x2;
-   valaddr_reg:x3; val_offset:872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7fc00001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x0;
-   valaddr_reg:x3; val_offset:912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x1;
-   valaddr_reg:x3; val_offset:916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x2;
-   valaddr_reg:x3; val_offset:920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x800000;
-   valaddr_reg:x3; val_offset:928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x800001;
-   valaddr_reg:x3; val_offset:932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffc55555; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x0;
-   valaddr_reg:x3; val_offset:960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x1;
-   valaddr_reg:x3; val_offset:964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x2;
-   valaddr_reg:x3; val_offset:968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x800000;
-   valaddr_reg:x3; val_offset:976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x800001;
-   valaddr_reg:x3; val_offset:980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:990*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:992*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:994*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:996*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:998*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1000*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1002*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1004*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f800001; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1006*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x0;
-   valaddr_reg:x3; val_offset:1008*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:1010*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x1;
-   valaddr_reg:x3; val_offset:1012*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:1014*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x2;
-   valaddr_reg:x3; val_offset:1016*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:1018*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:1020*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:1022*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x800000;
-   valaddr_reg:x3; val_offset:1024*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:1026*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x800001;
-   valaddr_reg:x3; val_offset:1028*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:1030*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1032*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1034*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:1036*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:1038*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:1040*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:1042*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:1044*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:1046*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1048*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1050*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1052*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xffaaaaaa; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1054*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1056*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:1058*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1060*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:1062*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1064*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:1066*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:1068*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:1070*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:1072*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:1074*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:1076*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:1078*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1080*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1082*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:1084*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:1086*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:1088*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:1090*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:1092*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:1094*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1096*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1098*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x0;
-   valaddr_reg:x3; val_offset:1104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:1106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x1;
-   valaddr_reg:x3; val_offset:1108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80000001;
-   valaddr_reg:x3; val_offset:1110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x2;
-   valaddr_reg:x3; val_offset:1112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x807ffffe;
-   valaddr_reg:x3; val_offset:1114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7fffff;
-   valaddr_reg:x3; val_offset:1116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x807fffff;
-   valaddr_reg:x3; val_offset:1118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x800000;
-   valaddr_reg:x3; val_offset:1120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80800000;
-   valaddr_reg:x3; val_offset:1122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x800001;
-   valaddr_reg:x3; val_offset:1124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x80855555;
-   valaddr_reg:x3; val_offset:1126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7f800000;
-   valaddr_reg:x3; val_offset:1132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xff800000;
-   valaddr_reg:x3; val_offset:1134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7fc00000;
-   valaddr_reg:x3; val_offset:1136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xffc00000;
-   valaddr_reg:x3; val_offset:1138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7fc00001;
-   valaddr_reg:x3; val_offset:1140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xffc55555;
-   valaddr_reg:x3; val_offset:1142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x7f800001;
-   valaddr_reg:x3; val_offset:1144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xffaaaaaa;
-   valaddr_reg:x3; val_offset:1146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0x3f800000;
-   valaddr_reg:x3; val_offset:1148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf800000; op2val:0xbf800000;
-   valaddr_reg:x3; val_offset:1150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x80000000;
-   valaddr_reg:x3; val_offset:1152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x1;
-   valaddr_reg:x3; val_offset:1154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
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-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 132*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b19-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b19-01.S
deleted file mode 100644
index 02c3eb393..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fminm_b19-01.S
+++ /dev/null
@@ -1,10074 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:09:34 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fminm.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fminm.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fminm_b19 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b19)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rd != rs2, rs1==f31, rs2==f30, rd==f31,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f31; op2:f30; dest:f31; op1val:0x7f222105; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 == rs2 != rd, rs1==f29, rs2==f29, rd==f30,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f29; op2:f29; dest:f30; op1val:0x7f222105; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1 == rs2 == rd, rs1==f28, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f28; op2:f28; dest:f28; op1val:0x7ec45459; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f28, f28, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs2 == rd != rs1, rs1==f30, rs2==f27, rd==f27,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f27; dest:f27; op1val:0x7f222105; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f27, f30, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1 != rs2  and rs1 != rd and rs2 != rd, rs1==f27, rs2==f31, rd==f29,fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f27; op2:f31; dest:f29; op1val:0x7eb70362; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f29, f27, f31, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f25, rs2==f24, rd==f26,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f25; op2:f24; dest:f26; op1val:0x7f222105; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f26, f25, f24, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f24, rs2==f26, rd==f25,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f24; op2:f26; dest:f25; op1val:0x7d81b404; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f25, f24, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f26, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x01b404 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f26; op2:f25; dest:f24; op1val:0x7f7fffff; op2val:0x7d81b404;
-   valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f24, f26, f25, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f22, rs2==f21, rd==f23,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f22; op2:f21; dest:f23; op1val:0x7d81b404; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f23, f22, f21, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rs2==f23, rd==f22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x01b404 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f21; op2:f23; dest:f22; op1val:0x7f222105; op2val:0x7d81b404;
-   valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f22, f21, f23, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f23, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f23; op2:f22; dest:f21; op1val:0x7f222105; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f21, f23, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f19, rs2==f18, rd==f20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f19; op2:f18; dest:f20; op1val:0x7f2eabd8; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f20, f19, f18, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f18; op2:f20; dest:f19; op1val:0x7f222105; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f20, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f20; op2:f19; dest:f18; op1val:0x7d81b404; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f18, f20, f19, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f16, rs2==f15, rd==f17,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x01b404 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f16; op2:f15; dest:f17; op1val:0xff7fffff; op2val:0x7d81b404;
-   valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f17, f16, f15, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rs2==f17, rd==f16,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f15; op2:f17; dest:f16; op1val:0x7d81b404; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f16, f15, f17, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f17, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f17; op2:f16; dest:f15; op1val:0x7f222105; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f15, f17, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f13, rs2==f12, rd==f14,fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f13; op2:f12; dest:f14; op1val:0xfee4815a; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f14, f13, f12, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f12; op2:f14; dest:f13; op1val:0x7f222105; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f14, rs2==f13, rd==f12,fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f14; op2:f13; dest:f12; op1val:0xfe9ffb35; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f12, f14, f13, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f10, rs2==f9, rd==f11,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f10; op2:f9; dest:f11; op1val:0x7f222105; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f11, f10, f9, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rs2==f11, rd==f10,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f9; op2:f11; dest:f10; op1val:0x7d81b404; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f10, f9, f11, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f11, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f11; op2:f10; dest:f9; op1val:0x7f222105; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f9, f11, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f7, rs2==f6, rd==f8,fs1 == 0 and fe1 == 0xf7 and fm1 == 0x4f866d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f7; op2:f6; dest:f8; op1val:0x7bcf866d; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f8, f7, f6, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x4f866d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f6; op2:f8; dest:f7; op1val:0xff7fffff; op2val:0x7bcf866d;
-   valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f8, rs2==f7, rd==f6,fs1 == 0 and fe1 == 0xf7 and fm1 == 0x4f866d and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f8; op2:f7; dest:f6; op1val:0x7bcf866d; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f6, f8, f7, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f4, rs2==f3, rd==f5,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x4f866d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f4; op2:f3; dest:f5; op1val:0x7f222105; op2val:0x7bcf866d;
-   valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f5, f4, f3, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rs2==f5, rd==f4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f3; op2:f5; dest:f4; op1val:0x7f222105; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f4, f3, f5, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f5, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f5; op2:f4; dest:f3; op1val:0x177770; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f3, f5, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f1, rs2==f0, rd==f2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f1; op2:f0; dest:f2; op1val:0x7f39f704; op2val:0x177770;
-   valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f2, f1, f0, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f0; op2:f2; dest:f1; op1val:0x177770; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f2, rs2==f1, rd==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f2; op2:f1; dest:f0; op1val:0x7f222105; op2val:0x177770;
-   valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f0, f2, f1, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
-
-inst_32:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
-
-inst_33:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
-
-inst_34:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x177770;
-   valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
-
-inst_35:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
-
-inst_36:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:72*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
-
-inst_37:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:74*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
-
-inst_38:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:76*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
-
-inst_39:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:78*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
-
-inst_40:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:80*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
-
-inst_41:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:82*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
-
-inst_42:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:84*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
-
-inst_43:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:86*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
-
-inst_44:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x177770;
-   valaddr_reg:x3; val_offset:88*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
-
-inst_45:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:90*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
-
-inst_46:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:92*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
-
-inst_47:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:94*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
-
-inst_48:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:96*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
-
-inst_49:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x5b0376 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0xff5b0376;
-   valaddr_reg:x3; val_offset:98*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
-
-inst_50:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x177770;
-   valaddr_reg:x3; val_offset:100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
-
-inst_51:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
-
-inst_52:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
-
-inst_53:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x177770; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
-
-inst_54:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
-
-inst_55:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0258be and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x258be; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 110*FLEN/8, x4, x1, x2)
-
-inst_56:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0258be and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x258be;
-   valaddr_reg:x3; val_offset:112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 112*FLEN/8, x4, x1, x2)
-
-inst_57:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0258be and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x258be; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
-
-inst_58:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0258be and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x258be;
-   valaddr_reg:x3; val_offset:116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 116*FLEN/8, x4, x1, x2)
-
-inst_59:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 118*FLEN/8, x4, x1, x2)
-
-inst_60:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x09ec91 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4009ec91; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
-
-inst_61:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09ec91 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x4009ec91;
-   valaddr_reg:x3; val_offset:122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 122*FLEN/8, x4, x1, x2)
-
-inst_62:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x09ec91 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x4009ec91;
-   valaddr_reg:x3; val_offset:124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 124*FLEN/8, x4, x1, x2)
-
-inst_63:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
-
-inst_64:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 128*FLEN/8, x4, x1, x2)
-
-inst_65:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 130*FLEN/8, x4, x1, x2)
-
-inst_66:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 132*FLEN/8, x4, x1, x2)
-
-inst_67:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x1d1047 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d1d1047; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 134*FLEN/8, x4, x1, x2)
-
-inst_68:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x1d1047 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7d1d1047;
-   valaddr_reg:x3; val_offset:136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 136*FLEN/8, x4, x1, x2)
-
-inst_69:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x1d1047 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d1d1047; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 138*FLEN/8, x4, x1, x2)
-
-inst_70:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfa and fm2 == 0x1d1047 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x7d1d1047;
-   valaddr_reg:x3; val_offset:140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 140*FLEN/8, x4, x1, x2)
-
-inst_71:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 142*FLEN/8, x4, x1, x2)
-
-inst_72:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 144*FLEN/8, x4, x1, x2)
-
-inst_73:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 146*FLEN/8, x4, x1, x2)
-
-inst_74:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x1d1047 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d1d1047; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 148*FLEN/8, x4, x1, x2)
-
-inst_75:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x1d1047 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7d1d1047;
-   valaddr_reg:x3; val_offset:150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 150*FLEN/8, x4, x1, x2)
-
-inst_76:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x1d1047 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d1d1047; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 152*FLEN/8, x4, x1, x2)
-
-inst_77:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 154*FLEN/8, x4, x1, x2)
-
-inst_78:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 156*FLEN/8, x4, x1, x2)
-
-inst_79:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 158*FLEN/8, x4, x1, x2)
-
-inst_80:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 160*FLEN/8, x4, x1, x2)
-
-inst_81:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 162*FLEN/8, x4, x1, x2)
-
-inst_82:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x1d1047 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d1d1047; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 164*FLEN/8, x4, x1, x2)
-
-inst_83:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 166*FLEN/8, x4, x1, x2)
-
-inst_84:
-// fs1 == 0 and fe1 == 0xf6 and fm1 == 0x7b4d3e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7b7b4d3e; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 168*FLEN/8, x4, x1, x2)
-
-inst_85:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xf6 and fm2 == 0x7b4d3e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7b7b4d3e;
-   valaddr_reg:x3; val_offset:170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 170*FLEN/8, x4, x1, x2)
-
-inst_86:
-// fs1 == 0 and fe1 == 0xf6 and fm1 == 0x7b4d3e and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7b7b4d3e; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 172*FLEN/8, x4, x1, x2)
-
-inst_87:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xf6 and fm2 == 0x7b4d3e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x7b7b4d3e;
-   valaddr_reg:x3; val_offset:174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 174*FLEN/8, x4, x1, x2)
-
-inst_88:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 176*FLEN/8, x4, x1, x2)
-
-inst_89:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 178*FLEN/8, x4, x1, x2)
-
-inst_90:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0e3558 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0xe3558;
-   valaddr_reg:x3; val_offset:180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 180*FLEN/8, x4, x1, x2)
-
-inst_91:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 182*FLEN/8, x4, x1, x2)
-
-inst_92:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0e3558 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0xe3558;
-   valaddr_reg:x3; val_offset:184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 184*FLEN/8, x4, x1, x2)
-
-inst_93:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 186*FLEN/8, x4, x1, x2)
-
-inst_94:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 188*FLEN/8, x4, x1, x2)
-
-inst_95:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0e3558 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xe3558;
-   valaddr_reg:x3; val_offset:190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 190*FLEN/8, x4, x1, x2)
-
-inst_96:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 192*FLEN/8, x4, x1, x2)
-
-inst_97:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 194*FLEN/8, x4, x1, x2)
-
-inst_98:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 196*FLEN/8, x4, x1, x2)
-
-inst_99:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 198*FLEN/8, x4, x1, x2)
-
-inst_100:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 200*FLEN/8, x4, x1, x2)
-
-inst_101:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 202*FLEN/8, x4, x1, x2)
-
-inst_102:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 204*FLEN/8, x4, x1, x2)
-
-inst_103:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 206*FLEN/8, x4, x1, x2)
-
-inst_104:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 208*FLEN/8, x4, x1, x2)
-
-inst_105:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0e3558 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xe3558;
-   valaddr_reg:x3; val_offset:210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 210*FLEN/8, x4, x1, x2)
-
-inst_106:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 212*FLEN/8, x4, x1, x2)
-
-inst_107:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 214*FLEN/8, x4, x1, x2)
-
-inst_108:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 216*FLEN/8, x4, x1, x2)
-
-inst_109:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 218*FLEN/8, x4, x1, x2)
-
-inst_110:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x5b0376 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0xff5b0376;
-   valaddr_reg:x3; val_offset:220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 220*FLEN/8, x4, x1, x2)
-
-inst_111:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0e3558 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0xe3558;
-   valaddr_reg:x3; val_offset:222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 222*FLEN/8, x4, x1, x2)
-
-inst_112:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 224*FLEN/8, x4, x1, x2)
-
-inst_113:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 226*FLEN/8, x4, x1, x2)
-
-inst_114:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0e3558 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xe3558; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 228*FLEN/8, x4, x1, x2)
-
-inst_115:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 230*FLEN/8, x4, x1, x2)
-
-inst_116:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x016bbc and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x16bbc; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 232*FLEN/8, x4, x1, x2)
-
-inst_117:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x016bbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x16bbc;
-   valaddr_reg:x3; val_offset:234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 234*FLEN/8, x4, x1, x2)
-
-inst_118:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x016bbc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x16bbc; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 236*FLEN/8, x4, x1, x2)
-
-inst_119:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x016bbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x16bbc;
-   valaddr_reg:x3; val_offset:238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 238*FLEN/8, x4, x1, x2)
-
-inst_120:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 240*FLEN/8, x4, x1, x2)
-
-inst_121:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x2704c6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3fa704c6; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 242*FLEN/8, x4, x1, x2)
-
-inst_122:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2704c6 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x3fa704c6;
-   valaddr_reg:x3; val_offset:244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 244*FLEN/8, x4, x1, x2)
-
-inst_123:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x2704c6 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x3fa704c6;
-   valaddr_reg:x3; val_offset:246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 246*FLEN/8, x4, x1, x2)
-
-inst_124:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 248*FLEN/8, x4, x1, x2)
-
-inst_125:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 250*FLEN/8, x4, x1, x2)
-
-inst_126:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x12691b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d12691b; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 252*FLEN/8, x4, x1, x2)
-
-inst_127:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x12691b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7d12691b;
-   valaddr_reg:x3; val_offset:254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 254*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_2)
-
-inst_128:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x12691b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d12691b; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 256*FLEN/8, x4, x1, x2)
-
-inst_129:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfa and fm2 == 0x12691b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x7d12691b;
-   valaddr_reg:x3; val_offset:258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 258*FLEN/8, x4, x1, x2)
-
-inst_130:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 260*FLEN/8, x4, x1, x2)
-
-inst_131:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 262*FLEN/8, x4, x1, x2)
-
-inst_132:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 264*FLEN/8, x4, x1, x2)
-
-inst_133:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x12691b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d12691b; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 266*FLEN/8, x4, x1, x2)
-
-inst_134:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x12691b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7d12691b;
-   valaddr_reg:x3; val_offset:268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 268*FLEN/8, x4, x1, x2)
-
-inst_135:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x12691b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d12691b; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 270*FLEN/8, x4, x1, x2)
-
-inst_136:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 272*FLEN/8, x4, x1, x2)
-
-inst_137:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 274*FLEN/8, x4, x1, x2)
-
-inst_138:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 276*FLEN/8, x4, x1, x2)
-
-inst_139:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 278*FLEN/8, x4, x1, x2)
-
-inst_140:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 280*FLEN/8, x4, x1, x2)
-
-inst_141:
-// fs1 == 0 and fe1 == 0xfa and fm1 == 0x12691b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d12691b; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 282*FLEN/8, x4, x1, x2)
-
-inst_142:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 284*FLEN/8, x4, x1, x2)
-
-inst_143:
-// fs1 == 0 and fe1 == 0xf6 and fm1 == 0x6a41c5 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7b6a41c5; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 286*FLEN/8, x4, x1, x2)
-
-inst_144:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xf6 and fm2 == 0x6a41c5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7b6a41c5;
-   valaddr_reg:x3; val_offset:288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 288*FLEN/8, x4, x1, x2)
-
-inst_145:
-// fs1 == 0 and fe1 == 0xf6 and fm1 == 0x6a41c5 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7b6a41c5; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 290*FLEN/8, x4, x1, x2)
-
-inst_146:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xf6 and fm2 == 0x6a41c5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x7b6a41c5;
-   valaddr_reg:x3; val_offset:292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 292*FLEN/8, x4, x1, x2)
-
-inst_147:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 294*FLEN/8, x4, x1, x2)
-
-inst_148:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 296*FLEN/8, x4, x1, x2)
-
-inst_149:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0d3ea3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0xd3ea3;
-   valaddr_reg:x3; val_offset:298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 298*FLEN/8, x4, x1, x2)
-
-inst_150:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 300*FLEN/8, x4, x1, x2)
-
-inst_151:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0d3ea3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0xd3ea3;
-   valaddr_reg:x3; val_offset:302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 302*FLEN/8, x4, x1, x2)
-
-inst_152:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 304*FLEN/8, x4, x1, x2)
-
-inst_153:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 306*FLEN/8, x4, x1, x2)
-
-inst_154:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0d3ea3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xd3ea3;
-   valaddr_reg:x3; val_offset:308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 308*FLEN/8, x4, x1, x2)
-
-inst_155:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 310*FLEN/8, x4, x1, x2)
-
-inst_156:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 312*FLEN/8, x4, x1, x2)
-
-inst_157:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 314*FLEN/8, x4, x1, x2)
-
-inst_158:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 316*FLEN/8, x4, x1, x2)
-
-inst_159:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 318*FLEN/8, x4, x1, x2)
-
-inst_160:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 320*FLEN/8, x4, x1, x2)
-
-inst_161:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 322*FLEN/8, x4, x1, x2)
-
-inst_162:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 324*FLEN/8, x4, x1, x2)
-
-inst_163:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 326*FLEN/8, x4, x1, x2)
-
-inst_164:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0d3ea3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xd3ea3;
-   valaddr_reg:x3; val_offset:328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 328*FLEN/8, x4, x1, x2)
-
-inst_165:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 330*FLEN/8, x4, x1, x2)
-
-inst_166:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 332*FLEN/8, x4, x1, x2)
-
-inst_167:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 334*FLEN/8, x4, x1, x2)
-
-inst_168:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 336*FLEN/8, x4, x1, x2)
-
-inst_169:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x5b0376 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0xff5b0376;
-   valaddr_reg:x3; val_offset:338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 338*FLEN/8, x4, x1, x2)
-
-inst_170:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0d3ea3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0xd3ea3;
-   valaddr_reg:x3; val_offset:340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 340*FLEN/8, x4, x1, x2)
-
-inst_171:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 342*FLEN/8, x4, x1, x2)
-
-inst_172:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 344*FLEN/8, x4, x1, x2)
-
-inst_173:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0d3ea3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xd3ea3; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 346*FLEN/8, x4, x1, x2)
-
-inst_174:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 348*FLEN/8, x4, x1, x2)
-
-inst_175:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x015310 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x15310; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 350*FLEN/8, x4, x1, x2)
-
-inst_176:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x015310 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x15310;
-   valaddr_reg:x3; val_offset:352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 352*FLEN/8, x4, x1, x2)
-
-inst_177:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x015310 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x15310; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 354*FLEN/8, x4, x1, x2)
-
-inst_178:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x015310 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x15310;
-   valaddr_reg:x3; val_offset:356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 356*FLEN/8, x4, x1, x2)
-
-inst_179:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 358*FLEN/8, x4, x1, x2)
-
-inst_180:
-// fs1 == 0 and fe1 == 0x7f and fm1 == 0x1bb0c0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f9bb0c0; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 360*FLEN/8, x4, x1, x2)
-
-inst_181:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1bb0c0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x3f9bb0c0;
-   valaddr_reg:x3; val_offset:362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 362*FLEN/8, x4, x1, x2)
-
-inst_182:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x1bb0c0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7eb70362; op2val:0x3f9bb0c0;
-   valaddr_reg:x3; val_offset:364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 364*FLEN/8, x4, x1, x2)
-
-inst_183:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 366*FLEN/8, x4, x1, x2)
-
-inst_184:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 368*FLEN/8, x4, x1, x2)
-
-inst_185:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 370*FLEN/8, x4, x1, x2)
-
-inst_186:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 372*FLEN/8, x4, x1, x2)
-
-inst_187:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 374*FLEN/8, x4, x1, x2)
-
-inst_188:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 376*FLEN/8, x4, x1, x2)
-
-inst_189:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 378*FLEN/8, x4, x1, x2)
-
-inst_190:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 380*FLEN/8, x4, x1, x2)
-
-inst_191:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 382*FLEN/8, x4, x1, x2)
-
-inst_192:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x0bbcad and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7d8bbcad;
-   valaddr_reg:x3; val_offset:384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 384*FLEN/8, x4, x1, x2)
-
-inst_193:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0bbcad and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d8bbcad; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 386*FLEN/8, x4, x1, x2)
-
-inst_194:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 388*FLEN/8, x4, x1, x2)
-
-inst_195:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 390*FLEN/8, x4, x1, x2)
-
-inst_196:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 392*FLEN/8, x4, x1, x2)
-
-inst_197:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 394*FLEN/8, x4, x1, x2)
-
-inst_198:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x36cde1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xfd36cde1;
-   valaddr_reg:x3; val_offset:396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 396*FLEN/8, x4, x1, x2)
-
-inst_199:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x36cde1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd36cde1; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 398*FLEN/8, x4, x1, x2)
-
-inst_200:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 400*FLEN/8, x4, x1, x2)
-
-inst_201:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 402*FLEN/8, x4, x1, x2)
-
-inst_202:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x7ff856 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xfcfff856;
-   valaddr_reg:x3; val_offset:404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 404*FLEN/8, x4, x1, x2)
-
-inst_203:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7ff856 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfcfff856; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 406*FLEN/8, x4, x1, x2)
-
-inst_204:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 408*FLEN/8, x4, x1, x2)
-
-inst_205:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 410*FLEN/8, x4, x1, x2)
-
-inst_206:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 412*FLEN/8, x4, x1, x2)
-
-inst_207:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 414*FLEN/8, x4, x1, x2)
-
-inst_208:
-// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2d2942 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x043521 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7cad2942; op2val:0xfe043521;
-   valaddr_reg:x3; val_offset:416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 416*FLEN/8, x4, x1, x2)
-
-inst_209:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x043521 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x2d2942 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe043521; op2val:0x7cad2942;
-   valaddr_reg:x3; val_offset:418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 418*FLEN/8, x4, x1, x2)
-
-inst_210:
-// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x2d2942 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7cad2942; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 420*FLEN/8, x4, x1, x2)
-
-inst_211:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x2d2942 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7cad2942;
-   valaddr_reg:x3; val_offset:422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 422*FLEN/8, x4, x1, x2)
-
-inst_212:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 424*FLEN/8, x4, x1, x2)
-
-inst_213:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x14c59d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x7d94c59d;
-   valaddr_reg:x3; val_offset:426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 426*FLEN/8, x4, x1, x2)
-
-inst_214:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x14c59d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d94c59d; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 428*FLEN/8, x4, x1, x2)
-
-inst_215:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 430*FLEN/8, x4, x1, x2)
-
-inst_216:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 432*FLEN/8, x4, x1, x2)
-
-inst_217:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 434*FLEN/8, x4, x1, x2)
-
-inst_218:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0aa123 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x7e0aa123;
-   valaddr_reg:x3; val_offset:436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 436*FLEN/8, x4, x1, x2)
-
-inst_219:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0aa123 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0aa123; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 438*FLEN/8, x4, x1, x2)
-
-inst_220:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 440*FLEN/8, x4, x1, x2)
-
-inst_221:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 442*FLEN/8, x4, x1, x2)
-
-inst_222:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x209de3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x7e209de3;
-   valaddr_reg:x3; val_offset:444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 444*FLEN/8, x4, x1, x2)
-
-inst_223:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x209de3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e209de3; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 446*FLEN/8, x4, x1, x2)
-
-inst_224:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 448*FLEN/8, x4, x1, x2)
-
-inst_225:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 450*FLEN/8, x4, x1, x2)
-
-inst_226:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x5abd82 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x7ddabd82;
-   valaddr_reg:x3; val_offset:452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 452*FLEN/8, x4, x1, x2)
-
-inst_227:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5abd82 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ddabd82; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 454*FLEN/8, x4, x1, x2)
-
-inst_228:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 456*FLEN/8, x4, x1, x2)
-
-inst_229:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 458*FLEN/8, x4, x1, x2)
-
-inst_230:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0f4d55 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x7e0f4d55;
-   valaddr_reg:x3; val_offset:460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 460*FLEN/8, x4, x1, x2)
-
-inst_231:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0f4d55 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0f4d55; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 462*FLEN/8, x4, x1, x2)
-
-inst_232:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 464*FLEN/8, x4, x1, x2)
-
-inst_233:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 466*FLEN/8, x4, x1, x2)
-
-inst_234:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03130e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0xfe03130e;
-   valaddr_reg:x3; val_offset:468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 468*FLEN/8, x4, x1, x2)
-
-inst_235:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03130e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03130e; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 470*FLEN/8, x4, x1, x2)
-
-inst_236:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 472*FLEN/8, x4, x1, x2)
-
-inst_237:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 474*FLEN/8, x4, x1, x2)
-
-inst_238:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x7671c2 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0xfdf671c2;
-   valaddr_reg:x3; val_offset:476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 476*FLEN/8, x4, x1, x2)
-
-inst_239:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x7671c2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdf671c2; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 478*FLEN/8, x4, x1, x2)
-
-inst_240:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 480*FLEN/8, x4, x1, x2)
-
-inst_241:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 482*FLEN/8, x4, x1, x2)
-
-inst_242:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x2f35f8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0xfdaf35f8;
-   valaddr_reg:x3; val_offset:484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 484*FLEN/8, x4, x1, x2)
-
-inst_243:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x2f35f8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdaf35f8; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 486*FLEN/8, x4, x1, x2)
-
-inst_244:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 488*FLEN/8, x4, x1, x2)
-
-inst_245:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 490*FLEN/8, x4, x1, x2)
-
-inst_246:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x048fde and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0xfe048fde;
-   valaddr_reg:x3; val_offset:492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 492*FLEN/8, x4, x1, x2)
-
-inst_247:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x048fde and fs2 == 0 and fe2 == 0x00 and fm2 == 0x4e52b1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe048fde; op2val:0x4e52b1;
-   valaddr_reg:x3; val_offset:494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 494*FLEN/8, x4, x1, x2)
-
-inst_248:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x4e52b1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x4e52b1; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 496*FLEN/8, x4, x1, x2)
-
-inst_249:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 498*FLEN/8, x4, x1, x2)
-
-inst_250:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x07d511 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2d09bb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d511; op2val:0xfe2d09bb;
-   valaddr_reg:x3; val_offset:500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 500*FLEN/8, x4, x1, x2)
-
-inst_251:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2d09bb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07d511 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2d09bb; op2val:0x7d511;
-   valaddr_reg:x3; val_offset:502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 502*FLEN/8, x4, x1, x2)
-
-inst_252:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x07d511 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d511; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 504*FLEN/8, x4, x1, x2)
-
-inst_253:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x07d511 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7d511;
-   valaddr_reg:x3; val_offset:506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 506*FLEN/8, x4, x1, x2)
-
-inst_254:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 508*FLEN/8, x4, x1, x2)
-
-inst_255:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x662bb0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40e62bb0; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 510*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_3)
-
-inst_256:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x662bb0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40e62bb0;
-   valaddr_reg:x3; val_offset:512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 512*FLEN/8, x4, x1, x2)
-
-inst_257:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x587392 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x662bb0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e587392; op2val:0x40e62bb0;
-   valaddr_reg:x3; val_offset:514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 514*FLEN/8, x4, x1, x2)
-
-inst_258:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 516*FLEN/8, x4, x1, x2)
-
-inst_259:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 518*FLEN/8, x4, x1, x2)
-
-inst_260:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0bbcad and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d8bbcad; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 520*FLEN/8, x4, x1, x2)
-
-inst_261:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x0bbcad and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x7d8bbcad;
-   valaddr_reg:x3; val_offset:522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 522*FLEN/8, x4, x1, x2)
-
-inst_262:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 524*FLEN/8, x4, x1, x2)
-
-inst_263:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0bbcad and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d8bbcad; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 526*FLEN/8, x4, x1, x2)
-
-inst_264:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x0bbcad and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7d8bbcad;
-   valaddr_reg:x3; val_offset:528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 528*FLEN/8, x4, x1, x2)
-
-inst_265:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0bbcad and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d8bbcad; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 530*FLEN/8, x4, x1, x2)
-
-inst_266:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 532*FLEN/8, x4, x1, x2)
-
-inst_267:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 534*FLEN/8, x4, x1, x2)
-
-inst_268:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 536*FLEN/8, x4, x1, x2)
-
-inst_269:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 538*FLEN/8, x4, x1, x2)
-
-inst_270:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 540*FLEN/8, x4, x1, x2)
-
-inst_271:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x0bbcad and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d8bbcad; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 542*FLEN/8, x4, x1, x2)
-
-inst_272:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 544*FLEN/8, x4, x1, x2)
-
-inst_273:
-// fs1 == 0 and fe1 == 0xf7 and fm1 == 0x5f9448 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7bdf9448; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 546*FLEN/8, x4, x1, x2)
-
-inst_274:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x5f9448 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7bdf9448;
-   valaddr_reg:x3; val_offset:548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 548*FLEN/8, x4, x1, x2)
-
-inst_275:
-// fs1 == 0 and fe1 == 0xf7 and fm1 == 0x5f9448 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7bdf9448; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 550*FLEN/8, x4, x1, x2)
-
-inst_276:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x5f9448 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x7bdf9448;
-   valaddr_reg:x3; val_offset:552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 552*FLEN/8, x4, x1, x2)
-
-inst_277:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 554*FLEN/8, x4, x1, x2)
-
-inst_278:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 556*FLEN/8, x4, x1, x2)
-
-inst_279:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x19482d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0x19482d;
-   valaddr_reg:x3; val_offset:558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 558*FLEN/8, x4, x1, x2)
-
-inst_280:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 560*FLEN/8, x4, x1, x2)
-
-inst_281:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x19482d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x19482d;
-   valaddr_reg:x3; val_offset:562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 562*FLEN/8, x4, x1, x2)
-
-inst_282:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 564*FLEN/8, x4, x1, x2)
-
-inst_283:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 566*FLEN/8, x4, x1, x2)
-
-inst_284:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x19482d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x19482d;
-   valaddr_reg:x3; val_offset:568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 568*FLEN/8, x4, x1, x2)
-
-inst_285:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 570*FLEN/8, x4, x1, x2)
-
-inst_286:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 572*FLEN/8, x4, x1, x2)
-
-inst_287:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 574*FLEN/8, x4, x1, x2)
-
-inst_288:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 576*FLEN/8, x4, x1, x2)
-
-inst_289:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 578*FLEN/8, x4, x1, x2)
-
-inst_290:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 580*FLEN/8, x4, x1, x2)
-
-inst_291:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 582*FLEN/8, x4, x1, x2)
-
-inst_292:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 584*FLEN/8, x4, x1, x2)
-
-inst_293:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 586*FLEN/8, x4, x1, x2)
-
-inst_294:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x19482d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x19482d;
-   valaddr_reg:x3; val_offset:588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 588*FLEN/8, x4, x1, x2)
-
-inst_295:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 590*FLEN/8, x4, x1, x2)
-
-inst_296:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 592*FLEN/8, x4, x1, x2)
-
-inst_297:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 594*FLEN/8, x4, x1, x2)
-
-inst_298:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 596*FLEN/8, x4, x1, x2)
-
-inst_299:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x5b0376 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0xff5b0376;
-   valaddr_reg:x3; val_offset:598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 598*FLEN/8, x4, x1, x2)
-
-inst_300:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x19482d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x19482d;
-   valaddr_reg:x3; val_offset:600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 600*FLEN/8, x4, x1, x2)
-
-inst_301:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 602*FLEN/8, x4, x1, x2)
-
-inst_302:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 604*FLEN/8, x4, x1, x2)
-
-inst_303:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x19482d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x19482d; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 606*FLEN/8, x4, x1, x2)
-
-inst_304:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 608*FLEN/8, x4, x1, x2)
-
-inst_305:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028737 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x28737; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 610*FLEN/8, x4, x1, x2)
-
-inst_306:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x028737 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x28737;
-   valaddr_reg:x3; val_offset:612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 612*FLEN/8, x4, x1, x2)
-
-inst_307:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x028737 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x28737; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 614*FLEN/8, x4, x1, x2)
-
-inst_308:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x028737 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x28737;
-   valaddr_reg:x3; val_offset:616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 616*FLEN/8, x4, x1, x2)
-
-inst_309:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 618*FLEN/8, x4, x1, x2)
-
-inst_310:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x149808 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40149808; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 620*FLEN/8, x4, x1, x2)
-
-inst_311:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x149808 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40149808;
-   valaddr_reg:x3; val_offset:622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 622*FLEN/8, x4, x1, x2)
-
-inst_312:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x149808 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f2eabd8; op2val:0x40149808;
-   valaddr_reg:x3; val_offset:624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 624*FLEN/8, x4, x1, x2)
-
-inst_313:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 626*FLEN/8, x4, x1, x2)
-
-inst_314:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 628*FLEN/8, x4, x1, x2)
-
-inst_315:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 630*FLEN/8, x4, x1, x2)
-
-inst_316:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 632*FLEN/8, x4, x1, x2)
-
-inst_317:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 634*FLEN/8, x4, x1, x2)
-
-inst_318:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 636*FLEN/8, x4, x1, x2)
-
-inst_319:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 638*FLEN/8, x4, x1, x2)
-
-inst_320:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 640*FLEN/8, x4, x1, x2)
-
-inst_321:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 642*FLEN/8, x4, x1, x2)
-
-inst_322:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 644*FLEN/8, x4, x1, x2)
-
-inst_323:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 646*FLEN/8, x4, x1, x2)
-
-inst_324:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x36cde1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfd36cde1;
-   valaddr_reg:x3; val_offset:648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 648*FLEN/8, x4, x1, x2)
-
-inst_325:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x36cde1 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd36cde1; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 650*FLEN/8, x4, x1, x2)
-
-inst_326:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 652*FLEN/8, x4, x1, x2)
-
-inst_327:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 654*FLEN/8, x4, x1, x2)
-
-inst_328:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x7ff856 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfcfff856;
-   valaddr_reg:x3; val_offset:656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 656*FLEN/8, x4, x1, x2)
-
-inst_329:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7ff856 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfcfff856; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 658*FLEN/8, x4, x1, x2)
-
-inst_330:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 660*FLEN/8, x4, x1, x2)
-
-inst_331:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 662*FLEN/8, x4, x1, x2)
-
-inst_332:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 664*FLEN/8, x4, x1, x2)
-
-inst_333:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 666*FLEN/8, x4, x1, x2)
-
-inst_334:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x14b67a and fs2 == 1 and fe2 == 0xfc and fm2 == 0x043521 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc94b67a; op2val:0xfe043521;
-   valaddr_reg:x3; val_offset:668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 668*FLEN/8, x4, x1, x2)
-
-inst_335:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x043521 and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x14b67a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe043521; op2val:0xfc94b67a;
-   valaddr_reg:x3; val_offset:670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 670*FLEN/8, x4, x1, x2)
-
-inst_336:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x14b67a and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc94b67a; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 672*FLEN/8, x4, x1, x2)
-
-inst_337:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x14b67a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xfc94b67a;
-   valaddr_reg:x3; val_offset:674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 674*FLEN/8, x4, x1, x2)
-
-inst_338:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 676*FLEN/8, x4, x1, x2)
-
-inst_339:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x14c59d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x7d94c59d;
-   valaddr_reg:x3; val_offset:678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 678*FLEN/8, x4, x1, x2)
-
-inst_340:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x14c59d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d94c59d; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 680*FLEN/8, x4, x1, x2)
-
-inst_341:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 682*FLEN/8, x4, x1, x2)
-
-inst_342:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 684*FLEN/8, x4, x1, x2)
-
-inst_343:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 686*FLEN/8, x4, x1, x2)
-
-inst_344:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0aa123 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x7e0aa123;
-   valaddr_reg:x3; val_offset:688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 688*FLEN/8, x4, x1, x2)
-
-inst_345:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0aa123 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0aa123; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 690*FLEN/8, x4, x1, x2)
-
-inst_346:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 692*FLEN/8, x4, x1, x2)
-
-inst_347:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 694*FLEN/8, x4, x1, x2)
-
-inst_348:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x209de3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x7e209de3;
-   valaddr_reg:x3; val_offset:696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 696*FLEN/8, x4, x1, x2)
-
-inst_349:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x209de3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e209de3; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 698*FLEN/8, x4, x1, x2)
-
-inst_350:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 700*FLEN/8, x4, x1, x2)
-
-inst_351:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 702*FLEN/8, x4, x1, x2)
-
-inst_352:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x5abd82 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x7ddabd82;
-   valaddr_reg:x3; val_offset:704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 704*FLEN/8, x4, x1, x2)
-
-inst_353:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5abd82 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ddabd82; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 706*FLEN/8, x4, x1, x2)
-
-inst_354:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 708*FLEN/8, x4, x1, x2)
-
-inst_355:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 710*FLEN/8, x4, x1, x2)
-
-inst_356:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0f4d55 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x7e0f4d55;
-   valaddr_reg:x3; val_offset:712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 712*FLEN/8, x4, x1, x2)
-
-inst_357:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0f4d55 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0f4d55; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 714*FLEN/8, x4, x1, x2)
-
-inst_358:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 716*FLEN/8, x4, x1, x2)
-
-inst_359:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 718*FLEN/8, x4, x1, x2)
-
-inst_360:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03130e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0xfe03130e;
-   valaddr_reg:x3; val_offset:720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 720*FLEN/8, x4, x1, x2)
-
-inst_361:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03130e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03130e; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 722*FLEN/8, x4, x1, x2)
-
-inst_362:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 724*FLEN/8, x4, x1, x2)
-
-inst_363:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 726*FLEN/8, x4, x1, x2)
-
-inst_364:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x7671c2 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0xfdf671c2;
-   valaddr_reg:x3; val_offset:728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 728*FLEN/8, x4, x1, x2)
-
-inst_365:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x7671c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdf671c2; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 730*FLEN/8, x4, x1, x2)
-
-inst_366:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 732*FLEN/8, x4, x1, x2)
-
-inst_367:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 734*FLEN/8, x4, x1, x2)
-
-inst_368:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x2f35f8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0xfdaf35f8;
-   valaddr_reg:x3; val_offset:736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 736*FLEN/8, x4, x1, x2)
-
-inst_369:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x2f35f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdaf35f8; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 738*FLEN/8, x4, x1, x2)
-
-inst_370:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 740*FLEN/8, x4, x1, x2)
-
-inst_371:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 742*FLEN/8, x4, x1, x2)
-
-inst_372:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x048fde and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0xfe048fde;
-   valaddr_reg:x3; val_offset:744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 744*FLEN/8, x4, x1, x2)
-
-inst_373:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x048fde and fs2 == 1 and fe2 == 0x00 and fm2 == 0x4343c4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe048fde; op2val:0x804343c4;
-   valaddr_reg:x3; val_offset:746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 746*FLEN/8, x4, x1, x2)
-
-inst_374:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x4343c4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x804343c4; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 748*FLEN/8, x4, x1, x2)
-
-inst_375:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 750*FLEN/8, x4, x1, x2)
-
-inst_376:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x06b9fa and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2d09bb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8006b9fa; op2val:0xfe2d09bb;
-   valaddr_reg:x3; val_offset:752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 752*FLEN/8, x4, x1, x2)
-
-inst_377:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2d09bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x06b9fa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2d09bb; op2val:0x8006b9fa;
-   valaddr_reg:x3; val_offset:754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 754*FLEN/8, x4, x1, x2)
-
-inst_378:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x06b9fa and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8006b9fa; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 756*FLEN/8, x4, x1, x2)
-
-inst_379:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x06b9fa and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x8006b9fa;
-   valaddr_reg:x3; val_offset:758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 758*FLEN/8, x4, x1, x2)
-
-inst_380:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 760*FLEN/8, x4, x1, x2)
-
-inst_381:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x45ac58 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc0c5ac58; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 762*FLEN/8, x4, x1, x2)
-
-inst_382:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x45ac58 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc0c5ac58;
-   valaddr_reg:x3; val_offset:764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 764*FLEN/8, x4, x1, x2)
-
-inst_383:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x39e419 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x45ac58 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe39e419; op2val:0xc0c5ac58;
-   valaddr_reg:x3; val_offset:766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 766*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_4)
-
-inst_384:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 768*FLEN/8, x4, x1, x2)
-
-inst_385:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 770*FLEN/8, x4, x1, x2)
-
-inst_386:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x36cde1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd36cde1; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 772*FLEN/8, x4, x1, x2)
-
-inst_387:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0xfa and fm2 == 0x36cde1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xfd36cde1;
-   valaddr_reg:x3; val_offset:774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 774*FLEN/8, x4, x1, x2)
-
-inst_388:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 776*FLEN/8, x4, x1, x2)
-
-inst_389:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x36cde1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd36cde1; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 778*FLEN/8, x4, x1, x2)
-
-inst_390:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 780*FLEN/8, x4, x1, x2)
-
-inst_391:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 782*FLEN/8, x4, x1, x2)
-
-inst_392:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 784*FLEN/8, x4, x1, x2)
-
-inst_393:
-// fs1 == 1 and fe1 == 0xfa and fm1 == 0x36cde1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfd36cde1; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 786*FLEN/8, x4, x1, x2)
-
-inst_394:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 788*FLEN/8, x4, x1, x2)
-
-inst_395:
-// fs1 == 1 and fe1 == 0xf7 and fm1 == 0x123e4e and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfb923e4e; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 790*FLEN/8, x4, x1, x2)
-
-inst_396:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xf7 and fm2 == 0x123e4e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfb923e4e;
-   valaddr_reg:x3; val_offset:792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 792*FLEN/8, x4, x1, x2)
-
-inst_397:
-// fs1 == 1 and fe1 == 0xf7 and fm1 == 0x123e4e and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfb923e4e; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 794*FLEN/8, x4, x1, x2)
-
-inst_398:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0xf7 and fm2 == 0x123e4e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xfb923e4e;
-   valaddr_reg:x3; val_offset:796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 796*FLEN/8, x4, x1, x2)
-
-inst_399:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 798*FLEN/8, x4, x1, x2)
-
-inst_400:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 800*FLEN/8, x4, x1, x2)
-
-inst_401:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108974 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0x80108974;
-   valaddr_reg:x3; val_offset:802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 802*FLEN/8, x4, x1, x2)
-
-inst_402:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 804*FLEN/8, x4, x1, x2)
-
-inst_403:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108974 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x80108974;
-   valaddr_reg:x3; val_offset:806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 806*FLEN/8, x4, x1, x2)
-
-inst_404:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 808*FLEN/8, x4, x1, x2)
-
-inst_405:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 810*FLEN/8, x4, x1, x2)
-
-inst_406:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108974 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x80108974;
-   valaddr_reg:x3; val_offset:812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 812*FLEN/8, x4, x1, x2)
-
-inst_407:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 814*FLEN/8, x4, x1, x2)
-
-inst_408:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 816*FLEN/8, x4, x1, x2)
-
-inst_409:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 818*FLEN/8, x4, x1, x2)
-
-inst_410:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 820*FLEN/8, x4, x1, x2)
-
-inst_411:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 822*FLEN/8, x4, x1, x2)
-
-inst_412:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 824*FLEN/8, x4, x1, x2)
-
-inst_413:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 826*FLEN/8, x4, x1, x2)
-
-inst_414:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 828*FLEN/8, x4, x1, x2)
-
-inst_415:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 830*FLEN/8, x4, x1, x2)
-
-inst_416:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108974 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80108974;
-   valaddr_reg:x3; val_offset:832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 832*FLEN/8, x4, x1, x2)
-
-inst_417:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 834*FLEN/8, x4, x1, x2)
-
-inst_418:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 836*FLEN/8, x4, x1, x2)
-
-inst_419:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 838*FLEN/8, x4, x1, x2)
-
-inst_420:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 840*FLEN/8, x4, x1, x2)
-
-inst_421:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x5b0376 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0xff5b0376;
-   valaddr_reg:x3; val_offset:842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 842*FLEN/8, x4, x1, x2)
-
-inst_422:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x108974 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x80108974;
-   valaddr_reg:x3; val_offset:844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 844*FLEN/8, x4, x1, x2)
-
-inst_423:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 846*FLEN/8, x4, x1, x2)
-
-inst_424:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 848*FLEN/8, x4, x1, x2)
-
-inst_425:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x108974 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80108974; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 850*FLEN/8, x4, x1, x2)
-
-inst_426:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 852*FLEN/8, x4, x1, x2)
-
-inst_427:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01a758 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8001a758; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 854*FLEN/8, x4, x1, x2)
-
-inst_428:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a758 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x8001a758;
-   valaddr_reg:x3; val_offset:856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 856*FLEN/8, x4, x1, x2)
-
-inst_429:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x01a758 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8001a758; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 858*FLEN/8, x4, x1, x2)
-
-inst_430:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x00 and fm2 == 0x01a758 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x8001a758;
-   valaddr_reg:x3; val_offset:860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 860*FLEN/8, x4, x1, x2)
-
-inst_431:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 862*FLEN/8, x4, x1, x2)
-
-inst_432:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x42640b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbfc2640b; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 864*FLEN/8, x4, x1, x2)
-
-inst_433:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x42640b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xbfc2640b;
-   valaddr_reg:x3; val_offset:866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 866*FLEN/8, x4, x1, x2)
-
-inst_434:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 1 and fe2 == 0x7f and fm2 == 0x42640b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfee4815a; op2val:0xbfc2640b;
-   valaddr_reg:x3; val_offset:868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 868*FLEN/8, x4, x1, x2)
-
-inst_435:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 870*FLEN/8, x4, x1, x2)
-
-inst_436:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 872*FLEN/8, x4, x1, x2)
-
-inst_437:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7ff856 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfcfff856; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 874*FLEN/8, x4, x1, x2)
-
-inst_438:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x7ff856 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xfcfff856;
-   valaddr_reg:x3; val_offset:876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 876*FLEN/8, x4, x1, x2)
-
-inst_439:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 878*FLEN/8, x4, x1, x2)
-
-inst_440:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7ff856 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfcfff856; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 880*FLEN/8, x4, x1, x2)
-
-inst_441:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 882*FLEN/8, x4, x1, x2)
-
-inst_442:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x7ff856 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfcfff856; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 884*FLEN/8, x4, x1, x2)
-
-inst_443:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 886*FLEN/8, x4, x1, x2)
-
-inst_444:
-// fs1 == 1 and fe1 == 0xf6 and fm1 == 0x4cc6ab and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfb4cc6ab; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 888*FLEN/8, x4, x1, x2)
-
-inst_445:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xf6 and fm2 == 0x4cc6ab and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0xfb4cc6ab;
-   valaddr_reg:x3; val_offset:890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 890*FLEN/8, x4, x1, x2)
-
-inst_446:
-// fs1 == 1 and fe1 == 0xf6 and fm1 == 0x4cc6ab and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfb4cc6ab; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 892*FLEN/8, x4, x1, x2)
-
-inst_447:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0xf6 and fm2 == 0x4cc6ab and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xfb4cc6ab;
-   valaddr_reg:x3; val_offset:894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 894*FLEN/8, x4, x1, x2)
-
-inst_448:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 896*FLEN/8, x4, x1, x2)
-
-inst_449:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 898*FLEN/8, x4, x1, x2)
-
-inst_450:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0b93ee and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0x800b93ee;
-   valaddr_reg:x3; val_offset:900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 900*FLEN/8, x4, x1, x2)
-
-inst_451:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 902*FLEN/8, x4, x1, x2)
-
-inst_452:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0b93ee and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x800b93ee;
-   valaddr_reg:x3; val_offset:904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 904*FLEN/8, x4, x1, x2)
-
-inst_453:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 906*FLEN/8, x4, x1, x2)
-
-inst_454:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 908*FLEN/8, x4, x1, x2)
-
-inst_455:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0b93ee and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f7fffff; op2val:0x800b93ee;
-   valaddr_reg:x3; val_offset:910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 910*FLEN/8, x4, x1, x2)
-
-inst_456:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 912*FLEN/8, x4, x1, x2)
-
-inst_457:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 914*FLEN/8, x4, x1, x2)
-
-inst_458:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 916*FLEN/8, x4, x1, x2)
-
-inst_459:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 918*FLEN/8, x4, x1, x2)
-
-inst_460:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 920*FLEN/8, x4, x1, x2)
-
-inst_461:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 922*FLEN/8, x4, x1, x2)
-
-inst_462:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 924*FLEN/8, x4, x1, x2)
-
-inst_463:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 926*FLEN/8, x4, x1, x2)
-
-inst_464:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 928*FLEN/8, x4, x1, x2)
-
-inst_465:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0b93ee and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x800b93ee;
-   valaddr_reg:x3; val_offset:930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 930*FLEN/8, x4, x1, x2)
-
-inst_466:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 932*FLEN/8, x4, x1, x2)
-
-inst_467:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 934*FLEN/8, x4, x1, x2)
-
-inst_468:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 936*FLEN/8, x4, x1, x2)
-
-inst_469:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 938*FLEN/8, x4, x1, x2)
-
-inst_470:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 1 and fe2 == 0xfe and fm2 == 0x5b0376 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0xff5b0376;
-   valaddr_reg:x3; val_offset:940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 940*FLEN/8, x4, x1, x2)
-
-inst_471:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0b93ee and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x800b93ee;
-   valaddr_reg:x3; val_offset:942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 942*FLEN/8, x4, x1, x2)
-
-inst_472:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 944*FLEN/8, x4, x1, x2)
-
-inst_473:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 946*FLEN/8, x4, x1, x2)
-
-inst_474:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0b93ee and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800b93ee; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 948*FLEN/8, x4, x1, x2)
-
-inst_475:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 950*FLEN/8, x4, x1, x2)
-
-inst_476:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x012864 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80012864; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 952*FLEN/8, x4, x1, x2)
-
-inst_477:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0x00 and fm2 == 0x012864 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff7fffff; op2val:0x80012864;
-   valaddr_reg:x3; val_offset:954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 954*FLEN/8, x4, x1, x2)
-
-inst_478:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x012864 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80012864; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 956*FLEN/8, x4, x1, x2)
-
-inst_479:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x012864 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x80012864;
-   valaddr_reg:x3; val_offset:958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 958*FLEN/8, x4, x1, x2)
-
-inst_480:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 960*FLEN/8, x4, x1, x2)
-
-inst_481:
-// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0818d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xbf8818d6; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 962*FLEN/8, x4, x1, x2)
-
-inst_482:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x0818d6 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xbf8818d6;
-   valaddr_reg:x3; val_offset:964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 964*FLEN/8, x4, x1, x2)
-
-inst_483:
-// fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x0818d6 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe9ffb35; op2val:0xbf8818d6;
-   valaddr_reg:x3; val_offset:966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 966*FLEN/8, x4, x1, x2)
-
-inst_484:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 968*FLEN/8, x4, x1, x2)
-
-inst_485:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 970*FLEN/8, x4, x1, x2)
-
-inst_486:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 972*FLEN/8, x4, x1, x2)
-
-inst_487:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 974*FLEN/8, x4, x1, x2)
-
-inst_488:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 976*FLEN/8, x4, x1, x2)
-
-inst_489:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 978*FLEN/8, x4, x1, x2)
-
-inst_490:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 980*FLEN/8, x4, x1, x2)
-
-inst_491:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 982*FLEN/8, x4, x1, x2)
-
-inst_492:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 984*FLEN/8, x4, x1, x2)
-
-inst_493:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x1608ad and fs2 == 1 and fe2 == 0xfc and fm2 == 0x043521 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc9608ad; op2val:0xfe043521;
-   valaddr_reg:x3; val_offset:986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 986*FLEN/8, x4, x1, x2)
-
-inst_494:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x043521 and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x1608ad and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe043521; op2val:0xfc9608ad;
-   valaddr_reg:x3; val_offset:988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 988*FLEN/8, x4, x1, x2)
-
-inst_495:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x1608ad and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc9608ad; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:990*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 990*FLEN/8, x4, x1, x2)
-
-inst_496:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x1608ad and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xfc9608ad;
-   valaddr_reg:x3; val_offset:992*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 992*FLEN/8, x4, x1, x2)
-
-inst_497:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:994*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 994*FLEN/8, x4, x1, x2)
-
-inst_498:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0xfb and fm2 == 0x14c59d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x7d94c59d;
-   valaddr_reg:x3; val_offset:996*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 996*FLEN/8, x4, x1, x2)
-
-inst_499:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x14c59d and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d94c59d; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:998*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 998*FLEN/8, x4, x1, x2)
-
-inst_500:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1000*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1000*FLEN/8, x4, x1, x2)
-
-inst_501:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1002*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1002*FLEN/8, x4, x1, x2)
-
-inst_502:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1004*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1004*FLEN/8, x4, x1, x2)
-
-inst_503:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0aa123 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x7e0aa123;
-   valaddr_reg:x3; val_offset:1006*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1006*FLEN/8, x4, x1, x2)
-
-inst_504:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0aa123 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0aa123; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1008*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1008*FLEN/8, x4, x1, x2)
-
-inst_505:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1010*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1010*FLEN/8, x4, x1, x2)
-
-inst_506:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1012*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1012*FLEN/8, x4, x1, x2)
-
-inst_507:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0xfc and fm2 == 0x209de3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x7e209de3;
-   valaddr_reg:x3; val_offset:1014*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1014*FLEN/8, x4, x1, x2)
-
-inst_508:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x209de3 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e209de3; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1016*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1016*FLEN/8, x4, x1, x2)
-
-inst_509:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1018*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1018*FLEN/8, x4, x1, x2)
-
-inst_510:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1020*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1020*FLEN/8, x4, x1, x2)
-
-inst_511:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0xfb and fm2 == 0x5abd82 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x7ddabd82;
-   valaddr_reg:x3; val_offset:1022*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1022*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_5)
-
-inst_512:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5abd82 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ddabd82; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1024*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1024*FLEN/8, x4, x1, x2)
-
-inst_513:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1026*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1026*FLEN/8, x4, x1, x2)
-
-inst_514:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1028*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1028*FLEN/8, x4, x1, x2)
-
-inst_515:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0f4d55 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x7e0f4d55;
-   valaddr_reg:x3; val_offset:1030*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1030*FLEN/8, x4, x1, x2)
-
-inst_516:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0f4d55 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0f4d55; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1032*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1032*FLEN/8, x4, x1, x2)
-
-inst_517:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1034*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1034*FLEN/8, x4, x1, x2)
-
-inst_518:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1036*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1036*FLEN/8, x4, x1, x2)
-
-inst_519:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03130e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0xfe03130e;
-   valaddr_reg:x3; val_offset:1038*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1038*FLEN/8, x4, x1, x2)
-
-inst_520:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03130e and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03130e; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1040*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1040*FLEN/8, x4, x1, x2)
-
-inst_521:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1042*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1042*FLEN/8, x4, x1, x2)
-
-inst_522:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1044*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1044*FLEN/8, x4, x1, x2)
-
-inst_523:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0xfb and fm2 == 0x7671c2 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0xfdf671c2;
-   valaddr_reg:x3; val_offset:1046*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1046*FLEN/8, x4, x1, x2)
-
-inst_524:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x7671c2 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdf671c2; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1048*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1048*FLEN/8, x4, x1, x2)
-
-inst_525:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1050*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1050*FLEN/8, x4, x1, x2)
-
-inst_526:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1052*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1052*FLEN/8, x4, x1, x2)
-
-inst_527:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0xfb and fm2 == 0x2f35f8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0xfdaf35f8;
-   valaddr_reg:x3; val_offset:1054*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1054*FLEN/8, x4, x1, x2)
-
-inst_528:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x2f35f8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdaf35f8; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1056*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1056*FLEN/8, x4, x1, x2)
-
-inst_529:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1058*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1058*FLEN/8, x4, x1, x2)
-
-inst_530:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1060*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1060*FLEN/8, x4, x1, x2)
-
-inst_531:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0xfc and fm2 == 0x048fde and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0xfe048fde;
-   valaddr_reg:x3; val_offset:1062*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1062*FLEN/8, x4, x1, x2)
-
-inst_532:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x048fde and fs2 == 1 and fe2 == 0x00 and fm2 == 0x43dcbc and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe048fde; op2val:0x8043dcbc;
-   valaddr_reg:x3; val_offset:1064*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1064*FLEN/8, x4, x1, x2)
-
-inst_533:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x43dcbc and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8043dcbc; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1066*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1066*FLEN/8, x4, x1, x2)
-
-inst_534:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1068*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1068*FLEN/8, x4, x1, x2)
-
-inst_535:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x06c946 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2d09bb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8006c946; op2val:0xfe2d09bb;
-   valaddr_reg:x3; val_offset:1070*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1070*FLEN/8, x4, x1, x2)
-
-inst_536:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2d09bb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x06c946 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2d09bb; op2val:0x8006c946;
-   valaddr_reg:x3; val_offset:1072*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1072*FLEN/8, x4, x1, x2)
-
-inst_537:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x06c946 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8006c946; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1074*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1074*FLEN/8, x4, x1, x2)
-
-inst_538:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x06c946 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x8006c946;
-   valaddr_reg:x3; val_offset:1076*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1076*FLEN/8, x4, x1, x2)
-
-inst_539:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1078*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1078*FLEN/8, x4, x1, x2)
-
-inst_540:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x476de3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc0c76de3; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1080*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1080*FLEN/8, x4, x1, x2)
-
-inst_541:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x476de3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc0c76de3;
-   valaddr_reg:x3; val_offset:1082*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1082*FLEN/8, x4, x1, x2)
-
-inst_542:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x3b8ad8 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x476de3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe3b8ad8; op2val:0xc0c76de3;
-   valaddr_reg:x3; val_offset:1084*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1084*FLEN/8, x4, x1, x2)
-
-inst_543:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1086*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1086*FLEN/8, x4, x1, x2)
-
-inst_544:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1088*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1088*FLEN/8, x4, x1, x2)
-
-inst_545:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1090*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1090*FLEN/8, x4, x1, x2)
-
-inst_546:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1092*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1092*FLEN/8, x4, x1, x2)
-
-inst_547:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1094*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1094*FLEN/8, x4, x1, x2)
-
-inst_548:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1096*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1096*FLEN/8, x4, x1, x2)
-
-inst_549:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x043521 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe043521; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1098*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1098*FLEN/8, x4, x1, x2)
-
-inst_550:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x043521 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xfe043521;
-   valaddr_reg:x3; val_offset:1100*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1100*FLEN/8, x4, x1, x2)
-
-inst_551:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1102*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1102*FLEN/8, x4, x1, x2)
-
-inst_552:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1104*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1104*FLEN/8, x4, x1, x2)
-
-inst_553:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x043521 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe043521; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1106*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1106*FLEN/8, x4, x1, x2)
-
-inst_554:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1108*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1108*FLEN/8, x4, x1, x2)
-
-inst_555:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1110*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1110*FLEN/8, x4, x1, x2)
-
-inst_556:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1112*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1112*FLEN/8, x4, x1, x2)
-
-inst_557:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x043521 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe043521; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1114*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1114*FLEN/8, x4, x1, x2)
-
-inst_558:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1116*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1116*FLEN/8, x4, x1, x2)
-
-inst_559:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x6e08fb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x7bee08fb;
-   valaddr_reg:x3; val_offset:1118*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1118*FLEN/8, x4, x1, x2)
-
-inst_560:
-// fs1 == 0 and fe1 == 0xf7 and fm1 == 0x6e08fb and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7bee08fb; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1120*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1120*FLEN/8, x4, x1, x2)
-
-inst_561:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1122*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1122*FLEN/8, x4, x1, x2)
-
-inst_562:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1124*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1124*FLEN/8, x4, x1, x2)
-
-inst_563:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1126*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1126*FLEN/8, x4, x1, x2)
-
-inst_564:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0xf8 and fm2 == 0x5dce9f and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x7c5dce9f;
-   valaddr_reg:x3; val_offset:1128*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1128*FLEN/8, x4, x1, x2)
-
-inst_565:
-// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x5dce9f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c5dce9f; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1130*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1130*FLEN/8, x4, x1, x2)
-
-inst_566:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1132*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1132*FLEN/8, x4, x1, x2)
-
-inst_567:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1134*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1134*FLEN/8, x4, x1, x2)
-
-inst_568:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x007e4f and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x7c807e4f;
-   valaddr_reg:x3; val_offset:1136*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1136*FLEN/8, x4, x1, x2)
-
-inst_569:
-// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x007e4f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c807e4f; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1138*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1138*FLEN/8, x4, x1, x2)
-
-inst_570:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1140*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1140*FLEN/8, x4, x1, x2)
-
-inst_571:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1142*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1142*FLEN/8, x4, x1, x2)
-
-inst_572:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0xf8 and fm2 == 0x2efe01 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x7c2efe01;
-   valaddr_reg:x3; val_offset:1144*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1144*FLEN/8, x4, x1, x2)
-
-inst_573:
-// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x2efe01 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c2efe01; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1146*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1146*FLEN/8, x4, x1, x2)
-
-inst_574:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1148*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1148*FLEN/8, x4, x1, x2)
-
-inst_575:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1150*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1150*FLEN/8, x4, x1, x2)
-
-inst_576:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0xf8 and fm2 == 0x654888 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x7c654888;
-   valaddr_reg:x3; val_offset:1152*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1152*FLEN/8, x4, x1, x2)
-
-inst_577:
-// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x654888 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c654888; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1154*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1154*FLEN/8, x4, x1, x2)
-
-inst_578:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1156*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1156*FLEN/8, x4, x1, x2)
-
-inst_579:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1158*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1158*FLEN/8, x4, x1, x2)
-
-inst_580:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x51b817 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0xfc51b817;
-   valaddr_reg:x3; val_offset:1160*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1160*FLEN/8, x4, x1, x2)
-
-inst_581:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x51b817 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc51b817; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1162*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1162*FLEN/8, x4, x1, x2)
-
-inst_582:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1164*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1164*FLEN/8, x4, x1, x2)
-
-inst_583:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1166*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1166*FLEN/8, x4, x1, x2)
-
-inst_584:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x4527ce and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0xfc4527ce;
-   valaddr_reg:x3; val_offset:1168*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1168*FLEN/8, x4, x1, x2)
-
-inst_585:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x4527ce and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc4527ce; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1170*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1170*FLEN/8, x4, x1, x2)
-
-inst_586:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1172*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1172*FLEN/8, x4, x1, x2)
-
-inst_587:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1174*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1174*FLEN/8, x4, x1, x2)
-
-inst_588:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x0c2b2c and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0xfc0c2b2c;
-   valaddr_reg:x3; val_offset:1176*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1176*FLEN/8, x4, x1, x2)
-
-inst_589:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x0c2b2c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc0c2b2c; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1178*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1178*FLEN/8, x4, x1, x2)
-
-inst_590:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1180*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1180*FLEN/8, x4, x1, x2)
-
-inst_591:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1182*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1182*FLEN/8, x4, x1, x2)
-
-inst_592:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x541963 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0xfc541963;
-   valaddr_reg:x3; val_offset:1184*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1184*FLEN/8, x4, x1, x2)
-
-inst_593:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x541963 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2fd6de and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc541963; op2val:0x802fd6de;
-   valaddr_reg:x3; val_offset:1186*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1186*FLEN/8, x4, x1, x2)
-
-inst_594:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2fd6de and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802fd6de; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1188*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1188*FLEN/8, x4, x1, x2)
-
-inst_595:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1190*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1190*FLEN/8, x4, x1, x2)
-
-inst_596:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04c8af and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x0a6e2f and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8004c8af; op2val:0xfc8a6e2f;
-   valaddr_reg:x3; val_offset:1192*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1192*FLEN/8, x4, x1, x2)
-
-inst_597:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x0a6e2f and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04c8af and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc8a6e2f; op2val:0x8004c8af;
-   valaddr_reg:x3; val_offset:1194*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1194*FLEN/8, x4, x1, x2)
-
-inst_598:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04c8af and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8004c8af; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1196*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1196*FLEN/8, x4, x1, x2)
-
-inst_599:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04c8af and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x8004c8af;
-   valaddr_reg:x3; val_offset:1198*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1198*FLEN/8, x4, x1, x2)
-
-inst_600:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1200*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1200*FLEN/8, x4, x1, x2)
-
-inst_601:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x0c9650 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc08c9650; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1202*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1202*FLEN/8, x4, x1, x2)
-
-inst_602:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0c9650 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc08c9650;
-   valaddr_reg:x3; val_offset:1204*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1204*FLEN/8, x4, x1, x2)
-
-inst_603:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x538835 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0c9650 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc538835; op2val:0xc08c9650;
-   valaddr_reg:x3; val_offset:1206*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1206*FLEN/8, x4, x1, x2)
-
-inst_604:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1208*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1208*FLEN/8, x4, x1, x2)
-
-inst_605:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1210*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1210*FLEN/8, x4, x1, x2)
-
-inst_606:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7f39f704;
-   valaddr_reg:x3; val_offset:1212*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1212*FLEN/8, x4, x1, x2)
-
-inst_607:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1214*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1214*FLEN/8, x4, x1, x2)
-
-inst_608:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1216*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1216*FLEN/8, x4, x1, x2)
-
-inst_609:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1218*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1218*FLEN/8, x4, x1, x2)
-
-inst_610:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1220*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1220*FLEN/8, x4, x1, x2)
-
-inst_611:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1222*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1222*FLEN/8, x4, x1, x2)
-
-inst_612:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1224*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1224*FLEN/8, x4, x1, x2)
-
-inst_613:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x14c59d and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d94c59d; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1226*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1226*FLEN/8, x4, x1, x2)
-
-inst_614:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x14c59d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7d94c59d;
-   valaddr_reg:x3; val_offset:1228*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1228*FLEN/8, x4, x1, x2)
-
-inst_615:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1230*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1230*FLEN/8, x4, x1, x2)
-
-inst_616:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1232*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1232*FLEN/8, x4, x1, x2)
-
-inst_617:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1234*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1234*FLEN/8, x4, x1, x2)
-
-inst_618:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x14c59d and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d94c59d; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1236*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1236*FLEN/8, x4, x1, x2)
-
-inst_619:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1238*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1238*FLEN/8, x4, x1, x2)
-
-inst_620:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1240*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1240*FLEN/8, x4, x1, x2)
-
-inst_621:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1242*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1242*FLEN/8, x4, x1, x2)
-
-inst_622:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f39f704; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1244*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1244*FLEN/8, x4, x1, x2)
-
-inst_623:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1246*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1246*FLEN/8, x4, x1, x2)
-
-inst_624:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x14c59d and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7d94c59d; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1248*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1248*FLEN/8, x4, x1, x2)
-
-inst_625:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1250*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1250*FLEN/8, x4, x1, x2)
-
-inst_626:
-// fs1 == 0 and fe1 == 0xf7 and fm1 == 0x6e08fb and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7bee08fb; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1252*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1252*FLEN/8, x4, x1, x2)
-
-inst_627:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x6e08fb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7bee08fb;
-   valaddr_reg:x3; val_offset:1254*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1254*FLEN/8, x4, x1, x2)
-
-inst_628:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1256*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1256*FLEN/8, x4, x1, x2)
-
-inst_629:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1258*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1258*FLEN/8, x4, x1, x2)
-
-inst_630:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1260*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1260*FLEN/8, x4, x1, x2)
-
-inst_631:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1262*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1262*FLEN/8, x4, x1, x2)
-
-inst_632:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1264*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1264*FLEN/8, x4, x1, x2)
-
-inst_633:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1266*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1266*FLEN/8, x4, x1, x2)
-
-inst_634:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1268*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1268*FLEN/8, x4, x1, x2)
-
-inst_635:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1270*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1270*FLEN/8, x4, x1, x2)
-
-inst_636:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1272*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1272*FLEN/8, x4, x1, x2)
-
-inst_637:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1274*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1274*FLEN/8, x4, x1, x2)
-
-inst_638:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1276*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1276*FLEN/8, x4, x1, x2)
-
-inst_639:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1278*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1278*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_6)
-
-inst_640:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1280*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1280*FLEN/8, x4, x1, x2)
-
-inst_641:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1282*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1282*FLEN/8, x4, x1, x2)
-
-inst_642:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1284*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1284*FLEN/8, x4, x1, x2)
-
-inst_643:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1286*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1286*FLEN/8, x4, x1, x2)
-
-inst_644:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1288*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1288*FLEN/8, x4, x1, x2)
-
-inst_645:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b110 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2b110; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1290*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1290*FLEN/8, x4, x1, x2)
-
-inst_646:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02b110 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x2b110;
-   valaddr_reg:x3; val_offset:1292*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1292*FLEN/8, x4, x1, x2)
-
-inst_647:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x02b110 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x2b110; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1294*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1294*FLEN/8, x4, x1, x2)
-
-inst_648:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02b110 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x2b110;
-   valaddr_reg:x3; val_offset:1296*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1296*FLEN/8, x4, x1, x2)
-
-inst_649:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1298*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1298*FLEN/8, x4, x1, x2)
-
-inst_650:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x1e3392 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x401e3392; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1300*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1300*FLEN/8, x4, x1, x2)
-
-inst_651:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1e3392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x401e3392;
-   valaddr_reg:x3; val_offset:1302*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1302*FLEN/8, x4, x1, x2)
-
-inst_652:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x1aeaa5 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x1e3392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x1aeaa5; op2val:0x401e3392;
-   valaddr_reg:x3; val_offset:1304*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1304*FLEN/8, x4, x1, x2)
-
-inst_653:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1306*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1306*FLEN/8, x4, x1, x2)
-
-inst_654:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1308*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1308*FLEN/8, x4, x1, x2)
-
-inst_655:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1310*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1310*FLEN/8, x4, x1, x2)
-
-inst_656:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1312*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1312*FLEN/8, x4, x1, x2)
-
-inst_657:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1314*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1314*FLEN/8, x4, x1, x2)
-
-inst_658:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1316*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1316*FLEN/8, x4, x1, x2)
-
-inst_659:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0aa123 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0aa123; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1318*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1318*FLEN/8, x4, x1, x2)
-
-inst_660:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0aa123 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7e0aa123;
-   valaddr_reg:x3; val_offset:1320*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1320*FLEN/8, x4, x1, x2)
-
-inst_661:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1322*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1322*FLEN/8, x4, x1, x2)
-
-inst_662:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1324*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1324*FLEN/8, x4, x1, x2)
-
-inst_663:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0aa123 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0aa123; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1326*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1326*FLEN/8, x4, x1, x2)
-
-inst_664:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1328*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1328*FLEN/8, x4, x1, x2)
-
-inst_665:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1330*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1330*FLEN/8, x4, x1, x2)
-
-inst_666:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1332*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1332*FLEN/8, x4, x1, x2)
-
-inst_667:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0aa123 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0aa123; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1334*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1334*FLEN/8, x4, x1, x2)
-
-inst_668:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1336*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1336*FLEN/8, x4, x1, x2)
-
-inst_669:
-// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x5dce9f and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c5dce9f; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1338*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1338*FLEN/8, x4, x1, x2)
-
-inst_670:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0xf8 and fm2 == 0x5dce9f and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7c5dce9f;
-   valaddr_reg:x3; val_offset:1340*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1340*FLEN/8, x4, x1, x2)
-
-inst_671:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1342*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1342*FLEN/8, x4, x1, x2)
-
-inst_672:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1344*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1344*FLEN/8, x4, x1, x2)
-
-inst_673:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1346*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1346*FLEN/8, x4, x1, x2)
-
-inst_674:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1348*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1348*FLEN/8, x4, x1, x2)
-
-inst_675:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1350*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1350*FLEN/8, x4, x1, x2)
-
-inst_676:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1352*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1352*FLEN/8, x4, x1, x2)
-
-inst_677:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1354*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1354*FLEN/8, x4, x1, x2)
-
-inst_678:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1356*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1356*FLEN/8, x4, x1, x2)
-
-inst_679:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1358*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1358*FLEN/8, x4, x1, x2)
-
-inst_680:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1360*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1360*FLEN/8, x4, x1, x2)
-
-inst_681:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1362*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1362*FLEN/8, x4, x1, x2)
-
-inst_682:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1364*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1364*FLEN/8, x4, x1, x2)
-
-inst_683:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1366*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1366*FLEN/8, x4, x1, x2)
-
-inst_684:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1368*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1368*FLEN/8, x4, x1, x2)
-
-inst_685:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1370*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1370*FLEN/8, x4, x1, x2)
-
-inst_686:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05042c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x5042c; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1372*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1372*FLEN/8, x4, x1, x2)
-
-inst_687:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05042c and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x5042c;
-   valaddr_reg:x3; val_offset:1374*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1374*FLEN/8, x4, x1, x2)
-
-inst_688:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05042c and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x5042c; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1376*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1376*FLEN/8, x4, x1, x2)
-
-inst_689:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05042c and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x5042c;
-   valaddr_reg:x3; val_offset:1378*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1378*FLEN/8, x4, x1, x2)
-
-inst_690:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1380*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1380*FLEN/8, x4, x1, x2)
-
-inst_691:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x136a86 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40936a86; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1382*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1382*FLEN/8, x4, x1, x2)
-
-inst_692:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x136a86 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40936a86;
-   valaddr_reg:x3; val_offset:1384*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1384*FLEN/8, x4, x1, x2)
-
-inst_693:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3229c1 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x136a86 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3229c1; op2val:0x40936a86;
-   valaddr_reg:x3; val_offset:1386*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1386*FLEN/8, x4, x1, x2)
-
-inst_694:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1388*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1388*FLEN/8, x4, x1, x2)
-
-inst_695:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1390*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1390*FLEN/8, x4, x1, x2)
-
-inst_696:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1392*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1392*FLEN/8, x4, x1, x2)
-
-inst_697:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1394*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1394*FLEN/8, x4, x1, x2)
-
-inst_698:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1396*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1396*FLEN/8, x4, x1, x2)
-
-inst_699:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1398*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1398*FLEN/8, x4, x1, x2)
-
-inst_700:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x209de3 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e209de3; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1400*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1400*FLEN/8, x4, x1, x2)
-
-inst_701:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x209de3 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7e209de3;
-   valaddr_reg:x3; val_offset:1402*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1402*FLEN/8, x4, x1, x2)
-
-inst_702:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1404*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1404*FLEN/8, x4, x1, x2)
-
-inst_703:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1406*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1406*FLEN/8, x4, x1, x2)
-
-inst_704:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x209de3 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e209de3; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1408*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1408*FLEN/8, x4, x1, x2)
-
-inst_705:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1410*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1410*FLEN/8, x4, x1, x2)
-
-inst_706:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1412*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1412*FLEN/8, x4, x1, x2)
-
-inst_707:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1414*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1414*FLEN/8, x4, x1, x2)
-
-inst_708:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x209de3 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e209de3; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1416*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1416*FLEN/8, x4, x1, x2)
-
-inst_709:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1418*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1418*FLEN/8, x4, x1, x2)
-
-inst_710:
-// fs1 == 0 and fe1 == 0xf9 and fm1 == 0x007e4f and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c807e4f; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1420*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1420*FLEN/8, x4, x1, x2)
-
-inst_711:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0xf9 and fm2 == 0x007e4f and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7c807e4f;
-   valaddr_reg:x3; val_offset:1422*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1422*FLEN/8, x4, x1, x2)
-
-inst_712:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1424*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1424*FLEN/8, x4, x1, x2)
-
-inst_713:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1426*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1426*FLEN/8, x4, x1, x2)
-
-inst_714:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1428*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1428*FLEN/8, x4, x1, x2)
-
-inst_715:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1430*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1430*FLEN/8, x4, x1, x2)
-
-inst_716:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1432*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1432*FLEN/8, x4, x1, x2)
-
-inst_717:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1434*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1434*FLEN/8, x4, x1, x2)
-
-inst_718:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1436*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1436*FLEN/8, x4, x1, x2)
-
-inst_719:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1438*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1438*FLEN/8, x4, x1, x2)
-
-inst_720:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1440*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1440*FLEN/8, x4, x1, x2)
-
-inst_721:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1442*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1442*FLEN/8, x4, x1, x2)
-
-inst_722:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1444*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1444*FLEN/8, x4, x1, x2)
-
-inst_723:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1446*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1446*FLEN/8, x4, x1, x2)
-
-inst_724:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1448*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1448*FLEN/8, x4, x1, x2)
-
-inst_725:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05cfda and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x5cfda; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1450*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1450*FLEN/8, x4, x1, x2)
-
-inst_726:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05cfda and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x5cfda;
-   valaddr_reg:x3; val_offset:1452*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1452*FLEN/8, x4, x1, x2)
-
-inst_727:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x05cfda and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x5cfda; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1454*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1454*FLEN/8, x4, x1, x2)
-
-inst_728:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x05cfda and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x5cfda;
-   valaddr_reg:x3; val_offset:1456*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1456*FLEN/8, x4, x1, x2)
-
-inst_729:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1458*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1458*FLEN/8, x4, x1, x2)
-
-inst_730:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x2acc0a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40aacc0a; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1460*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1460*FLEN/8, x4, x1, x2)
-
-inst_731:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x2acc0a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40aacc0a;
-   valaddr_reg:x3; val_offset:1462*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1462*FLEN/8, x4, x1, x2)
-
-inst_732:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x3a1e85 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x2acc0a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3a1e85; op2val:0x40aacc0a;
-   valaddr_reg:x3; val_offset:1464*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1464*FLEN/8, x4, x1, x2)
-
-inst_733:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1466*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1466*FLEN/8, x4, x1, x2)
-
-inst_734:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1468*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1468*FLEN/8, x4, x1, x2)
-
-inst_735:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1470*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1470*FLEN/8, x4, x1, x2)
-
-inst_736:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1472*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1472*FLEN/8, x4, x1, x2)
-
-inst_737:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1474*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1474*FLEN/8, x4, x1, x2)
-
-inst_738:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1476*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1476*FLEN/8, x4, x1, x2)
-
-inst_739:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5abd82 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ddabd82; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1478*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1478*FLEN/8, x4, x1, x2)
-
-inst_740:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x5abd82 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7ddabd82;
-   valaddr_reg:x3; val_offset:1480*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1480*FLEN/8, x4, x1, x2)
-
-inst_741:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1482*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1482*FLEN/8, x4, x1, x2)
-
-inst_742:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1484*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1484*FLEN/8, x4, x1, x2)
-
-inst_743:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5abd82 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ddabd82; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1486*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1486*FLEN/8, x4, x1, x2)
-
-inst_744:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1488*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1488*FLEN/8, x4, x1, x2)
-
-inst_745:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1490*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1490*FLEN/8, x4, x1, x2)
-
-inst_746:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1492*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1492*FLEN/8, x4, x1, x2)
-
-inst_747:
-// fs1 == 0 and fe1 == 0xfb and fm1 == 0x5abd82 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ddabd82; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1494*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1494*FLEN/8, x4, x1, x2)
-
-inst_748:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1496*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1496*FLEN/8, x4, x1, x2)
-
-inst_749:
-// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x2efe01 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c2efe01; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1498*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1498*FLEN/8, x4, x1, x2)
-
-inst_750:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0xf8 and fm2 == 0x2efe01 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7c2efe01;
-   valaddr_reg:x3; val_offset:1500*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1500*FLEN/8, x4, x1, x2)
-
-inst_751:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1502*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1502*FLEN/8, x4, x1, x2)
-
-inst_752:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1504*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1504*FLEN/8, x4, x1, x2)
-
-inst_753:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1506*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1506*FLEN/8, x4, x1, x2)
-
-inst_754:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1508*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1508*FLEN/8, x4, x1, x2)
-
-inst_755:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1510*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1510*FLEN/8, x4, x1, x2)
-
-inst_756:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1512*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1512*FLEN/8, x4, x1, x2)
-
-inst_757:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1514*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1514*FLEN/8, x4, x1, x2)
-
-inst_758:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1516*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1516*FLEN/8, x4, x1, x2)
-
-inst_759:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1518*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1518*FLEN/8, x4, x1, x2)
-
-inst_760:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1520*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1520*FLEN/8, x4, x1, x2)
-
-inst_761:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1522*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1522*FLEN/8, x4, x1, x2)
-
-inst_762:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f522 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f522; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1524*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1524*FLEN/8, x4, x1, x2)
-
-inst_763:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03f522 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x3f522;
-   valaddr_reg:x3; val_offset:1526*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1526*FLEN/8, x4, x1, x2)
-
-inst_764:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x03f522 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x3f522; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1528*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1528*FLEN/8, x4, x1, x2)
-
-inst_765:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x03f522 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x3f522;
-   valaddr_reg:x3; val_offset:1530*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1530*FLEN/8, x4, x1, x2)
-
-inst_766:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1532*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1532*FLEN/8, x4, x1, x2)
-
-inst_767:
-// fs1 == 0 and fe1 == 0x80 and fm1 == 0x689ac4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40689ac4; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1534*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1534*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_7)
-
-inst_768:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x80 and fm2 == 0x689ac4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40689ac4;
-   valaddr_reg:x3; val_offset:1536*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1536*FLEN/8, x4, x1, x2)
-
-inst_769:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x27935b and fs2 == 0 and fe2 == 0x80 and fm2 == 0x689ac4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x27935b; op2val:0x40689ac4;
-   valaddr_reg:x3; val_offset:1538*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1538*FLEN/8, x4, x1, x2)
-
-inst_770:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1540*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1540*FLEN/8, x4, x1, x2)
-
-inst_771:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7f7fffff;
-   valaddr_reg:x3; val_offset:1542*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1542*FLEN/8, x4, x1, x2)
-
-inst_772:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1544*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1544*FLEN/8, x4, x1, x2)
-
-inst_773:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1546*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1546*FLEN/8, x4, x1, x2)
-
-inst_774:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1548*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1548*FLEN/8, x4, x1, x2)
-
-inst_775:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1550*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1550*FLEN/8, x4, x1, x2)
-
-inst_776:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0f4d55 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0f4d55; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1552*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1552*FLEN/8, x4, x1, x2)
-
-inst_777:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x0f4d55 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7e0f4d55;
-   valaddr_reg:x3; val_offset:1554*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1554*FLEN/8, x4, x1, x2)
-
-inst_778:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1556*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1556*FLEN/8, x4, x1, x2)
-
-inst_779:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1558*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1558*FLEN/8, x4, x1, x2)
-
-inst_780:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0f4d55 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0f4d55; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1560*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1560*FLEN/8, x4, x1, x2)
-
-inst_781:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1562*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1562*FLEN/8, x4, x1, x2)
-
-inst_782:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1564*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1564*FLEN/8, x4, x1, x2)
-
-inst_783:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1566*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1566*FLEN/8, x4, x1, x2)
-
-inst_784:
-// fs1 == 0 and fe1 == 0xfc and fm1 == 0x0f4d55 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7e0f4d55; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1568*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1568*FLEN/8, x4, x1, x2)
-
-inst_785:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1570*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1570*FLEN/8, x4, x1, x2)
-
-inst_786:
-// fs1 == 0 and fe1 == 0xf8 and fm1 == 0x654888 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7c654888; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1572*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1572*FLEN/8, x4, x1, x2)
-
-inst_787:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0xf8 and fm2 == 0x654888 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7c654888;
-   valaddr_reg:x3; val_offset:1574*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1574*FLEN/8, x4, x1, x2)
-
-inst_788:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1576*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1576*FLEN/8, x4, x1, x2)
-
-inst_789:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1578*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1578*FLEN/8, x4, x1, x2)
-
-inst_790:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1580*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1580*FLEN/8, x4, x1, x2)
-
-inst_791:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1582*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1582*FLEN/8, x4, x1, x2)
-
-inst_792:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1584*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1584*FLEN/8, x4, x1, x2)
-
-inst_793:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1586*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1586*FLEN/8, x4, x1, x2)
-
-inst_794:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1588*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1588*FLEN/8, x4, x1, x2)
-
-inst_795:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1590*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1590*FLEN/8, x4, x1, x2)
-
-inst_796:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1592*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1592*FLEN/8, x4, x1, x2)
-
-inst_797:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x052f75 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x52f75; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1594*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1594*FLEN/8, x4, x1, x2)
-
-inst_798:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x052f75 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x52f75;
-   valaddr_reg:x3; val_offset:1596*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1596*FLEN/8, x4, x1, x2)
-
-inst_799:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x052f75 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x52f75; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1598*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1598*FLEN/8, x4, x1, x2)
-
-inst_800:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x052f75 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x52f75;
-   valaddr_reg:x3; val_offset:1600*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1600*FLEN/8, x4, x1, x2)
-
-inst_801:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1602*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1602*FLEN/8, x4, x1, x2)
-
-inst_802:
-// fs1 == 0 and fe1 == 0x81 and fm1 == 0x186289 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x40986289; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1604*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1604*FLEN/8, x4, x1, x2)
-
-inst_803:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x186289 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x40986289;
-   valaddr_reg:x3; val_offset:1606*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1606*FLEN/8, x4, x1, x2)
-
-inst_804:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x33da99 and fs2 == 0 and fe2 == 0x81 and fm2 == 0x186289 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x33da99; op2val:0x40986289;
-   valaddr_reg:x3; val_offset:1608*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1608*FLEN/8, x4, x1, x2)
-
-inst_805:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1610*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1610*FLEN/8, x4, x1, x2)
-
-inst_806:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1612*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1612*FLEN/8, x4, x1, x2)
-
-inst_807:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1614*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1614*FLEN/8, x4, x1, x2)
-
-inst_808:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1616*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1616*FLEN/8, x4, x1, x2)
-
-inst_809:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1618*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1618*FLEN/8, x4, x1, x2)
-
-inst_810:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1620*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1620*FLEN/8, x4, x1, x2)
-
-inst_811:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03130e and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03130e; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1622*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1622*FLEN/8, x4, x1, x2)
-
-inst_812:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x03130e and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xfe03130e;
-   valaddr_reg:x3; val_offset:1624*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1624*FLEN/8, x4, x1, x2)
-
-inst_813:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1626*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1626*FLEN/8, x4, x1, x2)
-
-inst_814:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1628*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1628*FLEN/8, x4, x1, x2)
-
-inst_815:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03130e and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03130e; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1630*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1630*FLEN/8, x4, x1, x2)
-
-inst_816:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1632*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1632*FLEN/8, x4, x1, x2)
-
-inst_817:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1634*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1634*FLEN/8, x4, x1, x2)
-
-inst_818:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1636*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1636*FLEN/8, x4, x1, x2)
-
-inst_819:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x03130e and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe03130e; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1638*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1638*FLEN/8, x4, x1, x2)
-
-inst_820:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1640*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1640*FLEN/8, x4, x1, x2)
-
-inst_821:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x51b817 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc51b817; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1642*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1642*FLEN/8, x4, x1, x2)
-
-inst_822:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x51b817 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xfc51b817;
-   valaddr_reg:x3; val_offset:1644*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1644*FLEN/8, x4, x1, x2)
-
-inst_823:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1646*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1646*FLEN/8, x4, x1, x2)
-
-inst_824:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1648*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1648*FLEN/8, x4, x1, x2)
-
-inst_825:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1650*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1650*FLEN/8, x4, x1, x2)
-
-inst_826:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1652*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1652*FLEN/8, x4, x1, x2)
-
-inst_827:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1654*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1654*FLEN/8, x4, x1, x2)
-
-inst_828:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1656*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1656*FLEN/8, x4, x1, x2)
-
-inst_829:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1658*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1658*FLEN/8, x4, x1, x2)
-
-inst_830:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04be30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8004be30; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1660*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1660*FLEN/8, x4, x1, x2)
-
-inst_831:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04be30 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x8004be30;
-   valaddr_reg:x3; val_offset:1662*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1662*FLEN/8, x4, x1, x2)
-
-inst_832:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04be30 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8004be30; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1664*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1664*FLEN/8, x4, x1, x2)
-
-inst_833:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04be30 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x8004be30;
-   valaddr_reg:x3; val_offset:1666*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1666*FLEN/8, x4, x1, x2)
-
-inst_834:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1668*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1668*FLEN/8, x4, x1, x2)
-
-inst_835:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x0b61db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc08b61db; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1670*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1670*FLEN/8, x4, x1, x2)
-
-inst_836:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0b61db and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc08b61db;
-   valaddr_reg:x3; val_offset:1672*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1672*FLEN/8, x4, x1, x2)
-
-inst_837:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2f6de8 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0b61db and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802f6de8; op2val:0xc08b61db;
-   valaddr_reg:x3; val_offset:1674*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1674*FLEN/8, x4, x1, x2)
-
-inst_838:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1676*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1676*FLEN/8, x4, x1, x2)
-
-inst_839:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1678*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1678*FLEN/8, x4, x1, x2)
-
-inst_840:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1680*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1680*FLEN/8, x4, x1, x2)
-
-inst_841:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1682*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1682*FLEN/8, x4, x1, x2)
-
-inst_842:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1684*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1684*FLEN/8, x4, x1, x2)
-
-inst_843:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1686*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1686*FLEN/8, x4, x1, x2)
-
-inst_844:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x7671c2 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdf671c2; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1688*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1688*FLEN/8, x4, x1, x2)
-
-inst_845:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x7671c2 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xfdf671c2;
-   valaddr_reg:x3; val_offset:1690*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1690*FLEN/8, x4, x1, x2)
-
-inst_846:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1692*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1692*FLEN/8, x4, x1, x2)
-
-inst_847:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1694*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1694*FLEN/8, x4, x1, x2)
-
-inst_848:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x7671c2 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdf671c2; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1696*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1696*FLEN/8, x4, x1, x2)
-
-inst_849:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1698*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1698*FLEN/8, x4, x1, x2)
-
-inst_850:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1700*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1700*FLEN/8, x4, x1, x2)
-
-inst_851:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1702*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1702*FLEN/8, x4, x1, x2)
-
-inst_852:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x7671c2 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdf671c2; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1704*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1704*FLEN/8, x4, x1, x2)
-
-inst_853:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1706*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1706*FLEN/8, x4, x1, x2)
-
-inst_854:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x4527ce and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc4527ce; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1708*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1708*FLEN/8, x4, x1, x2)
-
-inst_855:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x4527ce and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xfc4527ce;
-   valaddr_reg:x3; val_offset:1710*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1710*FLEN/8, x4, x1, x2)
-
-inst_856:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1712*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1712*FLEN/8, x4, x1, x2)
-
-inst_857:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1714*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1714*FLEN/8, x4, x1, x2)
-
-inst_858:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1716*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1716*FLEN/8, x4, x1, x2)
-
-inst_859:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1718*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1718*FLEN/8, x4, x1, x2)
-
-inst_860:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1720*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1720*FLEN/8, x4, x1, x2)
-
-inst_861:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x047573 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80047573; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1722*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1722*FLEN/8, x4, x1, x2)
-
-inst_862:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x047573 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x80047573;
-   valaddr_reg:x3; val_offset:1724*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1724*FLEN/8, x4, x1, x2)
-
-inst_863:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x047573 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80047573; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1726*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1726*FLEN/8, x4, x1, x2)
-
-inst_864:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x047573 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x80047573;
-   valaddr_reg:x3; val_offset:1728*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1728*FLEN/8, x4, x1, x2)
-
-inst_865:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1730*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1730*FLEN/8, x4, x1, x2)
-
-inst_866:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x030845 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc0830845; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1732*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1732*FLEN/8, x4, x1, x2)
-
-inst_867:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x030845 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc0830845;
-   valaddr_reg:x3; val_offset:1734*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1734*FLEN/8, x4, x1, x2)
-
-inst_868:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2c9686 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x030845 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802c9686; op2val:0xc0830845;
-   valaddr_reg:x3; val_offset:1736*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1736*FLEN/8, x4, x1, x2)
-
-inst_869:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1738*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1738*FLEN/8, x4, x1, x2)
-
-inst_870:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1740*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1740*FLEN/8, x4, x1, x2)
-
-inst_871:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x5b0376 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xff5b0376;
-   valaddr_reg:x3; val_offset:1742*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1742*FLEN/8, x4, x1, x2)
-
-inst_872:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1744*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1744*FLEN/8, x4, x1, x2)
-
-inst_873:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1746*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1746*FLEN/8, x4, x1, x2)
-
-inst_874:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1748*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1748*FLEN/8, x4, x1, x2)
-
-inst_875:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1750*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1750*FLEN/8, x4, x1, x2)
-
-inst_876:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1752*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1752*FLEN/8, x4, x1, x2)
-
-inst_877:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1754*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1754*FLEN/8, x4, x1, x2)
-
-inst_878:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x2f35f8 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdaf35f8; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1756*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1756*FLEN/8, x4, x1, x2)
-
-inst_879:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xfb and fm2 == 0x2f35f8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xfdaf35f8;
-   valaddr_reg:x3; val_offset:1758*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1758*FLEN/8, x4, x1, x2)
-
-inst_880:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1760*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1760*FLEN/8, x4, x1, x2)
-
-inst_881:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1762*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1762*FLEN/8, x4, x1, x2)
-
-inst_882:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1764*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1764*FLEN/8, x4, x1, x2)
-
-inst_883:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x2f35f8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdaf35f8; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1766*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1766*FLEN/8, x4, x1, x2)
-
-inst_884:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1768*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1768*FLEN/8, x4, x1, x2)
-
-inst_885:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1770*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1770*FLEN/8, x4, x1, x2)
-
-inst_886:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1772*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1772*FLEN/8, x4, x1, x2)
-
-inst_887:
-// fs1 == 1 and fe1 == 0xfe and fm1 == 0x5b0376 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xff5b0376; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1774*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1774*FLEN/8, x4, x1, x2)
-
-inst_888:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1776*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1776*FLEN/8, x4, x1, x2)
-
-inst_889:
-// fs1 == 1 and fe1 == 0xfb and fm1 == 0x2f35f8 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfdaf35f8; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1778*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1778*FLEN/8, x4, x1, x2)
-
-inst_890:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1780*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1780*FLEN/8, x4, x1, x2)
-
-inst_891:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x0c2b2c and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc0c2b2c; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1782*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1782*FLEN/8, x4, x1, x2)
-
-inst_892:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x0c2b2c and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xfc0c2b2c;
-   valaddr_reg:x3; val_offset:1784*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1784*FLEN/8, x4, x1, x2)
-
-inst_893:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1786*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1786*FLEN/8, x4, x1, x2)
-
-inst_894:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1788*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1788*FLEN/8, x4, x1, x2)
-
-inst_895:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1790*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1790*FLEN/8, x4, x1, x2)
-RVTEST_SIGBASE(x1,signature_x1_8)
-
-inst_896:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x032b85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80032b85; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1792*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1792*FLEN/8, x4, x1, x2)
-
-inst_897:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x032b85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x80032b85;
-   valaddr_reg:x3; val_offset:1794*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1794*FLEN/8, x4, x1, x2)
-
-inst_898:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x032b85 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x80032b85; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1796*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1796*FLEN/8, x4, x1, x2)
-
-inst_899:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x032b85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x80032b85;
-   valaddr_reg:x3; val_offset:1798*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1798*FLEN/8, x4, x1, x2)
-
-inst_900:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1800*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1800*FLEN/8, x4, x1, x2)
-
-inst_901:
-// fs1 == 1 and fe1 == 0x80 and fm1 == 0x3a50eb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc03a50eb; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1802*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1802*FLEN/8, x4, x1, x2)
-
-inst_902:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3a50eb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc03a50eb;
-   valaddr_reg:x3; val_offset:1804*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1804*FLEN/8, x4, x1, x2)
-
-inst_903:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x1fb335 and fs2 == 1 and fe2 == 0x80 and fm2 == 0x3a50eb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x801fb335; op2val:0xc03a50eb;
-   valaddr_reg:x3; val_offset:1806*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1806*FLEN/8, x4, x1, x2)
-
-inst_904:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1808*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1808*FLEN/8, x4, x1, x2)
-
-inst_905:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1810*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1810*FLEN/8, x4, x1, x2)
-
-inst_906:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1812*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1812*FLEN/8, x4, x1, x2)
-
-inst_907:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1814*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1814*FLEN/8, x4, x1, x2)
-
-inst_908:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1816*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1816*FLEN/8, x4, x1, x2)
-
-inst_909:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1818*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1818*FLEN/8, x4, x1, x2)
-
-inst_910:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x048fde and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe048fde; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1820*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1820*FLEN/8, x4, x1, x2)
-
-inst_911:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x048fde and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xfe048fde;
-   valaddr_reg:x3; val_offset:1822*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1822*FLEN/8, x4, x1, x2)
-
-inst_912:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1824*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1824*FLEN/8, x4, x1, x2)
-
-inst_913:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1826*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1826*FLEN/8, x4, x1, x2)
-
-inst_914:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x048fde and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe048fde; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1828*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1828*FLEN/8, x4, x1, x2)
-
-inst_915:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1830*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1830*FLEN/8, x4, x1, x2)
-
-inst_916:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1832*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1832*FLEN/8, x4, x1, x2)
-
-inst_917:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1834*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1834*FLEN/8, x4, x1, x2)
-
-inst_918:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x048fde and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe048fde; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1836*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1836*FLEN/8, x4, x1, x2)
-
-inst_919:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1838*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1838*FLEN/8, x4, x1, x2)
-
-inst_920:
-// fs1 == 1 and fe1 == 0xf8 and fm1 == 0x541963 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc541963; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1840*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1840*FLEN/8, x4, x1, x2)
-
-inst_921:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x541963 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xfc541963;
-   valaddr_reg:x3; val_offset:1842*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1842*FLEN/8, x4, x1, x2)
-
-inst_922:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1844*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1844*FLEN/8, x4, x1, x2)
-
-inst_923:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04cbf8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8004cbf8; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1846*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1846*FLEN/8, x4, x1, x2)
-
-inst_924:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04cbf8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x8004cbf8;
-   valaddr_reg:x3; val_offset:1848*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1848*FLEN/8, x4, x1, x2)
-
-inst_925:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x04cbf8 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x8004cbf8; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1850*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1850*FLEN/8, x4, x1, x2)
-
-inst_926:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x04cbf8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x8004cbf8;
-   valaddr_reg:x3; val_offset:1852*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1852*FLEN/8, x4, x1, x2)
-
-inst_927:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1854*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1854*FLEN/8, x4, x1, x2)
-
-inst_928:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x0cf6cd and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc08cf6cd; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1856*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1856*FLEN/8, x4, x1, x2)
-
-inst_929:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0cf6cd and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc08cf6cd;
-   valaddr_reg:x3; val_offset:1858*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1858*FLEN/8, x4, x1, x2)
-
-inst_930:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x2ff7b4 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x0cf6cd and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x802ff7b4; op2val:0xc08cf6cd;
-   valaddr_reg:x3; val_offset:1860*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1860*FLEN/8, x4, x1, x2)
-
-inst_931:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1862*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1862*FLEN/8, x4, x1, x2)
-
-inst_932:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xff7fffff;
-   valaddr_reg:x3; val_offset:1864*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1864*FLEN/8, x4, x1, x2)
-
-inst_933:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1866*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1866*FLEN/8, x4, x1, x2)
-
-inst_934:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1868*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1868*FLEN/8, x4, x1, x2)
-
-inst_935:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1870*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1870*FLEN/8, x4, x1, x2)
-
-inst_936:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1872*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1872*FLEN/8, x4, x1, x2)
-
-inst_937:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2d09bb and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2d09bb; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1874*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1874*FLEN/8, x4, x1, x2)
-
-inst_938:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xfc and fm2 == 0x2d09bb and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xfe2d09bb;
-   valaddr_reg:x3; val_offset:1876*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1876*FLEN/8, x4, x1, x2)
-
-inst_939:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1878*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1878*FLEN/8, x4, x1, x2)
-
-inst_940:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1880*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1880*FLEN/8, x4, x1, x2)
-
-inst_941:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2d09bb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2d09bb; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1882*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1882*FLEN/8, x4, x1, x2)
-
-inst_942:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1884*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1884*FLEN/8, x4, x1, x2)
-
-inst_943:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1886*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1886*FLEN/8, x4, x1, x2)
-
-inst_944:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1888*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1888*FLEN/8, x4, x1, x2)
-
-inst_945:
-// fs1 == 1 and fe1 == 0xfc and fm1 == 0x2d09bb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfe2d09bb; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1890*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1890*FLEN/8, x4, x1, x2)
-
-inst_946:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1892*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1892*FLEN/8, x4, x1, x2)
-
-inst_947:
-// fs1 == 1 and fe1 == 0xf9 and fm1 == 0x0a6e2f and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xfc8a6e2f; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1894*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1894*FLEN/8, x4, x1, x2)
-
-inst_948:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0xf9 and fm2 == 0x0a6e2f and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xfc8a6e2f;
-   valaddr_reg:x3; val_offset:1896*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1896*FLEN/8, x4, x1, x2)
-
-inst_949:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1898*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1898*FLEN/8, x4, x1, x2)
-
-inst_950:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1900*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1900*FLEN/8, x4, x1, x2)
-
-inst_951:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x3e9d25 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x803e9d25;
-   valaddr_reg:x3; val_offset:1902*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1902*FLEN/8, x4, x1, x2)
-
-inst_952:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1904*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1904*FLEN/8, x4, x1, x2)
-
-inst_953:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1906*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1906*FLEN/8, x4, x1, x2)
-
-inst_954:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1908*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1908*FLEN/8, x4, x1, x2)
-
-inst_955:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1910*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1910*FLEN/8, x4, x1, x2)
-
-inst_956:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1912*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1912*FLEN/8, x4, x1, x2)
-
-inst_957:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1914*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1914*FLEN/8, x4, x1, x2)
-
-inst_958:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1916*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1916*FLEN/8, x4, x1, x2)
-
-inst_959:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1918*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1918*FLEN/8, x4, x1, x2)
-
-inst_960:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1920*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1920*FLEN/8, x4, x1, x2)
-
-inst_961:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1922*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1922*FLEN/8, x4, x1, x2)
-
-inst_962:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1924*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1924*FLEN/8, x4, x1, x2)
-
-inst_963:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1926*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1926*FLEN/8, x4, x1, x2)
-
-inst_964:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1928*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1928*FLEN/8, x4, x1, x2)
-
-inst_965:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1930*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1930*FLEN/8, x4, x1, x2)
-
-inst_966:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1932*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1932*FLEN/8, x4, x1, x2)
-
-inst_967:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x3e9d25 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x803e9d25; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1934*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1934*FLEN/8, x4, x1, x2)
-
-inst_968:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1936*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1936*FLEN/8, x4, x1, x2)
-
-inst_969:
-// fs1 == 1 and fe1 == 0x81 and fm1 == 0x38016d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0xc0b8016d; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1938*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1938*FLEN/8, x4, x1, x2)
-
-inst_970:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x81 and fm2 == 0x38016d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xc0b8016d;
-   valaddr_reg:x3; val_offset:1940*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1940*FLEN/8, x4, x1, x2)
-
-inst_971:
-// fs1 == 1 and fe1 == 0x00 and fm1 == 0x0642ea and fs2 == 1 and fe2 == 0x81 and fm2 == 0x38016d and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x800642ea; op2val:0xc0b8016d;
-   valaddr_reg:x3; val_offset:1942*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1942*FLEN/8, x4, x1, x2)
-
-inst_972:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1944*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1944*FLEN/8, x4, x1, x2)
-
-inst_973:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0007f0 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7f0;
-   valaddr_reg:x3; val_offset:1946*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1946*FLEN/8, x4, x1, x2)
-
-inst_974:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1948*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1948*FLEN/8, x4, x1, x2)
-
-inst_975:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7eb70362;
-   valaddr_reg:x3; val_offset:1950*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1950*FLEN/8, x4, x1, x2)
-
-inst_976:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7e587392;
-   valaddr_reg:x3; val_offset:1952*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1952*FLEN/8, x4, x1, x2)
-
-inst_977:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x7f2eabd8;
-   valaddr_reg:x3; val_offset:1954*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1954*FLEN/8, x4, x1, x2)
-
-inst_978:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfe39e419;
-   valaddr_reg:x3; val_offset:1956*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1956*FLEN/8, x4, x1, x2)
-
-inst_979:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfee4815a;
-   valaddr_reg:x3; val_offset:1958*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1958*FLEN/8, x4, x1, x2)
-
-inst_980:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfe9ffb35;
-   valaddr_reg:x3; val_offset:1960*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1960*FLEN/8, x4, x1, x2)
-
-inst_981:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfe3b8ad8;
-   valaddr_reg:x3; val_offset:1962*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1962*FLEN/8, x4, x1, x2)
-
-inst_982:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0xfc538835;
-   valaddr_reg:x3; val_offset:1964*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1964*FLEN/8, x4, x1, x2)
-
-inst_983:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x1aeaa5;
-   valaddr_reg:x3; val_offset:1966*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1966*FLEN/8, x4, x1, x2)
-
-inst_984:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x3229c1;
-   valaddr_reg:x3; val_offset:1968*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1968*FLEN/8, x4, x1, x2)
-
-inst_985:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3a1e85 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x3a1e85;
-   valaddr_reg:x3; val_offset:1970*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1970*FLEN/8, x4, x1, x2)
-
-inst_986:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x27935b and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x27935b;
-   valaddr_reg:x3; val_offset:1972*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1972*FLEN/8, x4, x1, x2)
-
-inst_987:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x33da99 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x33da99;
-   valaddr_reg:x3; val_offset:1974*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1974*FLEN/8, x4, x1, x2)
-
-inst_988:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2f6de8 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x802f6de8;
-   valaddr_reg:x3; val_offset:1976*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1976*FLEN/8, x4, x1, x2)
-
-inst_989:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2c9686 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x802c9686;
-   valaddr_reg:x3; val_offset:1978*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1978*FLEN/8, x4, x1, x2)
-
-inst_990:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x1fb335 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x801fb335;
-   valaddr_reg:x3; val_offset:1980*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1980*FLEN/8, x4, x1, x2)
-
-inst_991:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x2ff7b4 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x802ff7b4;
-   valaddr_reg:x3; val_offset:1982*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1982*FLEN/8, x4, x1, x2)
-
-inst_992:
-// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x0642ea and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f0; op2val:0x800642ea;
-   valaddr_reg:x3; val_offset:1984*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1984*FLEN/8, x4, x1, x2)
-
-inst_993:
-// fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7f222105; op2val:0x7ec45459;
-   valaddr_reg:x3; val_offset:1986*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1986*FLEN/8, x4, x1, x2)
-
-inst_994:
-// fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and  fcsr == 0  
-/* opcode: fminm.s ; op1:f30; op2:f29; dest:f31; op1val:0x7ec45459; op2val:0x7f222105;
-   valaddr_reg:x3; val_offset:1988*FLEN/8; fcsr: 0;
-   correctval:??; testreg:x2
-*/
-TEST_FPRR_OP_NRM(fminm.s, f31, f30, f29, 0, 0, x3, 1988*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2125923170,32,FLEN)
-NAN_BOXED(2125923170,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2133765080,32,FLEN)
-NAN_BOXED(2133765080,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4276388186,32,FLEN)
-NAN_BOXED(4276388186,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4271897397,32,FLEN)
-NAN_BOXED(4271897397,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(2105652228,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(2077197933,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2077197933,32,FLEN)
-NAN_BOXED(2077197933,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2077197933,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(1764005,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(2134505220,32,FLEN)
-NAN_BOXED(2134505220,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(1764005,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(3287489,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(3287489,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(3808901,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(3808901,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2593627,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(2593627,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(3398297,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(3398297,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2150591976,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(2150591976,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2150405766,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(2150405766,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(4284154742,32,FLEN)
-NAN_BOXED(4284154742,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(1537904,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(153790,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(153790,32,FLEN)
-NAN_BOXED(153790,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(153790,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1074392209,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1074392209,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(1074392209,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2125923170,32,FLEN)
-NAN_BOXED(2125923170,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(2099056711,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2099056711,32,FLEN)
-NAN_BOXED(2099056711,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2099056711,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2133765080,32,FLEN)
-NAN_BOXED(2133765080,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(2099056711,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2099056711,32,FLEN)
-NAN_BOXED(2099056711,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(4276388186,32,FLEN)
-NAN_BOXED(4276388186,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(4271897397,32,FLEN)
-NAN_BOXED(4271897397,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(2099056711,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(2071678270,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2071678270,32,FLEN)
-NAN_BOXED(2071678270,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2071678270,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(1764005,32,FLEN)
-NAN_BOXED(931160,32,FLEN)
-NAN_BOXED(2134505220,32,FLEN)
-NAN_BOXED(2134505220,32,FLEN)
-NAN_BOXED(931160,32,FLEN)
-NAN_BOXED(931160,32,FLEN)
-NAN_BOXED(1764005,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(931160,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(3287489,32,FLEN)
-NAN_BOXED(931160,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(931160,32,FLEN)
-NAN_BOXED(931160,32,FLEN)
-NAN_BOXED(3287489,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(3808901,32,FLEN)
-NAN_BOXED(931160,32,FLEN)
-NAN_BOXED(3808901,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2593627,32,FLEN)
-NAN_BOXED(931160,32,FLEN)
-NAN_BOXED(2593627,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(3398297,32,FLEN)
-NAN_BOXED(931160,32,FLEN)
-NAN_BOXED(3398297,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
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-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3233284461,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(3233284461,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2125923170,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2119725970,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2133765080,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4265206809,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4276388186,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4271897397,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4265315032,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(4233332789,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(1764005,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3287489,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3808901,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2593627,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(3398297,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2150591976,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2150405766,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2149561141,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2150627252,32,FLEN)
-NAN_BOXED(2032,32,FLEN)
-NAN_BOXED(2147893994,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2126795865,32,FLEN)
-NAN_BOXED(2132943109,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_2:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_3:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_4:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_5:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_6:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_7:
-    .fill 256*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_8:
-    .fill 198*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fround_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fround_b1-01.S
deleted file mode 100644
index edebce8fd..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/F_Zfa/src/fround_b1-01.S
+++ /dev/null
@@ -1,353 +0,0 @@
-
-// -----------
-// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
-// version   : 0.10.3
-// timestamp : Mon May 22 12:11:47 2023 GMT
-// usage     : riscv_ctg \
-//                  -- cgf //                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
-//                  --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fround.s.cgf \
- \
-//                  -- xlen 64  \
-// -----------
-//
-// -----------
-// Copyright (c) 2020. RISC-V International. All rights reserved.
-// SPDX-License-Identifier: BSD-3-Clause
-// -----------
-//
-// This assembly file tests the fround.s instruction of the RISC-V RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fround_b1 covergroup.
-// 
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-#ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fround_b1)
-
-RVTEST_FP_ENABLE()
-RVTEST_VALBASEUPD(x3,test_dataset_0)
-RVTEST_SIGBASE(x1,signature_x1_1)
-
-inst_0:
-// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3;
-val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
-
-inst_1:
-// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f29; dest:f30; op1val:0x80000000; valaddr_reg:x3;
-val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f30, f29, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
-
-inst_2:
-// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3;
-val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f29, f30, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
-
-inst_3:
-// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3;
-val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f28, f27, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
-
-inst_4:
-// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3;
-val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f27, f28, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
-
-inst_5:
-// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f25; dest:f26; op1val:0x807ffffe; valaddr_reg:x3;
-val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f26, f25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
-
-inst_6:
-// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f26; dest:f25; op1val:0x7fffff; valaddr_reg:x3;
-val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f25, f26, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
-
-inst_7:
-// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f23; dest:f24; op1val:0x807fffff; valaddr_reg:x3;
-val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f24, f23, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
-
-inst_8:
-// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3;
-val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f23, f24, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
-
-inst_9:
-// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3;
-val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f22, f21, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
-
-inst_10:
-// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f22; dest:f21; op1val:0x800001; valaddr_reg:x3;
-val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f21, f22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
-
-inst_11:
-// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f19; dest:f20; op1val:0x80855555; valaddr_reg:x3;
-val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f20, f19, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
-
-inst_12:
-// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f20; dest:f19; op1val:0x7f7fffff; valaddr_reg:x3;
-val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f19, f20, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
-
-inst_13:
-// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f17; dest:f18; op1val:0xff7fffff; valaddr_reg:x3;
-val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f18, f17, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
-
-inst_14:
-// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f18; dest:f17; op1val:0x7f800000; valaddr_reg:x3;
-val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f17, f18, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
-
-inst_15:
-// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f15; dest:f16; op1val:0xff800000; valaddr_reg:x3;
-val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f16, f15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
-
-inst_16:
-// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f16; dest:f15; op1val:0x7fc00000; valaddr_reg:x3;
-val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f15, f16, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
-
-inst_17:
-// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f13; dest:f14; op1val:0xffc00000; valaddr_reg:x3;
-val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f14, f13, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
-
-inst_18:
-// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f14; dest:f13; op1val:0x7fc00001; valaddr_reg:x3;
-val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f13, f14, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
-
-inst_19:
-// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f11; dest:f12; op1val:0xffc55555; valaddr_reg:x3;
-val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f12, f11, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
-
-inst_20:
-// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f12; dest:f11; op1val:0x7f800001; valaddr_reg:x3;
-val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f11, f12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
-
-inst_21:
-// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f9; dest:f10; op1val:0xffaaaaaa; valaddr_reg:x3;
-val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f10, f9, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
-
-inst_22:
-// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f10; dest:f9; op1val:0x3f800000; valaddr_reg:x3;
-val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f9, f10, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
-
-inst_23:
-// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and  fcsr == 0x0 and rm_val == 7   
-/* opcode: fround.s ; op1:f7; dest:f8; op1val:0xbf800000; valaddr_reg:x3;
-val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f8, f7, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
-
-inst_24:
-// rs1==f8, rd==f7,
-/* opcode: fround.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
-val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f7, f8, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
-
-inst_25:
-// rs1==f5, rd==f6,
-/* opcode: fround.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
-val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f6, f5, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
-
-inst_26:
-// rs1==f6, rd==f5,
-/* opcode: fround.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
-val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f5, f6, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
-
-inst_27:
-// rs1==f3, rd==f4,
-/* opcode: fround.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
-val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f4, f3, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
-
-inst_28:
-// rs1==f4, rd==f3,
-/* opcode: fround.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
-val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f3, f4, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
-
-inst_29:
-// rs1==f1, rd==f2,
-/* opcode: fround.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
-val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f2, f1, dyn, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
-
-inst_30:
-// rs1==f2, rd==f1,
-/* opcode: fround.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
-val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f1, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
-
-inst_31:
-// rs1==f0,
-/* opcode: fround.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
-val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f31, f0, dyn, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
-
-inst_32:
-// rd==f0,
-/* opcode: fround.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
-val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
-fcsr_val: 0 */
-TEST_FPSR_OP(fround.s, f0, f31, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
-#endif
-
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0xbabecafe
-.word 0xabecafeb
-.word 0xbecafeba
-.word 0xecafebab
-test_dataset_0:
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(2147483648,32,FLEN)
-NAN_BOXED(1,32,FLEN)
-NAN_BOXED(2147483649,32,FLEN)
-NAN_BOXED(2,32,FLEN)
-NAN_BOXED(2155872254,32,FLEN)
-NAN_BOXED(8388607,32,FLEN)
-NAN_BOXED(2155872255,32,FLEN)
-NAN_BOXED(8388608,32,FLEN)
-NAN_BOXED(2155872256,32,FLEN)
-NAN_BOXED(8388609,32,FLEN)
-NAN_BOXED(2156221781,32,FLEN)
-NAN_BOXED(2139095039,32,FLEN)
-NAN_BOXED(4286578687,32,FLEN)
-NAN_BOXED(2139095040,32,FLEN)
-NAN_BOXED(4286578688,32,FLEN)
-NAN_BOXED(2143289344,32,FLEN)
-NAN_BOXED(4290772992,32,FLEN)
-NAN_BOXED(2143289345,32,FLEN)
-NAN_BOXED(4291122517,32,FLEN)
-NAN_BOXED(2139095041,32,FLEN)
-NAN_BOXED(4289374890,32,FLEN)
-NAN_BOXED(1065353216,32,FLEN)
-NAN_BOXED(3212836864,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-NAN_BOXED(0,32,FLEN)
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-rvtest_sig_begin:
-sig_begin_canary:
-CANARY;
-
-
-
-signature_x1_0:
-    .fill 0*((SIGALIGN)/4),4,0xdeadbeef
-
-
-signature_x1_1:
-    .fill 66*((SIGALIGN)/4),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-tsig_begin_canary:
-CANARY;
-
-mtrap_sigptr:
-    .fill 64*XLEN/32,4,0xdeadbeef
-
-tsig_end_canary:
-CANARY;
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*XLEN/32,4,0xdeadbeef
-
-#endif
-
-
-sig_end_canary:
-CANARY;
-rvtest_sig_end:
-RVMODEL_DATA_END
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
deleted file mode 100644
index 26b2f501c..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
+++ /dev/null
@@ -1,142 +0,0 @@
-///////////////////////////////////////////
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
-// David_Harris@hmc.edu & Katherine Parry
-// Created 2022-06-17 22:58:09.914370//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64I")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-RVTEST_SIGBASE( x6, wally_signature)
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add)
-
-# Testcase 0:  rs1:x20(0x0000000000000000), rs2:x22(0x0000000000000000), result rd:x3(0x0000000000000000)
-li x20, MASK_XLEN(0x0000000000000000)
-li x22, MASK_XLEN(0x0000000000000000)
-ADD x3, x20, x22
-sd x3, 0(x6)
-
-# Testcase 1:  rs1:x1(0x0000000000000000), rs2:x4(0x0000000000000001), result rd:x21(0x0000000000000001)
-li x1, MASK_XLEN(0x0000000000000000)
-li x4, MASK_XLEN(0x0000000000000001)
-ADD x21, x1, x4
-sd x21, 8(x6)
-
-# Testcase 2:  rs1:x7(0x0000000000000000), rs2:x20(0xffffffffffffffff), result rd:x27(0xffffffffffffffff)
-li x7, MASK_XLEN(0x0000000000000000)
-li x20, MASK_XLEN(0xffffffffffffffff)
-ADD x27, x7, x20
-sd x27, 16(x6)
-
-# Testcase 3:  rs1:x19(0x0000000000000001), rs2:x4(0x0000000000000000), result rd:x13(0x0000000000000001)
-li x19, MASK_XLEN(0x0000000000000001)
-li x4, MASK_XLEN(0x0000000000000000)
-ADD x13, x19, x4
-sd x13, 24(x6)
-
-# Testcase 4:  rs1:x3(0x0000000000000001), rs2:x12(0x0000000000000001), result rd:x27(0x0000000000000002)
-li x3, MASK_XLEN(0x0000000000000001)
-li x12, MASK_XLEN(0x0000000000000001)
-ADD x27, x3, x12
-sd x27, 32(x6)
-
-# Testcase 5:  rs1:x4(0x0000000000000001), rs2:x2(0xffffffffffffffff), result rd:x20(0x0000000000000000)
-li x4, MASK_XLEN(0x0000000000000001)
-li x2, MASK_XLEN(0xffffffffffffffff)
-ADD x20, x4, x2
-sd x20, 40(x6)
-
-# Testcase 6:  rs1:x1(0xffffffffffffffff), rs2:x7(0x0000000000000000), result rd:x31(0xffffffffffffffff)
-li x1, MASK_XLEN(0xffffffffffffffff)
-li x7, MASK_XLEN(0x0000000000000000)
-ADD x31, x1, x7
-sd x31, 48(x6)
-
-# Testcase 7:  rs1:x16(0xffffffffffffffff), rs2:x7(0x0000000000000001), result rd:x24(0x0000000000000000)
-li x16, MASK_XLEN(0xffffffffffffffff)
-li x7, MASK_XLEN(0x0000000000000001)
-ADD x24, x16, x7
-sd x24, 56(x6)
-
-# Testcase 8:  rs1:x26(0xffffffffffffffff), rs2:x2(0xffffffffffffffff), result rd:x30(0xfffffffffffffffe)
-li x26, MASK_XLEN(0xffffffffffffffff)
-li x2, MASK_XLEN(0xffffffffffffffff)
-ADD x30, x26, x2
-sd x30, 64(x6)
-
-# Testcase 9:  rs1:x20(0x05d51433ade9b2b4), rs2:x4(0x6cf55b158b53031d), result rd:x27(0x72ca6f49393cb5d1)
-li x20, MASK_XLEN(0x05d51433ade9b2b4)
-li x4, MASK_XLEN(0x6cf55b158b53031d)
-ADD x27, x20, x4
-sd x27, 72(x6)
-
-# Testcase 10:  rs1:x21(0x11ebcd49428a1c22), rs2:x10(0x126cbc8f38884479), result rd:x12(0x245889d87b12609b)
-li x21, MASK_XLEN(0x11ebcd49428a1c22)
-li x10, MASK_XLEN(0x126cbc8f38884479)
-ADD x12, x21, x10
-sd x12, 80(x6)
-
-# Testcase 11:  rs1:x15(0x2e2950656fa231e9), rs2:x2(0x80ee526e0fa07a3f), result rd:x20(0xaf17a2d37f42ac28)
-li x15, MASK_XLEN(0x2e2950656fa231e9)
-li x2, MASK_XLEN(0x80ee526e0fa07a3f)
-ADD x20, x15, x2
-sd x20, 88(x6)
-
-.EQU NUMTESTS,12
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0x98765432
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-
-
-wally_signature:
-    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*(XLEN/32),4,0xdeadbeef
-
-#endif
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-
-RVMODEL_DATA_END
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
-// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
deleted file mode 100644
index 8dd500f83..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
+++ /dev/null
@@ -1,142 +0,0 @@
-///////////////////////////////////////////
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
-// David_Harris@hmc.edu & Katherine Parry
-// Created 2022-06-17 22:58:09.916813//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64I")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-RVTEST_SIGBASE( x6, wally_signature)
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",slt)
-
-# Testcase 0:  rs1:x18(0x0000000000000000), rs2:x9(0x0000000000000000), result rd:x5(0x0000000000000000)
-li x18, MASK_XLEN(0x0000000000000000)
-li x9, MASK_XLEN(0x0000000000000000)
-SLT x5, x18, x9
-sd x5, 0(x6)
-
-# Testcase 1:  rs1:x8(0x0000000000000000), rs2:x25(0x0000000000000001), result rd:x31(0x0000000000000001)
-li x8, MASK_XLEN(0x0000000000000000)
-li x25, MASK_XLEN(0x0000000000000001)
-SLT x31, x8, x25
-sd x31, 8(x6)
-
-# Testcase 2:  rs1:x16(0x0000000000000000), rs2:x12(0xffffffffffffffff), result rd:x20(0x0000000000000000)
-li x16, MASK_XLEN(0x0000000000000000)
-li x12, MASK_XLEN(0xffffffffffffffff)
-SLT x20, x16, x12
-sd x20, 16(x6)
-
-# Testcase 3:  rs1:x10(0x0000000000000001), rs2:x22(0x0000000000000000), result rd:x12(0x0000000000000000)
-li x10, MASK_XLEN(0x0000000000000001)
-li x22, MASK_XLEN(0x0000000000000000)
-SLT x12, x10, x22
-sd x12, 24(x6)
-
-# Testcase 4:  rs1:x19(0x0000000000000001), rs2:x31(0x0000000000000001), result rd:x29(0x0000000000000000)
-li x19, MASK_XLEN(0x0000000000000001)
-li x31, MASK_XLEN(0x0000000000000001)
-SLT x29, x19, x31
-sd x29, 32(x6)
-
-# Testcase 5:  rs1:x21(0x0000000000000001), rs2:x28(0xffffffffffffffff), result rd:x20(0x0000000000000000)
-li x21, MASK_XLEN(0x0000000000000001)
-li x28, MASK_XLEN(0xffffffffffffffff)
-SLT x20, x21, x28
-sd x20, 40(x6)
-
-# Testcase 6:  rs1:x5(0xffffffffffffffff), rs2:x23(0x0000000000000000), result rd:x10(0x0000000000000001)
-li x5, MASK_XLEN(0xffffffffffffffff)
-li x23, MASK_XLEN(0x0000000000000000)
-SLT x10, x5, x23
-sd x10, 48(x6)
-
-# Testcase 7:  rs1:x13(0xffffffffffffffff), rs2:x24(0x0000000000000001), result rd:x14(0x0000000000000001)
-li x13, MASK_XLEN(0xffffffffffffffff)
-li x24, MASK_XLEN(0x0000000000000001)
-SLT x14, x13, x24
-sd x14, 56(x6)
-
-# Testcase 8:  rs1:x27(0xffffffffffffffff), rs2:x21(0xffffffffffffffff), result rd:x3(0x0000000000000000)
-li x27, MASK_XLEN(0xffffffffffffffff)
-li x21, MASK_XLEN(0xffffffffffffffff)
-SLT x3, x27, x21
-sd x3, 64(x6)
-
-# Testcase 9:  rs1:x8(0x983631890063e42f), rs2:x21(0xb2d650af313b32b7), result rd:x15(0x0000000000000001)
-li x8, MASK_XLEN(0x983631890063e42f)
-li x21, MASK_XLEN(0xb2d650af313b32b7)
-SLT x15, x8, x21
-sd x15, 72(x6)
-
-# Testcase 10:  rs1:x19(0xb5d97ef760ef1471), rs2:x28(0xac7c8803e01bbf50), result rd:x14(0x0000000000000000)
-li x19, MASK_XLEN(0xb5d97ef760ef1471)
-li x28, MASK_XLEN(0xac7c8803e01bbf50)
-SLT x14, x19, x28
-sd x14, 80(x6)
-
-# Testcase 11:  rs1:x19(0x66faf98908135d58), rs2:x14(0xb3ab1b2cdf26f517), result rd:x25(0x0000000000000000)
-li x19, MASK_XLEN(0x66faf98908135d58)
-li x14, MASK_XLEN(0xb3ab1b2cdf26f517)
-SLT x25, x19, x14
-sd x25, 88(x6)
-
-.EQU NUMTESTS,12
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0x98765432
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-
-
-wally_signature:
-    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*(XLEN/32),4,0xdeadbeef
-
-#endif
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-
-RVMODEL_DATA_END
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
-// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S
deleted file mode 100644
index 0aec30e56..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S
+++ /dev/null
@@ -1,142 +0,0 @@
-///////////////////////////////////////////
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S
-// David_Harris@hmc.edu & Katherine Parry
-// Created 2022-06-17 22:58:09.917963//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64I")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-RVTEST_SIGBASE( x6, wally_signature)
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sltu)
-
-# Testcase 0:  rs1:x22(0x0000000000000000), rs2:x23(0x0000000000000000), result rd:x2(0x0000000000000000)
-li x22, MASK_XLEN(0x0000000000000000)
-li x23, MASK_XLEN(0x0000000000000000)
-SLTU x2, x22, x23
-sd x2, 0(x6)
-
-# Testcase 1:  rs1:x15(0x0000000000000000), rs2:x17(0x0000000000000001), result rd:x29(0x0000000000000001)
-li x15, MASK_XLEN(0x0000000000000000)
-li x17, MASK_XLEN(0x0000000000000001)
-SLTU x29, x15, x17
-sd x29, 8(x6)
-
-# Testcase 2:  rs1:x16(0x0000000000000000), rs2:x30(0xffffffffffffffff), result rd:x18(0x0000000000000001)
-li x16, MASK_XLEN(0x0000000000000000)
-li x30, MASK_XLEN(0xffffffffffffffff)
-SLTU x18, x16, x30
-sd x18, 16(x6)
-
-# Testcase 3:  rs1:x20(0x0000000000000001), rs2:x25(0x0000000000000000), result rd:x1(0x0000000000000000)
-li x20, MASK_XLEN(0x0000000000000001)
-li x25, MASK_XLEN(0x0000000000000000)
-SLTU x1, x20, x25
-sd x1, 24(x6)
-
-# Testcase 4:  rs1:x29(0x0000000000000001), rs2:x2(0x0000000000000001), result rd:x16(0x0000000000000000)
-li x29, MASK_XLEN(0x0000000000000001)
-li x2, MASK_XLEN(0x0000000000000001)
-SLTU x16, x29, x2
-sd x16, 32(x6)
-
-# Testcase 5:  rs1:x11(0x0000000000000001), rs2:x10(0xffffffffffffffff), result rd:x27(0x0000000000000001)
-li x11, MASK_XLEN(0x0000000000000001)
-li x10, MASK_XLEN(0xffffffffffffffff)
-SLTU x27, x11, x10
-sd x27, 40(x6)
-
-# Testcase 6:  rs1:x15(0xffffffffffffffff), rs2:x2(0x0000000000000000), result rd:x26(0x0000000000000000)
-li x15, MASK_XLEN(0xffffffffffffffff)
-li x2, MASK_XLEN(0x0000000000000000)
-SLTU x26, x15, x2
-sd x26, 48(x6)
-
-# Testcase 7:  rs1:x27(0xffffffffffffffff), rs2:x29(0x0000000000000001), result rd:x26(0x0000000000000000)
-li x27, MASK_XLEN(0xffffffffffffffff)
-li x29, MASK_XLEN(0x0000000000000001)
-SLTU x26, x27, x29
-sd x26, 56(x6)
-
-# Testcase 8:  rs1:x14(0xffffffffffffffff), rs2:x7(0xffffffffffffffff), result rd:x18(0x0000000000000000)
-li x14, MASK_XLEN(0xffffffffffffffff)
-li x7, MASK_XLEN(0xffffffffffffffff)
-SLTU x18, x14, x7
-sd x18, 64(x6)
-
-# Testcase 9:  rs1:x3(0xf689a4a5ffda0336), rs2:x27(0xfa83ada4a2121ac5), result rd:x24(0x0000000000000001)
-li x3, MASK_XLEN(0xf689a4a5ffda0336)
-li x27, MASK_XLEN(0xfa83ada4a2121ac5)
-SLTU x24, x3, x27
-sd x24, 72(x6)
-
-# Testcase 10:  rs1:x31(0xfca055362169df82), rs2:x22(0x66dd779403c54c71), result rd:x14(0x0000000000000000)
-li x31, MASK_XLEN(0xfca055362169df82)
-li x22, MASK_XLEN(0x66dd779403c54c71)
-SLTU x14, x31, x22
-sd x14, 80(x6)
-
-# Testcase 11:  rs1:x23(0x00de59f550f0fc2b), rs2:x25(0x03a8987936a98d74), result rd:x1(0x0000000000000001)
-li x23, MASK_XLEN(0x00de59f550f0fc2b)
-li x25, MASK_XLEN(0x03a8987936a98d74)
-SLTU x1, x23, x25
-sd x1, 88(x6)
-
-.EQU NUMTESTS,12
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0x98765432
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-
-
-wally_signature:
-    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*(XLEN/32),4,0xdeadbeef
-
-#endif
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-
-RVMODEL_DATA_END
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S
-// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S
deleted file mode 100644
index 1157c194c..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S
+++ /dev/null
@@ -1,142 +0,0 @@
-///////////////////////////////////////////
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S
-// David_Harris@hmc.edu & Katherine Parry
-// Created 2022-06-17 22:58:09.915580//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64I")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-RVTEST_SIGBASE( x6, wally_signature)
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sub)
-
-# Testcase 0:  rs1:x4(0x0000000000000000), rs2:x23(0x0000000000000000), result rd:x13(0x0000000000000000)
-li x4, MASK_XLEN(0x0000000000000000)
-li x23, MASK_XLEN(0x0000000000000000)
-SUB x13, x4, x23
-sd x13, 0(x6)
-
-# Testcase 1:  rs1:x7(0x0000000000000000), rs2:x9(0x0000000000000001), result rd:x12(0xffffffffffffffff)
-li x7, MASK_XLEN(0x0000000000000000)
-li x9, MASK_XLEN(0x0000000000000001)
-SUB x12, x7, x9
-sd x12, 8(x6)
-
-# Testcase 2:  rs1:x29(0x0000000000000000), rs2:x24(0xffffffffffffffff), result rd:x16(0x0000000000000001)
-li x29, MASK_XLEN(0x0000000000000000)
-li x24, MASK_XLEN(0xffffffffffffffff)
-SUB x16, x29, x24
-sd x16, 16(x6)
-
-# Testcase 3:  rs1:x27(0x0000000000000001), rs2:x29(0x0000000000000000), result rd:x30(0x0000000000000001)
-li x27, MASK_XLEN(0x0000000000000001)
-li x29, MASK_XLEN(0x0000000000000000)
-SUB x30, x27, x29
-sd x30, 24(x6)
-
-# Testcase 4:  rs1:x22(0x0000000000000001), rs2:x7(0x0000000000000001), result rd:x31(0x0000000000000000)
-li x22, MASK_XLEN(0x0000000000000001)
-li x7, MASK_XLEN(0x0000000000000001)
-SUB x31, x22, x7
-sd x31, 32(x6)
-
-# Testcase 5:  rs1:x25(0x0000000000000001), rs2:x2(0xffffffffffffffff), result rd:x26(0x0000000000000002)
-li x25, MASK_XLEN(0x0000000000000001)
-li x2, MASK_XLEN(0xffffffffffffffff)
-SUB x26, x25, x2
-sd x26, 40(x6)
-
-# Testcase 6:  rs1:x9(0xffffffffffffffff), rs2:x4(0x0000000000000000), result rd:x20(0xffffffffffffffff)
-li x9, MASK_XLEN(0xffffffffffffffff)
-li x4, MASK_XLEN(0x0000000000000000)
-SUB x20, x9, x4
-sd x20, 48(x6)
-
-# Testcase 7:  rs1:x30(0xffffffffffffffff), rs2:x15(0x0000000000000001), result rd:x22(0xfffffffffffffffe)
-li x30, MASK_XLEN(0xffffffffffffffff)
-li x15, MASK_XLEN(0x0000000000000001)
-SUB x22, x30, x15
-sd x22, 56(x6)
-
-# Testcase 8:  rs1:x22(0xffffffffffffffff), rs2:x14(0xffffffffffffffff), result rd:x29(0x0000000000000000)
-li x22, MASK_XLEN(0xffffffffffffffff)
-li x14, MASK_XLEN(0xffffffffffffffff)
-SUB x29, x22, x14
-sd x29, 64(x6)
-
-# Testcase 9:  rs1:x10(0xdff3334b91b15f5d), rs2:x21(0xeae2025e82339e23), result rd:x12(0xf51130ed0f7dc13a)
-li x10, MASK_XLEN(0xdff3334b91b15f5d)
-li x21, MASK_XLEN(0xeae2025e82339e23)
-SUB x12, x10, x21
-sd x12, 72(x6)
-
-# Testcase 10:  rs1:x5(0xd670f668637e0edc), rs2:x18(0x403d1f83a859890c), result rd:x23(0x9633d6e4bb2485d0)
-li x5, MASK_XLEN(0xd670f668637e0edc)
-li x18, MASK_XLEN(0x403d1f83a859890c)
-SUB x23, x5, x18
-sd x23, 80(x6)
-
-# Testcase 11:  rs1:x11(0x753c7c99032f06ca), rs2:x24(0x143e2e04bdd7d19b), result rd:x2(0x60fe4e944557352f)
-li x11, MASK_XLEN(0x753c7c99032f06ca)
-li x24, MASK_XLEN(0x143e2e04bdd7d19b)
-SUB x2, x11, x24
-sd x2, 88(x6)
-
-.EQU NUMTESTS,12
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0x98765432
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-
-
-wally_signature:
-    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*(XLEN/32),4,0xdeadbeef
-
-#endif
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-
-RVMODEL_DATA_END
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S
-// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S
deleted file mode 100644
index 949672e42..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S
+++ /dev/null
@@ -1,142 +0,0 @@
-///////////////////////////////////////////
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S
-// David_Harris@hmc.edu & Katherine Parry
-// Created 2022-06-17 22:58:09.919138//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64I")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-RVTEST_SIGBASE( x6, wally_signature)
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",xor)
-
-# Testcase 0:  rs1:x27(0x0000000000000000), rs2:x22(0x0000000000000000), result rd:x17(0x0000000000000000)
-li x27, MASK_XLEN(0x0000000000000000)
-li x22, MASK_XLEN(0x0000000000000000)
-XOR x17, x27, x22
-sd x17, 0(x6)
-
-# Testcase 1:  rs1:x20(0x0000000000000000), rs2:x4(0x0000000000000001), result rd:x7(0x0000000000000001)
-li x20, MASK_XLEN(0x0000000000000000)
-li x4, MASK_XLEN(0x0000000000000001)
-XOR x7, x20, x4
-sd x7, 8(x6)
-
-# Testcase 2:  rs1:x4(0x0000000000000000), rs2:x20(0xffffffffffffffff), result rd:x21(0xffffffffffffffff)
-li x4, MASK_XLEN(0x0000000000000000)
-li x20, MASK_XLEN(0xffffffffffffffff)
-XOR x21, x4, x20
-sd x21, 16(x6)
-
-# Testcase 3:  rs1:x7(0x0000000000000001), rs2:x28(0x0000000000000000), result rd:x10(0x0000000000000001)
-li x7, MASK_XLEN(0x0000000000000001)
-li x28, MASK_XLEN(0x0000000000000000)
-XOR x10, x7, x28
-sd x10, 24(x6)
-
-# Testcase 4:  rs1:x4(0x0000000000000001), rs2:x16(0x0000000000000001), result rd:x28(0x0000000000000000)
-li x4, MASK_XLEN(0x0000000000000001)
-li x16, MASK_XLEN(0x0000000000000001)
-XOR x28, x4, x16
-sd x28, 32(x6)
-
-# Testcase 5:  rs1:x30(0x0000000000000001), rs2:x13(0xffffffffffffffff), result rd:x21(0xfffffffffffffffe)
-li x30, MASK_XLEN(0x0000000000000001)
-li x13, MASK_XLEN(0xffffffffffffffff)
-XOR x21, x30, x13
-sd x21, 40(x6)
-
-# Testcase 6:  rs1:x3(0xffffffffffffffff), rs2:x1(0x0000000000000000), result rd:x9(0xffffffffffffffff)
-li x3, MASK_XLEN(0xffffffffffffffff)
-li x1, MASK_XLEN(0x0000000000000000)
-XOR x9, x3, x1
-sd x9, 48(x6)
-
-# Testcase 7:  rs1:x30(0xffffffffffffffff), rs2:x15(0x0000000000000001), result rd:x26(0xfffffffffffffffe)
-li x30, MASK_XLEN(0xffffffffffffffff)
-li x15, MASK_XLEN(0x0000000000000001)
-XOR x26, x30, x15
-sd x26, 56(x6)
-
-# Testcase 8:  rs1:x26(0xffffffffffffffff), rs2:x4(0xffffffffffffffff), result rd:x28(0x0000000000000000)
-li x26, MASK_XLEN(0xffffffffffffffff)
-li x4, MASK_XLEN(0xffffffffffffffff)
-XOR x28, x26, x4
-sd x28, 64(x6)
-
-# Testcase 9:  rs1:x27(0x2227d96d41a93f90), rs2:x21(0x8557716aa7502a81), result rd:x21(0xa770a807e6f91511)
-li x27, MASK_XLEN(0x2227d96d41a93f90)
-li x21, MASK_XLEN(0x8557716aa7502a81)
-XOR x21, x27, x21
-sd x21, 72(x6)
-
-# Testcase 10:  rs1:x9(0x1d77ce4058d87776), rs2:x28(0x27896389df3277fd), result rd:x1(0x3afeadc987ea008b)
-li x9, MASK_XLEN(0x1d77ce4058d87776)
-li x28, MASK_XLEN(0x27896389df3277fd)
-XOR x1, x9, x28
-sd x1, 80(x6)
-
-# Testcase 11:  rs1:x9(0x0a68e88e0ad40415), rs2:x18(0xae55cdff34ab18fd), result rd:x11(0xa43d25713e7f1ce8)
-li x9, MASK_XLEN(0x0a68e88e0ad40415)
-li x18, MASK_XLEN(0xae55cdff34ab18fd)
-XOR x11, x9, x18
-sd x11, 88(x6)
-
-.EQU NUMTESTS,12
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0x98765432
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-
-
-wally_signature:
-    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*(XLEN/32),4,0xdeadbeef
-
-#endif
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-
-RVMODEL_DATA_END
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S
-// David_Harris@hmc.edu & Katherine Parry